NSC DP83901AV Datasheet

DP83901A SNIC Serial Network Interface Controller

November 1995

General Description

The DP83901A Serial Network Interface Controller (SNIC) is a microCMOS VLSI device designed for easy implementation of CSMA/CD local area networks. These include Ethernet (10BASE5), Thin Ethernet (10BASE2) and Twisted-pair Ethernet (10BASE-T). The overall SNIC solution provides the Media Access Control (MAC) and Encode-Decode (ENDEC) functions in accordance with the IEEE 802.3 standard.

The integrated ENDEC module allows Manchester encoding and decoding via a differential transceiver and phase lock loop at 10 Mbit/sec. Also included is a collision detect translator and diagnostic loopback capability. (Continued)

1.0 System Diagram

Features

Compatible with IEEE 802.3, 10BASE5, 10BASE2, 10BASE-T

Dual 16-byte DMA channels

16-byte internal FIFO

Network statistics storage

Supports physical, multicast and broadcast address filtering

10 Mbit/sec Manchester encoding and decoding plus clock recovery

No external precision components required

Efficient buffer management implementation

Transmitter can be selected for half or full step mode

Integrated squelch on receive and collision pairs

3 levels of loopback supported

Utilizes independent system and network clocks

Lock Time 5 bits typical

Decodes Manchester data with up tog18 ns jitter

TL/F/10469– 1

TRI-STATEÉis a registered trademark of National Semiconductor Corporation.

1995 National Semiconductor Corporation RRD-B30M115/Printed in U. S. A.

TL/F/10469

General Description (Continued)

The MAC function (NIC) provides simple and efficient packet transmission and reception control by means of unique dual DMA channels and an internal FIFO. Bus arbitration and memory control logic are integrated to reduce board cost and area overheads.

SNIC used in conjunction with the DP8392 Coaxial Transceiver Interface (CTI) provides a comprehensive 2 chip solution for IEEE 802.3 networks and is designed for easy interface to the latest 10BASE-T transceivers.

Due to the inherent constraints of CMOS processing, isolation is required at the differential signal interfaces for 10BASE5 and 10BASE2 applications. Capacitive or inductive isolation may be used.

Connection Diagram

Table Of Contents

1.0 SYSTEM DIAGRAM

2.0 PIN DESCRIPTION

3.0 BLOCK DIAGRAM

4.0 FUNCTIONAL DESCRIPTION

5.0 TRANSMIT/RECEIVE PACKET ENCAPSULATION/DECAPSULATION

6.0 DIRECT MEMORY ACCESS CONTROL (DMA)

7.0 PACKET RECEPTION

8.0 PACKET TRANSMISSION

9.0 REMOTE DMA

10.0 INTERNAL REGISTERS

11.0 INITIALIZATION PROCEDURE

12.0 LOOPBACK DIAGNOSTICS

13.0 BUS ARBITRATION

14.0 PRELIMINARY ELECTRICAL CHARACTERISTICS

15.0 SWITCHING CHARACTERISTICS

16.0 AC TIMING TEST CONDITIONS

17.0 PHYSICAL DIMENSIONS

Top View

Order Number DP83901AV

See NS Package Number V68A

TL/F/10469– 2

Pin Description

Pin No Pin Name I/O Description

BUS INTERFACE PINS

2 PRD O PORT READ: Enables data from external latch on to local bus during a memory write cycle to

3–6 RA0–RA3 I REGISTER ADDRESS: These four pins are used to select a register to be read or written. The

7–17, AD0– AD15 I/O, Z MULTIPLEXED ADDRESS/DATA BUS:

19,

22–25 used to read and write register data. AD8–AD15 float during I/O transfers, SRD, SWR pins are

26 ADS0 I/O, Z ADDRESS STROBE 0:

27 CS O CHIP SELECT: Chip Select places controller in slave mode for mP access to internal registers.

28 MWR O, Z MASTER WRITE STROBE: (Strobe for DMA transfers)

29 MRD O, Z MASTER READ STROBE: (Strobe for DMA transfers)

30 SWR I SLAVE WRITE STROBE: Strobe from CPU to write an internal register selected by RA0 –RA3.

31 SRD I SLAVE READ STROBE: Strobe from CPU to read an internal register selected by RA0 –RA3.

32 ACK O ACKNOWLEDGE: Active low when SNIC grants access to CPU. Used to insert WAIT states to

34 BSCK I BUS CLOCK: This clock is used to establish the period of the DMA memory cycle. Four clock

36 RACK I READ ACKNOWLEDGE: Indicates that the system DMA or host CPU has read the data placed

37 PWR O PORT WRITE: Strobe used to latch data from the SNIC into external latch for transfer to host

38 READY I READY: This pin is set high to insert wait states during a DMA transfer. The SNIC will sample this

local memory (remote write operation). This allows asynchronous transfer of data from the system memory to local memory.

state of these inputs is ignored when the NIC is not in slave mode (CS

used to select direction of transfer. Bus Master with BACK input asserted.

During t1 of memory cycle AD0–AD15 contain address. During t2, t3, t4 AD0–AD15 contain data (word transfer mode). During t2, t3, t4 AD0–AD7 contain data, AD8 –AD15 contain address (byte transfer mode). Direction of transfer is indicated by SNIC on MWR

Input: with DMA inactive and CS low, latches RA0–RA3 inputs on falling edge. If high, data

present on RA0–RA3 will flow through latch. Output: When Bus Master, latches address bits (A0–A15) to external memory during DMA

transfers.

Must be valid through data portion of bus cycle. RA0–RA3 are used to select the internal register. SWR and SRD select direction of data transfer.

Active low during write cycles (t2, t3, tw) to buffer memory. Rising edge coincides with the presence of valid output data. TRI-STATE

Active during read cycles (t2, t3, tw) to buffer memory. Input data must be valid on rising edge of MRD. TRI-STATE until BACK asserted.

Data is latched into the SNIC on the rising edge of this input.

The register data is output when SRD

CPU until SNIC is synchronized for a register read or write operation.

cycles (t1, t2, t3, t4) are used per DMA cycle. DMA transfers can be extended by one BSCK increments using the READY input.

in the external latch by the SNIC. The SNIC will begin a read cycle to update the latch.

memory during Remote Read transfers. The rising edge of PWR valid data on the local bus.

signal at t3 during DMA transfers.

goes low.

, MRD lines.

until BACK asserted.

high).

coincides with the presence of

Pin Description (Continued)

Pin No Pin Name I/O Description

BUS INTERFACE PINS (Continued)

39 PRQ/ADS1 O, Z PORT REQUEST/ADDRESS STROBE 1

40 BACK I BUS ACKNOWLEDGE: Bus Acknowledge is an active high signal indicating that the CPU has

41 BREQ O BUS REQUEST: Bus Request is an active high signal used to request the bus for DMA transfers.

65 RESET I RESET: Reset is active low and places the SNIC in a reset immediately, no packets are

67 INT O INTERRUPT: Indicates that the SNIC requires CPU attention after reception transmission or

68 WACK I WRITE ACKNOWLEDGE: Issued from system to SNIC to indicate that data has been written to

NETWORK INTERFACE PINS

42, TX

43 TX

b a

46 TEST I FACTORY TEST INPUT: Used to check the chip’s internal functions. Tied low during normal

47 SEL I MODE SELECT: When high, Transmitaand Transmitbare the same voltage in the idle state.

50 X1 I EXTERNAL OSCILLATOR INPUT

51 GND/X2 O GROUND/X2: This in should normally be connected to ground. It is possible to use a crystal

56 SNISEL I FACTORY TEST INPUT: For normal operation tied to VCC. When low enables the ENDEC

60, RX

61 RX

62, CD

63 CD

b a

32-BIT MODE: If LAS is set in the Data Configuration Register, this line is programmed

as ADS1

. It is used to strobe addresses A16–A31 into external latches. (A16 –A31 are the

fixed addresses stored in RSAR0, RSAR1). ADS1

will remain at TRI-STATE until BACK is

received. 16-BIT MODE: If LAS is not set in the Data Configuration Register, this line is programmed as

PRQ and is used for Remote DMA Transfers. The SNIC initiates a single remote DMA read or write operation by asserting this pin. In this mode PRQ will be a standard logic output.

Note: This line will power up as TRI-STATE until the Data Configuration Register is programmed.

granted the bus to the SNIC. If immediate bus access is desired, BREQ should be tied to BACK.

Tying BACK to V

will result in a deadlock.

This signal is automatically generated when the FIFO needs servicing.

transmitted or received by the SNIC until STA bit is set. Affects Command Register, Interrupt Mask Register, Data Configuration Register and Transmit Configuration Register. The SNIC will execute reset within 10 BSCK cycles and TXC cycles.

completion of DMA transfers. The interrupt is cleared by writing to the ISR (Interrupt Service Register). All interrupts are maskable.

the external latch. The SNIC will begin a write cycle to place the data in local memory.

O TRANSMIT OUTPUT: Differential driver which sends the encoded data to the transceiver. The

outputs are source followers which require 270X pulldown resistors.

operation.

When low, Transmit

is positive with respect to Transmitbin the idle state, at the transformer’s

primary.

oscillator using X1 and GND/X2 if certain precautions are taken. Contact National Semiconductor for more information.

module to be tested independently of the SNIC module.

I RECEIVE INPUT: Differential receive input pair from the transceiver.

I COLLISION INPUT: Differential collision pair input from the transceiver.

Pin Description (Continued)

Pin No Pin Name I/O Description

POWER SUPPLY PINS

21, 48, V

53, 55

20, 33, 49 GND DIGITAL NEGATIVE (GROUND) SUPPLY PINS: It is suggested that a decoupling capacitor be

54, 66

59 V

64 GND AUI RECEIVE GROUND: Ground pin for AUI receiver.

45 V

44 GND AUI TRANSMIT GROUND: Ground pin for AUI transmitter

58 V

57 GND VCO GROUND PIN: Care should be taken to reduce noise on this pin as it is the ground to the

NO CONNECTION

1, 18, NC NO CONNECTION: Do not connect to these pins.

35, 52

DIGITAL POSITIVE 5V SUPPLY PINS:

connected between the V

AUI RECEIVE 5V SUPPLY: Power pin supplies 5V to the AUI receiver.

AUI TRANSMIT 5V SUPPLY: Power pin supplies 5V to the AUI transmitter.

VCO 5V SUPPLY: Care should be taken to reduce noise on this pin as it supplies 5V to the

ENDEC’s Phase Lock Loop.

and GND pins.

3.0 Block Diagram

FIGURE 1

TL/F/10469– 3

4.0 Functional Description (Refer to

Figure 1

ENCODER/DECODER (ENDEC) MODULE

The ENDEC consists of four main logical blocks:

a) The Manchester encoder accepts NRZ data from the

controller, encodes the data to Manchester, and transmits it differentially to the transceiver, through the differential transmit driver.

b) The Manchester decoder receives Manchester data from

the transceiver, converts it to NRZ data and clock pulses, and sends it to the controller.

c) The collision translator indicates to the controller the

presence of a valid 10 MHz collision signal to the PLL.

MANCHESTER ENCODER AND DIFFERENTIAL DRIVER

The differential transmit pair, on the secondary of the employed transformer, drives up to 50 meters of twisted pair AUI cable. These outputs are source followers which require two 270X pull-down resistors to ground.

The DP83901A allows both half-step and full-step to be compatible with Ethernet and IEEE 802.3. With the SEL pin low (for Ethernet I). Transmit

Transmit Transmit provides zero differential voltage to operate with transformer coupled loads.

MANCHESTER DECODER

The decoder consists of a differential receiver and a PLL to separate a Manchester decoded data stream into internal clock signals and data. The differential input must be externally terminated with two 39X resistors connected in series if the standard 78X transceiver drop cable is used, in thin Ethernet applications, these resistors are optional. To prevent noise from falsely triggering the decoder, a squelch circuit at the input rejects signals with levels less than

175 mV. Signals more negative thanb300 mV and a duration greater than 30 ns are decoded. Data becomes valid typically within 5 bit times. The DP83901A may tolerate bit jitter up to 18 ns in the received data. The decoder detects the end of a frame when no more mid-bit transitions are detected.

COLLISION TRANSLATOR

When the Ethernet transceiver (DP8392 CTI) detects a collision, it generates a 10 MHz signal to the differential collision inputs (CD tected active, the DP83901A uses this signal to back off its current transmission and reschedule another one.

The collision differential inputs are terminated the same way as the differential receive inputs. The squelch circuitry is also similar, rejecting pulses with levels less than

during idle; with SEL high (for IEEE 802.3),

and Transmitbare equal in the idle state. This

) of the DP83901A. When these inputs are de-

is positive with respect to

175 mV.

)

NIC (Media Access Control) MODULE

RECEIVE DESERIALIZER

The Receive Deserializer is activated when the input signal Carrier Sense is asserted to allow incoming bits to be shifted into the shift register by the receive clock. The serial receive data is also routed to the CRC generator/checker. The Receive Deserializer includes a synch detector which detects the SFD (Start of Frame Delimiter) to establish where byte boundaries within the serial bit stream are located. After every eight receive clocks, the byte wide data is transferred to the 16-byte FIFO and the Receive Byte Count is incremented. The first six bytes after the SFD are checked for valid comparison by the Address Recognition Logic. If the Address Recognition Logic does not recognize the packet, the FIFO is cleared.

CRC GENERATOR/CHECKER

During transmission, the CRC logic generates a local CRC field for the transmitted bit sequence. The CRC encodes all fields after the SFD. The CRC is shifted out MSB first following the last transmit byte. During reception the CRC logic generates a CRC field from the incoming packet. This local CRC is serially compared to the incoming CRC appended to the end of the packet by the transmitting node. If the local and received CRC match, a specific pattern will be generated and decoded to indicate no data errors. Transmission errors result in different pattern and are detected, resulting in rejection of a packet (if so programmed).

TRANSMIT SERIALIZER

The Transmit Serializer reads parallel data from the FIFO and serializes it for transmission. The serializer is clocked by the transmit clock generated internally. The serial data is also shifted into the CRC generator/checker. At the beginning of each transmission, the Preamble and Synch Generator append 62 bits of 1,0 preamble and a 1,1 synch pattern. After the last data byte of the packet has been serialized the 32-bit FCS field is shifted directly out of the CRC generator. In the event of a collision the Preamble and Synch generator is used to generate a 32-bit JAM pattern of all 1’s.

ADDRESS RECOGNITION LOGIC

The address recognition logic compares the Destination Address Field (first 6 bytes of the received packet) to the Physical address registers stored in the Address Register Array. If any one of the six bytes does not match the pre-programmed physical address, the Protocol Control Logic rejects the packet. All multicast destination addresses are filtered using a hashing technique. (See register description.) If the multicast address indexes a bit that has been set in the filter bit array of the Multicast Address Register Array the packet is accepted, otherwise it is rejected by the Proto-

4.0 Functional Description (Continued)

col Control Logic. Each destination address is also checked for all 1’s which is the reserved broadcast address.

FIFO AND BUS OPERATIONS

Overview

To accommodate the different rates at which data comes from (or goes to) the network and goes to (or comes from) the system memory, the SNIC contains a 16-byte FIFO for buffering data between the media. The FIFO threshold is programmable, allowing filling (or emptying) the FIFO at different rates. When the FIFO has filled to its programmed threshold, the local DMA channel transfers these bytes (or words) into local memory. It is crucial that the local DMA is given access to the bus within a minimum bus latency time; otherwise a FIFO underrun (or overrun) occurs.

FIFO underruns or overruns are caused by two conditions: (1) the bus latency is so long that the FIFO has filled (or emptied) from the network before the local DMA has serviced the FIFO and (2) the bus latency has slowed the throughput of the local DMA to point where it is slower than the network data rate (10 Mbit/sec). This second condition is also dependent upon DMA clock and word width (byte wide or word wide). The worst case condition ultimately limits the overall bus latency which the SNIC can tolerate.

Beginning of Receive

At the beginning or reception, the SNIC stores entire Address field of each incoming packet in the FIFO to determine whether the packet matches its Physical Address Registers or maps to one of its Multicast Registers. This causes the FIFO to accumulate 8 bytes. Furthermore, there are some synchronization delays in the DMA PLA. Thus, the actual time that BREQ is asserted from the time the Start of Frame Delimiter (SFD) is detected is 7.8 ms. This operation affects the bus latencies at 2 and 4-byte thresholds during the first receive BREQ since the FIFO must be filled to 8 bytes (or 4 words) before issuing a BREQ.

End of Receive

When the end of a packet is detected by the ENDEC module, the SNIC enters its end of packet processing sequence, emptying its FIFO and writing the status information at the beginning of the packet. The SNIC holds onto the bus for the entire sequence. The longest time BREQ may be extended occurs when a packet ends just as the SNIC performs its last FIFO burst. The SNIC, in this case, performs a programmed burst transfer followed by flushing the remaining bytes in the FIFO, and completed by writing the header information to memory. The following steps occur during this sequence.

1. SNIC issues BREQ because the FIFO threshold has been reached.

2. During the burst, packet ends, resulting in BREQ extended.

3. SNIC flushes remaining bytes from FIFO.

4. SNIC performs internal processing to prepare for writing the header.

5. SNIC writes 4-byte (2-word) header.

6. SNIC de-asserts BREQ.

FIFO Threshold Detection

To assure that no overwriting of data in the FIFO, the FIFO logic flags a FIFO overrun as the 13th byte is written into the FIFO, effectively shortening the FIFO to 13 bytes. The FIFO logic also operates differently in Byte Mode and in Word Mode. In Byte Mode, a threshold is indicated when the n byte has entered the FIFO; thus, with an 8-byte threshold, the SNIC issues Bus Request (BREQ) when the 9th byte has entered the FIFO. For Word Mode, BREQ is not generated until the n a 4 word threshold (equivalent to 8-byte threshold), BREQ is issued when the 10th byte has entered the FIFO.

Beginning of Transmit

Before transmitting, the SNIC performs a prefetch from memory to load the FIFO. The number of bytes prefetched is the programmed FIFO threshold. The next BREQ is not issued until after the SNIC actually begins transmitting data, i.e., after SFD.

Reading the FIFO

During normal operation, the FIFO must not be read. The SNIC will not issue an ACKnowledge back to the CPU if the FIFO is read. The FIFO should only be read during loopback diagnostics.

PROTOCOL PLA

The protocol PLA is responsible for implementing the IEEE

802.3 protocol, including collision recovery with random

backoff. The Protocol PLA also formats packets during transmission and strips preamble and synch during reception.

DMA AND BUFFER CONTROL LOGIC

The DMA and Buffer Control Logic is used to control two 16-bit DMA channels. During reception, the local DMA stores packets in a receive buffer ring, located in buffer memory. During transmission the Local DMA uses programmed pointer and length registers to transfer a packet from local buffer memory to the FIFO. A second DMA channel is used as a slave DMA to transfer data between the local buffer memory and the host system. The Local DMA and Remote DMA are internally arbitrated, with the Local DMA channel having highest priority. Both DMA channels use a common external bus clock to generate all required bus timing. External arbitration is performed with a standard bus request, bus acknowledge handshake protocol.

2 bytes have entered the FIFO. Thus, with

5.0 Transmit/Receive Packet Encapsulation/Decapsulation

A standard IEEE 802.3 packet consists of the following fields: preamble, Start of Frame Delimiter (SFD), destination address, source address, length, data, and Frame Check Sequence (FCS). The typical format is shown in

Figure 2.

The packets are Manchester encoded and decoded by the ENDEC module and transferred serially to the NIC module using NRZ data with a clock. All fields are of fixed length except for the data field. The SNIC generates and appends the preamble, SFD and FCS field during transmission. The Preamble and SFD fields are stripped during reception. (The CRC is passed through to buffer memory during reception.)

PREAMBLE AND START OF FRAME DELIMITER (SFD)

The Manchester encoded alternating 1,0 preamble field is used by the ENDEC to acquire bit synchronization with an incoming packet. When transmitted each packet contains 62 bits of alternating 1,0 preamble. Some of this preamble will be lost as the packet travels through the network. The preamble field is stripped by the NIC module. Byte alignment is performed with the Start of Frame Delimiter (SFD) pattern which consists of two consecutive 1’s. The SNIC does not treat the SFD pattern as a byte, it detects only the two bit pattern. This allows any preceding preamble within the SFD to be used for phase locking.

DESTINATION ADDRESS

The destination address indicates the destination of the packet on the network and is used to filter unwanted packets from reaching a node. There are three types of address formats supported by the SNIC: physical, multicast and broadcast. The physical address is a unique address that corresponds only to a single node. All physical addresses have an MSB of ‘‘0’’. These addresses are compared to the internally stored physical address registers. Each bit in the destination address must match in order for the SNIC to accept the packet. Multicast addresses begin with an MSB

of ‘‘1’’. The SNIC filters multicast addresses using a standard hashing algorithm that maps all multicast addresses into a 6-bit value. This 6-bit value indexes a 64-bit array that filters the value. If the address consists of all 1’s it is a broadcast address, indicating that the packet is intended for all nodes. A promiscuous mode allows reception of all packets: the destination address is not required to match any filters. Physical, broadcast, multicast, and promiscuous address modes can be selected.

SOURCE ADDRESS

The source address is the physical address of the node that sent the packet. Source addresses cannot be multicast or broadcast addresses. This field is simply passed to buffer memory.

LENGTH FIELD

The 2-byte length field indicates the number of bytes that are contained in the data field of the packet. This field is not interpreted by the SNIC.

DATA FIELD

The data field consists of anywhere from 46 to 1500 bytes. Messages longer than 1500 bytes need to be broken into multiple packets. Messages shorter than 46 bytes will require appending a pad to bring the data field to the minimum length of 46 bytes. If the data field is padded, the number of valid data bytes is indicated in the length field. The SNIC

does not strip or append pad bytes for short packets, or check for oversize packets.

FCS FIELD

The Frame Check Sequence (FCS) is a 32-bit CRC field calculated and appended to a packet during transmission to allow detection of errors when a packet is received. During reception, error free packets result in a specific pattern in the CRC generator. Packets with improper CRC will be rejected. The AUTODIN II (X

polynomial is used for the CRC calculations.

FIGURE 2

TL/F/10469– 5

6.0 Direct Memory Access Control (DMA)

The DMA capabilities of the SNIC greatly simplify the use of the DP83901A in typical configurations. The local DMA channel transfers data between the FIFO and memory. On transmission, the packet is DMA’d from memory to the FIFO in bursts. Should a collision occur (up to 15 times), the packet is retransmitted with no processor intervention. On reception, packets are DMAed from the FIFO to the receive buffer ring (as explained below).

A remote DMA channel is also provided on the SNIC to accomplish transfers between a buffer memory and system memory. The two DMA channels can alternatively be combined to form a single 32-bit address with 8- or 16-bit data.

DUAL DMA CONFIGURATION

An example configuration using both the local and remote DMA channels is shown below. Network activity is isolated

Dual Bus System

on a local bus, where the SNIC’s local DMA channel performs burst transfers between the buffer memory and the SNIC’s FIFO. The Remote DMA transfers data between the buffer memory and the host memory via a bidirectional I/O port. The Remote DMA provides local addressing capability and is used as a slave DMA by the host. Host side addressing must be provided by a host DMA or the CPU. The SNIC allows Local and Remote DMA operations to be interleaved.

SINGLE CHANNEL DMA OPERATION

If desirable, the two DMA channels can be combined to provide a 32-bit DMA address. The upper 16 bits of the 32-bit address are static and are used to point to a 64 kbyte (or 32k word) page of memory where packets are to be received and transmitted.

TL/F/10469– 6

7.0 Packet Reception

The Local DMA receive channel uses a Buffer Ring Structure comprised of a series of contiguous fixed length 256-byte (128 word) buffers for storage of received packets. The location of the Receive Buffer Ring is programmed in two registers, a Page Start and a Page Stop Register. Ethernet packets consist of a distribution of shorter link control packets and longer data packets, the 256-byte buffer length provides a good compromise between short packets and longer packets to most efficiently use memory. In addition these buffers provide memory resources for storage of back-to-back packets in loaded networks. The assignment of buffers for storing packets is controlled by Buffer Management Logic in the SNIC. The Buffer Management Logic

NIC Receive Buffer Ring

provides three basic functions: linking receive buffers for long packets, recovery of buffers when a packet is rejected, and recirculation of buffer pages that have been read by the host.

At initialization, a portion of the 64 kbyte (or 32k word) address space is reserved for the receive buffer ring. Two 8-bit registers, The Page Start Address Register (PSTART) and the Page Stop Address Register (PSTOP) define the physical boundaries of where the buffers reside. The SNIC treats the list of buffers as a logical ring; whenever the DMA address reaches the Page Stop Address, the DMA is reset to the Page Start Address.

TL/F/10469– 7

7.0 Packet Reception (Continued)

INITIALIZATION OF THE BUFFER RING

Two static registers and two working registers control the operation of the Buffer Ring. These are the Page Start Register, Page Stop Register (both described previously), the Current Page Register and the Boundary Pointer Register. The Current Page Register points to the first buffer used to store a packet and is used to restore the DMA for writing status to the Buffer Ring or for restoring the DMA address in the event of a Runt packet, a CRC, or Frame Alignment error. The Boundary Register points to the first packet in the Ring not yet read by the host. If the local DMA address ever reaches the Boundary, reception is aborted. The Boundary Pointer is also used to initialize the Remote DMA for removing a packet and is advanced when a packet is removed. A

Buffer Ring at Initialization

simple analogy to remember the function of these registers is that the Current Page Register acts as a Write Pointer and the Boundary Pointer acts as a Read Pointer.

Note: At initialization, the Page Start Register value should be loaded into

both the Current Page Register and the Boundary Pointer Register.

Note: The Page Start Register must not be initialized to 00H.

BEGINNING OF RECEPTION

When the first packet begins arriving the SNIC begins storing the packet at the location pointed to by the Current Page Register. An offset of 4 bytes is saved in this first buffer to allow room for storing receive status corresponding to this packet.

Received Packet Enters the Buffer Pages

TL/F/10469– 8

TL/F/10469– 9

7.0 Packet Reception (Continued)

LINKING RECEIVE BUFFER PAGES

If the length of the packet exhausts the first 256-byte buffer, the DMA performs a forward link to the next buffer to store the remainder of the packet. For a maximal length packet the buffer logic will link six buffers to store the entire packet. Buffers cannot be skipped when linking, a packet will always be stored in contiguous buffers. Before the next buffer can be linked, the Buffer Management Logic performs two comparisons. The first comparison tests for equality between the DMA address of the next buffer and the contents of the Page Stop Register. If the buffer address equals the Page Stop Register, the buffer management logic will restore the DMA to the first buffer in the Receive Buffer Ring value programmed in the Page Start Address Register. The second comparison tests for equality between the DMA ad-

Linking Receive Buffer Pages

dress of the next buffer address and the contents of the Boundary Pointer Register. If the two values are equal the reception is aborted. The Boundary Pointer Register can be used to protect against overwriting any area in the receive buffer ring that has not yet been read. When linking buffers, buffer management will never cross this pointer, effectively avoiding any overwrites. If the buffer address does not match either the Boundary Pointer or Page Stop Address, the link to the next buffer is performed.

Linking Buffers

Before the DMA can enter the next contiguous 256-byte buffer, the address is checked for equality to PSTOP and to the Boundary Pointer. If neither are reached, the DMA is allowed to use the next buffer.

1) Check foreto PSTOP

2) Check for

to Boundary

TL/F/10469– 10

7.0 Packet Reception (Continued)

Buffer Ring Overflow

If the Buffer Ring has been filled and the DMA reaches the Boundary Pointer Address, reception of the incoming packet will be aborted by the SNIC. Thus, the packets previously received and still contained in the Ring will not be destroyed.

In heavily loaded network which cause overflows of the Receive Buffer Ring, the SNIC may disable the local DMA and suspend further receptions even if the Boundary register is advanced beyond the Current register. To guarantee this will not happen, a software reset must be issued during all Receive Buffer Ring overflows (indicated by the OVW bit in the Interrupt Status Register). The following procedure is required to recover from a Receiver Buffer Ring Overflow.

If this routine is not adhered to, the SNIC may act in an unpredictable manner. It should also be noted that it is not permissible to service an overflow interrupt by continuing to empty packets from the receive buffer without implementing the prescribed overflow routine. A flow chart of the SNIC’s overflow routine can be found on the next page.

Note: It is necessary to define a variable in the driver, which will be called

‘‘Resend’’.

1. Read and store the value of the TXP bit in the SNIC’s Command Register.

2. Issue the STOP command to the SNIC. This is accomplished by setting the STP bit in the SNIC’s Command Register. Writing 21H to the Command Register will stop the SNIC.

3. Wait for at least 1.6 ms. Since the SNIC will complete any transmission or reception that is in progress, it is necessary to time out for the maximum possible duration of an Ethernet transmission or reception. By waiting

1.6 ms this is achieved with some guard band added. Previously, it was recommended that the RST bit of the Interrupt Status Register be polled to insure that the pending transmission or reception is completed. This bit is not a reliable indicator and subsequently should be ignored.

4. Clear the SNIC’s Remote Byte Count registers (RBCR0 and RBCR1).

5. Read the stored value of the TXP bit from step 1, above.

If this value is a 0, set the ‘‘Resend’’ variable toa0and jump to step 6.

If this value is a 1, read the SNIC’s Interrupt Status Register. If either the Packet Transmitted bit (PTX) or Trans-

Received Packet Aborted If It Hits Boundary

mit Error bit (TXE) is set to a 1, set the ‘‘Resend’’ variable to a 0 and jump to step 6. If neither of these bits is set, placea1inthe‘‘Resend’’ variable and jump to step

This step determines if there was a transmission in progress when the stop command was issued in step 2. If there was a transmission in progress, the SNIC’s ISR is read to determine whether or not the packet was recognized by the SNIC. If neither the PTX nor TXE bit was set, then the packet will essentially be lost and re-transmitted only after a time-out takes place in the upper level software. By determining that the packet was lost at the driver level, a transmit command can be reissued to the SNIC once the overflow routine is completed (as in step 11). Also, it is possible for the SNIC to defer indefinitely, when it is stopped on a busy network. Step 5 also alleviates this problem. Step 5 is essential and should not be omitted from the overflow routine, in order for the SNIC to operate correctly.

6. Place the SNIC in either mode 1 or mode 2 loopback. This can be accomplished by setting bits D2 and D1, of the Transmit Configuration Register, to ‘‘0,1’’ or ‘‘1,0’’, respectively.

7. Issue the START command to the SNIC. This can be accomplished by writing 22H to the Command Register. This is necessary to activate the SNIC’s Remote DMA channel.

8. Remove one or more packets from the receive buffer ring.

9. Reset the overwrite warning (OVW, overflow) bit in the Interrupt Status Register.

10. Take the SNIC out of loopback. This is done by writing the Transmit Configuration Register with the value it contains during normal operation. (Bits D2 and D1 should both be programmed to 0.)

11. If the ‘‘Resend’’ variable is set to a 1, reset the ‘‘Resend’’ variable and reissue the transmit command. This is done by writing a value of 26H to the Command Register. If the ‘‘Resend’’ variable is 0, nothing needs to be done.

Note 1: If Remote DMA is not being used, the SNIC does not need to be started before packets can be removed from the receive buffer ring. Hence, step 8 could be done before step 7.

Note 2: When the SNIC is in STOP mode, the Missed Talley Counter is disabled.

TL/F/10469– 11

7.0 Packet Reception (Continued)

Overflow Routine Flow Chart

TL/F/10469– 52

7.0 Packet Reception (Continued)

Enabling the SNIC On An Active Network

After the SNIC has been initialized the procedure for disabling and then re-enabling the SNIC on the network is similar to handling Receive Buffer Ring overflow as described previously.

1. Program Command Register for page 0 (Command

2. Initialize Data Configuration Register (DCR)

3. Clear Remote Byte Count Registers (RBCR0, RBCR1)

4. Initialize Receive Configuration Register (RCR)

5. Place the SNIC in LOOPBACK mode 1 or 2 (Transmit

6. Initialize Receive Buffer Ring: Boundary Pointer

7. Clear Interrupt Status Register (ISR) by writing 0FFH to

8. Initialize Interrupt Mask Register (IMR)

9. Program Command Register for page 1 (Command

Configuration Register

(BNDRY), Page Start (PSTART), and Page Stop (PSTOP)

it.

i) Initialize Physical Address Registers (PAR0 –PAR5)

ii) Initialize Multicast Address Registers (MAR0 –MAR7)

iii) Initialize CURRent pointer

21H)

02H or 04H)

61H)

Termination of Received PacketÐPacket Accepted

10) Put SNIC in START mode (Command Register The local receive DMA is still not active since the SNIC is in LOOPBACK.

11) Initialize the Transmit Configuration for the intended value. The SNIC is now ready for transmission and reception.

END OF PACKET OPERATIONS

At the end of the packet the SNIC determines whether the received packet is to be accepted or rejected. It either branches to a routine to store the Buffer Header or to another routine that recovers the buffers used to store the packet.

SUCCESSFUL RECEPTION

If the packet is successfully received, the DMA is restored to the first buffer used to store the packet (pointed to by the Current Page Register). The DMA then stores the Receive Status, a Pointer to where the next packet will be stored (Buffer 4) and the number of received bytes. Note that the remaining bytes in the last buffer are discarded and reception of the next packet begins on the next empty 256-byte buffer boundary. The Current Page Register is then initialized to the next available buffer in the Buffer Ring. (The location of the next buffer had been previously calculated and temporarily stored in an internal scratchpad register.)

22H).

TL/F/10469– 12

7.0 Packet Reception (Continued)

BUFFER RECOVERY FOR REJECTED PACKETS

If the packet is a runt packet or contains CRC or Frame Alignment errors, it is rejected. The buffer management logic resets the DMA back to the first buffer page used to store the packet (pointed to by CURR), recovering all buffers that had been used to store the rejected packet. This operation will not be performed if the SNIC is programmed to accept either runt packets or packets with CRC or Frame Alignment

Termination of Receive PacketÐPacket Reject

errors. The received CRC is always stored in buffer memory after the last byte of received data for the packet.

Error Recovery

If the packet is rejected as shown, the DMA is restored by the SNIC by reprogramming the DMA starting address pointed to by the Current Page Register.

TL/F/10469– 13

7.0 Packet Reception (Continued)

REMOVING PACKETS FROM THE RING

Packets are removed from the ring using the Remote DMA or an external device. When using the Remote DMA the Send Packet command can be used. This programs the Remote DMA to automatically remove the received packet pointed to by the Boundary Pointer. At the end of the transfer, the SNIC moves the Boundary Pointer, freeing additional buffers for reception. The Boundary Pointer can also be moved manually by programming the Boundary Register.

STORAGE FORMAT FOR RECEIVED PACKETS

The following diagrams describe the format for how received packets are placed into memory by the local DMA channel. These modes are selected in the Data Configuration Register.

AD15 AD8 AD7 AD0

Next Packet Pointer Receive Status

Receive Byte Count 1 Receive Byte Count 0

Byte 2 Byte 1

BOSe0, WTSe1 in Data Configuration Register. This format is used with Series 32xxx, or 808xx processors.

1st Received Packet Removed by Remote DMA

AD15 AD8 AD7 AD0

Next Packet Pointer Receive Status

Receive Byte Count 0 Receive Byte Count 1

Byte 1 Byte 2

BOSe1, WTSe1 in Data Configuration Register. This format is used with 680x0 type processors. (Note: The Receive Count ordering remains the same for BOS

0or1.)

Receive Status

Next Packet Pointer

Receive Byte Count 0

Receive Byte Count 1

Byte 0

Byte 1

BOSe0, WTSe0 in Data Configuration Register. This format is used with general 8-bit processors.

TL/F/10469– 14

8.0 Packet Transmission

The Local DMA is also used during transmission of a packet. Three registers control the DMA transfer during transmission, a Transmit Page Start Address Register (TPSR) and the Transmit Byte Count Registers (TBCR0, 1). When the SNIC receives a command to transmit the packet pointed to by these registers, buffer memory data will be moved into the FIFO as required during transmission. The SNIC will generate and append the preamble, synch and CRC fields.

General Transmit Packet Format

Transmit Destination Address 6 Bytes

Byte Source Address 6 Bytes

Count Type/Length 2 Bytes

TBCR0, 1

Data

Pad (If Datak46 Bytes)

TRANSMIT PACKET ASSEMBLY

The SNIC requires a contiguous assembled packet with the format shown. The transmit byte count includes the Destination Address, Source Address, Length Field and Data. It does not include preamble and CRC. When transmitting data smaller than 46 bytes, the packet must be padded to a minimum size of 64 bytes. The programmer is responsible for adding and stripping pad bytes.

TRANSMISSION

Prior to transmission, the TPSR (Transmit Page Start Register) and TBCR0, TBCR1 (Transmit Byte Count Registers) must be initialized. To initiate transmission of the packet the TXP bit in the Command Register is set. The Transmit Status Register (TSR) is cleared and the SNIC begins to prefetch transmit data from memory (unless the SNIC is currently receiving). If the interframe gap has timed out the SNIC will begin transmission.

CONDITIONS REQUIRED TO BEGIN TRANSMISSION

In order to transmit a packet, the following three conditions must be met:

1. The Interframe Gap Timer has timed out the first 6.4 ms of the Interframe Gap.

2. At least one byte has entered the FIFO. (This indicates that the burst transfer has been started.)

3. If a collision had been detected then before transmission the packet time must have timed out.

In typical systems the SNIC prefetchs the first burst of bytes before the 6.4 m s timer expires. The time during which SNIC transmits preamble can also be used to load the FIFO.

Note: If carrier sense is asserted before a byte has been loaded into the

FIFO, the SNIC will become a receiver.

COLLISION RECOVERY

During transmission, the Buffer Management logic monitors the transmit circuitry to determine if a collision has occurred. If a collision is detected, the Buffer Management logic will reset the FIFO and restore the Transmit DMA pointers for retransmission of the packet. The COL bit will be set in the TSR and the NCR (Number of Collisions Register) will be incremented. If 15 retransmissions each result in a collision the transmission will be aborted and the ABT bit in the TSR will be set.

Note: NCR reads as zeroes if excessive collisions are encountered.

46 Bytes

TRANSMIT PACKET ASSEMBLY FORMAT

The following diagrams describe the format for how packets must be assembled prior to transmission for different byte ordering schemes. The various formats are selected in the Data Configuration Register.

D15 D8 D7 D0

Destination Address 1 Destination Address 0

Destination Address 3 Destination Address 2

Destination Address 5 Destination Address 4

Source Address 1 Source Address 0

Source Address 3 Source Address 2

Source Address 5 Source Address 4

Type/Length 1 Type/Length 0

Data 1 Data 0

BOSe0, WTSe1 in Data Configuration Register.

This format is used with Series 32xxx, or 808xx processors.

D15 D8 D7 D0

Destination Address 0 Destination Address 1

Destination Address 2 Destination Address 3

Destination Address 4 Destination Address 5

Source Address 0 Source Address 1

Source Address 2 Source Address 3

Source Address 4 Source Address 5

Type/Length 0 Type/Length 1

Data 0 Data 1

BOSe1, WTSe1 in Data Configuration Register.

This format is used with 680x0 type processors.

D1 D0

Destination Address 0

Destination Address 1

Destination Address 2

Destination Address 3

Destination Address 4

Destination Address 5

Source Address 0

Source Address 1

Source Address 2

Source Address 3

Source Address 4

Source Address 5

BOSe0, WTSe0 in Data Configuration Register.

This format is used with general 8-bit processors.

Note: All examples above will result in a transmission of a packet in order of

DA0, DA1, DA3 . . . bits within each byte will be transmitted least significant bit first.

Destination Address.

9.0 Remote DMA

The Remote DMA channel is used to both assemble packets for transmission, and to remove received packets from the Receive Buffer Ring. It may also be used as a general purpose slave DMA channel for moving blocks of data or commands between host memory and local buffer memory. There are three modes of operation, Remote Write, Remote Read, or Send Packet.

Two register pairs are used to control the Remote DMA, a Remote Start Address (RSAR0, RSAR1) and a Remote Byte Count (RBCR0, RBCR1) register pair. The Start Address Register pair points to the beginning of the block to be moved while the Byte Count Register pair is used to indicate the number of bytes to be transferred. Full handshake logic is provided to move data between local buffer memory and a bidirectional I/O port.

REMOTE WRITE

A Remote Write transfer is used to move a block of data from the host into local buffer memory. The Remote DMA will read data from the I/O port and sequentially write it to local buffer memory beginning at the Remote Start Address. The DMA Address will be incremented and the Byte Counter will be decremented after each transfer. The DMA is terminated when the Remote Byte Count Register reaches a count of zero.

REMOTE READ

A Remote Read transfer is used to move a block of data from local buffer memory to the host. The Remote DMA will

Remote DMA Autoinitialization from Buffer Ring

sequentially read data from the local buffer memory, beginning at the Remote Start Address, and write data to the I/O port. The DMA Address will be incremented and the Byte Counter will be decremented after each transfer. The DMA is terminated when the Remote Byte Count Register reaches zero.

SEND PACKET COMMAND

The Remote DMA channel can be automatically initialized to transfer a single packet from the Receive Buffer Ring. The CPU begins this transfer by issuing a ‘‘Send Packet’’ Command. The DMA will be initialized to the value of the Boundary Pointer Register and the Remote Byte Count Register pair (RBCR0, RBCR1) will be initialized to the value of the Receive Byte Count fields found in the Buffer Header of each packet. After the data is transferred, the Boundary Pointer is advanced to allow the buffers to be used for new receive packets. The Remote Read will terminate when the Byte Count equals zero. The Remote DMA is then prepared to read the next packet from the Receive Buffer Ring. If the DMA pointer crosses the Page Stop Register, it is reset to the Page Start Address. This allows the Remote DMA to remove packets that have wrapped around to the top of the Receive Buffer Ring.

Note 1: In order for the SNIC to correctly execute the Send Packet Com-

mand, the upper Remote Byte Count Register (RBCR1) must first be loaded with 0FH.

Note 2: The Send Packet command cannot be used with 680x0 type proc-

essors.

TL/F/10469– 15

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