NSC DP83858VF Datasheet
DP83858
100 Mb/s TX/T4 Repeater Interface Controller (100RIC8™)
DP83858 100 Mb/s TX/T4 Repeater Interface Controller (100RIC8™)
June 1998
General Description
The DP83858 100 Mb/s TX/T4 Repeater Interface Controller, known as 100RIC8, is designed specifically to meet the
needs of today's high speed Ethernet networking systems.
The DP83858 is fully compatible with the IEEE 802.3
repeater's clause 27. This device is targeted at low port
count managed and unmanaged repeater applications.
The DP83858 supports up to eight 100 Mb/s links with its
network interface ports. The 100RIC8 can be configured to
be used with either 100BASE-TX or 100BASE-T4 PHY
technologies. Larger repeaters may be constructed by
cascading DP83858s together using the built-in Inter
Repeater bus.
In conjunction with a DP83856 100 Mb/s Repeater Information Base device, a DP83858 based repeater becomes
a managed entity that is compatible with IEEE 802.3u
(clause 30), collecting and providing an easy interface to
all the required network statistics.
Features
■ IEEE 802.3u repeater and management compatible
System Diagram
DP83858
100 Mb/s
Repeater Interface Controller
(100RIC8)
■ Supports Class II TX translational repeater and Class I
T4 repeater
■ Supports 8 network connections (ports)
■ Up to 31 repeater chips cascadable for larger hub appli-
cations--may use DP83858 in conjunction with DP83850
100RIC (12 ports per chip)
■ Separate jabber and partition state machines for each
port
■ Management interface to DP83856 allows all repeater
MIBs to be maintained
■ Large per-port management counters - reduces management CPU overhead
■ On-chip elasticity buffer for PHY signal re-timing to the
DP83858 clock source
■ Serial register interface - reduces cost
■ Physical layer device control/status access available via
the serial register interface
■ Detects repeater identification errors
■ 132 pin PQFP package
DP83856
100 Mb/s
Repeater Information Base
(100RIB)
Inter Repeater Bus
Management Bus
RX Enable [7..0]
MII
DP83840A
100 PHY
#0
DP83223
100BASE-X
100Mb/s
Transceiver
Ethernet
Ports
Note: The above system diagram depicts the repeater configured in 100BASE-TX mode.
FAST® is a registered trademark of Fairchild Semiconductor Corporation.
TRI-STATE
100RIC
1998 National Semiconductor Corporation
®
is a registered trademark of National Semiconductor Corporation.
™
is a trademark of National Semiconductor Corporation.
Port 0
DP83840A
100 PHY
#1
DP83223
100BASE-X
Transceiver
Port 1
DP83840A
100 PHY
#2
DP83223
100BASE-X
Transceiver
Port 2
(IR_COL, IR_DV)
DP83840A
100 PHY
DP83223
100BASE-X
Transceiver
Port 7
#7
Statistics
(TXD[3:0], TX_ER, TX_RDY)
SRAM
Management
Program
Memory
Management
I/O Devices
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CPU
Block Diagram
EE_CK
EE_CS
EE_DI
EE_DO
EEPROM INTERFACE
LCK
/RST
EEPROM
ACCESS LOGIC
Other Registers
MANAGEMENT & INTER REPEATER BUS INTERFACE
/M_ER
M_CK
/M_DV
MD[3:0]
RID_ER
RID[4:0]
LOGIC
MANAGEMENT
Active Port #
IRD_ODIR
IR_VECT[4:0]
LOGIC
DISTRIBUTED
ARBITRATION
State
/ACTIVEO
/IR_COL_IN
/IR_COL_OUT
SELECT/COL.
DETECT LOGIC
IRD[3:0], /IRD_ER, IRD_CK, /IRD_V
100RIC8
DP83858
MUX
REGISTER
RDIR
RDIO
RDC
/SDV
GRDIO
BRDC
PART[5:0]
ACCESS LOGIC
SERIAL REGISTER
SERIAL REGISTER/MANAGEMENT INTERFACE
COUNTERS
LATE EVENT
PER PORT
CRS[7:0]
COUNTERS
SHORT EVENT
PER PORT
STATE MACHINES
JABBER CONTROL
& AUTO-PARTITION
RXD[3:0], RX_ER, RXC, RX_DV
REGISTERS
CONFIG./STATUS
COUNTERS
COL & PART
ACTIVITY[7:0]
TXD[3:0], TX_ER
TXE[7:0]
RXE[7:0]
CRS[7:0]
STATE
MACHINE
REPEATER
PORT_COL[7:0]
TXE
CONTROL
TX_RDY
TXE[7:0]
CRS[7:0]
RXE[7:0]
BUFFER
ELASTICITY
EB_ERROR
Jam
Pattern
RXD[3:0],RX_ER, RXC, RX_DV
TXD[3:0], TX_ER
RXE[0]
CRS[0]
TXE[0]
#0
PHY
RXE[1]
CRS[1]
TXE[1]
#1
PHY
PHYSICAL LAYER INTERFACE
2
CRS[7]
RXE[7]
TXE[7]
#7
PHY
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1.0 Pin Connection Diagram
1.1 Pin Table
2.0 Pin Description
2.1 Physical Layer Interface
2.2 Inter Repeater and Management Bus Interface
2.3 EEPROM Interface
2.4 Miscellaneous
2.5 Pin Type Designation
3.0 Functional Description
3.1 Repeater State Machine
3.2 RXE Control
3.3 TXE Control
3.4 Data Path
3.5 Elasticity Buffer
3.6 Jabber Protection State Machine
3.7 Auto-Partition State Machine
3.8 Inter Repeater Bus Interface
3.9 Management Bus
3.10 Management Event Flags and Counters
3.11 Serial Register Interface
3.12 Jabber/Partition LED Driver Logic
3.13 EEPROM Serial Read Access
Table of Contents
4.0 Registers
4.1 Page 0 Register Map
4.2 Page 1 Register Map
4.3 Configuration Register (CONFIG)
4.4 Page Register (PAGE)
4.5 Partition Status Register (PARTITION)
4.6 Jabber Status Register (JABBER)
4.7 Administration Register (ADMIN)
4.8 Device ID Register (DEVICEID)
4.9 Hub ID 0 Register (HUBID0)
4.10 Hub ID 1 Register (HUBID1)
4.11 Port Management Counter Registers
4.12 Silicon Revision Register (SIREV)
5.0 DP83858 Applications
5.1 MII Interface Connections
5.2 Repeater ID Interface
5.3 Inter Repeater Bus Connections
5.4 DP83856 100RIB Connections
5.5 Port Partition and Jabber Status LEDs
6.0 AC and DC Specifications
6.1 DC Specifications
6.2 AC Specifications
7.0 Physical Dimensions
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1.0 Pin Connection Diagram
IRD_ODIR
/IRD_ER
RSM3/RXECONFIG
RXD0
RXD1
RXD2
RXD3
RX_DV
RX_ER
RXC
GND
VCC
CRS0
CRS1
CRS2
CRS3
CRS4
CRS5
CRS6
CRS7
NC
NC
NC
NC
RXE0
RXE1
RXE2
RXE3
GND
VCC
RXE4
RXE5
RXE6
IRD3
GND
/IRD_V
VCC
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
53
52
51
IRD0
IRD1
IRD2
11
12
13
14
DP83858VF
Repeater Interface Controller
57
56
55
54
VCC
IRD_CK
9
10
59
58
TX_ER
GND
7
8
100 Mb/s TX/T4
62
61
60
TXD3
TXD2
TXD0
6
TXD1
5
GND
VCC
/IR_ACTIVE
1
2
3
4
132
(100RIC8)
132 pin PQFP
(top view)
67
66
65
64
63
69
68
/IR_COL_OUT
IR_VECT1
IR_VECT0
/IR_COL_IN
129
130
128
131
72
71
70
IR_VECT3
IR_VECT2
126
127
75
74
73
IR_VECT4
VCC
GND
123
124
125
77
76
122
78
MD0
79
MD1
121
120
80
MD2
MD3
119
81
82
VCC
118
GND
117
83
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
/M_DV
M_CK
/M_ER
/IR_BUS_EN
VCC
GND
/ACTIVE0
/SDV
RDIR
RDIO
RDC
GRDIO
BRDC
/RST
VCC
GND
LCK
RID0
RID1
RID2
RID3
VCC
GND
RID4
RID_ER
PART0
PART1
PART2
PART3
PART4
VCC
GND
PART5
RXE7
NC
NC
NC
NC
GND
VCC
TXE0
TXE1
TXE2
TXE3
TXE4
TXE5
TXE6
TXE7
GND
VCC
NC
NC
RSM0
RSM1
RSM2
GND
TX_RDY
VCC
EE_CK
EE_CS
EE_DI
EE_DO
MODE1
MODE0
NC
NC
NC: These pins shall not have any connections and are reserved by National for future use.
Pinout subject to change. Please contact National Semiconductor for the latest design information.
Order Number DP83858VF
NS Package Number VF132A
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1.1 Pin Table
Pin Name Pin No. Section
/ACTIVEO 110 2.2
/IR_ACTIVE 132 2.2
/IR_BUS_EN 113 2.2
/IR_COL_IN 130 2.2
/IR_COL_OUT 131 2.2
/IRD_ER 19 2.2
/IRD_V 15 2.2
/M_DV 116 2.2
/M_ER 114 2.2
/RST 103 2.4
/SDV 109 2.2
BRDC 104 2.4
CRS[7:0] 37-30 2.1
EE_CK 79 2.3
EE_CS 78 2.3
EE_DI 81 2.3
EE_DO 80 2.3
GND 1, 8, 16, 28, 46, 56, 66,76, 85, 94, 101, 111, 117,123 N/A
GRDIO 105 2.4
IR_VECT[4:0] 125-129 2.2
IRD[3:0] 14-11 2.2
IRD_CK 10 2.2
IRD_ODIR 18 2.4
LCK 100 2.4
M_CK 115 2.2
MD[3:0] 119-122 2.2
MODE[1:0] 83-82 2.4
PART[5:0] 84, 87-91 2.4
RDC 106 2.2
RDIO 107 2.2
RDIR 108 2.4
RID[4:0] 93, 96-99 2.4
RID_ER 92 2.4
RSM[2:0] 74-72 2.4
RSM[3]/ RXECONFIG 20 2.4
RX_DV 25 2.1
RX_ER 26 2.1
RXC 27 2.1
RXD[3:0] 24-21 2.1
RXE[7:0] 51-48, 45-42 2.1
TX_ER 7 2.1
TX_RDY 75 2.1
TXD[3:0] 3-6 2.1
TXE[7:0] 65-58 2.1
VCC 2, 9, 17, 29, 47, 57, 67, 77, 86, 95, 102, 112, 118, 124 N/A
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2.0 Pin Descriptions
2.1 Physical Layer Interface
Signal Name Type Active Description
RXD[3:0] I — Receive Data: Nibble data inputs from each Physical layer chip. Up to 12 ports are sup-
RXE[7:0] O, L high (low) Receive Enable: Asserted to the respective Physical Layer chip to enable its Receive
RX_DV I high Receive Data Valid: Asserted High when valid data is present on RXD[3:0].
RX_ER I high Receive Error: The physical Layer asserts this signal high when it detects receive error.
RXC I — Receive Clock: Recovered clock from the Physical Layer device. RXD, RX_DV, and
CRS[7:0] I high Carrier Sense: Asynchronous carrier indication from the Physical Layer device.
TXE[7:0] O, L high Transmit Enable: Enables corresponding port for transmitting data.
TX_RDY O, L high Transmit Ready: Indicates when a transmit is in progress. Essentially, this signal is the
TX_ER O, M high Transmit Error: Asserted high when a code violation is requested to be transmitted.
TXD[3:0] O, H high Transmit Data: Nibble data output to be transmitted by each Physical Layer device.
Note: A table showing pin type designation is given in section 2.5
ported.
Note: Input buffer has a weak pull-up.
Data. These pins are either active high or active low depending on the polarity of RSM3
pin as shown below:
RXE[7:0] RSM3
Active High Unconnected or pulled high
Active Low Pulled down
Note: To ensure that during idle, when 100PHYs TRI-STATE®, this signal is NOT interpreted as “logic one” by the repeater, a 1kΩ pull down resistor must be placed on this
pin. The location on this pull down should be between the repeater and the nearest tristateable component to the repeater.
When this signal is asserted, the 100PHY (TX or T4) device indicates the type of error
on RXD[3:0] as shown below. Note that this data is passed only to the Inter Repeater
Bus, and not onto the TX Bus:
RX_ER RXD[3:0] Receive Error Condition
0 data Normal data reception
1 0h Symbol code violation
1
1h
1
Elasticity Buffer Over/Under-run
1 2h Invalid Frame Termination
1
1
1
The 100PHY must be configured with the Elasticity Buffer bypassed; hence this error
3h
4h
2
2
Reserved
10Mb Link Detected
code will never be generated.
2
These error codes will only appear when CRS from the 100PHY is not asserted. Since
the DP83858 only enables a 100PHY when its CRS is asserted, these error codes will
never be passed through the chip.
Note: Input buffer has a weak pull-down.
RX_ER are generated from the falling edge of this clock.
Note: Input buffer has a weak pull-down.
logical 'OR' of all TXEs.
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2.2 Inter Repeater and Management Bus Interface
Signal Name Type Active Description
IRD[3:0] I/O/Z, M — Inter Repeater Data: Nibble data input/output. Transfers data from the “active”
/IRD_ER I/O/Z, M low Inter Repeater Data Error: This signal carries the RX_ER state across the Inter Re-
/IRD_V I/O/Z, M low Inter Repeater Data Valid: This signal carries the inv erted RX_DV state across the
IRD_CK I/O/Z, M — Inter Repeater Data Clock:All Inter Repeater signals are synchroniz ed to the rising
IRD_ODIR O, L high Inter Repeater Data Outward Direction: This pin indicates the direction of data for
/IR_ACTIVE I/O/OC, M low Inter Repeater Activity: This “open-collector” type output is asserted when the re-
/IR_COL_IN I low Inter Repeater Collision In: Indication from another DP83858 that it senses two or
/IR_COL_OUT O/OC, M low Inter Repeater Collision Out: Asserted when the DP83858 senses two or more
IR_VECT[4:0] I/O/OC, M high Inter Repeater Vector: When the repeater senses at least one of its ports active, it
MD[3:0] I/O/Z, M high Management Data: Outputs management information for the DP83856 manage-
/M_DV I/O/Z, M low Management Data Valid: Asserted when valid data is present on MD[3:0].
M_CK I/O/Z, M — Management Clock: All data transfers on the management bus are synchronize to
/M_ER I/O/Z, M low Management Error: Asserted when an Elasticity Buffer overrun or under-run error
/IR_BUS_EN O,L low Inter-Repeater Bus Enable: This signal is asserted at all times (either when the
DP83858 to all other “inactive” DP83858s. The bus master of the IRD bus is determined by IR_VECT bus arbitration.
Note: Input buffer has a weak pull-up.
peater bus. Used to track receive errors from the physical layer in real-time
Inter Repeater bus. It is used to frame good packets.
Note: A recommended 1.5K pull-up prevents first repeated packet corruption .
edge of this clock.
Note: Input buffer has a weak pull-up.
an external transceiver. It is HIGH when IRD[3:0], /IRD_V, /IRD_CK, and /IRD_ER
are driven out towards the Inter Repeater bus, and LO W when data is being received
from the bus.
peater senses network activity.
Note: Input buffer has a weak pull-up.
more ports receiving or another DP83858 has detected a collision.
Note: Input buffer has a weak pull-up.
ports receiving or non-idle, either 1) within this DP83858 or 2) in another DP83858,
using the IR_VECT number to decide (the IR_VECT number read will differ from the
number of this DP83858 if another device is active).
drives its unique vector (from RID[4:0]) onto these pins. If the vector v alue read bac k
differs from its own (because another vector is being asserted by another device),
then this DP83858 will:
1) not drive IRD_ODIR signal and,
2) tri-states the IRD[3:0], /IRD_ER, /IRD_V, and IRD_CK signals.
Howev er, if the v alue read back is the same as its own RID number , this DP83858 will
continue to drive the Inter Repeater bus signals. Note that these v ectors are driv en
onto the bus for the duration of /ACTIVEO assertion.
Note: Input buffer has a weak pull-up.
ment chip. During packet reception the DP83858 drives its RID n umber and the port
number of the receiving port onto this bus.
Note: Input buffer has a weak pull-up.
Note: Input buffer has a weak pull-up.
the rising edge of this clock.
Note: Input buffer has a weak pull-up.
has been detected.
Note: Input buffer has a weak pull-up.
100RIC8 is driving the bus or receiving from the bus) and it is deasserted only when
the 100RIC8 switches direction from an input (receiving) mode to an output (driving)
mode. After this switch, this signal becomes asserted again.
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Signal Name Type Active Description
RDIO I/O/Z, L — Register Data I/O: Serial data input/output transfers data to/from the internal regis-
ters. Serial protocol conforms to the IEEE 802.3u MII (Media Independent Interface)
specification.
Note: Input buffer has a weak pull-up.
RDC I — Register Data Clock: All data transfers on RDIO are synchroniz ed to the rising edge
of this clock. RDC is limited to a maximum frequency of 2.5 MHz. At least 3 cycles
of RDC must be provided during assertion of /RST (pin 103) to ensure proper reset
of all internal blocks.
/SDV I low Serial Data Valid: Asserted when a valid read or write command is present. Used to
detect disconnection of the management bus so that synchronization is not lost. If not
used, tie this pin to GND.
Note: Input buffer has a weak pull-up.
/ACTIVEO O/OC, M low Active Out: Enable for the IR_VECT[4:0] and /IR_ACTIVE signals. Used in multi-
DP83858 systems to enable the external buffers driving these Inter Repeater Bus
signals.
A pull up of 680 Ω must be used with this signal.
Note: A table showing pin type designation is given in section 2.5
2.3 EEPROM Interface
Signal Name Type Active Pin Description
EE_CS O, L high EEPROM Chip Select: Asserted during reads to EEPROM.
EE_CK O, L — EEPROM Serial Clock: Local Clock ÷ 32 = 0.78125MHz
EE_DO I — EEPROM Serial Data Out: Connected to the serial data out of the EEPROM.
EE_DI O, L — EEPROM Serial Data In: Connected to the serial data in of the EEPROM.
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2.4 Miscellaneous
Signal Name Type Active Pin Description
LCK I — Local Clock: Must be 25 MHz ± 50ppm. Used for TX data transfer to Physical Layer
RID[4:0] I — Repeater Identification Number: Provides the unique vector for the IR_VECT[4:0]
/RST I low Reset: The chip is reset when this signal is asserted low.
GRDIO I/O/Z, L — Gated Register Data Input/Output: This I/O is a gated version of RDIO. When the
BRDC O, L — Buffered Register Data Clock: Buffered version of RDC. Allows more devices to be
RDIR O, L high Register Data Direction: Direction signal for an external bi-directional buffer on the
PART[5:0] O, L — Partition: Used to indicate each port's Jabber and Partition status. PART[3:0] cycle
RID_ER O, L high Repeater ID Err or: This pin is asserted under the conditions which set the RID_error
RSM[3]
I/O, L — Repeater State Machine Output/ RXE Polarity: This pin is an input during reset and
/RXECONFIG
RSM[3]
I/O, L O, L — Test Outputs indicating the state of the Repeater State Machine.
RSM[2:0]
MODE[1:0] I — Mode Inputs: The 100RIC8 may be configured in the following modes:
Note: A table showing pin type designation is given in section 2.5
devices, TX Bus data transfers and DP83858 internal state machines.
signals used in Inter Repeater bus arbitration. These bit are also used to uniquely identify this chip for serial register accesses. The RID value is latched when reset is deasserted.
Note: The arbiter cannot use the value 1Fh as its arbitration vector. This is the
IR_VECT[4:0] bus idle state, therefore RID[4:0] must never be set to this value.
“phy_access” bit in the CONFIG register is set high, the RDIO signal is passed through
to GRDIO for accessing the physical layer chips.
Note: Input buffer has a weak pull-up.
chained on the MII serial bus.
RDIO signal.
0 = RDIO data flows into the DP83858
1 = RDIO data flows out of the DP83858
Defaults to 0 when no register access is present.
through each port number (0-11) continuously. PART[4] indicates the Partition status
for each port (1 = Port Partitioned). PART[5] indicates the Jabber status for each port
(1 = Port Jabbering). These pins are intended to be decoded to drive LEDs.
bit in the DEVICEID register.
it is used to latch the desired polarity of RXE[7:0] signals.
When this pin is pulled high or it is unconnected, then the RXE signals become active
high. However, if this signal is pulled low, then the RXE signals become active low.
In all other non-reset times, this pin reflects the output of the Repeater State Machine.
RSM[3:0] State
0 idle
1 collision
2 one port left
3 repeat
4 noise
Other states are undefined.
MODE[1:0] Operation
0,0 No special modes selected
1,0 Test mode
0,1 Test mode
1,1 Preamble regeneration (T4) mode
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2.5 Pin Type Designation
Pin Type Description
I Input Buffer
O Output Buffer, driven high or low at all times
I/O/Z Bi-directional Buffer with high impedance output
O/Z Output Buffer with high impedance capability
OC Open Collector like signals. These buffers are
either driven low or in a high-impedance state.
L Output low drive: 4 mA
M Output medium drive: 12 mA
H Output high drive : 24 mA
3.0 Functional Description
The following sections describe the different functional
blocks of the DP83858 100 Mb/s Repeater Interface Controller. The IEEE 802.3u repeater specification details a
number of functions a repeater system is required to perform. These functions are split between those tasks that
are common to all data channels and those that are specific to each individual channel. The DP83858 follows this
split task approach for implementing the required functions.
Where necessary, the difference between the TX and T4
modes is discussed.
3.1 Repeater State Machine
The Repeater State Machine (RSM) is the main block that
governs the overall operation of the repeater. At any one
time, the RSM is in one of the following states: Idle,
Repeat, Collision, One Port Left, or Noise.
3.1.1 Idle State
The RSM enters this state after reset or when there is no
activity on the network and the carrier sense is not present.
The RSM exits from this state if the above conditions are
no longer true.
3.1.2 Repeat State
This state is entered when there is a reception on only one
of the ports, port N. While in this state, the data is transmitted to all the ports except the receiving port (por t N). The
RSM either returns to Idle state when the reception ends,
or transitions to Collision state if there is reception activity
on more than one port.
3.1.3 Collision State
When there is receive activity on more than one port of the
repeater, the RSM moves to Collision state. In this state,
transmit data is replaced by Jam and sent out to all ports
including the original port N.
There are two ways for the repeater to leave the Collision
state. The first is when there is no receive activity on any
of the ports. In this case, the repeater moves to Idle state.
The second is when there is only one port experiencing
collision in which case the repeater enters the One Port
Left state.
3.1.4 One Port Left State
This state is entered only from the Collision state. It guarantees that repeaters connected hierarchically will not jam
each other indefinitely. While in this state, Jam is sent out
to all ports except the port that has the receive activity. If
more receive activity occurs on any other port, then the
repeater moves to Collision state.
Otherwise, the repeater will transition to Idle state when the
receive activity ends.
3.1.5 Noise State
When there is an Elasticity Buffer overflow or underflow
during packet reception, then the repeater enters the Noise
state. During this state, the Jam pattern is sent to all transmitting ports. The repeater leaves this state by moving
either to the Idle state, if there is no receive activity on any
ports, or to the Collision state, if there is a collision on one
of its segments.
3.2 RXE Control
When only one port has receive activity, the RXE signal
(receive enable) is activated. If multiple ports are active
(i.e. a collision scenario), then RXE will not be enabled for
any port. The Port Select Logic asserts the open-collector
outputs /IR_COL_OUT and /IR_ACTIVE to indicate to
other cascaded DP83858s that there is collision or receive
activity present on this DP83858.
The polarity of the RXE signal can be set through an external pull down resistor placed at the RSM[3] pin. That is, if
the RSM[3] pin is unconnected or pulled high, then the
RXE is active high and when the RSM[3] is pulled low, then
the RXE is active low.
3.3 TXE Control
This control logic enables the appropriate ports for data
transmission according to the four states of the RSM. For
example, during Idle state, no ports are enabled; during
Repeat state, all ports but port N are enabled; in Collision
state, all ports including port N are enabled ; during One
Port Left state, all ports except the port experiencing the
collision will be enabled.
3.4 Data Path
After the Port Selection logic has enabled the active port,
receive data (RXD), receive clock (RXC), receive error
(RX_ER) and receive data valid (RX_DV) will flow through
the chip from that port out onto the Inter Repeater (IR) bus
if no collisions are present. The signals on the IR bus flow
either in to or out of the chip depending upon the
Repeater’s state.
If the DP83858 is currently receiving and no collisions are
present, the IR signals flow out of the chip. The DP83858's
Arbitration Logic guarantees that only one DP83858 will
gain ownership of the IR bus. In all other states, the IR signals are inputs.
When IR signals are inputs, the signals flow into the Elasticity Buffer (EB). Here, the data is re-timed and then sent
out to the transmit ports. The Transmit Control logic determines which ports are enabled for data transmission.
If a collision occurs, a Jam pattern is sent out from the EB
instead of the data. The Jam pattern (3,4,3,4,..... from the
DP83858, encoded by the Physical Layer device as
1,0,1,0,.....) is transmitted for the duration of the collision
activity.
If the repeater is configured in the preamble regeneration
mode (T4 mode), approximately 12 clock cycles after the
assertion of /IR_ACTIVE (indicating a packet reception on
a segment), the 100RIC8 begins to transmit the preamble
pattern onto the other network segments. While the pre-
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amble is being transmitted, the EB monitors the received
clock and data signals. When the start of the frame delimiter "SFD" is detected, the received data stream is written
into the EB. After this point, data from the EB is sent out to
the Transmit interface. The preamble is always generated
in its entirety (i.e. fifteen 5’s and one D) even if a collision
occurs.
3.5 Elasticity Buffer
The elasticity buffer, or a logical FIFO buffer, is used to
compensate for the variations and timing differences
between the recovered Receive Clock and the local clock.
This buffer supports maximum clock skews of 200 ppm for
the preamble regeneration (T4) mode, and 100 ppm for the
TX mode, within a maximum packet size of 1518 bytes.
3.6 Jabber Protection State Machine
The jabber specification for 100BASE-T is functionally different than 10BASE-T.
In 10BASE-T, each port's Jabber Protect State machine
ensures that Jabber transmissions are stopped after 5ms
and followed by 96 to 116 bit times silence before the port
is re-enabled.
In 100BASE-T, when a por t jabbers, its receive and transmit ports are cutoff until the jabber activity ceases. All other
ports remain unaffected and continue normal operation.
The 100BASE-T Jabber Protect Limit (that is, the time for
which a port can jabber until it is cutoff) for the DP83858 is
reached if the CRS is active for more than 655µs.
A jabbering port that is cut off will be re-enabled when the
jabber activity ceases and the IDLE line condition is
sensed.
3.7 Auto-Partition State Machine
In order to protect the network from a port that is experiencing excessive consecutive collisions, each port must
have its own auto-partition state machine.
A port with excessive consecutive collisions will be partitioned after a programmed number of consecutive collisions occur on that port. Transmitting ports will not be
affected.
The DP83858 has a configuration bit that allows the user to
choose how many consecutive collisions a port should
experience before partitioning. This bit can be set for
either 32 or 64 consecutive collisions. The IEEE802.3u
100BASE-T standard specifies the consecutive collisions
limit as greater than 60. A partitioned port will be reconnected when a collision-free packet of length 512 bits or
more (that is, at least a minimum sized packet) is transmitted out of that port.
The DP83858 also provides a configuration bit that disables the auto-partition function completely.
3.8 Inter Repeater Bus Interface
The Inter Repeater bus is used to connect multiple
DP83858s together to form a logical repeater unit and also
to allow a managed entity. The IR bus allows received data
packets to be transferred from the receiving DP83858 to
the other DP83858s in the system. These DP83858s then
send the data stream to their transmit enabled ports.
Notification of collisions to other cascaded DP83858s is as
important as data transfer across the network. The arbitration logic asynchronously determines if more than one
100RIC8, cascaded together, are receiving simultaneously.
The IR bus has a set of status lines capable of conveying
collision information between DP83858s to ensure their
main state machines operate in the appropriate manner.
The IR bus consists of the following signals:
■ Inter Repeater Data. This is the transfer data, in nibble
format, from the active DP83858 to all other cascaded
DP83858s.
■ Inter Repeater Data Error. This signal carries the receive error status from the physical layer in real-time.
■ Inter Repeater Data Valid. This signal is used to frame
good packets.
■ Inter Repeater Data Clock. All IR data is synchronized
to this clock.
■ Inter Repeater Data Outward Direction. This pin indicates the direction of the data flow with respect to the
DP83858. When the DP83858 is driving the IR bus (i.e.
it contains port N) this signal is HIGH and when the
DP83858 is receiving data from other DP83858s over
the IR bus this signal is LOW.
■ Inter Repeater Bus Enable. This signal (connected to
the /ENABLE pin of the external transceivers on the IR
bus) is used in conjunction with the IRD_ODIR signal
(connected to the DIR pin of the transceivers) to TRISTATE these transceivers during the change of direction
from input to output, or vice versa. This signal is always
active allowing the IR bus signals to pass through the
transceivers into or out of the 100RIC8. However when
the 100RIC8 switches from input mode (IRD_ODIR=0)
to output mode (IRD_ODIR=1), the /IR_BUS_EN signal
is deasserted allowing the transceivers to TRI-STATE
during the direction change. After this turn-around, this
signal is asserted back again. (IRD_ODIR assertion
(high) to /IR_BUS_EN low timing is a minimum of 0.1 ns.
and a maximum of 1.0. The time from /IR_BUS_EN
(high) to the IRD_ODIR high is a minimum of 10 ns. and
a maximum of 20 ns. In addition, /ACTIVEO assertion
(low) to /IR_BUS_EN high timing is a maximum of 1.0
ns.)
■ Inter Repeater Activity. When there is network activity
the DP83858 asserts this output signal.
■ Inter Repeater Collision Output. If there are multiple receptions on ports of a DP83858 or if the DP83858 senses concurrent activity on another DP83858 it asserts this
output.
■ Inter Repeater Collision Input. This input indicates that
one of the cascaded DP83858s is experiencing a collision.
■ Inter Repeater Vector. When there is reception on a port
the DP83858 drives a unique vector onto these lines.
The vector on the IR bus is compared with the Repeater
ID (RID). The DP83858 will continue to drive the IR bus
if both the vector and RID match.
The following figure shows the conditions that cause an
open collector vector signal to be asserted on the backplane bus.
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RID[n]=0
&
/ACTIVEO=0
Figure 1. Open Collector /IR_VECT[n]
/IR_VECT[n]
As seen, if the RID[n]=1, and the repeater is receiving on a
port, then the /IR_VECT[n] value would be 1 due to the
pull-up on this pin. In the case that RID[n]=0, then a zero is
driven out on the /IR_VECT[n] signal.
As an example assume that two repeaters with RIDs equal
to RID #1=00010 and RID #2=00011 are connected
through the Inter-RIC bus. The following diagrams depict
the values of /IR_VECT signals over the backplane.
■ Active Output. This signal is asserted by a DP83858
when at least one of its ports is active. It is used to enable
external bus transceivers.
Activity on the 100RIC8
with RID=00010
Activity on the 100RIC8
with RID=00011
/IR_Vect value on
the backplane
Activity on the 100RIC8
with RID=00011
Activity on the 100RIC8
with RID=00010
/IR_VECT value on
the backplane
Collision
RID=00010
RID=00011
00010 0001100010
Collision
RID=00011
RID=00010
00010 0001000011
Figure 2. RID to /IR_VECT Mapping
One port left
One port left
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