NSC DP83848HSQ, DP83848H Datasheet

DP83848H PHYTER® Mini - Extreme Temperature Single 10/100 Ethernet Transceiver

© 2006 National Semiconductor Corporation

www.national.com

DP83848H PHYTER® Mini - Extreme Temperature
Single 10/100 Ethernet Transceiver

September 2006

Features

• Low-power 3.3V, 0.18µm CMO S techn ol ogy

• 3.3V MAC Interface

• Auto-MDIX for 10/100 Mb/s

• Energy Detection Mode

• MII Interface and MII serial management interface (MDC

and MDIO)

• IEEE 802.3u Auto-Negotiation and Parallel Detection

• IEEE 802.3u ENDEC, 10BASE-T transceivers and filters

• IEEE 802.3u PCS, 100BASE-TX transceivers and filters

• Integrated ANSI X3.263 co mp lia nt TP-PM D ph ys ic al s ub -

layer with adaptive equalization and Baseline Wander
compensation

• Error-free Operation up to 137 meters

• ESD protection - 4KV Human body model

• LED support for Link

• Supports system clock from oscillator

• Single register access for complete PHY status

• 10/100 Mb/s packet BIST (Built in Self Test)

• 40 pin LLP package (6mm) x (6mm) x (0.8mm)

Applications

• Peripheral devices

• Mobile devices

• Factory and building automation

• Basestations

General Description

The DP83848H PHYTER® Mini Extreme addresses the
high quality, high reliability and small form factor required
for rugged operation in space sensitive and thermally
demanding environments. This device is ideally suited for
industrial and motor control, building/factory automation,
automotive and test equipment applications.

The DP83848H is designed from ground up for extreme
temperature performance, with a thermally efficient pack­age ensuring reliable operation over an operating range of

-40C to 125C. Rigorously tested at both low temperature
and high temperature extremes, the device is ideal for out­door environment s and dem anding factory floor co nditio ns.

The device offers performance beyond the IEEE specifica­tions, with superior interoperability and industry leading
performance. The DP83848H offers Auto-MDIX to remove
cabling complications, superior ESD protection of greater
than 4KV HBM for greater reliability, and superior cable
length operation (greater than 137m) to provide a high
level of performance in all applications.

A number of system cost-reducing features have been
integrated that are not commonly found in other Ethernet
Physical layer products (PHYs). For example, the
DP83848H offers a 25MHz clock out that eliminates the
need and hence the space and cost, of an additional
Media Access Control (MAC) clock source component.

DP83848H is offered in a small 6mm x 6mm LLP 40-pin
package.

System Diagram

PHYTER® is a registered trademark of National Semiconductor Corporation.

Status

10BASE-T

or

100BASE-TX

MII

Typical Ethernet Application

Magnetics

RJ-45

Clock

LED

DP83848H

10/100 Ethernet

Transceiver

Media Access Controller

MPU/CPU

Source

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N

A

T

I

O

N

A

L

S

E

M

I

C

O

N

D

U

C

T

O

R

C

O

N

F

I

D

E

N

T

I

A

L

SERIAL

MANAGEMENT

TX_CLK

TXD[3:0]

TX_EN

MDIO

MDC

COL

CRS

RX_ER

RX_DV

RXD[3:0]

RX_CLK

Auto-Negotiation

State Machine

Clock

RX_DATA

RX_CLK

TX_DATA TX_CLK

REFERENCE CLOCK

TD±

RD±

LED

Generation

MII INTERFACE

Figure 1. DP83848H Functional Block Diagram

MII

Registers

Transmit Block

10BASE-T &

100BASE-TX

10BASE-T &

100BASE-TX

Receive Block

Auto-MDIX

DAC

ADC

LED

Driver

MII

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DP83848H

Table of Contents

1.0 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

1.1 Serial Management Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

1.2 MAC Data Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

1.3 Clock Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

1.4 LED Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

1.5 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

1.6 Strap Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

1.7 10 Mb/s and 100 Mb/s PMD Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

1.8 Special Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

1.9 Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

1.10 Package Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

2.0 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.1 Auto-Negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

2.1.1 Auto-Negotiation Pin Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.1.2 Auto-Negotiation Register Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.1.3 Auto-Negotiation Parallel Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.1.4 Auto-Negotiation Restart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.1.5 Enabling Auto-Negotiation via Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.1.6 Auto-Negotiation Complete Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.2 Auto-MDIX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

2.3 PHY Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

2.3.1 MII Isolate Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.4 LED Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

2.4.1 LED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.4.2 LED Direct Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.5 Half Duplex vs. Full Duplex . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

2.6 Internal Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

2.7 BIST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

3.0 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.1 MII Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

3.1.1 Nibble-wide MII Data Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.1.2 Collision Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.1.3 Carrier Sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.2 802.3u MII Serial Management Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

3.2.1 Serial Management Register Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.2.2 Serial Management Access Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.2.3 Serial Management Preamble Suppression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.0 Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.1 100BASE-TX TRANSMITTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

4.1.1 Code-group Encoding and Injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.1.2 Scrambler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.1.3 NRZ to NRZI Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.1.4 Binary to MLT-3 Convertor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.2 100BASE-TX RECEIVER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

4.2.1 Analog Front End . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.2.2 Digital Signal Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.2.2.1 Digital Adaptive Equalization and Gain Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.2.2.2 Base Line Wander Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

4.2.3 Signal Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

4.2.4 MLT-3 to NRZI Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

4.2.5 NRZI to NRZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

4.2.6 Serial to Parallel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

4.2.7 Descrambler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4.2.8 Code-group Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4.2.9 4B/5B Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

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DP83848H

4.2.10 100BASE-TX Link Integrity Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4.2.11 Bad SSD Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4.3 10BASE-T TRANSCEIVER MODULE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

4.3.1 Operational Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4.3.2 Smart Squelch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

4.3.3 Collision Detection and SQE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

4.3.4 Carrier Sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

4.3.5 Normal Link Pulse Detection/Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

4.3.6 Jabber Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

4.3.7 Automatic Link Polarity Detection and Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

4.3.8 Transmit and Receive Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

4.3.9 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

4.3.10 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

5.0 Design Guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

5.1 TPI Network Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

5.2 ESD Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

5.3 Clock In (X1) Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

5.4 Power Feedback Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

5.5 Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

5.6 Energy Detect Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

6.0 Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

6.1 Hardware Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

6.2 Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

7.0 Register Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

7.1 Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

7.1.1 Basic Mode Control Register (BMCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

7.1.2 Basic Mode Status Register (BMSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

7.1.3 PHY Identifier Register #1 (PHYIDR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

7.1.4 PHY Identifier Register #2 (PHYIDR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

7.1.5 Auto-Negotiation Advertisement Register (ANAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

7.1.6 Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page) . . . . . . . . . . . . . . . . 42

7.1.7 Auto-Negotiation Link Partner Ability Register (ANLPAR) (Next Page) . . . . . . . . . . . . . . . . . 43

7.1.8 Auto-Negotiate Expansion Register (ANER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

7.1.9 Auto-Negotiation Next Page Transmit Register (ANNPTR) . . . . . . . . . . . . . . . . . . . . . . . . . . 44

7.2 Extended Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

7.2.1 PHY Status Register (PHYSTS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

7.2.2 False Carrier Sense Counter Register (FCSCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

7.2.3 Receiver Error Counter Register (RECR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

7.2.4 100 Mb/s PCS Configuration and Status Register (PCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . 48

7.2.5 LED Direct Control Register (LEDCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

7.2.6 PHY Control Register (PHYCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

7.2.7 10Base-T Status/Control Register (10BTSCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

7.2.8 CD Test and BIST Extensions Register (CDCTRL1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

7.2.9 Energy Detect Control (EDCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

8.0 Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

8.1 DC Specs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

8.2 AC Specs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

8.2.1 Power Up Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

8.2.2 Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

8.2.3 MII Serial Management Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

8.2.4 100 Mb/s MII Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

8.2.5 100 Mb/s MII Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

8.2.6 100BASE-TX Transmit Packet Latency Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

8.2.7 100BASE-TX Transmit Packet Deassertion Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

8.2.8 100BASE-TX Transmit Timing (tR/F & Jitter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

8.2.9 100BASE-TX Receive Packet Latency Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

8.2.10 100BASE-TX Receive Packet Deassertion Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

8.2.11 10 Mb/s MII Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

8.2.12 10 Mb/s MII Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

8.2.13 10BASE-T Transmit Timing (Start of Packet) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

5 www.national.com

DP83848H

8.2.14 10BASE-T Transmit Timing (End of Packet) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

8.2.15 10BASE-T Receive Timing (Start of Packet) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

8.2.16 10BASE-T Receive Timing (End of Packet) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

8.2.17 10 Mb/s Heartbeat Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

8.2.18 10 Mb/s Jabber Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

8.2.19 10BASE-T Normal Link Pulse Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

8.2.20 Auto-Negotiation Fast Link Pulse (FLP) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

8.2.21 100BASE-TX Signal Detect Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

8.2.22 100 Mb/s Internal Loopback Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

8.2.23 10 Mb/s Internal Loopback Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

8.2.24 Isolation Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

8.2.25 25 MHz_OUT Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

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DP83848H

List of Figures

Figure 1. DP83848H Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Figure 2. PHYAD Strapping Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 3. AN0 Strapping and LED Loading Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 4. Typical MDC/MDIO Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 5. Typical MDC/MDIO Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 6. 100BASE-TX Transmit Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 7. 100BASE-TX Receive Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Figure 8. EIA/TIA Attenuation vs. Frequency for 0, 50, 100, 130 & 150 meters of CAT 5 cable . . . . . . . . . . .25

Figure 9. 100BASE-TX BLW Event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 10. 10BASE-T Twisted Pair Smart Squelch Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Figure 11. 10/100 Mb/s Twisted Pair Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 12. Crystal Oscillator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Figure 13. Power Feeback Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

7 www.national.com

DP83848H

List of Tables

Table 1. Auto-Negotiation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Table 2. PHY Address Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Table 3. LED Mode Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Table 4. Typical MDIO Frame Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Table 5. 4B5B Code-Group Encoding/Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Table 6. 25 MHz Oscillator Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Table 7. 25 MHz Crystal Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Table 8. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Table 9. Register Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Table 10. Basic Mode Control Register (BMCR), address 0x00 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Table 11. Basic Mode Status Register (BMSR), address 0x01 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

Table 12. PHY Identifier Register #1 (PHYIDR1), address 0x02 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

Table 13. PHY Identifier Register #2 (PHYIDR2), address 0x03 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

Table 14. Negotiation Advertisement Register (ANAR), address 0x04 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

Table 15. Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page), address 0x05 . . . . . . . .42

Table 16. Auto-Negotiation Link Partner Ability Register (ANLPAR) (Next Page), address 0x05 . . . . . . . . .43

Table 17. Auto-Negotiate Expansion Register (ANER), address 0x06 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

Table 18. Auto-Negotiation Next Page Transmit Register (ANNPTR), address 0x07 . . . . . . . . . . . . . . . . . . . 44

Table 19. PHY Status Register (PHYSTS), address 0x10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

Table 20. False Carrier Sense Counter Register (FCSCR), address 0x14 . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

Table 21. Receiver Error Counter Register (RECR), address 0x15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

Table 22. 100 Mb/s PCS Configuration and Status Register (PCSR), address 0x16 . . . . . . . . . . . . . . . . . . . .48

Table 23. LED Direct Control Register (LEDCR), address 0x18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

Table 24. PHY Control Register (PHYCR), address 0x19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

Table 25. 10Base-T Status/Control Register (10BTSCR), address 0x1A . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

Table 26. CD Test and BIST Extensions Register (CDCTRL1), address 0x1B . . . . . . . . . . . . . . . . . . . . . . . . .53

Table 27. Energy Detect Control (EDCR), address 0x1D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

www.national.com 8

DP83848H

Pin Layout

PFBIN2
DGND
X1
X2
IOVDD33
MDC
MDIO
RESET_N
LED_LNK
25MHz_OUT

RBIAS

PFBOUT

AVDD33

AGND

PFBIN1

TD +

TD -

AGND

RD +

RD -

IOVDD33

TX_CLK

TX_EN

TXD_0
TXD_1
TXD_2

TXD_3
RESERVED
RESERVED
RESERVED

RX_CLK

RX_DV

CRS/LED_CFG

RX_ER/MDIX_EN

COL/PHYAD0

RXD_0/PHYAD1

RXD_1/PHYAD2

RXD_2/PHYAD3

RXD_3/PHYAD4

IOGND

1
2
3
4
5
6
7
8
9
10

20

19

18

17

16

15

14

13

12

11

30
29
28
27
26
25
24
23
22
21

31

32

33

34

35

36

37

38

39

40

Top View

Order Number DP83848H

NS Package Number NSQAU040

9 www.national.com

DP83848H

1.0 Pin Descriptions

The DP83848H pins are classified into the following inter­face categories (each interface is described in the sections
that follow):

— Serial Management Interface
— MAC Data Interface
— Clock Interface
— LED Interface
—Reset
— Strap Options
— 10/100 Mb/s PMD Interface
— Special Connect Pins
— Power and Ground pins

Note: Strapping pin option. Please see Se ction 1.6 for strap
definitions.

All DP83848H signal pins are I/O cells regardless of the
particular use. The defi nition s below defi ne the func tiona lity
of the I/O cells for each pin.

1.1 Serial Managemen t Interface

1.2 MAC Data Interface

Type: I Input
Type: O Output
Type: I/O Input/Output
Type: PD,PU Internal Pulldown/Pullup
Type: S Strapping Pin (All strap pins have weak in-

ternal pu ll-ups or pull- downs. If the default
strap value is needed to b e changed then an
external 2.2 kΩ resistor should be used.
Please see Section 1.6 for details.)

Signal Name Type Pin # Description

MDC I 25 MANAGEMENT DATA CLOCK: Synchronous clock to the M DIO

management data input/output serial interface which may be
asynchronous to transmit and receive clocks. The maximum clock
rate is 25 MHz with no minimum clock rate.

MDIO I/O 24 MANAGEMENT DATA I/O: Bi-dir ectional management instru c-

tion/data signal th at may be s ourc ed by th e st atio n m ana gem en t
entity or the PHY. This pin requires a 1.5 kΩ pullup resistor.

Signal Name Type Pin # Description

TX_CLK O 2 MII TRANSMIT CLOCK: 25 MHz Transmit clock output in 100

Mb/s mode or 2.5 MHz in 10 Mb/s mode de rived from t he 25 MHz
reference clock.

TX_EN I, PD 3 MII TRANSMIT ENABLE: Active high input indicates the pres-

ence of valid data inputs on TXD[3:0].
TXD_0
TXD_1

TXD_2
TXD_3

I

I, PD

4
5
6
7

MII TRANSMIT DATA: Transmit dat a MII input pins , TXD[3:0],

that accept data sync hronous to the TX_CL K (2.5 MHz in 10 Mb/s

mode or 25 MHz in 100 Mb/s mode).

RX_CLK O 31 MII RECEIVE CLOCK: Provides th e 25 MHz recover ed receive

clocks for 100 Mb/s mode and 2.5 MHz for 10 Mb/s mode.
RX_DV O, PD 32 MII RECEIVE DATA VALID: Asserted high to indic ate tha t vali d

data is present on the corresponding RXD[3:0].
RX_ER S, O, PU 34 MII RECEIVE ERROR: Asserted high synchronously to RX_CLK

to indicate that an invalid symbol has been detected within a re-

ceived packet in 100 Mb/s mode.
RXD_0
RXD_1
RXD_2

RXD_3

S, O, PD 36

37
38
39

MII RECEIVE DATA: Nibble wide receiv e data signals d riven syn-

chronously to the RX_CL K , 25 MH z for 1 00 M b/s mod e, 2. 5 MHz

for 10 Mb/s mode). RXD[3:0] signals contain valid data when

RX_DV is asserted.

CRS/LED_CFG S, O, PU 33 MII CARRIER SENSE: Asserted high to indicate the receive me-

dium is non-idle.

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DP83848H

1.3 Clock Interface

1.4 LED Interface

See Table 3 for LED Mode Selection.

1.5 Reset

COL S, O, PU 35 MII COLLISION DETECT: Asserted high to indica te de tec t io n of

a collision condition (simultaneous transmit and receive activity)
in 10 Mb/s and 100 Mb/s Half Duplex Modes.

While in 10BASE-T Half Dup lex mode with hea rtbeat enabled t his
pin is also asserted f or a duration of a pproximately 1µs at the end
of transmission to indicate heartbeat (SQE test).

In Full Duplex Mode, for 10 Mb/s or 100 Mb/s operation, this sig­nal is always logic 0. There is no heartbeat function during 10
Mb/s full duplex operation.

Signal Name Type Pin # Description

Signal Name Type Pin # Description

X1 I 28 CRYSTAL/OSCILLATOR INPUT: This pin is the primary clock

reference input for t he DP83848H a nd must be c onnected to a 25
MHz 0.005% (+

50 ppm) clock source. The DP83848H supports
either an external crystal res onator connected across pins X1 and
X2, or an external CMOS-level oscillator source connected to pin
X1 only.

X2 O 27 CRYSTAL OUTPUT: This pin is the primary clock reference out-

put to connect to an external 25 MHz crystal resonator device.
This pin must be l eft unc on nec ted if an external CMOS osc il la t or
clock source is used.

25MHz_OUT O 21 25 MHz CLOCK OUTPUT:

This pin provides a 25 MHz clock output to the system.
This allows other devices to use the reference clock from the

DP83848H without requiring additional clock sources.

Signal Name Type Pin # Description

LED_LINK S, O, PU 22 LINK LED: In Mode 1, this pin indicates the status of the LINK.

The LED will be ON when Link is good.
LINK/ACT LED: In Mode 2, this pin indicates trans mit and receive

activity in addition to the status of the Link. The LED will be ON
when Link is good. It will blink when the transmitter or receiver is
active.

Signal Name Type Pin # Description

RESET_N I, PU 23 RESET: Active Low input that initializes or re-initializes the

DP83848H. Asserting th is pin low for at least 1 µs will f orce a reset
process to occur. All internal registers will re-initialize to their de­fault states as specified fo r each bit in the Register Blo ck sectio n.
All strap options are re-initialized as well.

11 www.national.com

DP83848H

1.6 Strap Options

DP83848H uses many functional pins as strap options.
The values of these pins are sampled during reset and
used to strap the device into specific modes of operation.
The strap option pin assignments are defined below. The
functional pin name is indicated in parentheses.

A 2.2 kΩ resistor should be used for pull-down or pull-up to
change the default strap option. If the default option is
required, then there is no need for external pull-up or pull
down resistors. Since these pins may have alternate func­tions after reset is deasserted, they should not be con­nected directly to VCC or GND.

Signal Name Type Pin # Description

PHYAD0 (COL)
PHYAD1 (RXD_0)
PHYAD2 (RXD_1)
PHYAD3 (RXD_2)
PHYAD4 (RXD_3)

S, O, PU
S, O, PD

35
36
37
38
39

PHY ADDRESS [4:0]: The DP83848H provides five PHY ad­dress pins, the state of w hi ch ar e la tch ed in to th e PH YCTR L reg ­ister at system Hardware-Reset.

The DP83848H supports PHY Address strapping values 0
(<00000>) through 31 (<11111 >). A PHY Address of 0 puts the
part into the MII Isolate Mode. The MII isolate mod e must be se ­lected by strapping Phy Addres s 0; changing to Addres s 0 by reg­ister write will not p ut the Phy in the MII is olate mode. Plea se refer
to section 2.3 for additional information.

PHYAD0 pin has weak internal pull-up resistor.
PHYAD[4:1] pins have weak internal pull-down resistors.

AN0 (LED_LINK) S, O, PU 22 This input pin controls the advertised operating mode of the

DP83848H accordin g to the followin g table. The value on thi s pin
is set by connecting it to GND (0) or V

CC

(1) through 2.2 kΩ resis-

tors. This pin should NEVER be connected directly to GND or

VCC.

The value set at this input is latched into the DP83848H at Hard­ware-Reset.

The float/pull-down status of this pin is latched into the Basic
Mode Control Register and the Auto_Negotiation Advertisement
Register during Hardware-Reset.

The default is 1 since this pin has an internal pull-up.

LED_CFG (CRS) S, O, PU 33 LED CONFIGURATION: This strapping option determines the

mode of operation of the LED pins . Default is Mode 1. Mode 1 and
Mode 2 can be controlled via the s trap opti on. All m odes are con­figurable via register ac cess.

SeeTable 3 for LED Mode Selection.

MDIX_EN (RX_ER) S, O, PU 34 MDIX ENABLE: Default is to enable MDIX. This strapping option

disables Auto-MDIX. An external pull-down will disable Auto­MDIX mode.

AN0 Advertised Mode

0 10BASE-T Half-Duplex

100BASE-TX, Half-Duplex

1 10BASE-T, Half/Full-Duplex

100BASE-TX, Half/Full-Duplex

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DP83848H

1.7 10 Mb/s and 100 Mb/s PMD Interface

1.8 Special Connections

1.9 Power Supply Pins

Signal Name Type Pin # Description

TD-, TD+ I/O 14, 15 Differential common driver transmit output (PMD Output Pair).

These differential outputs are automatically configured to either
10BASE-T or 100BASE-TX signaling.

In Auto-MDIX mode of operati on, this pair can be used as th e Re­ceive Input pair.

These pins require 3.3V bias for operation.

RD-, RD+ I/O 11, 12 Differential receive input (PMD Input Pair). These differential in-

puts are automatically configured to accept either 100BASE-TX
or 10BASE-T signaling.

In Auto-MDIX mode of operation, this pair can be used as the
Transmit Output pair.

These pins require 3.3V bias for operation.

Signal Name Type Pin # Description

RBIAS I 20 Bias Resist or Con nectio n. A 4 .87 kΩ 1% resistor should be con-

nected from RBIAS to GND.

PFBOUT O 19 Power Feedback Output. Parallel caps, 10µ F (Tantalum pre-

ferred) and 0.1µF, should be placed close to the PFBOUT. Con­nect this pin to PFBIN1 (pin 16) and PFBIN2 (pin 30). See
Section 5.4 for proper placement pin.

PFBIN1
PFBIN2

I1630Power Feedback Input. These pins are fed with power from

PFBOUT pi n. A small capaci tor of 0.1µF should be connected
close to each pin.

Note: Do not supply power to these pins other than from
PFBOUT.

RESERVED I/O 8,9,10 RESERVED: These pins must be left unconnected.

Signal Name Pin # Description

IOVDD33 1, 26 I/O 3.3V Supply
IOGND 40 I/O Ground
DGND 29 Digital Ground
AVDD33 18 Analog 3.3V Supply
AGND 13, 17 Analog Ground

13 www.national.com

DP83848H

1.10 Package Pin Assignments

NSQAu040

Pin #

Pin Name

1IO_VDD
2TX_CLK
3 TX_EN
4TXD_0
5TXD_1
6TXD_2
7TXD_3
8 RESERVED

9 RESERVED
10 RESERVED
11 RD­12 RD+
13 AGND
14 TD ­15 TD +
16 PFBIN1
17 AGND
18 AVDD33
19 PFBOUT
20 RBIAS
21 25MHz_OUT
22 LED_LINK/AN0
23 RESET_N
24 MDIO
25 MDC
26 IOVDD33
27 X2
28 X1
29 DGND
30 PFBIN2
31 RX_CLK
32 RX_DV
33 CRS/LED_CFG
34 RX_ER/MDIX_EN
35 COL/PHYAD0
36 RXD_0/PHYAD1
37 RXD_1/PHYAD2
38 RXD_2/PHYAD3
39 RXD_3/PHYAD4
40 IOGND

www.national.com 14

DP83848T

2.0 Configuration

This section include s infor mat ion on t he vari ous co nfigura ­tion options available with the DP83848H. The configura­tion options described below include:

— Auto-Negotiation
— PHY Address and LED
— Half Duplex vs. Full Duplex
— Isolate mode
— Loopback mode
—BIST

2.1 Auto-Negotiation

The Auto-N egotiation fu nction provid es a mechanism for
exchanging configuration information between two ends
of a link segment and automatically selecting the highest
performance mode of operation supported by both
devices. Fast Link Pulse (FLP) Bursts provide the signal­ling used to communicate Auto-Negotiation abilities
between two devices at each end of a link segment. For
further detail regarding Auto-Negotiation, refer to Clause
28 of the IEEE 802.3u specification. The DP83848H sup­ports four different Ethernet protocols (10 Mb/s Half
Duplex, 10 Mb/s Full Duplex, 100 Mb/s Half Duplex, and
100 Mb/s Full Duplex), so the inclusion of Auto-Negotia­tion ensures that the highest performance protocol will be
selected based on the advertised ability of the Link Part­ner. The Auto-Negotiation function within the DP83848H
can be controlled either by internal register access or by
the use of the AN0 pin.

2.1.1 Auto-Negotiation Pin Control

The state of AN0 determine s the spe cif ic mode adverti se d
by DP83848H as given in Table 1. The state of AN 0 , upo n
power-up/reset, determines the state of bits [8:5] of the
ANAR register.

The Auto-Negotiation function selected at power-up or
reset can be changed at any time by writing to the Basic
Mode Control Register (BMCR) at address 0x00h

2.1.2 Auto-Negotiation Register Control

When Auto-Negotiation is enabled, the DP83848H trans­mits the abilities programmed into the Auto-Negotiation
Advertisement register (ANAR) at address 04h via FLP
Bursts. Any combination of 10 Mb/s, 100 Mb/s, Half­Duplex, and Full Duplex modes may be selected.

Auto-Negotiation Priority Resolution:
— (1) 100BASE-TX Full Duplex (Highest Priority)

— (2) 100BASE-TX Half Duplex
— (3) 10BASE-T Full Duplex
— (4) 10BASE-T Half Duplex (Lowest Priority)
The Basic Mode Control Register (BMCR) at address 00h

provides control for enabling, disabling, and restarting the
Auto-Negotiation process. When Auto-Negotiation is dis­abled, the Speed Selection bit in the BMCR controls
switching between 10 Mb/s or 100 Mb/s operation, and
the Duplex Mode bit controls switching between full
duplex operation and half duplex operation. The Speed
Selection and Duplex Mode bits have no effect on the
mode of operation when the Auto-Negotiation Enable bit
is set.

The Link Speed can be examined through the PHY Status
Register (PHYSTS) at address 10h after a Link is
achieved.

The Basic Mode Status Register (BMSR) indicates the set
of available abilities for technology types, Auto-Negotia­tion ability, and Extended Register Capability. These bits
are permanently set to indicate the full functionality of the
DP83848H (only the 100BASE-T4 bit is not set since the
DP83848H does not support that function).

The BMSR also provides status on:
— Completion of Auto-Negotiation
— Occurence of a remote fault as advertised by the Link

Partner
— Establishment of a valid link
— Support for Management Frame Preamble suppr ession
The Auto-Negotiation Advertisement Register (ANAR)

indicates the Auto-Neg otia tio n ab ili ties to be advertised by
the DP83848H. All available abilities are transmitted by
default, but any ability can be s uppressed by writing to the
ANAR. Updating the ANAR to suppress an ability is one
way for a management ag en t to cha nge (restrict) the tech­nology that is used.

The Auto-Negotiation Link Partner Ability Register
(ANLPAR) at address 05h is used to receive the base link
code word as well as all next page code words during the
negotiation. Furthermore, the ANLPAR will be updated to
either 0081h or 0021h for parallel detection to either 100
Mb/s or 10 Mb/s respectively.

The Auto-Negotiation Expansion Register (ANER) indi­cates additional Auto-Negotiation status. The ANER pro­vides status on:

— Occurance of a Parallel Detect Fault
— Next Page function support by the Link Partner
— Next page support function by DP83848H
— Reception of the current page that is exchanged by

Auto-Negotiation
— Auto-Negotiation support by the Link Partner

Table 1. Auto-Negotiation Modes

AN0 Advertised Mode

0 10BASE-T Half-Duplex

100BASE-TX, Half-Duplex

1 10BASE-T, Half/Full-Duplex

100BASE-TX, Half/Full-Duplex

15 www.national.com

DP83848H

2.1.3 Auto-Negotiation Parall el Detection

The DP83848H supports the Parallel Detection function as
defined in the IEEE 802.3u specifi ca tio n. Para lle l Detec tion
requires both the 10 Mb/s and 100 Mb/s receivers to moni­tor the receive signal and report link status to the Auto­Negotiation function. Auto-Negotiation uses this informa­tion to configure th e correct t echno logy i n the e vent that th e
Link Partner does not support Auto-Negotiation but is
transmitting link signals that the 100BASE-TX or 10BASE­T PMAs recognize as valid link signa ls .

If the DP83848H completes Auto-Negotiation as a result of
Parallel Detection, bit 5 or bit 7 within the ANLPAR register
will be set to reflect the mode of operation present in the
Link Partner. Note that bits 4:0 of the ANLPAR will also be
set to 00001 based on a successful parallel detection to
indicate a valid 802.3 selector field. Software may deter­mine that negotiation completed via Parallel Detection by
reading a zero in the Link Partn er Au to-Neg oti ati on Ab le b it
once the Auto-Negotiatio n Com pl ete b it i s s et. I f co nfi gure d
for parallel detect mode and any condition other than a sin­gle good link occurs then the parallel detect fault bit will be
set.

2.1.4 Auto-Negotiat ion Restart

Once Auto-Negotiation has completed, it may be restarted
at any time by setting bit 9 (Res tart Auto-Ne gotiat ion) of th e
BMCR to one. If the mode confi gured b y a su ccessfu l Auto­Negotiation loses a valid link, then the Auto-Negotiation
process will resume and attempt to determine the configu­ration for the link. This function ensures that a valid config­uration is maintained if the cable becomes disconnected.

A renegotiation requ es t fro m any en tity, such as a manage­ment agent, will cause the DP83848H to halt any transmit
data and link pulse activity until the break_link_timer
expires (~1500 ms). Consequently, the Link Partner will go
into link fail and normal Auto-Negotiation resumes. The
DP83848H will resume Auto-Negotiation after the
break_link_timer has expired by issuing FLP (Fast Link
Pulse) bursts.

2.1.5 Enabling Auto-Negotiation via Software

It is important t o no te t hat if the DP83848H has be en initial­ized upon power-up as a non-auto-negotiating device
(forced technology), and it is then requ ire d that Auto-Nego­tiation or re-Auto-Negotiation be initiated via software,
bit 12 (Auto-Negotiation Enable) of the Basic Mode Control
Register (BMCR) must first be cleared and then set for any
Auto-Negotiation function to take effect.

2.1.6 Auto-Negotiation Complete Time

Parallel detection and Auto-Negotiation take approximately
2-3 seconds to co mp let e. In addition, Auto-Negotia tio n w i th
next page should take approximately 2-3 seconds to com­plete, depending on the number of next pages sent.

Refer to Clause 28 of the IEEE 802.3u standard for a full
description of the individual timers related to Auto-Negotia­tion.

2.2 Auto-MDIX

When enabled, this function utilizes Auto-Negotiation to
determine the proper configuration for transmission and
reception of data and subsequently selects the appropriate
MDI pair for MD I/ MD IX o per a ti on. T h e fu nc t io n us es a r an ­dom seed to control switching of the crossover circuitry.
This implementati on co mpl ie s with the corres po ndi ng IEEE

802.3 Auto-Negotiation and Crossover Specifications.
Auto-MDIX is enabled by default and can be configu r ed vi a

strap or via PHYCR (0x19h) register, bits [15:14].
Neither Auto-Negotiation nor Auto-MDIX is required to be

enabled in forcing crossover of the MDI pairs. Forced
crossover can be achieved through the FORCE_MDIX bit,
bit 14 of PHYCR (0x19h) register.

Note: Auto-MDIX will not work in a forced mode of opera­tion.

www.national.com 16

DP83848T

2.3 PHY Address

The 5 PHY address inputs pins are shared with the
RXD[3:0] pins and COL pin as shown below.

The DP83848 H can be set to res pond to an y of 32 po ssi­ble PHY addresses via strap pins. The information is
latched into the PHYCR register (address 19h, bits [4:0])
at device power-up and hardware reset. The PHY
Address pins are shared with the RXD and COL pins.
Each DP83848H or port sharin g an MD I O bu s in a syst em
must have a unique physical address.

The DP83848H support s PHY Address strapping values 0
(<00000>) through 31 (<11111>). S trapp in g PHY Ad dress
0 puts the p art into I solate Mode . It s hould al so be note d
that selecting PHY Address 0 via an MDIO write to
PHYCR will not put the device in Isolate Mode. See
Section 2.3.1 for more information.

For further detail relating to the latch-in timing require­ments of the PHY Address pins, as well as the oth er hard ­ware configuration pins, refer to the Reset summary in
Section 6.0.

Since the PHYAD[0] pin has weak internal pull-up resistor
and PHYAD[4:1] pins have weak internal pull-down resis­tors, the default setting for the PHY address is 00001
(01h).

Refer to Figure 2 for an example of a PHYAD connection
to external components. In this example, the PHYAD
strapping results in address 00011 (03h).

2.3.1 MII Isolate Mode

The DP83848H can be put into MII Isolate mode by writ­ing to bit 10 of the BMCR register or by strapping in Phys­ical Address 0. It should be noted that selecting Physical
Address 0 via an MDIO write to PHYCR will not put the
device in the MII isolate mode.

When in the MII isolate mode, the DP83848H does not
respond to packet dat a p resent a t TXD[3:0], T X_EN in put s
and presents a high imp edanc e on the TX_C LK, RX_ CLK,
RX_DV, RX_ER, RXD[3:0], COL, and CRS outputs. When
in Isolate mode, the DP83848H will continue to respond to
all management transactions.

While in Isolate mode, the PMD output pair will not trans­mit packet data but will continue to source 100BASE-TX
scrambled idles or 10BASE-T normal link pulses.

The DP83848 H can Auto -Nego tiate or parall el dete ct to a
specific technology depending on the receive signal at the
PMD input pair. A valid link can be established for the
receiver even when the DP83848H is in Isolate mode.

Table 2. PHY Address Mapping

Pin # PHYAD Function RXD Function

35 PHYAD0 COL
36 PHYAD1 RXD_0
37 PHYAD2 RXD_1
38 PHYAD3 RXD_2
39 PHYAD4 RXD_3

Figure 2. PHYAD Strapping Example

COL

RXD_0

RXD_1

RXD_2

RXD_3

VCC

2.2kΩ

PHYAD0 = 1

PHYAD1 = 1

PHYAD2 = 0PHY AD3 = 0

PHYAD4= 0

17 www.national.com

DP83848H

2.4 LED Interface

The DP83848H supports a configurable Light Emitting
Diode (LED) pin for configuring the link. The PHY Control
Register (PHYCR) for the LED can also be selected
through address 19h, bit [5].

See Table 3 for LED Mode selection.

The LED_LINK pin in Mode 1 indicates the link status of
the port. In 100BASE-T mode, link is established as a
result of input receive amplitude compliant with the TP­PMD specifications which will result in internal generation
of signal detect. A 10 Mb/s Link is est abli shed as a result of
the reception of at least seven consecutive normal Link
Pulses or the reception of a valid 10BASE-T packet. This
will cause the as se rtion of LED_LINK. L E D_LIN K w il l d ea s­sert in accordance with the Link Loss Timer as specified in
the IEEE 802.3 specification.

The LED_LINK p in in Mo de 1 w ill be OF F w h en no LI NK is
present.

The LED_LINK pin in Mode 2 will be ON to indicate Link is
good and BLINK to indicate activity is present on either
transmit or receive activity.

Since the LED_LINK pin is also used as a strap option, the
polarity of the LED is dependent on whether the pin is
pulled up or down.

2.4.1 LED

Since the Auto-Negotiation (AN0) strap option shares the
LED_LINK output pin, the external components required
for strapping and LED usage must be considered in order
to avoid contention.

Specifically, when the LED output is used to drive the LED
directly, the active state of the output driver is dependent
on the logic level sampled by the AN0 input upon power­up/reset. For example, if the AN0 input is resistively pulled
low then the corresponding output will be configured as an
active high driver. Conversely, if the AN0 input is resistively
pulled high, then the corresponding output will be config­ured as an active low driver.

Refer to Figure 3 for an example of AN0 connection to
external components. In this example, the AN0 strapping
results in Auto-Negotiation with 10/100 Half/Full-Duplex
advertised.

The adaptive nature of the LED output helps to simplify
potential implementation issues of this dual purpose pin..

2.4.2 LED Direct Control

The DP83848H provides another option to directly control
thel LED output through the LED Direct Control Register
(LEDCR), address 18h. The register does not provide read
access to the LED.

Table 3. LED Mode Select

Mode LED_CFG[0]

(bit 5)

or (pin40)

LED_LINK

1 1 ON for Good Link

OFF for No Link

2 0 ON for Good Link

BLINK for Activity

LED_LINK

VCC

110Ω

AN0 = 1

2.2kΩ

Figure 3. AN0 Strapping and LED Loading Example

www.national.com 18

DP83848T

2.5 Half Duplex vs. Full Duplex

The DP83848H supports both half and full duplex opera­tion at both 10 Mb/s and 100 Mb/s speeds.

Half-duplex relies on th e CSMA/CD pro tocol to handle col­lisions and network access. In Half-Duplex mode, CRS
responds to both transmit and receive activity in order to
maintain compliance with the IEEE 802.3 specification.

Since the DP83848H is designed to support simultaneous
transmit and receive ac tivity it is cap abl e of sup porting full­duplex switched applications with a throughput of up to
200 Mb/s per port when operating in 100BASE-TX mode.
Because the CSMA/CD protocol does not apply to full­duplex operation, the DP83848H disables its own internal
collision sensing and reporting functions and modifies the
behavior of Carrier Sense (CRS) such that it indicates
only receive activity. This allows a full-duplex capable
MAC to operate properly.

All modes of operation (100BASE-TX and 10BASE- T) ca n
run either half-duplex or full-duplex. Additionally, other
than CRS and Collision rep orti ng, al l rem ai nin g MII signal­ing remains the same regardless of the selected duplex
mode.

It is important to understand that while Auto-Negotiation
with the use of Fast Link Pulse code words can interpret
and configure to full-duplex operation, parallel detection
can not recognize the difference between full and half­duplex from a fixed 10 Mb/s or 100 Mb/s link partner over
twisted pair. As specif ied in the 802.3u specification , if a
far-end link partner is configured to a forced full duplex
100BASE-TX ability, the parallel detection state machine
in the partner would be unable to detect the full duplex
capability of the far-end link partner. This link segment
would negotiate to a half duplex 100BASE-TX configura­tion (same scenario for 10 Mb/s).

2.6 Internal Loopback

The DP83848H includes a Loopback Test mode for facili­tating system diagnostics. The Loopback mode is
selected through bit 14 (Loopback) of the Basic Mode
Control Register (BMCR). Writing 1 to this bit enables MII
transmit data to be routed to the MII receive outputs.
Loopback status may be checked in bit 3 of the PHY Sta­tus Register (PHYSTS). While in Loop bac k m ode the data
will not be transmitted onto the media. To ensure that the

desired operating mode is maintained, Auto-Negotiation
should be disabled before selecting the Loopback mode.

2.7 BIST

The DP83848H incorporates an internal Built-in Self Test
(BIST) circuit to accommodate in-circuit testing or diag­nostics. The BIST circuit can be utilized to test the integ­rity of the transmit and receive data paths. BIST testing
can be performed with the part in the internal loopback
mode or externally looped back using a loopback cable
fixture.

The BIST is implemented with independent transmit and
receive paths, with the transmit block generating a contin­uous stream of a pseudo ran dom seq uen ce . The us er ca n
select a 9 bit or 15 bit pseudo random sequence from the
PSR_15 bit in the PHY Control Register (PHYCR). The
received data is compared to the generated pseudo-ran­dom data by the BIST Linear Feedback Shift Register
(LFSR) to determine the BIST pass/fail status.

The pass/fail status of the BIST is stored in the BIST sta­tus bit in the PHYCR register. The status bit defaults to 0
(BIST fail) and will transition on a successful comparison.
If an error (mis-compare) occurs, the status bit is latched
and is cleared upon a subsequent write to the Start/Stop
bit.

For transmit VOD testing, the Packet BIST Continuous
Mode can be used to allow continuous data transmission,
setting BIST_CONT_MODE, bit 5, of CDCTRL1 (0x1Bh).

The number of BIST errors can be monitored through the
BIST Error Count in the CDCTRL1 (0x1Bh), bits [15:8].

19 www.national.com

DP83848H

3.0 Functional Description

The DP83848H supports MII mode of operation using the
MII interface pins. The MII mode uses 25 MHz clock.

In the MII mode, the IEEE 802.3 serial management inter­face is operational for device configuration and status. The
serial management interface of the MII allows for the con­figuration and control of multiple PHY devices, gathering of
status, error information, and the determination of the type
and capabilities of the attached PHY(s).

3.1 MII Interface

The DP83848H incorporates the Media Independent Inter­face (MII) as specified in Clause 22 of the IEEE 802.3u
standard. This interface may be used to connect PHY
devices to a MAC in 10/100 Mb/s systems. This section
describes the nibble wide MII data interface.

The nibble wide MII data interface c ons is t s of a receive bus
and a transmit bus each with control signals to facilitate
data transfer between the PHY and the upper layer (MAC).

3.1.1 Nibble-wide MII Data Interface

Clause 22 of the IEEE 802.3u specification defines the
Media Independent Interface. This interface includes a
dedicated recei ve bu s an d a d edicated transmit b us . These
two data buses, along with various control and status sig­nals, allow for the simultaneous exchange of data between
the DP83848H and the upper layer agent (MAC).

The receive interface consists of a nibble wide data bus
RXD[3:0], a receive error signal RX_ER, a receive data
valid flag RX_DV, and a receive clock RX_CLK for syn­chronous transfer of the data. The receive clock operates
at either 2.5 MHz to su pport 10 Mb/s operation mo des or at
25 MHz to support 100 Mb/s operational modes.

The transmit interface consists of a nibble wide data bus
TXD[3:0], a transmit enable control signal TX_EN, and a
transmit cloc k TX_CL K which runs at ei ther 2. 5 MHz or 25
MHz.

Additionally, the MII includes the carrier sense signal CRS,
as well as a collision detect signal COL. The CRS signal
asserts to ind icate the re ception of d ata from the ne twork
or as a function of transmit data in Half Duplex mode. The
COL signal asse rt s as an ind ic atio n of a collision which can
occur during half-duplex operation when both a transmit
and receive operation occur simultaneously.

3.1.2 Collision Detect

For Half Duplex, a 10BASE-T or 100BASE-TX collision is
detected when the receive and transmit channels are
active simu ltaneously. Collisions are reported by the COL
signal on the MII.

If the DP83848H is transmitting in 10 Mb/s mode when a
collision is dete ct ed, the c ollision is not repo rted un til s eve n
bits have been received while in the collision state. This
prevents a collision being reported incorrectly due to noise
on the network. The COL signal remains set for the dura­tion of the collision.

If a collision occ urs du ring a rec eiv e o pera tio n, it is immedi­ately reported by the COL signal.

When heartbeat is enabled (only applicable to 10 Mb/s
operation), approximately 1µs after the transmission of
each packet, a Si gn al Q u ali ty Error (SQE) signal of approx ­imately 10 bit times is generated (internally) to indicate
successful transmiss io n. SQ E is repo rted as a pul se on th e
COL signal of the MII.

3.1.3 Carrier Sense

Carrier Sense (CRS) is asserted due to receive activity,
once valid data is detected via the squelch function during
10 Mb/s operation. During 100 Mb/s operation CRS is
asserted when a valid link (SD) and two non-contiguous
zeros are detected on the line.

For 10 or 100 Mb/s Half Duple x op era tio n, C RS is a sserte d
during either packet trans mission or re ception.

For 10 or 100 Mb/s Full Duplex operation, CRS is asserted
only due to receive activity.

CRS is deasserted following an end of packet.

3.2 802.3u MII Serial Management Interface

3.2.1 Serial Management Register Access

The serial management MII specification defines a set of
thirty-two 16-bit status and control registers that are acces­sible through the management interface pins MDC and
MDIO. The DP83848H implements all the required MII reg­isters as well as several optional registers. These registers
are fully described in Sect ion 7.0. A description of the serial
management access protocol follows.

3.2.2 Serial Management Access Protocol

The serial control interface consists of two pins, Manage­ment Data Clock (MDC) and Management Data Input/Out­put (MDIO). MDC has a maximum clock rate of 25 MHz
and no minimum rate. The MDIO line is bi-directional and
may be shared by up to 32 devices. The MDIO frame for­mat is shown below in Table 4.

The MDIO pin requires a pull-up resistor (1.5 kΩ) which,
during IDLE and turnaro und, will pull M DIO hi gh. In o rder to
initialize the MDIO int erface , the st atio n manag ement entit y
sends a sequence of 32 contiguous logic ones on MDIO to
provide the DP83848H with a sequence that can be used
to establish sy nchr oniz ati on. Th is pr eamb le may be gene r­ated either by driving MDIO high for 32 consecutive MDC
clock cycles, or by simply allowing the MDIO pull-up resis­tor to pull the MDIO pin high during which time 32 MDC
clock cycles are provided. In addition, 32 MDC clock cycles
should be used to re-sync the device if an invalid start,
opcode, or turnaround bit is detected.

The DP83848H waits until it has received this preamble
sequence before responding to any other transaction.
Once the DP83848H serial management port has been ini­tialized no further preamble sequencing is required until
after a power-on/reset, invalid Start, invalid Opcode, or
invalid turnaround bit has occurred.

The St art co de is in dic ate d by a <01> p atte rn. Th is assures
the MDIO line transitions from the default idle line state.

www.national.com 20

DP83848T

Turnaround is defined as an idle bit time inserted between
the Register Address field and the Data field. To avoid
contention during a read transaction, no device shall
actively drive the MDIO signal during the first bit of Turn­around. The addressed DP83848H drives the MDIO with
a zero for the second bit of turnaround and follows this
with the required data. Figure 4 shows the timing relation­ship between MDC and the MDIO as driven/received by
the Station (STA) and the DP83848H (PHY) for a typical
register read access.

For write transactions, the station management entity
writes data to the addressed DP83848H thus eliminating
the requirement for MDIO Turnaround. The Turnaround
time is filled by the management entity by inserting <10>.
Figure 5 shows the timing relationship for a typical MII
register write access.

3.2.3 Serial Management Preamble Suppression

The DP83848H supports a Preamble S uppression mode
as indicated by a one in bit 6 of the Basic Mode Status
Register (BMSR, addre ss 01 h.) If the station mana gem en t
entity (i.e. MAC or other management controller) deter­mines that all PHYs in the system support Preamble Sup­pression by returning a one in this bit, then the station
management entity need not generate preamble for each
management transaction.

The DP83848H requires a single initializa tion sequence of
32 bits of preamble following hardware/software reset.
This requirement is generally met by the mandatory pull­up resistor on MDIO in conjunction with a continuous
MDC, or the management access made to determine
whether Preamble Suppression is supported.

While the DP83848H requires an initial preamble
sequence of 32 bits for management initialization, it does
not require a full 32-bit sequence between each subse­quent transaction. A minimum of one idle bit between
management transactions is required as specified in the
IEEE 802.3u specification.

Table 4. Typical MDIO Frame Format

MII Management

Serial Protocol

<idle><start><op code><device addr><reg addr><turnaround><data><idle>

Read Operation <idle><01><10><AAAAA><RRRRR><Z0><xxxx xxxx xxxx xxxx><idle>
Write Operation <idle><01><01><AAAAA><RRRRR><10><xxxx xxxx xxxx xxxx><idle>

Figure 4. Typical MDC/MDIO Read Operation

Figure 5. Typical MDC/MDIO Write Operation

MDC

MDIO

00011 110000000

(STA)

Idle Start

Opcode

(Read)

PHY Address

(PHYAD = 0Ch)

Register Address

(00h = BMCR)

TA

Register Data

Z

MDIO

(PHY)

Z

Z

Z

0 0 011000100000000

Z

Idle

Z

Z

MDC

MDIO

00011110000000

(STA)

Idle Start

Opcode

(Write)

PHY Address

(PHYAD = 0Ch)

Register Address

(00h = BMCR)

TA

Register Data

Z

0 0 0 000 00000000

Z

Idle

1000

ZZ

21 www.national.com

DP83848H

4.0 Architecture

This section describes the operations within each trans­ceiver module, 100BASE-TX and 10BASE-T. Each opera­tion consists of several functional blocks and described in
the following:

— 100BASE-TX Transmitter
— 100BASE-TX Receiver
— 10BASE-T Transceiver Module

4.1 100BASE-TX TRANSMITTER

The 100BASE-TX transmitter consists of several functional
blocks which conver t sync hronous 4-bit ni bble d at a, as p ro­vided by the MII, to a scrambled MLT-3 125 Mb/s serial
data stream. Because the 100BASE-TX TP-PMD is inte­grated, the differential output pins, PMD Output Pair, can
be directly routed to the magnetics.

The block diagram in Figure 6. provides an overview of
each functional block within the 100BASE-TX transmit sec­tion.

The Transmitter section consists of the following functional
blocks:

— Code-group Encoder and Injection block
— Scrambler block (bypass option)
— NRZ to NRZI encoder block
— Binary to MLT-3 converter / Common Driver
The bypass option for the functional blocks within the

100BASE-TX transmitter provides flexibility for applications
where data conversion is not always required. The
DP83848H implements the 100BASE-TX transmit state
machine diagram as specified in the IEEE 802.3u Stan­dard, Clause 24.

Figure 6. 100BASE-TX Transmit Block Diagram

4B5B CODE-GROUP

ENCODER &

INJECTOR

SCRAMBLER

NRZ TO NRZI

ENCODER

5B PARALLEL

TO SERIAL

PMD OUTPUT PAIR

TX_CLK

TXD[3:0] /

TX_EN

BINARY TO

MLT-3 /

COMMON

DRIVER

125MHZ CLOCK

BP_SCR

MUX

100BASE-TX

LOOPBACK

MLT[1:0]

DIVIDE

BY 5

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DP83848T

Table 5. 4B5B Code-Group Encoding/Decoding

DATA CODES

0 11110 0000
1 01001 0001
2 10100 0010
3 10101 0011
4 01010 0100
5 01011 0101
6 01110 0110
7 01111 0111
8 10010 1000

9 10011 1001
A 10110 1010
B 10111 1011
C 11010 1100
D 11011 1101
E 11100 1110
F 11101 1111

IDLE AND CONTROL CODES

H 00100 HALT code-group - Error code

I 11111 Inter-Packet IDLE - 0000 (

Note 1)

J 11000 First Start of Packet - 0101 (Note 1)
K 10001 Second Start of Packet - 0101 (Note 1)
T 01101 First End of Packet - 0000 (Note 1)
R 00111 Second End of Packet - 0000 (Note 1)

INVALID CODES

V 00000
V 00001
V 00010
V 00011
V 00101
V 00110
V 01000
V 01100

Note: Control code-groups I, J, K, T and R in data fields will be mapped as invalid codes, together with RX_ER as­serted.