NSC DP83846AVHG Datasheet
Preliminary
April 2000
DP83846A DsPHYTER® — Single 10/100 Ethernet Transceiver
DP83846A DsPHYTER® — Single 10/100 Ethernet Transceiver
General Description
The DP83846A is a full feature single Physical Layer
device with integrated PMD sublayers to support both
10BASE-T and 100BASE-TX Ethernet protocols over Category 3 (10 Mb/s) or Category 5 unshielded twisted pair
cables.
The DP83846A is designed for easy implementation of
10/100 Mb/sEthernet home or office solutions. Itinterfaces
to Twisted Pair media via an external transformer. This
device interfaces directly to MAC devices through the IEEE
802.3u standard Media Independent Interface (MII) ensuring interoperability between products from different vendors.
The DP83846A utilizes on chip Digital Signal Processing
(DSP) technology and digital Phase Lock Loops (PLLs) for
robust performance under all operating conditions,
enhanced noise immunity, and lower external component
count when compared to analog solutions.
Features
■ IEEE 802.3 ENDEC, 10BASE-T transceivers and filters
■ IEEE 802.3u PCS, 100BASE-TX transceivers and filters
■ IEEE 802.3 compliant Auto-Negotiation
■ Output edge rate control eliminates external filtering for
Transmit outputs
■ BaseLine Wander compensation
■ 5V/3.3V MAC interface
■ IEEE 802.3u MII (16 pins/port)
■ LED support (Link, Rx, Tx, Duplex, Speed, Collision)
■ Single register access for complete PHY status
■ 10/100 Mb/s packet loopback BIST (Built in Self Test)
■ Low-power 3.3V, 0.35um CMOS technology
■ 5V tolerant I/Os
■ 80-pin LQFP package (12w) x (12l) x (1.4h) mm
System Diagram
DP83846A
Clock
10/100 Mb/s
DsPHYTER
Status
LEDs
Typical DsPHYTER application
Ethernet MAC
MII
25 MHz
PHYTER® and TRI-STATE® are registered trademarks of National Semiconductor Corporation.
© 2000 National Semiconductor Corporation
Magnetics
RJ-45
10BASE-T
or
100BASE-TX
www.national.com
MII
HARDWARE
CONFIGURATION
PINS
(AN_EN, AN0, AN1)
(PAUSE_EN)
(LED_CFG, PHYAD)
TX_DATA
TRANSMIT CHANNELS &
STATE MACHINES
100 Mb/s 10 Mb/s
4B/5B
ENCODER
PARALLEL TO
SERIAL
SCRAMBLER
NRZ TO NRZI
ENCODER
BINARY TO
MLT-3
ENCODER
10/100 COMMON
OUTPUT DRIVER
TX_CLK
TXD[3:0]
TX_DATA
NRZ TO
MANCHESTER
ENCODER
LINK PULSE
GENERATOR
TRANSMIT
FILTER
TX_ER
TX_CLK
SERIAL
MANAGEMENT
TX_EN
MDIO
MII INTERFACE/CONTROL
REGISTERS
PHY ADDRESS
AUTO
NEGOTIATION
BASIC MODE
CONTROL
PCS CONTROL
10BASE-T
100BASE-TX
AUTO-NEGOTIATION
STATE MACHINE
CLOCK
GENERATION
MDC
MII
COL
CRS
RX_CLK
RX_DV
RX_ER
RX_DATA
RECEIVE CHANNELS &
4B/5B
DECODER
CODE GROUP
ALIGNMENT
SERIAL TO
PARALLEL
DESCRAMBLER
NRZI TO NRZ
DECODER
CLOCK
RECOVERY
MLT-3 TO
BINARY
DECODER
ADAPTIVE
BLW
AND EQ
COMP
RXD[3:0]
STATE MACHINES
100 Mb/s 10 Mb/s
RX_CLK
RX_DATA
RX_CLK
MANCHESTER
TO NRZ
DECODER
CLOCK
RECOVERY
LINK PULSE
DETECTOR
RECEIVE
FILTER
SMART
SQUELCH
TD
LED
DRIVERS
LEDS
SYSTEM CLOCK
REFERENCE
Figure 1. Block Diagram of the 10/100 DSP based core.
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10/100 COMMON
INPUT BUFFER
RD
Table of Contents
1.0 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
1.1 MII Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
1.2 10 Mb/s and 100 Mb/s PMD Interface . . . . . . . . . .6
1.3 Clock Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
1.4 Special Connections . . . . . . . . . . . . . . . . . . . . . . . 7
1.5 LED Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
1.6 Strapping Options/Dual Purpose Pins . . . . . . . . . .8
1.7 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
1.8 Power and Ground Pins . . . . . . . . . . . . . . . . . . . . .9
1.9 Package Pin Assignments . . . . . . . . . . . . . . . . . . 10
2.0 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
2.1 Auto-Negotiation . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2 PHY Address and LEDs . . . . . . . . . . . . . . . . . . .12
2.3 LED INTERFACES . . . . . . . . . . . . . . . . . . . . . . . 13
2.4 Half Duplex vs. Full Duplex . . . . . . . . . . . . . . . . .13
2.5 MII Isolate Mode . . . . . . . . . . . . . . . . . . . . . . . . .14
2.6 Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
2.7 BIST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
3.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . .15
3.1 802.3u MII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
3.2 100BASE-TX TRANSMITTER . . . . . . . . . . . . . . .16
3.3 100BASE-TX RECEIVER . . . . . . . . . . . . . . . . . . 20
3.4 10BASE-T TRANSCEIVER MODULE . . . . . . . . .23
3.5 TPI Network Circuit . . . . . . . . . . . . . . . . . . . . . . .24
3.6 ESD Protection . . . . . . . . . . . . . . . . . . . . . . . . . .25
3.7 Crystal Oscillator Circuit . . . . . . . . . . . . . . . . . . .26
4.0 Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
4.1 Hardware Reset . . . . . . . . . . . . . . . . . . . . . . . . . .26
4.2 Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . .26
5.0 Register Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
5.1 Register Definition . . . . . . . . . . . . . . . . . . . . . . . .29
5.2 Extended Registers . . . . . . . . . . . . . . . . . . . . . . .37
6.0 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . .44
6.1 DC Electrical Specification . . . . . . . . . . . . . . . . . .44
6.2 PGM Clock Timing . . . . . . . . . . . . . . . . . . . . . . .46
6.3 MII Serial Management Timing . . . . . . . . . . . . . .46
6.4 100 Mb/s Timing . . . . . . . . . . . . . . . . . . . . . . . . .47
6.5 10 Mb/s Timing . . . . . . . . . . . . . . . . . . . . . . . . . .51
6.6 Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
6.7 Loopback Timing . . . . . . . . . . . . . . . . . . . . . . . .57
6.8 Isolation Timing . . . . . . . . . . . . . . . . . . . . . . . . . .58
7.0 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . .59
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Connection Diagram
COL
60
CRS/LED_CFG
RESET
RESERVED
IO_GND
IO_VDD
RESERVED
RESERVED
RESERVED
RESERVED
CORE_VDD
CORE_GND
RESERVED
RESERVED
SUB_GND
RESERVED
RESERVED
SUB_GND
RESERVED
61
62
63
64
65
X2
66
X1
67
68
69
70
71
72
73
74
75
76
77
78
79
80
1
TXD_3
59
2
TXD_2
58
3
IO_VDD
57
4
IO_GND
TXD_1
56
55
5
6
TXD_0
IO_GND
TX_EN
TX_CLK
54
53
52
51
50
DP83846A
DSPHYTER
7
8
9
10
11
TX_ER
CORE_VDD
CORE_GND
49
48
12
13
RESERVED
RX_ER/PAUSE_EN
47
46
14
15
RX_CLK
45
16
RX_DV
44
17
IO_VDD
43
18
IO_GND
42
19
RXD_0
41
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
RXD_1
RXD_2
RXD_3
MDC
MDIO
IO_VDD
IO_GND
LED_DPLX/PHYAD0
LED_COL/PHYAD1
LED_GDLNK/PHYAD2
LED_TX/PHYAD3
LED_RX/PHYAD4
LED_SPEED
AN_EN
AN_1
AN_0
CORE_VDD
CORE_GND
RESERVED
RESERVED
ANA_GND
RESERVED
RD-
ANA_GND
RD+
ANA_VDD
ANA_GND
RBIAS
ANA_VDD
RESERVED
ANA_VDD
ANA_GND
RESERVED
Plastic Quad Flat Package JEDEC (LQFP)
Order Number DP83846AVHG
NS Package Number VHG80A
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ANA_VDD
ANA_GND
TD+
TD-
ANA_GND
SUB_GND
RESERVED
1.0 Pin Descriptions
The DP83846A pins are classified into the following interface categories (each interface is described in the sections
that follow):
— MII Interface
— 10/100 Mb/s PMD Interface
— Clock Interface
— Special Connect Pins
— LED Interface
— Strapping Options/Dual Function pins
— Reset
— Power and Ground pins
Note: Strapping pin option (BOLD) Please see Section 1.6
for strap definitions.
1.1 MII Interface
Signal Name Type Pin # Description
MDC I 37 MANAGEMENT DATA CLOCK: Synchronousclock to the
MDIO I/O, OD 36 MANAGEMENT DATA I/O: Bi-directional management in-
CRS/
LED_CFG O, S 61 CARRIER SENSE: Asserted high to indicate the presence
COL O 60 COLLISION DETECT: Asserted high to indicate detection
TX_CLK O 51 TRANSMIT CLOCK: 25 MHz Transmit clock outputs in
TXD[3]
TXD[2]
TXD[1]
TXD[0]]
TX_EN I 52 TRANSMIT ENABLE: Active high input indicates the pres-
TX_ER I 50 TRANSMIT ERROR: In 100MB/s mode, when this signal is
I 59,58,55,54TRANSMIT DATA: Transmit data MII input pinsthat accept
All DP83846A signal pins are I/O cells regardless of the
particular use. Below definitions define the functionality of
the I/O cells for each pin.
Type: I Inputs
Type: O Outputs
Type: I/O Input/Output
Type OD Open Drain
Type: PD,PU Internal Pulldown/Pullup
Type: S Strapping Pin (All strap pins except PHY-
AD[0:4] have internal pull-ups or pulldowns. If the default strap value is needed
to be changed then anexternal 5kΩ resistor
should be used. Please see Table 1.6 on
page 8 for details.)
MDIO management data input/output serialinterface which
may be asynchronous to transmit and receive clocks. The
maximum clockrate is 25 MHz with no minimum clock rate.
struction/data signal that may be sourced by the station
management entity or the PHY. This pin requires a 1.5 kΩ
pullup resistor.
of carrier due to receive or transmit activity in 10BASE-T or
100BASE-TX Half Duplex Modes, whilein full duplex mode
carrier sense is asserted to indicate the presence of carrier
due only to receive activity.
of a collision condition (simultaneous transmit and receive
activity) in 10 Mb/s and 100 Mb/s Half Duplex Modes.
While in 10BASE-T Half Duplex mode with Heartbeat enabled this pin are also asserted for a duration of approximately 1µs at the end of transmission to indicateheartbeat
(SQE test).
In Full Duplex Mode,for 10Mb/s or100Mb/s operation, this
signal is always logic 0. There is no heartbeat function during 10 Mb/s full duplex operation.
100BASE-TX mode or2.5 MHzin 10BASE-T modederived
from the 25 MHz reference clock.
nibble data synchronous to the TX_CLK (2.5 MHz in
10BASE-T Mode or 25 MHz in 100BASE-TX mode).
ence of valid nibble data on data inputs, TXD[3:0] for both
100 Mb/s or 10 Mb/s nibble mode.
high and thecorresponding TX_EN is active the HALT symbol is substituted for data.
In 10 Mb/s this input is ignored.
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Signal Name Type Pin # Description
RX_CLK O, PU 45 RECEIVE CLOCK: Provides the 25MHz recovered receive
RXD[3]
RXD[2]
RXD[1]
RXD[0]
RX_ER/PAUSE_EN S, O, PU 46 RECEIVE ERROR: Asserted high to indicate that an invalid
RX_DV O 44 RECEIVE DATAVALID: Asserted high toindicate thatvalid
O, PU/PD 38,39,40,41RECEIVE DATA: Nibble wide receivedata (synchronous to
clocks for 100BASE-TX mode and 2.5 MHz for 10BASE-T
nibble mode.
corresponding RX_CLK, 25 MHz for 100BASE-TX mode,
2.5 MHz for 10BASE-T nibble mode). Data is driven on the
falling edge of RX_CLK. RXD[2]has aninternal pulldown resistor. The remaining RXD pins have pullups.
symbol has been detected within a received packet in
100BASE-TX mode.
data is present on the corresponding RXD[3:0] for nibble
mode. Data is driven on the falling edge of the corresponding RX_CLK.
1.2 10 Mb/s and 100 Mb/s PMD Interface
Signal Name Type Pin # Description
TD+, TD- O 16, 17 Differential common driver transmit output. These differen-
RD-, RD+ I 10, 11 Differential receive input. These differential inputs can be
tial outputs are configurable to either 10BASE-T or
100BASE-TX signaling.
The DP83846A will automatically configure the common
driver outputs for the proper signal type as a result of either
forced configuration or Auto-Negotiation.
configured to accept either 100BASE-TX or 10BASE-T signaling.
The DP83846A will automatically configure the receive inputs to accept the proper signal type as a result of either
forced configuration or Auto-Negotiation.
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1.3 Clock Interface
Signal Name Type Pin # Description
X1 I 67 REFERENCE CLOCK INPUT 25 MHz: This pin is the pri-
X2 O 66 REFERENCE CLOCK OUTPUT 25 MHz: This pin is the
mary clock reference input for the DP83846A and must be
connected to a 25 MHz 0.005% (±50 ppm) clock source.
The DP83846A supports CMOS-level oscillator sources.
primary clock reference output.
1.4 Special Connections
Signal Name Type Pin # Description
RBIAS I 3 Bias Resistor Connection. A 9.31 kΩ1%resistor should be
RESERVED I/O 1, 5, 8, 20,
21, 22, 47,
63, 68, 69,
70, 71, 74,
75, 77, 78,
80
connected from RBIAS to ANA_GND.
RESERVED: These pins must be left unconnected.
1.5 LED Interface
Signal Name Type Pin # Description
LED_DPLX/PHYAD0 S, O 33 FULL DUPLEX LED STATUS: Indicates Full-Duplex sta-
LED_COL/PHYAD1 S, O 32 COLLISION LED STATUS: Indicates Collision activity in
LED_GDLNK/PHYAD2 S, O 31 GOOD LINK LED STATUS: Indicates Good Link Status for
LED_TX/PHYAD3 S, O 30 TRANSMIT LED STATUS: Indicates transmit activity. LED
LED_RX/PHYAD4 S, O 29 RECEIVE LED STATUS: Indicates receive activity. LED is
LED_SPEED O 28 SPEED LED STATUS: Indicates link speed; high for 100
tus.
Half Duplex mode.
10BASE-T and 100BASE-TX.
is on for activity, off for no activity.
on for activity, off for no activity.
Mb/s, low for 10 Mb/s.
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1.6 Strapping Options/Dual Purpose Pins
A5kΩ resistor should beused for pull-down or pull-up to changethe default strap option. Ifthe default option is required,
then there is no need for external pull-up or pull down resistors, since the internal pull-up or pull down resistors will set
the default value. Please note that the PHYAD[0:4] pins have no internal pull-ups or pull-downs and they must be
strapped. Since these pins may have alternate functions after reset is deasserted, they should not be connected directly
to Vcc or GND.
Signal Name Type Pin # Description
LED_DPLX/PHYAD0
LED_COL/PHYAD1
LED_GDLNK/PHYAD2
LED_TX/PHYAD3
LED_RX/PHYAD4
AN_EN
AN_1
AN_0
S, O 33
32
31
30
29
PHY ADDRESS [4:0]: The DP83846A provides five PHY
address pins,the state of which are latched into the PHYCTRL register at system Hardware-Reset.
The DP83846A supports PHY Address strapping values 0
(<00000>) through 31 (<11111>). PHY Address 0 puts
the part into the MII Isolate Mode. The MII isolate mode
must be selected by strapping Phy Address 0; changing to
Address 0 by register write will not put the Phy in the MII
isolate mode.
The status of these pins are latched into the PHY Control
Register during Hardware-Reset. (Please note these pins
have no internal pull-up orpull-down resistors andthey must
be strapped high or low using 5 kΩ resistors.)
S, O, PU 27, 26, 25 Auto-Negotiation Enable: When high enables Auto-Nego-
tiation with the capability set by ANO and AN1 pins. When
low, puts the part into Forced Mode with the capability set
by AN0 and AN1 pins.
AN0 / AN1: These input pins control the forced or advertised operating mode of the DP83846Aaccording tothe following table. The value on these pins is set by connecting
the input pins to GND (0) or V
These pins should NEVER be connected directly to
GND or V
CC.
(1) through 5 kΩ resistors.
CC
The value set at this input is latched into the DP83846A at
Hardware-Reset.
The float/pull-down status of these pins are latched into the
Basic Mode Control Register and the Auto_Negotiation Advertisement Register during Hardware-Reset. After reset is
deasserted, these pins may switch to outputs so if pull-ups
or pull-downs are implemented, they should be pulled
through a 5kΩ resistor.
The default is 111 since these pins have pull-ups.
AN_EN AN1 AN0 Forced Mode
0 0 0 10BASE-T, Half-Duplex
0 0 1 10BASE-T, Full-Duplex
0 1 0 100BASE-TX, Half-Duplex
0 1 1 100BASE-TX, Full-Duplex
AN_EN AN1 AN0 Advertised Mode
1 0 0 10BASE-T, Half/Full-Duplex
1 0 1 100BASE-TX,Half/Full-Duplex
1 1 0 10BASE-T Half-Duplex
100BASE-TX, Half-Duplex
1 1 1 10BASE-T, Half/Full-Duplex
100BASE-TX,Half/Full-Duplex
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Signal Name Type Pin # Description
RX_ER/PAUSE_EN S, O, PU 46 PAUSE ENABLE: This strapping option allows advertise-
CRS/
LED_CFG S, O
PU
61 LED CONFIGURATION: This strapping option defines the
,
ment of whether or not the DTE(MAC) has implemented
both the optional MAC control sublayer andthe pausefunction as specified in clause 31 and annex 31B of the IEEE
802.3x specification (Full Duplex Flow Control).
When left floating the Auto-Negotiation Advertisement Reg-
ister will be set to 0, indicatingthat Full Duplex Flow Control
is not supported.
When tied low through a 5 kΩ, the Auto-Negotiation Advertisement Register will be set to 1,indicating that Full Duplex
Flow Control is supported.
The float/pull-down status ofthispin is latchedinto theAutoNegotiation Advertisement Register during Hardware-Reset.
polarity and function of the FDPLX LED pin.
See Section 2.3 for further descriptions of this strappingop-
tion.
1.7 Reset
Signal Name Type Pin # Description
RESET I 62 RESET: Active Low input that initializes or re-initializes the
DP83846A. Asserting this pin low for at least 160 µs will
force a reset processto occurwhich willresult inall internal
registers re-initializing to theirdefault states as specified for
each bit in the Register Block section and all strapping options are re-initialized.
1.8 Power and Ground Pins
Signal Name Pin # Description
TTL/CMOS INPUT/OUTPUT SUPPLY
IO_VDD 35, 43, 57, 65 I/O Supply
IO_GND 34, 42, 53, 56, 64 I/O Ground
INTERNAL SUPPLY PAIRS
CORE_VDD 24, 49, 72 Digital Core Supply
CORE_GND 23, 48, 73 Digital Core Ground
ANALOG SUPPLY PINS
ANA_VDD 4, 7, 12, 14 Analog Supply
ANA_GND 2, 6, 9, 13, 15, 18, Analog Ground
SUBSTRATE GROUND
SUB_GND 19, 76, 79 Bandgap Substrate connection
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1.9 Package Pin Assignments
Pin # Pin Name
1 RESERVED
2 ANA_GND
3 RBIAS
4 ANA_VDD
5 RESERVED
6 ANA_GND
7 ANA_VDD
8 RESERVED
9 ANA_GND
10 RD11 RD+
12 ANA_VDD
13 ANA_GND
14 ANA_VDD
15 ANA_GND
16 TD+
17 TD18 ANA_GND
19 SUB_GND
20 RESERVED
21 RESERVED
22 RESERVED
23 CORE_GND
24 CORE_VDD
25 AN_0
26 AN_1
27 AN_EN
28 LED_SPEED
29 LED_RX /PHYAD4
30 LED_TX /PHYAD3
31 LED_GDLNK/PHYAD2
32 LED_COL /PHYAD1
33 LED_FDPLX /PHYAD0
34 IO_GND
35 IO_VDD
36 MDIO
37 MDC
38 RXD_3
39 RXD_2
40 RXD_1
Pin # Pin Name
41 RXD_0
42 IO_GND
43 IO_VDD
44 RX_DV
45 RX_CLK
46 RX_ER/
PAUSE_EN
47 RESERVED
48 CORE_GND
49 CORE_VDD
50 TX_ER
51 TX_CLK
52 TX_EN
53 IO_GND
54 TXD_0
55 TXD_1
56 IO_GND
57 IO_VDD
58 TXD_2
59 TXD_3
60 COL
61 CRS/
LED_CFG
62 RESET
63 RESERVED
64 IO_GND
65 IO_VDD
66 X2
67 X1
68 RESERVED
69 RESERVED
70 RESERVED
71 RESERVED
72 CORE_VDD
73 CORE_GND
74 RESERVED
75 RESERVED
76 SUB_GND
77 RESERVED
78 RESERVED
79 SUB_GND
80 RESERVED
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2.0 Configuration
This section includes information on the various configuration options available with the DP83846A. The configuration options described below include:
— Device Configuration
— Auto-Negotiation
— PHY Address and LEDs
— Half Duplex vs. Full Duplex
— Isolate mode
— Loopback mode
— BIST
2.1 Auto-Negotiation
The Auto-Negotiation function provides a mechanism for
exchanging configuration information between two ends of
a link segment and automatically selecting the highest performance mode of operation supported by both devices.
Fast Link Pulse (FLP) Bursts provide the signalling used to
communicate Auto-Negotiation abilities between two
devices at each end of a link segment. For further detail
regarding Auto-Negotiation, refer to Clause 28 of the IEEE
802.3u specification. The DP83846A supports four different Ethernet protocols (10 Mb/s Half Duplex, 10 Mb/s Full
Duplex, 100 Mb/s Half Duplex, and 100 Mb/s Full Duplex),
so the inclusion of Auto-Negotiation ensures that the highest performance protocol will be selected based on the
advertised ability of the Link Partner. The Auto-Negotiation
function within the DP83846A can be controlled either by
internal register access or by the use of the AN_EN, AN1
and AN0 pins..
2.1.1 Auto-Negotiation Pin Control
The state of AN_EN, AN0 and AN1 determines whether
the DP83846A is forced intoa specific mode or Auto-Negotiation will advertise a specific ability (or set of abilities) as
given in Table 1. These pins allow configuration options to
be selected without requiring internal register access.
The state of AN_EN, AN0 and AN1, upon power-up/reset,
determines the state of bits [8:5] of the ANAR register.
The Auto-Negotiation function selected at power-up or
reset can be changed at any time by writing to the Basic
Mode Control Register (BMCR) at address 00h.
Table 1. Auto-Negotiation Modes
AN_EN AN1 AN0 Forced Mode
0 0 0 10BASE-T, Half-Duplex
0 0 1 10BASE-T, Full-Duplex
0 1 0 100BASE-TX, Half-Duplex
0 1 1 100BASE-TX, Full-Duplex
AN_EN AN1 AN0 Advertised Mode
1 0 0 10BASE-T, Half/Full-Duplex
1 0 1 100BASE-TX, Half/Full-Duplex
1 1 0 10BASE-T Half-Duplex
100BASE-TX, Half-Duplex
1 1 1 10BASE-T, Half/Full-Duplex
100BASE-TX, Half/Full-Duplex
2.1.2 Auto-Negotiation Register Control
When Auto-Negotiation is enabled, the DP83846A transmits the abilities programmed into the Auto-Negotiation
Advertisement register (ANAR) at address 04h via FLP
Bursts. Any combination of 10 Mb/s, 100 Mb/s, HalfDuplex, and Full Duplex modes may be selected. The
BMCR provides software with a mechanism to control the
operation of the DP83846A. The AN0 and AN1 pins do not
affect the contents of the BMCR and cannot be used by
software to obtainstatus of the mode selected.Bits 1 & 2 of
the PHYSTS register are only valid if Auto-Negotiation is
disabled or after Auto-Negotiation is complete. The AutoNegotiation protocol comparesthe contents of the ANLPAR
and ANAR registers and uses the results to automatically
configure to the highest performance protocol between the
local and far-end port. The results of Auto-Negotiation
(Auto-Neg Complete, Duplex Status and Speed) may be
accessed in the PHYSTS register.
Auto-Negotiation Priority Resolution:
— (1) 100BASE-TX Full Duplex (Highest Priority)
— (2) 100BASE-TX Half Duplex
— (3) 10BASE-T Full Duplex
— (4) 10BASE-T Half Duplex (Lowest Priority)
The Basic Mode Control Register (BMCR) at address 00h
provides control for enabling, disabling, and restarting the
Auto-Negotiation process. When Auto-Negotiation is disabled the Speed Selection bit inthe BMCR controls switching between 10 Mb/s or 100 Mb/s operation, and the
Duplex Mode bit controls switching between full duplex
operation and half duplex operation. The Speed Selection
and Duplex Modebits have no effect on the mode of operation when the Auto-Negotiation Enable bit is set.
The Basic Mode Status Register (BMSR) indicates the set
of available abilities for technology types, Auto-Negotiation
ability, and Extended Register Capability. These bits are
permanently set to indicate the full functionality of the
DP83846A (only the 100BASE-T4 bit is not set since the
DP83846A does not support that function).
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The BMSR also provides status on:
— Whether Auto-Negotiation is complete
— Whether the Link Partner is advertising that a remote
fault has occurred
— Whether valid link has been established
— Support for Management FramePreamble suppression
The Auto-Negotiation Advertisement Register (ANAR) indi-
cates the Auto-Negotiation abilities to be advertised by the
DP83846A. Allavailable abilities are transmitted by default,
but any ability can be suppressed by writing to the ANAR.
Updating the ANAR to suppress an ability is one way for a
management agent to change (force)the technologythat is
used.
The Auto-Negotiation Link Partner Ability Register
(ANLPAR) at address 05h is used to receive the base link
code word as well as all next page code words during the
negotiation. Furthermore, the ANLPAR will be updated to
either 0081h or 0021h for parallel detection to either 100
Mb/s or 10 Mb/s respectively.
The Auto-Negotiation Expansion Register (ANER) indicates additional Auto-Negotiation status. The ANER provides status on:
— Whether a Parallel Detect Fault has occurred
— Whether the Link Partner supports the Next Page func-
tion
— Whether the DP83846A supportsthe NextPage function
— Whether the current page beingexchanged by Auto-Ne-
gotiation has been received
— Whether the Link Partner supports Auto-Negotiation
2.1.3 Auto-Negotiation Parallel Detection
The DP83846A supports the Parallel Detection function as
defined in the IEEE 802.3u specification. Parallel Detection
requires both the 10 Mb/s and 100 Mb/s receivers to monitor the receive signal and report link status to the AutoNegotiation function. Auto-Negotiation uses this information to configure the correct technology inthe event that the
Link Partner does not support Auto-Negotiation but is
transmitting link signals that the 100BASE-TX or 10BASET PMAs recognize as valid link signals.
If the DP83846A completes Auto-Negotiation as a result of
Parallel Detection, bits 5 and 7 within the ANLPAR register
will be set to reflect the mode of operation present in the
Link Partner. Note that bits 4:0 of the ANLPAR will also be
set to 00001 based on a successful parallel detection to
indicate a valid 802.3 selector field. Software may determine that negotiation completed via Parallel Detection by
reading azero inthe Link Partner Auto-NegotiationAble bit
once the Auto-Negotiation Complete bit is set. If configured
for parallel detect mode and any condition other than a single good link occurs then the paralleldetect fault bitwill set.
2.1.4 Auto-Negotiation Restart
Once Auto-Negotiation has completed, it may be restarted
at any timeby setting bit 9 (Restart Auto-Negotiation) of the
BMCR to one. If themode configured by a successfulAutoNegotiation loses a valid link, then the Auto-Negotiation
process will resume and attempt to determine the configuration for the link. This function ensures that a valid configuration is maintained if the cable becomes disconnected.
A renegotiation request from any entity, such as a management agent, will cause the DP83846A to halt any transmit
data and link pulse activity until the break_link_timer
expires (~1500 ms). Consequently, the Link Partner will go
into link fail and normal Auto-Negotiation resumes. The
DP83846A will resume Auto-Negotiation after the
break_link_timer has expired by issuing FLP (Fast Link
Pulse) bursts.
2.1.5 Enabling Auto-Negotiation via Software
It is important to note that if the DP83846A has been initialized upon power-up as a non-auto-negotiating device
(forced technology), and it is then required that Auto-Negotiation or re-Auto-Negotiation be initiated via software,
bit 12 (Auto-Negotiation Enable) of the Basic Mode Control
Register must first be cleared and then set for any AutoNegotiation function to take effect.
2.1.6 Auto-Negotiation Complete Time
Parallel detection and Auto-Negotiation take approximately
2-3 seconds to complete. In addition, Auto-Negotiation with
next page should take approximately 2-3 seconds to complete, depending on the number of next pages sent.
Refer to Clause 28 of the IEEE 802.3u standard for a full
description of the individual timers related to Auto-Negotiation.
2.2 PHY Address and LEDs
The 5 PHY address inputs pins are shared with the LED
pins as shown below.
Table 2. PHY Address Mapping
Pin # PHYAD Function LED Function
33 PHYAD0 Duplex
32 PHYAD1 COL
31 PHYAD2 Good Link
30 PHYAD3 TX Activity
29 PHYAD4 RX Activity
28 n/a Speed
The DP83846A can be set to respond to any of 32 possible
PHY addresses. Each DP83846A or port sharing an MDIO
bus in a system must have a unique physical address.
Refer to Section 3.1.4, PHY Address Sensing section for
more details.
The state of each of the PHYAD inputs latched into the
PHYCTRL register bits [4:0] at system power-up/reset
depends on whether a pull-up or pull-down resistor has
been installed for each pin. For further detail relating to the
latch-in timing requirements of the PHY Address pins, as
well as the other hardware configuration pins, refer to the
Reset summary in Section 4.0.
Since the PHYAD strap options share the LED output pins,
the external components required for strapping and LED
usage must be considered in order to avoid contention.
Specifically, when the LED outputs are used to drive LEDs
directly, the active state of each output driver is dependent
on the logic level sampled by the corresponding PHYAD
input upon power-up/reset. For example, if a given PHYAD
input is resistively pulled low then the corresponding output
will be configured as an active high driver. Conversely, if a
given PHYAD input is resistivelypulled high, then the corresponding output will be configured as an active low driver.
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Refer to Figure 2 for an example of a PHYAD connection to
external components. In this example, the PHYAD strapping results in address 00011 (03h).
The adaptive nature of the LED outputs helps to simplify
potential implementation issues of these dual purpose
pins.
LED_RX
PHYAD4= 0
1kΩ
10kΩ
Figure 2. PHYAD Strapping and LED Loading Example
LED_TX
1kΩ
10kΩ
LED_GDLNK
10kΩ
2.3 LED INTERFACES
The DP83846A has 6 Light Emitting Diode (LED) outputs
to indicate the status of Link, Transmit, Receive, Collision,
Speed, and Full/Half Duplex operation. The LED_CFG
strap option is used to configure the LED_FDPLX output
for use as an LED driver or more general purpose control
pin. See the table below:
Table 3. LED Mode Select
LED_CFG Mode Description
1 LED polarity adjusted
0 Duplex active-high
The LED_FDPLX pin indicates the Half or Full Duplex configuration of the port in both 10 Mb/s and 100 Mb/s operation. Since this pin is also used as the PHY address strap
option, thepolarity of this indicator may be adjusted so that
in the “active” (FULL DUPLEX selected) state it drives
against the pullup/pulldown strap. In this configuration it is
suitable for use as an LED. When LED_CFG is high this
mode is selected and DsPHYTER automatically adjusts
the polarity of the output. If LED_CFG is low, the output
drives high to indicate the “active” state. In this configuration the output is suitable for use as a control pin. The
LED_SPEED pin indicates 10 or 100 Mb/s data rate of the
port. The standard CMOS driver goes high when operating
in 100 Mb/s operation. Since this pin is not utilized as a
strap option, it is not affected by polarity adjustment.
The LED_GDLNK pin indicates the link status of the port.
Since this pin is also used as the PHY address strap
option, the polarity of this indicator is adjusted to be the
inverse of the strap value.
LED_COL
PHYAD2 = 0PHYAD3 = 0
1kΩ
In 100BASE-T mode, link is established as a result of input
receive amplitude compliant with TP-PMD specifications
which will result in internal generation of signal detect.
10 Mb/s Link is establishedas a result of the reception ofat
least seven consecutive normal Link Pulses or the reception of a valid 10BASE-T packet. This will cause the assertion of GD_LINK. GD_LINK will deassert in accordance
with the Link Loss Timer as specified in IEEE 802.3.
The Collision LED indicates the presence of collision activity for 10 Mb/s or 100 Mb/s Half Duplex operation. This bit
has no meaning in Full Duplex operation and will be deasserted when the port is operating in Full Duplex. Since this
pin is also used as the PHY addressstrap option, thepolarity of this indicator is adjusted to be the inverse of the strap
value. In 10 Mb/s half duplex mode, the collision LED is
based on the COL signal. When in this mode, the user
should disable the Heartbeat (SQE) to avoid asserting the
COL LED during transmission. See Section 3.4.2 for more
information about the Heartbeat signal.
The LED_RX and LED_TX pins indicate the presence of
transmit and/or receive activity. Since these pins are also
used in PHY address strap options, the polarity is adjusted
to be the inverse of the respective strap values.
PHYAD1 = 1
1kΩ
10kΩ
LED_FDPLX
PHYAD0 = 1
1kΩ
10kΩ
VCC
2.4 Half Duplex vs. Full Duplex
The DP83846A supports both half and fullduplex operation
at both 10 Mb/s and 100 Mb/s speeds. Half-duplex is the
standard, traditional mode of operation which relies on the
CSMA/CD protocol to handle collisions and network
access. In Half-Duplex mode, CRS responds to both transmit and receive activity in order to maintain compliance
with IEEE 802.3 specification.
Since the DP83846A is designed to support simultaneous
transmit and receive activity it is capable of supporting fullduplex switched applicationswith athroughput ofup to200
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Mb/s per port when operating in 100BASE-TX mode.
Because the CSMA/CD protocol does not apply to fullduplex operation, the DP83846A disables its own internal
collision sensing and reporting functions and modifies the
behavior of Carrier Sense (CRS) such that it indicates only
receive activity. This allows a full-duplex capable MAC to
operate properly.
All modes of operation (100BASE-TX and 10BASE-T) can
run either half-duplex or full-duplex. Additionally, other than
CRS and Collision reporting, all remaining MII signaling
remains the same regardless of the selected duplex mode.
It is important to understand that while Auto-Negotiation
with the use of Fast Link Pulse code words can interpret
and configure to full-duplex operation, parallel detection
can not recognize the difference between full and halfduplex from a fixed 10 Mb/s or 100 Mb/s link partner over
twisted pair. As specified in 802.3u, if a far-end link partner
is transmitting forced full duplex 100BASE-TX for example,
the parallel detection state machine in the receiving station
would be unable to detect the full duplex capability of the
far-end link partner and would negotiate to a half duplex
100BASE-TX configuration (same scenario for 10 Mb/s).
2.5 MII Isolate Mode
The DP83846A can be put into MII Isolate mode by writing
to bit 10 of the BMCR register. In addition, the MII isolate
mode can be selected by strapping in Physical Address 0.
It should be noted that selecting Physical Address 0 via an
MDIO write to PHYCTRL will not put the device in the MII
isolate mode.
When in the MII isolate mode, the DP83846A does not
respond to packet data present at TXD[3:0], TX_EN, and
TX_ER inputs and presents a high impedance on the
TX_CLK, RX_CLK, RX_DV, RX_ER, RXD[3:0], COL, and
CRS outputs. The DP83846A will continue to respond toall
management transactions.
While in Isolate mode, the TD± outputs will not transmit
packet data but will continue to source 100BASE-TX
scrambled idles or 10BASE-T normal link pulses.
2.6 Loopback
The DP83846A includes a LoopbackTest mode for facilitating system diagnostics. The Loopback mode is selected
through bit 14 (Loopback) of the Basic Mode Control Register (BMCR). Writing 1 to this bit enables MII transmit data
to be routed to the MII receive outputs. Loopback status
may be checked in bit 3 of the PHY Status Register
(PHYSTS). While in Loopback mode the data will not be
transmitted onto the media in 100 Mb/s mode. To ensure
that the desired operating mode is maintained, Auto-Negotiation should be disabled before selecting the Loopback
mode.
During 10BASE-T operation, in order to be standard compliant, the loopback mode loopsMII transmitdata to the MII
receive data, however, Link Pulses are not looped back.
When selecting 10 Mb/s Loopback, Good Link must be
forced via the FORCE_LINK_10 bit in the 10BTSCR. Also
in the 10 Mb/s Loopback mode, the CD should be disabled
(bit 15 in the CDCTRL) to prevent transmission of the
Loopback data onto the network.
In 100BASE-TX Loopback mode the data is routed through
the PCS and PMA layers into the PMD sublayer before it is
looped back. In addition to serving as a board diagnostic,
this mode serves as a functional verification of the device.
2.7 BIST
The DsPHYTER incorporates an internal Built-in Self Test
(BIST) circuit to accommodate in-circuit testing or diagnostics. The BIST circuit can be utilized to test the integrity of
the transmit and receive data paths. BIST testing can be
performed with the part in the internal loopback mode or
externally looped back using a loopback cable fixture.
The BIST is implemented with independent transmit and
receive paths, with the transmit block generating a continuous stream of a pseudo random sequence. The user can
select a 9 bit or 15 bit pseudo random sequence from the
PSR_15 bit in the PHY Control Register (PHYCTRL). The
looped back data is compared to the data generated bythe
BIST Linear Feedback Shift Register (LFSR, which generates a pseudo random sequence) to determine the BIST
pass/fail status.
The pass/fail status of the BIST is stored in the BIST status
bit in the PHYCTRL register. The status bit defaults to 0
(BIST fail) and will transition on a successful comparison. If
an error (mis-compare) occurs, the status bit is latched and
is cleared upon a subsequent write to the Start/Stop bit.
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3.0 Functional Description
3.1 802.3u MII
The DP83846A incorporates the Media Independent Interface (MII) as specified in Clause 22 of the IEEE 802.3u
standard. This interface may be used to connect PHY
devices to a MAC in 10/100 Mb/s systems. This section
describes both the serial MII management interface as well
as the nibble wide MII data interface.
The serial management interface of the MII allows for the
configuration and control of multiple PHY devices, gathering of status, error information, and the determination of
the type and capabilities of the attached PHY(s).
The nibble wide MII data interface consistsof areceive bus
and a transmit bus each with control signals to facilitate
data transfer between the PHY and the upper layer (MAC).
3.1.1 Serial Management Register Access
The serial management MII specification defines a set of
thirty-two 16-bit status and control registers that are accessible through the management interface pins MDC and
MDIO. The DP83846A implements all the required MII registers as well as several optional registers. These registers
are fully described in Section 5. A description of the serial
management access protocol follows.
3.1.2 Serial Management Access Protocol
The serial control interface consists of two pins, Management Data Clock (MDC) and Management Data Input/Output (MDIO). MDC has a maximum clock rate of 25 MHz
and no minimum rate. The MDIO line is bi-directional and
may be shared by up to 32 devices. The MDIO frame format is shown below in Table 4.
The MDIO pin requires a pull-up resistor (1.5 kΩ) which,
during IDLE and turnaround, will pull MDIO high. In order
to initialize the MDIO interface, the station management
entity sends a sequence of 32 contiguous logic ones on
MDIO to provide the DP83846A with a sequence that can
be used to establish synchronization. This preamble may
be generated either by driving MDIO high for 32 consecutive MDC clock cycles, orby simply allowing the MDIO pullup resistor to pull the MDIO pin high during which time 32
MDC clock cycles are provided. In addition 32 MDC clock
cycles should be used to re-sync the device if an invalid
start, opcode, or turnaround bit is detected.
The DP83846A waits until it has received this preamble
sequence before responding to any other transaction.
Once the DP83846A serial management port has been initialized no further preamble sequencing is required until
after a power-on/reset, invalid Start, invalid Opcode, or
invalid turnaround bit has occurred.
The Start code is indicated bya <01> pattern. Thisassures
the MDIO line transitions from the default idle line state.
Turnaround is defined as an idle bit time inserted between
the Register Address field and the Data field. To avoid contention during a read transaction, no device shall actively
drive the MDIOsignal during the first bitof Turnaround.The
addressed DP83846A drives the MDIO with a zero for the
second bit of turnaround and follows this with the required
data. Figure 3 shows the timing relationship between MDC
and the MDIO as driven/received by the Station (STA) and
the DP83846A (PHY) for a typical register read access.
Table 4. Typical MDIO Frame Format
MII Management
<idle><start><op code><device addr><reg addr><turnaround><data><idle>
Serial Protocol
Read Operation <idle><01><10><AAAAA><RRRRR><Z0><xxxx xxxx xxxx xxxx><idle>
Write Operation <idle><01><01><AAAAA><RRRRR><10><xxxx xxxx xxxx xxxx><idle>
MDC
MDIO
(STA)
MDIO
(PHY)
Z
Z
00011 110000000
Idle Start
Opcode
(Read)
PHY Address
(PHYAD = 0Ch)
Register Address
(00h = BMCR)
Z
Z
Z
0 0 011000100000000
TA
Register Data
Figure 3. Typical MDC/MDIO Read Operation
For write transactions, the station management entity
writes data to the addressed DP83846A thus eliminating
the requirement for MDIO Turnaround. The Turnaround
time is filled by the management entity by inserting <10>.
Figure 4 shows the timing relationship for a typical MII register write access.
3.1.3 Serial Management Preamble Suppression
The DP83846A supports a Preamble Suppression mode
as indicated by a one in bit 6 of the Basic Mode Status
Register (BMSR, address 01h.) If the station management
entity (i.e. MAC or other management controller) determines that all PHYs in the system support Preamble Suppression by returning a one in this bit, then the station
Z
Z
Idle
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MDC
MDIO
(STA)
Z
00011110000000
Idle Start
Opcode
(Write)
PHY Address
(PHYAD = 0Ch)
Register Address
(00h = BMCR)
Figure 4. Typical MDC/MDIO Write Operation
management entity need not generate preamble for each
management transaction.
The DP83846A requires a single initialization sequence of
32 bits of preamble following hardware/software reset. This
requirement is generally met by the mandatory pull-up
resistor on MDIO in conjunction with a continuous MDC, or
the management access made to determine whether Preamble Suppression is supported.
While the DP83846A requires an initial preamblesequence
of 32 bits for management initialization, it does not require
a full 32-bit sequence between each subsequent transaction. A
transactions is required
minimum of one idle bit between management
as specified in IEEE 802.3u.
3.1.4 PHY Address Sensing
The DP83846A provides five PHY address pins, the information is latched into the PHYCTRL register (address 19h,
bits [4:0]) at device power-up/Hardware reset.
The DP83846A supports PHY Address strapping values 0
(<00000>) through 31 (<11111>). Strapping PHY Address
0 puts the part into Isolate Mode. It should also be noted
that selecting PHY Address 0 via an MDIO write to PHYCTRL will not put the device in Isolate Mode; Address 0 must
be strapped in.
3.1.5 Nibble-wide MII Data Interface
Clause 22 of the IEEE 802.3u specification defines the
Media Independent Interface. This interface includes a
dedicated receive bus and a dedicated transmit bus. These
two data buses, along with various control and indicate signals, allow for the simultaneous exchange of data between
the DP83846A and the upper layer agent (MAC).
The receive interface consists of a nibble wide data bus
RXD[3:0], a receive error signal RX_ER, a receive data
valid flag RX_DV,and a receive clock RX_CLK for synchronous transfer of the data. The receive clock can operate at
either 2.5 MHz to support 10 Mb/s operation modes or at
25 MHz to support 100 Mb/s operational modes.
The transmit interface consists of a nibble wide data bus
TXD[3:0], a transmit enable control signal TX_EN, and a
transmit clock TX_CLK which runs at either 2.5 MHz or 25
MHz.
Additionally, the MII includes the carrier sense signal CRS,
as well as a collision detect signal COL. The CRS signal
asserts to indicate the reception of data from the network
or as a function of transmit data in Half Duplex mode. The
COL signal asserts asan indication of a collision which can
occur during half-duplex operation when both a transmit
and receive operation occur simultaneously.
ZZ
0 0 0 000 00000000
1000
TA
Register Data
3.1.6 Collision Detect
For Half Duplex, a 10BASE-T or 100BASE-TX collision is
detected when the receive and transmit channels are
active simultaneously. Collisions are reported by the COL
signal on the MII.
If the DP83846A is transmitting in 10 Mb/s mode when a
collision is detected, the collision is not reported until seven
bits have been received while in the collision state. This
prevents a collision being reported incorrectly due to noise
on the network. The COL signal remains set for the duration of the collision.
If a collision occurs during areceive operation, it is immediately reported by the COL signal.
When heartbeat is enabled (only applicable to 10 Mb/s
operation), approximately 1µs after the transmission of
each packet, a Signal Quality Error (SQE) signal of approximately 10 bit times is generated (internally) to indicate
successful transmission. SQE is reported asa pulseon the
COL signal of the MII.
3.1.7 Carrier Sense
Carrier Sense(CRS) may be asserted due to receive activity, once valid data is detected via the squelch function during 10 Mb/s operation. During 100 Mb/s operation CRS is
asserted when a valid link (SD) and two non-contiguous
zeros are detected on the line.
For 10 or 100 Mb/s Half Duplex operation, CRS is asserted
during either packet transmission or reception.
For 10 or 100 Mb/s Full Duplex operation, CRS is asserted
only due to receive activity.
CRS is deasserted following an end of packet.
3.2 100BASE-TX TRANSMITTER
The 100BASE-TX transmitter consists of several functional
blocks which convert synchronous 4-bit nibble data,as provided by theMII, to a scrambled MLT-3125 Mb/s serial data
stream. Because the 100BASE-TX TP-PMD is integrated,
the differential output pins, TD±, can be directly routed to
the magnetics.
The block diagram in Figure 5 provides an overview of
each functional block within the 100BASE-TX transmit section.
The Transmitter section consists of the following functional
blocks:
— Code-groupEncoderandInjectionblock(bypassoption)
— Scrambler block (bypass option)
— NRZ to NRZI encoder block
— Binary to MLT-3 converter / Common Driver
Z
Idle
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The bypass option for the functional blocks within the
100BASE-TX transmitter provides flexibility for applications
where data conversion is not always required. The
DP83846A implements the 100BASE-TX transmit state
machine diagram as specified in the IEEE 802.3u Standard, Clause 24.
FROM PGM
BP_4B5B
BP_SCR
TX_CLK
DIV BY 5
TXD[3:0]/
TX_ER
4B5B CODE-
GROUP ENCODER
& INJECTOR
MUX
5B PARALLEL
TO SERIAL
SCRAMBLER
MUX
100BASE-TX
LOOPBACK
Figure 5. 100BASE-TX Transmit Block Diagram
3.2.1 Code-group Encoding and Injection
The code-group encoder converts 4-bit (4B) nibble data
generated by the MAC into 5-bit (5B) code-groups for
transmission. This conversion is required to allow control
data to be combined with packet data code-groups. Refer
to Table 5 for 4B to 5B code-group mapping details.
The code-group encoder substitutes the first 8-bits of the
MAC preamble with a J/K code-group pair (11000 10001)
upon transmission. The code-group encoder continues to
replace subsequent 4B preamble and data nibbles with
corresponding 5B code-groups. At the end of the transmit
packet, upon the deassertion of Transmit Enable signal
from the MAC, the code-group encoder injects the T/R
code-group pair (01101 00111) indicating the endof frame.
After the T/R code-group pair, the code-group encoder
continuously injects IDLEs into the transmit data stream
NRZ TO NRZI
ENCODER
BINARY TO
MLT-3 /
COMMON
DRIVER
TD±
until the next transmit packet is detected (reassertion of
Transmit Enable).
3.2.2 Scrambler
The scrambler is required to control the radiated emissions
at the media connector and on the twisted pair cable (for
100BASE-TX applications). By scrambling the data, the
total energy launched onto the cable is randomly distributed over a wide frequency range. Without the scrambler,
energy levels at the PMD and on the cable could peak
beyond FCC limitations at frequencies related to repeating
5B sequences (i.e., continuous transmission of IDLEs).
The scrambler is configured as a closed loop linear feedback shift register (LFSR) with an 11-bit polynomial. The
output of the closed loop LFSR is X-ORd with the serial
NRZ data from the code-group encoder. The result is a
scrambled data stream with sufficient randomization to
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decrease radiated emissions at certain frequencies by as
much as 20 dB. The DP83846A uses the PHY_ID (pins
PHYAD [4:0]) to set a unique seed value.
3.2.3 NRZ to NRZI Encoder
After the transmit data stream has been serialized and
scrambled, the data must be NRZI encoded in order to
comply with the TP-PMD standard for 100BASE-TX transmission over Category-5 Unsheilded twisted pair cable.
binary_plus
D
binary_in
Q
Q
Figure 6. Binary to MLT-3 conversion
binary_minus
differential MLT-3
3.2.4 Binary to MLT-3 Convertor / Common Driver
The Binary to MLT-3 conversion is accomplished by converting the serial binary data stream output from the NRZI
encoder into two binary data streams with alternately
phased logic one events. These two binary streams are
then fed to the twisted pair output driverwhich converts the
voltage to current and alternately drives either side of the
transmit transformer primary winding, resulting in aminimal
current (20 mA max) MLT-3 signal. Refer to Figure 6 .
binary_in
binary_plus
COMMON
DRIVER
binary_minus
MLT-3
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