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DP83840AVCE
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NSC DP83840AVCE Datasheet

1
National SemiconductorVersion A
March 1997
DP83840A 10/100 Mb/s Ethernet Physical Layer
General Description
The DP83840A is a Physical Layer device for Ethernet 10BASE-T and 100BASE-X using category 5 Unshielded, Type 1 Shielded and Fiber Optic cables.
The DP83840A is designed with National Semiconductor's BiCMOS process. Its system architecture is based on the integration of several of National Semiconductor's industry proven core technologies:
10BASE-T ENDEC/Transceiver module to provide the 10
Mb/s IEEE 802.3 functions
Clock Recovery/Generator Modules from National
Semiconductor's leading FDDI product
FDDI Stream Cipher (Cyclone)100BASE-X physical coding sub-layer (PCS) and control
logic that integrate the core modules into a dual speed Ethernet physical layer controller
System Diagram
Features
• IEEE 802.3 10BASE-T compatible--ENDEC and UTP/ STP transceivers and filters built-in
• IEEE 802.3u 100BASE-X compatible--support for 2 pair Category 5 UTP (100m), Type 1 STP and Fiber Optic Transceivers--Connects directly to the DP83223 Twisted Pair Transceiver
• ANSI X3T12 TP-PMD compatible
• IEEE 802.3u Auto-Negotiation for automatic speed
selection
• IEEE 802.3u compatible Media Independent Interface (MII) with Serial Management Interface
• Integrated high performance 100 Mb/s clock recovery circuitry requiring no external filters
• Full Duplex support for 10 and 100 Mb/s
• MII Serial 10 Mb/s output mode
• Fully configurable node and repeater modes--allows
operation in either application
• Programmable loopback modes for easy system diagnostics
• Flexible LED support
• IEEE 1149.1 Standard Test Access Port and Boundary-
Scan compatible
• Small footprint 100-pin PQFP package
• Individualized scrambler seed for multi-PHY applications
DP83840A 10/100 Mb/s Ethernet Physical Layer
10 AND/OR 100 Mb/s ETHERNET MAC OR REPEATER/SWITCH
PORT
DP83840A
10/100 Mb/s
ETHERNET PHYSICAL LAYER
CLOCKS
STATUS
LEDS
DP83223
100BASE-TX
TRANSCEIVER
MAGNETICS
RJ-45
10BASE-T
OR
100BASE-TX
MII
10BASE-T
100BASE-FX
TRANSCEIVER
2
National SemiconductorVersion A
DP83840A 10/100 Mb/s Ethernet Physical Layer
Block Diagram
SERIAL
MANAGEMENT
MII
IEEE
1149.1 (JTAG)
TX_CLK
TXD[3:0]
TX_ER
TX_EN
MDIO
MDC
COL
CRS
RX_ER
RX_DV
RXD[3:0]
RX_CLK
MII INTERFACE/CONTROL
TEST
ACCESS
PORT
LED
DRIVERS
LED 1-5
100 Mb/s
RECEIVE
CLOCK
DATA
REGISTERS
AUTO
NEGOTIATION
RX STATE MACHINE
PCS
SSD
DETECT
CARRIER
SENSE
COLLISION
DETECTION
CODE-GROUP
DECODER
CODE-GROUP
ALIGNMENT
DESCRAMBLER
RD +/-
SD +/-
SERIAL TO
PARALLEL
CRM
NRZI TO NRZ
100BASE-X
10BASE-T
MII
NODE/
REPEATER
PCS
CONTROL
10BASE-T
TX
UTP/STP
RX
AUTO
NEGOTIATION
100 Mb/s
RECEIVE
CLOCK
DATA
PCS
CODE-GROUP
ENCODER AND
INJECTION
SCRAMBLER
CLOCK(S)
PARALLEL TO
SERIAL
100BASE-X
RECEIVE INTERFACE
RXI +/-
TXS+/-
TXU+/-
TD +/-
100BASE-X
TRANSMIT INTERFACE
10 BASE-T
INTERFACE
CGM
NRZ / NRZI
TX STATE MACHINE
RX_EN
3
Table of Contents
National SemiconductorVersion A
DP83840A 10/100 Mb/s Ethernet Physical Layer
GENERAL DESCRIPTION FEATURES SYSTEM DIAGRAM BLOCK DIAGRAM REVISION HISTORY TABLE OF CONTENTS
1.0 PIN CONNECTION DIAGRAM
2.0 PIN DESCRIPTION
2.1 MII Interface
2.2 100 Mb/s Serial PMD Interface
2.3 10 Mb/s Interface
2.4 Clock Interface
2.5 Device Configuration Interface
2.6 LED Interface
2.7 IEEE 1149.1 Interface
2.8 PHY Address Interface
2.9 Miscellaneous
2.10 Power and Ground Pins
2.11 Special Connect Pins
2.12
3.0 FUNCTIONAL DESCRIPTION
3.1 PCS Control
3.2 MII Serial Management Register Access
3.3 100BASE-X Transmitter
3.4 100BASE-X Receiver
3.5 Clock Generation Module
3.6 100 Mb/s Clock Recovery Module
3.7 10BASE-T Transceiver Module
3.8 IEEE 1149.1 Controller
3.9 IEEE 802.3u Auto-Negotiation
3.10 Reset Operation
3.11 Loopback Operation
3.12 Alternative 100BASE-X Operation
3.13 Low Power Mode
4.0 Registers
4.1 Key to Defaults
4.2 Basic Mode Control Register
4.3 Basic Mode Status Register
4.4 PHY Identifier Register #1
4.5 PHY Identifier Register #2
4.6 Auto-Negotiation Advertisement Register
4.7 Auto-Negotiation Link Partner Ability Register
4.8 Auto-Negotiation Expansion Register
4.9 Disconnect Counter Register
4.10 False Carrier Sense Counter Register
4.11 Receive Error Counter Register
4.12 Silicon Revision Register
4.13 PCS Sub-Layer Configuration Register
4.14 Loopback, Bypass, and Receive Error Mask Register
4.15 PHY Address Register
4.16 10BASE-T Status Register
4.17 10BASE-T Configuration Register
5.0 DP83840A APPLICATION
5.1 Typical Board Level Application
5.2 Layout Recommendations
5.3 Plane Partitioning
5.4 Power and Ground Filtering
6.0 Hardware User Information
6.1 Jabber/Timeout
6.2 Link Timer
6.3 Link LED, Link Status Bit
6.4 PHYAD[3] and Speed_100
6.5 Collision De-Assertion Time
6.6 Synchronization of Idle
6.7 100 Mb/s Differential Output Voltage
6.8 10Base-T Transmit Differential Output Impedance
6.9 Low Power Mode
6.10 Software Reset
6.11 Receive Error Counter
6.12 Auto-Negotiation Test Compliancy
7.0 Software User information
7.1 100Mb/s Full Duplex Log-On
7.2 Auto-Negotiation to Link Sending 100Mb/ s Scrambled Idles
7.3 840A Auto-Negotiating to Legacy Devices
7.4 HBE Disable in 10Mb/s Repeater Mode
7.5 CRS Glitching in 10Mb/s Repeater Mode
8.0 ELECTRICAL SPECIFICATIONS
8.1 Ratings and Operating Conditions
8.2 DC Specifications
8.3 Clock Timing
8.4 MII Serial Management AC Timing
8.5 100 Mb/s AC Timing
8.6 10 Mb/s AC Timing
8.7 Fast Link Pulse Timing
8.8 Clock Recovery Module Timing
8.9 Reset Timing
8.10 Loopback Timing
8.11 PHY Isolation Timing
9.0 Package Dimensions
4
National Semiconductor Subject to change without notice.
Version A
DP83840A 10/100 Mb/s Ethernet Physical Layer
2
1
4
3
BPSCR
OSCIN
LOWPWR
RES_0
6
5
8
7
RD+
RD­SD-
SD+
10
9
12
11
ANAV
CC
ANAGND
CRMGND
CRMV
CC
14
13
16
15
NC NC
ECLV
CC
TD-
TD+
RXV
CC
RXGND
RXI-
RXI+
TDV
CC
TXS-
TXS+
TXU-
TXU+
TDGND
RTX
REQ
PLLGND
18
17
20
19
22
21
24
23
26
25
28
27
30
29
81
CLK25M
TX_CLK
NC
REFV
CC
REFGND
REFIN
CGMV
CC
CGMGND
SPEED_100 / PHYAD[3]
RES_0
TDI
TRST
TCLK
TMS
AN0
IOV
CC1
IOGND1
10BTSER
BPALIGN
828384858687888990919293949596979899100
BP4B5B
5049484746454443424140393837363534333231
79
80
77
78
75
76
73
74
71
72
69
70
67
68
65
66
63
64
61
62
59
60
57
58
55
56
53
54
51
52
IOGND6 IOV
CC6
TXD[0] TXD[1] TXD[2] TXD[3] TX_EN TX_ER MDC PCSGND PCSV
CC
IOGNDS IOV
CC5
MDIO CRS / PHYAD[2] COL RX_DV RX_ER / PHYAD[4] RX_CLK RCLKGND IOGND4 IOV
CC4
RXD[0] RXD[1] RXD[2] RXD[3] SPEED_10 ENCSEL / PHYAD[1] IOGND3 IOV
CC3
TDO
LBEN / PHYAD[0]
RES_0
REPEATER
AN1
RES_0
RESET
RX_EN
LED1
LED2
IOGND2
IOV
CC2
LED3
LED4
LED5
OGND
X2
X1
OV
CC
PLLV
CC
DP83840AVCE
10/100BASE-X ETHERNET PHYSICAL LAYER
100 -PIN JEDEC METRIC PQFP
FIGURE 1. DP83840A Pin Connection Diagram
2.0 Pin Connection Diagram
5
National Semiconductor Subject to change without notice.
Version A
DP83840A 10/100 Mb/s Ethernet Physical Layer
2.0 Pin Description
The DP83840A pins are classified into the following interface categories (each interface is described in the sections that follow):
MII INTERFACE 100 Mb/s SERIAL PMD INTERFACE 10 Mb/s INTERFACE CLOCK INTERFACE DEVICE CONFIGURATION INTERFACE
LED INTERFACE IEEE 1149.1 INTERFACE PHY ADDRESS INTERFACE MISCELLANEOUS PINS POWER AND GROUND PINS SPECIAL CONNECT PINS
2.1 MII INTERFACE
Signal Name Type Pin # Description
TX_CLK O, Z 82 TRANSMIT CLOCK: Transmit clock output from the DP83840A:
25 MHz nibble transmit clock derived from Clock Generator Module's (CGM) PLL in 100BASE-TX mode
2.5 MHz transmit clock in 10BASE-T nibble mode 10 MHz transmit clock in 10BASE-T serial mode
TXD[3] TXD[2] TXD[1] TXD[0]
I, J 75
76 77 78
TRANSMIT DATA: Transmit data MII input pins that accept nibble data during normal nibble-wide MII operation at either 2.5 MHz (10BASE-T mode) or 25MHz (100BASE-X mode)
In 10 Mb/s serial mode, the TXD[0] pin is used as the serial data input pin. TXD[3:1] are ignored.
TX_EN I, J 74 TRANSMIT ENABLE: Active high input indicates the presence of valid nibble data
on TXD[3:0] for both 100 Mb/s or 10 Mb/s nibble mode. In 10 Mb/s serial mode, active high indicates the presence of valid 10 Mb/s data on
TXD[0].
TX_ER (TXD[4])
I, J 73 TRANSMIT ERROR: In 100 Mb/s mode, when this signal is high and TX_EN is
active the HALT symbol is substituted for the actual data nibble. In 10 Mb/s mode, this input is ignored. In encoder bypass mode (BP_4B5B or BP_ALIGN), TX_ER becomes the TXD [4]
pin, the new MSB for the transmit 5-bit data word.
MDC I,J 72 MANAGEMENT DATA CLOCK: Synchronous clock to the MDIO management
data input/output serial interface which may be asynchronous to transmit and receive clocks. The maximum clock rate is 2.5 MHz. There is no minimum clock rate.
MDIO I/O, Z, J 67 MANAGEMENT DATA I/O: Bi-directional management instruction/data signal that
may be sourced by the station management entity or the PHY. This pin requires a
1.5kΩ pullup resistor.
I = TTL/CMOS input O = TTL/CMOS output Z = TRI-STATE output J = IEEE 1149.1 pin
2.0 Pin Description (Continued)
6
National SemiconductorVersion A
DP83840A 10/100 Mb/s Ethernet Physical Layer
CRS (PHYAD[2])
I/O, Z, J 66 CARRIER SENSE: This pin is asserted high to indicate the presence of carrier due
to receive or transmit activities in 10BASE-T or 100BASE-X Half Duplex modes. In Repeater or Full Duplex mode a logic 1 indicates presence of carrier due only to
receive activity. This is also the PHY address sensing (PHYAD[2]) pin for multiple PHY
applications--see Section 2.8 for further detail.
COL O, Z, J 65 COLLISION DETECT: Asserted high to indicate detection of collision conditions in
10 Mb/s and 100 Mb/s Half Duplex modes. During 10BASE-T Half Duplex mode with Heartbeat asserted (bit 4, register 1Ch),
this pin is also asserted for a duration of approximately 1µs at the end of transmission to indicate CD heartbeat.
In Full Duplex mode, for 10 Mb/s or 100 Mb/s operation, this signal is always logic
0. There is no heartbeat function during 10 Mb/s full duplex operation.
RX_CLK O, Z 62 RECEIVE CLOCK: Provides the recovered receive clock for different modes of
operation:
• 25 MHz nibble clock in 100 Mb/s mode
• 2.5 MHz nibble clock in 10 Mb/s nibble mode
• 10 MHz receive clock in 10 Mb/s serial mode
RX_ER (RXD[4]) (PHYAD[4])
O, Z, J 63 RECEIVE ERROR: Asserted high to indicate that an invalid symbol has been
detected within a received packet in 100 Mb/s mode. In decoder bypass mode (BP_4B5B or BP_ALIGN modes), RX_ER becomes
RXD[4], the new MSB for the receive 5-bit data word. This is also the PHY address sensing (PHYAD) pin for multiple PHY applications--
see Section 2.8 for more details.
RX_DV O, Z, J 64 RECEIVE DATA VALID: Asserted high to indicate that valid data is present on
RXD[3:0]. This pin is not meaningful during either transparent or phaser mode. Refer to
section 3.12 for further detail.
RXD[3] RXD[2] RXD[1] RXD[0]
O, Z, J 55
56 57 58
RECEIVE DATA: Nibble wide receive data (synchronous to RX_CLK, 25 MHz for 100BASE-X mode, 2.5 MHz for 10BASE-T nibble mode). Data is driven on the falling edge of RX_CLK.
In 10 Mb/s serial mode, the RXD[0] pin is used as the data output pin which is also clocked out on the falling edge of RX_CLK. During 10 Mb/s serial mode RXD[3:1] become don't care.
RX_EN I, J 43 RECEIVE ENABLE: Active high enable for receive signals RXD[3:0], RX_CLK,
RX_DV and RX_ER. A low on this input tri-states these output pins. For normal operation in a node application this pin should be pulled high.
2.2 100 Mb/s SERIAL PMD INTERFACE
Signal Name Type Pin # Description
SPEED_10 O, J 54 SPEED 10 Mb/s: Indicates 10 Mb/s operation when high. Indicates 100 Mb/s
operation when low. This pin can be used to drive peripheral circuitry such as an LED indicator or control circuits for common magnetics.
SPEED_100 (PHYAD[3])
I/O, J 89 SPEED 100 Mb/s: Indicates 100 Mb/s operation when high. Indicates 10 Mb/s
operation when low. This pin can be used to drive peripheral circuitry such as an LED indicator or control circuits for common magnetics.
This is also the PHY address sensing (PHYAD[3]) pin for multiple PHY applications-
-see Section 2.8 for more details.
2.1 MII INTERFACE
I = TTL/CMOS input O = TTL/CMOS output Z = TRI-STATE output J = IEEE 1149.1 pin
2.0 Pin Description (Continued)
7
National SemiconductorVersion A
DP83840A 10/100 Mb/s Ethernet Physical Layer
ENCSEL (PHYAD[1])
I/O, J 53 ENCODE SELECT: Used to select binary or MLT-3 coding scheme in the PMD
transceiver (at the DP83223, logic high selects binary coding scheme and logic low selects MLT-3 coding scheme).
This is also the PHY address sensing (PHYAD[1]) pin for multiple PHY applications-
-see Section 2.8 for more details.
LBEN (PHYAD[0])
I/O, J 49 LOOPBACK ENABLE: For 100BASE-TX operation, this pin should be connected
to the Loopback Enable pin of a DP83223 100 Mb/s Transceiver: 1 = local 100BASE-TX transceiver Loopback enabled 0 = local 100BASE-TX transceiver Loopback disabled (normal operation) This is also the PHY address sensing (PHYAD[0]) pin for multiple PHY applications-
-see Section 2.8 for more details. This pin has no effect during 10 Mb/s operation.
TD­TD+
O (ECL) 1617TRANSMIT DATA: Differential ECL 125 Mb/s serialized transmit data outputs to
the PMD transceiver (such as the DP83223).
SD­SD+
I (ECL) 78SIGNAL DETECT: Differential ECL signal detect inputs. Indicates that the PMD
transceiver has detected a receive signal from the twisted pair or fiber media.
RD­RD+
I (ECL) 65RECEIVE DATA: Differential ECL 125 Mb/s receive data inputs from the PMD
transceiver (such as the DP83223).
2.3 10 Mb/s INTERFACE
Signal Name Type Pin # Description
REQ I 29 EQUALIZATION RESISTOR: A resistor connected between this pin and GND or
V
CC
adjusts the equalization step amplitude on the 10BASE-T Manchester
encoded transmit data (TXU+/- or TXS+/-). Typically no resistor is required for operation with cable lengths less than 100m. Great care must be taken to ensure system timing integrity when using cable lengths greater than 100m. Refer to the IEEE 802.3u standard, Clause 29 for more details on system topology issues.
This value must be determined empirically. Refer to section 3.7.8 for further detail.
RTX I 28 EXTENDED CABLE RESISTOR: A resistor connected between this pin and GND
or V
CC
adjusts the amplitude of the differential transmit outputs (TXU+/- or TXS+/-
). Typically no resistor is required for operation with cable lengths less than 100m. Great care must be taken to ensure system timing integrity when using cable lengths greater than 100m. Refer to the IEEE 802.3u standard, Clause 29 for more details on system topology issues.
This value must be determined empirically. Refer to section 3.7.8 for further detail.
TXU­TXU+
O 2526UNSHIELDED TWISTED PAIR OUTPUT: This differential output pair sources the
10BASE-T transmit data and link pulses for UTP cable.
TXS­TXS+
O 2324SHIELDED TWISTED PAIR OUTPUT: This differential output pair sources the
10BASE-T transmit data and link pulses for STP cable.
RXI­RXI+
I 2021TWISTED PAIR RECEIVE INPUT: These are the differential 10BASE-T receive
data inputs for either STP or UTP.
2.2 100 Mb/s SERIAL PMD INTERFACE
I = TTL/CMOS input O = TTL/CMOS output Z = TRI-STATE output J = IEEE 1149.1 pin
2.0 Pin Description (Continued)
8
National SemiconductorVersion A
DP83840A 10/100 Mb/s Ethernet Physical Layer
2.4 CLOCK INTERFACE
Signal Name Type Pin # Description
REFIN I 86 REFERENCE INPUT: 25 MHz TTL reference clock input. This clock can be
supplied from an external oscillator module or from the CLK25M output (pin 81).
CLK25M O, Z 81 25 MHz CLOCK OUTPUT: Derived from the 50 MHz OSCIN input. When not in
use, this clock output may be shut off through software by setting bit 7 of the PCS Configuration Register at address 17h. This output remains unaffected by hardware and software reset.
OSCIN I 2 OSCILLATOR INPUT: 50 MHz  50 ppm external TTL oscillator input. If not used,
pull down to GND (4.7 kΩ pull down resistor suggested).
X2 O 34 CRYSTAL OSCILLATOR OUTPUT: External 20 MHz  0.005% crystal
connection. Used for 10BASE-T timing. When using an external 20 MHz oscillator connected to X1 or with no reference to X1, leave this pin unconnected.
X1 I 33 CRYSTAL OSCILLATOR INPUT: External 20 MHz  0.005% crystal connection.
Used for 10BASE-T timing and Auto-Negotiation. If not used, this pin should be pulled up to V
CC.
(4.7 kΩ pull up resistor suggested). When pulled high, the DP83840A detects this condition, enables the internal 2.5 divider, and switches the 10 Mb/s and Auto-Negotiation circuitry to the internally derived 20 MHz clock.
I = TTL/CMOS input O = TTL/CMOS output Z = TRI-STATE output J = IEEE 1149.1 pin
2.0 Pin Description (Continued)
9
National SemiconductorVersion A
DP83840A 10/100 Mb/s Ethernet Physical Layer
2.5 DEVICE CONFIGURATION INTERFACE
Signal Name Type Pin # Description
AN0 I 95 AN0: This is a quad state input pin (i.e, 1, M, 0, Clock) that works in conjunction
with the AN1 pin to control the forced or advertised operating mode of the DP83840A according to the following table. The value on this pin is set by connecting the input pin to GND (0), V
CC
(1), a continuous 25 MHz clock (C), or
leaving it unconnected (M.) The unconnected state, M, refers to the mid-level (VCC2) set by internal resistors. This value is latched into the DP83840A at power-up/reset. See section 3.9 for more details.
AN1 I 46 AN1: This is a quad-state input pin (i.e., 1, M, 0, Clock) that works in conjunction
with the AN0 pin to control the forced or advertised operating mode of the DP83840A according to the table given in the AN0 pin description above. The value on this pin is set by connecting the input pin to GND (0), V
CC
(1), a continuous
25 MHz clock (C), or leaving it unconnected (M.) This value is latched into the DP83840A at power-up/reset. See Section 3.9 for more details.
REPEATER I, J 47 REPEATER/NODE MODE: Selects REPEATER mode when set high and NODE
mode when set low. In REPEATER mode (or NODE mode with Full Duplex configured), the Carrier Sense (CRS) output from the DP83840A is asserted due to receive activity only. In NODE mode, and not configured for Full Duplex operation, CRS is asserted due to either receive and transmit activity.
The Carrier Integrity Monitor (CIM) function is automatically disabled when this pin is set low (node mode) and enabled when this pin is set high (Repeater mode) in order to facilitate 802.3u /D5.3 CIM requirements.
At power-up/reset, the value on this pin (set by a pull-up or pull-down resistor, typically 4.7 kΩ) is latched to bit 12 of the PCS Configuration Register, address 17h.
AN1 AN0 Forced Mode
0 M 10BASE-T, Half-Duplex without Auto-Negotiation
1 M 10BASE-T, Full Duplex without Auto-Negotiation M 0 100BASE-TX, Half-Duplex without Auto-Negotiation M 1 100BASE-TX, Full Duplex without Auto-Negotiation C M 100BASE-TX, Full Duplex without Auto-Negotiation
ANAR, register address 04h default modified
M C 100BASE-TX, Full Duplex without Auto-Negotiation
ANAR, register address 04h default modified
C C 100BASE-TX, Half Duplex without Auto-Negotiation
ANAR, register address 04h default modified
AN1 AN0 Advertised Mode
M M All capable (i.e. Full Duplex for 10BASE-T and 100BASE-
TX) advertised via Auto-Negotiation 0 0 10BASE-T, Half-Duplex advertised via Auto-Negotiation 0 1 10BASE-T, Full Duplex advertised via Auto-Negotiation 1 0 100BASE-TX, Half-Duplex advertised via Auto-Negotiation 1 1 100BASE-TX, Full Duplex advertised via Auto-Negotiation
C 1 100BASE-TX Full Duplex and 10BASE-T Full Duplex
advertised via Auto-Negotiation
C 0 100BASE-TX Half Duplex and 10BASE-T Half Duplex
advertised via Auto-Negotiation 1 C 100BASE-TX Half Duplex and 100BASE-TX Full Duplex
advertised via Auto-Negotiation 0 C 10BASE-T Half Duplex and 10BASE-T Full Duplex
advertised via Auto-Negotiation
I = TTL/CMOS input O = TTL/CMOS output Z = TRI-STATE output J = IEEE 1149.1 pin
2.0 Pin Description (Continued)
10
National SemiconductorVersion A
DP83840A 10/100 Mb/s Ethernet Physical Layer
10BTSER I, J 98 SERIAL/NIBBLE SELECT:
10 Mb/s Serial Operation: When set high, this input selects serial data transfer mode. Transmit and receive
data is exchanged serially at a 10 MHz clock rate on the least significant bits of the nibble-wide MII data buses, pins TXD[0] and RXD[0] respectively. This mode is intended for use with the DP83840A connected to a device (MAC or Repeater) using a 10 Mb/s serial interface. Serial operation is not supported in 100 Mb/s mode, therefore this input is ignored during 100 Mb/s operation
10 and 100 Mb/s Nibble Operation: When set low, this input selects the MII compliant nibble data transfer mode.
Transmit and receive data is exchanged in nibbles on the TXD[3:0] and RXD[3:0] pins respectively.
At power-up/reset, the value on this pin (set by a pull-up or pull-down resistor, typically 4.7 kΩ) is latched into bit 9 of the 10BASE-T Status Register at address 1Bh.
BPALIGN I, J 99 BYPASS ALIGNMENT: Allows 100 Mb/s transmit and receive data streams to
bypass all of the transmit and receive operations when set high. Refer to Figures 4 and 5. Note that the PCS signaling (CRS, RX_DV, RX_ER, and COL) is not meaningful during this mode. Additionally TXD[4]/TX_ER is always active.
At power-up/reset, the value on this pin (set by a pull-up or pull-down resistor, typically 4.7 kΩ) is latched into bit 12 of the Loopback, Bypass and Receiver Error Mask Register at address 18h.
BP4B5B I, J 100 BYPASS 4B5B ENCODER/DECODER: Allows 100 Mb/s transmit and receive
data streams to bypass the 4B to 5B encoder and 5B to 4B decoder circuits when set high. All PCS signaling (CRS, RX_DV, RX_ER, and COL) remain active and unaffected by this bypass mode. Additionally, TXD[4]/TX_ER is gated by TX_EN. Refer to figures 4 and 5.
At power-up/reset, the value on this pin (set by a pull-up or pull-down resistor, typically 4.7 kΩ) is latched into bit 14 of the Loopback, Bypass and Receiver Error Mask Register at address 18h.
BPSCR I, J 1 BYPASS SCRAMBLER/DESCRAMBLER: Allows 100 Mb/s transmit and receive
data streams to bypass the scrambler and descrambler circuits when set high to facilitate 100BASE-FX operation. All PCS signaling (CRS, RX_DV, RX_ER, and COL) remain active and unaffected by this bypass mode. Refer to figures 4 and 5.
At power-up/reset, the value on this pin (set by a pull-up or pull-down resistor, typically 4.7 kΩ) is latched into bit 13 of the Loopback, Bypass and Receiver Error Mask Register at address 18h.
2.5 DEVICE CONFIGURATION INTERFACE
I = TTL/CMOS input O = TTL/CMOS output Z = TRI-STATE output J = IEEE 1149.1 pin
2.0 Pin Description (Continued)
11
National SemiconductorVersion A
DP83840A 10/100 Mb/s Ethernet Physical Layer
2.6 LED INTERFACE
These outputs can be used to drive LEDs directly, or can be used to provide status information to a network management device. Refer to Figure 12 for the LED connection diagram. Refer to section 2.2 for a description of how to generate LED indication of 100 Mb/s mode. Note that these outputs are standard CMOS voltage drivers and not
open-drain.
Signal Name Type Pin # Description
LED1 O, J 42 TRANSMIT LED: Indicates the presence of transmit activity (TXE asserted) for 10
Mb/s and 100 Mb/s operation. Active low. If bit 2 (
LED1_MODE) of the PCS Configuration Register (address 17h) is set
high, then the
LED1 pin function is changed to indicate the status of the Disconnect Function as defined by the state of bit 5 (CON_STATUS) in the PHY address register (address 19h).
The DP83840A incorporates a “monostable” function on the
LED1 output. This ensures that even minimum size packets generate adequate LED ON time (approximately 50ms) for visibility.
LED2 O, J 41 RECEIVE LED: Indicates the presence of any receive activity (CRS active) for 10
Mb/s and 100 Mb/s operation. Active low. The DP83840A incorporates a “monostable” function on the
LED2 output. This ensures that even minimum size packets generate adequate LED ON time (approximately 50ms) for visibility.
LED3 O, J 38 LINK LED: Indicates Good Link status for 10 Mb/s and 100 Mb/s operation. Active
low. 100 Mb/s Link is established as a result of the assertion of the Signal Detect input
to the DP83840A.
LED3 will assert after SD has remained asserted for a minimum
of 500µs.
LED3 will deassert immediately following the deassertion of Signal
Detect. 10 Mb/s Link is established as a result of the reception of at least seven
consecutive normal Link Pulses or the reception of a valid 10BASE-T packet which will cause the assertion of
LED3. LED3 will deassert in accordance with the
Link Loss Timer as specified in 802.3.
LED4 O, J 37 POLARITY/FULL DUPLEX LED: Indicates Good Polarity status for 10 Mb/s
operation. Can be configured to Indicate Full Duplex mode status for 10 Mb/s or 100 Mb/s operation. Active low.
The DP83840A automatically compensates for polarity inversion. Polarity inversion is indicated by the assertion of
LED4.
If bit 1 (
LED4_MODE) in the PCS Configuration Register (address 17h) is set
high, the
LED4 pin function is changed to indicate Full Duplex mode status for 10
Mb/s and 100 Mb/s operation.
LED5 O, J 36 COLLISION LED: Indicates the presence of collision activity for 10 Mb/s and 100
Mb/s Half Duplex operation. This LED has no meaning for 10 Mb/s or 100 Mb/s Full Duplex operation and will remain deasserted. Active low.
I = TTL/CMOS input O = TTL/CMOS output Z = TRI-STATE output J = IEEE 1149.1 pin
2.0 Pin Description (Continued)
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2.7 IEEE 1149.1 INTERFACE
The IEEE 1149.1 Standard Test Access Port and Boundary Scan (sometimes referred to as JTAG) interface signals allow system level boundary scan to be performed. These pins may be left floating when JTAG testing is not required.
Signal Name Type Pin # Description
TDO O, Z 50 TEST DATA OUTPUT: Serial instruction/test output data for the IEEE 1149.1
scan chain. If Boundary-Scan is not implemented this pin may be left unconnected (NC).
TDI I 91 TEST DATA INPUT: Serial instruction/test input data for the IEEE 1149.1 scan
chain.
TRST I 92 TEST RESET: An asynchronous low going pulse will reset and initialize the IEEE
1149.1 test circuitry. If Boundary-Scan is not implemented, this pin may be left unconnected (NC) since
it has an internal pull-up resistor (10 kΩ).
TCLK I 93 TEST CLOCK: Test clock for the IEEE 1149.1 circuitry.
If Boundary-Scan is not implemented this pin may be left unconnected (NC).
TMS I 94 TEST MODE SELECT: Control input to the IEEE 1149.1 test circuitry.
If Boundary-Scan is not implemented, this pin may be left unconnected (NC) since it has an internal pull-up resistor (10 kΩ).
I = TTL/CMOS input O = TTL/CMOS output Z = TRI-STATE output J = IEEE 1149.1 pin
2.0 Pin Description (Continued)
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2.8 PHY ADDRESS INTERFACE
The DP83840A PHYAD[4:0] inputs provide up to 32 unique PHY address options. An address selection of all zeros (00000) will result in a PHY isolation condition. See the Isolate bit description in the BMCR, address 00h, Section 4.2
for further detail.
Signal Name Type Pin # Description
PHYAD[0] (LBEN)
I/O, J 49 PHY ADDRESS [0]: PHY address sensing pin (bit 0) for multiple PHY
applications. PHY address sensing is achieved by strapping a pull-up/pull-down resistor (typically 4.7 kΩ) to this pin as required.
The pull-up/pull-down status of this pin is latched into the PHYAD address register (address 19h) during power up/reset.
This pin is also the Loopback Enable output pin (LBEN) for the 100 Mb/s Serial PMD Interface. See Section 2.2 for further detail.
PHYAD[1] (ENCSEL)
I/O, J 53 PHY ADDRESS [1]: PHY address sensing pin (bit 1) for multiple PHY
applications. PHY address sensing is achieved by strapping a pull-up/pull-down resistor (typically 4.7 kΩ) to this pin as required.
The pull-up/pull-down status of this pin is latched into the PHYAD address register (address 19h) during power up/reset.
This pin is also the Encode Select output pin (ENCSEL) for the 100 Mb/s Serial PMD Interface. See Section 2.2 for further detail.
PHYAD[2] (CRS)
I/O, Z, J 66 PHY ADDRESS [2]: PHY address sensing pin (bit 2) for multiple PHY
applications. PHY address sensing is achieved by strapping a pull-up/pull-down resistor (typically 4.7 kΩ) to this pin as required.
The pull-up/pull-down status of this pin is latched into the PHYAD address register (address 19h) during power up/reset.
This pin is also the Carrier Sense output pin (CRS) for the MII Interface. See Section 2.1 for further detail.
PHYAD[3] (SPEED_100)
I/O, J 89 PHY ADDRESS [3]: PHY address sensing pin (bit 3) for multiple PHY
applications. PHY address sensing is achieved by strapping a pull-up/pull-down resistor (typically 4.7 kΩ) to this pin as required.
The pull-up/pull-down status of this pin is latched into the PHYAD address register (address 19h) during power up/reset.
This pin is also the Speed 100 Mb/s output pin (SPEED_100) for optional control of peripheral circuitry. See Section 2.2 for further detail.
PHYAD[4] (RX_ER)
I/O, Z, J 63 PHY ADDRESS [4]: PHY address sensing pin (bit 4) for multiple PHY
applications. PHY address sensing is achieved by strapping a pull-up/pull-down resistor (typically 4.7 kΩ) to this pin as required.
The pull-up/pull-down status of this pin is latched into the PHYAD address register (address 19h) during power up/reset.
This pin is also the Receive Error output pin (RX_ER) for the MII Interface. See Section 2.1 for further detail.
2.9 MISCELLANEOUS
Signal Name Type Pin # Description
RESET I, J 44 RESET: Active high input that initializes or reinitializes the DP83840A. See
section 3.10 for further detail.
LOWPWR I, J 3 LOW POWER MODE SELECT: Active high input that enables the low power
mode (100 Mb/s operation only). See section 3.13 for further detail.
I = TTL/CMOS input O = TTL/CMOS output Z = TRI-STATE output J = IEEE 1149.1 pin
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2.10 POWER AND GROUND PINS
The power (VCC) and ground (GND) pins of the DP83840A are grouped in pairs into four categories--TTL/CMOS Input pairs, TTL/CMOS Output and I/O pairs, 10 Mb/s pairs and 100 Mb/s pairs. This grouping allows for optimizing the layout and filtering of the power and ground supplies to this device. Refer to section 5.0 for fur ther detail relating to power supply filtering.
Signal Name Pin # Description
GROUP A - TTL/CMOS INPUT SUPPLY PAIRS
IOVCC1, IOGND1 96, 97 TTL Input/Output Supply #1 IOVCC2, IOGND2 39, 40 TTL Input/Output Supply #2 IOVCC3, IOGND3 51, 52 TTL Input/Output Supply #3 PCSVCC, PCSGND 70, 71 Physical Coding Sublayer Supply
GROUP B- TTL/CMOS OUTPUT AND I/O SUPPLY PAIRS
IOVCC4, IOGND4 59, 60 TTL Input/Output Supply #4 RCLKGND 61 Receive Clock Ground, No paired V
CC
IOVCC5, IOGND5 68, 69 TTL Input/Output Supply #5 IOVCC6, IOGND6 79, 80 TTL Input/Output Supply #6 REFVCC, REFGND 84, 85 25 MHz Clock Supply
GROUP C- 10 Mb/s SUPPLY PAIRS
RXVCC, RXGND 18, 19 Receive Section Supply TDVCC, TDGND 22, 27 Transmit Section Supply PLLVCC, PLLGND 31, 30 Phase Locked Loop Supply OVCC, OGND 32, 35 Internal Oscillator Supply
GROUP D- 100 Mb/s SUPPLY PAIRS
ANAVCC, ANAGND 9, 10 Analog Section Supply CRMVCC, CRMGND 12, 11 Clock Recovery Module Supply ECLVCC 15 ECL Outputs Supply CGMVCC, CGMGND 87, 88 Clock Generator Module Supply
2.11 SPECIAL CONNECT PINS
Signal Name Type Pin # Description
NC 13
14 83
NO CONNECT: These pins are reserved for future use. Leave them unconnected (floating).
RES_0 4 RESERVED_0: These pins are reserved for future use. This pin must be
connected to ground. For future upgradability, connect this pin to GND via a 0Ω resistor.
RES_0 J 45
48 90
RESERVED_0: These pins are reserved for future use. These pins must be connected to ground. For future upgradability, connect these pins to GND via 0Ω
resistors.
I = TTL/CMOS input O = TTL/CMOS output Z = TRI-STATE output J = IEEE 1149.1 pin
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3.0 Functional Description
The 100BASE-X section of the device consists of the following functional blocks:
• Transmitter
• Receiver
• Clock Generation Module (CGM)
• Clock Recovery Module (CRM)
The 100BASE-X and 10BASE-T sections share the following functional blocks:
• PCS Control
• MII Registers
• IEEE 1149.1 Controller
• IEEE 802.3u Auto-Negotiation
A description of each of these functional blocks follows.
3.1 PCS CONTROL
The IEEE 802.3u 100BASE-X Standard defines the Physical Coding Sublayer (PCS) as the transmit, receive and carrier sense functions. These functions within the DP83840A are controlled via external pins and internal registers via the MII serial management interface.
3.1.1 100BASE-X Bypass Options
The DP83840A incorporates a highly flexible transmit and receive channel architecture. Each of the major 100BASE­X transmit and receive functional blocks of the DP83840A may be selectively bypassed to provide increased flexibility for various applications.
3.1.1.1 Bypass 4B5B and 5B4B
The 100BASE-X 4B5B code-group encoder in the transmit channel and the 100BASE-X 5B4B code-group decoder in the receive channel may be bypassed by setting the BP_4B5B bit in the LBREMR (bit 14, register address 18h). The default value for this bit is set by the BP4B5B pin 100 at power-up/reset. This mode of operation is referred to as the “Transparent” mode as further defined in section 3.12.
3.1.1.2 Bypass Scrambler and Descrambler
The 100BASE-T scrambler in the transmit channel and the 100BASE-T descrambler in the receive channel may be bypassed by setting the BP_SCR bit in the LBREMR (bit 13, register address 18h). The default value for this bit is set by the BPSCR signal (pin 1) at power-up/reset. This bypass option has been included to facilitate 100BASE-FX operation where data scrambling is not required.
3.1.1.3 Bypass NRZI Encoder and Decoder
The 100BASE-X NRZI encoder in the transmit channel and the 100BASE-X NRZI decoder in the receive channel may be bypassed by setting the NRZI_EN bit in the PCR (bit 15, register address 17h). The default for this bit is a 1, which enables the NRZI encoder and decoder. This bypass option has been included for test purposes only and should not be selected during normal 100BASE-X operation.
3.1.1.4 Bypass Align
The 100BASE-X transmit channel operations (4B5B code­group encoder, scrambler and NRZ to NRZI) and the 100BASE-X receive channel operations (NRZI to NRZ, descrambler and 4B5B code-group decoding) may all be bypassed by setting the BP_ALIGN bit in the LBREMR (bit 12, register address 18h). The default value for this bit is set by the BP_ALIGN signal (pin 99) at power-up/reset.
The bypass align function is intended for those repeater applications where none of the transmit and receive channel operations are required. This mode of operation is referred to as the “Phaser” mode as further defined in section 3.12
3.1.2 Repeater Mode
66) is asserted for receive activity only. When set low, the CRS output is asserted for either receive or transmit activity. The default value for this bit is set by the REPEATER pin 47 at power-up/reset.
When the Repeater mode of operation is selected during 10 Mb/s operation, all functional parameters other than CRS remain unaffected. CRS will respond only to receive activity during 10 Mb/s repeater mode.
When the repeater mode of operation is selected during 100 Mb/s operation, there are three parameters that are directly effected. First, as with 10 Mb/s Repeater operation, CRS will only respond to receive activity.
Second, in compliance with D5 of the 802.3 standard, the Carrier Integrity Monitor (CIM) function is automatically enabled for detection and reporting of bad start of stream delimiters (whereas in node mode the CIM is disabled).
Finally, the deasser tion of CRS during the reception of a long Jabber event is effected by the selection of the repeater mode. If the repeater mode is selected, CRS will remain asserted even if a long Jabber event (>722us) occurs. This facilitates proper handling of a jabber event by the Repeater Controller device. This Jabber related CRS function can be over-ridden. Refer to section 4.15 (bit 11 of register 19h) for further detail.
3.1.3 MII Control
The DP83840A provides three basic MII modes of operation:
3.1.3.1 100 Mb/s Operation
For 100 Mb/s operation, the MII operates in nibble mode with a clock rate of 25 MHz. This clock rate is independent of bypass conditions.
In normal (non-bypassed) operation the MII data at RXD[3:0] and TXD[3:0] is nibble wide. In bypass mode (BP_4B5B or BP_ALIGN set) the MII data takes the form of
3.0 Functional Description (Continued)
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5-bit code-groups. The lower significant 4 bits appear on TXD[3:0] and RXD[3:0] as normal, and the most significant bits (TXD[4] and RXD[4]) appear on the TX_ER and RX_ER pins respectively.
3.1.3.2 10 Mb/s Nibble Mode Operation
For 10 Mb/s nibble mode operation, the MII cloc k r ate is 2.5 MHz. The 100BASE-X bypass functions do not apply to 10 Mb/s operation.
3.1.3.3 10 Mb/s Serial Mode Operation
For applications based on serial repeater controllers for 10 Mb/s operation, the DP83840A accepts NRZ serial data on the TXD[0] input and provides NRZ serial data output on RXD[0] with a clock rate of 10 MHz. The unused MII inputs and outputs (TXD[3:1] and RXD[3:1] are ignored during serial mode. The PCS control signals, CRS, COL, TX_ER, RX_ER, and RX_DV, continue to function normally.
This mode is selected by setting the 10BT_SER bit in the 10BTSR (bit 9, register address 1Bh). The default value for this bit is set by the 10BTSER pin 98 at power-up/reset.
3.2 MII SERIAL MANAGEMENT REGISTER ACCESS
The MII specification defines a set of thirty-two 16-bit status and control registers that are accessible through the serial management data interface pins MDC and MDIO. The DP83840A implements all the required MII registers as well as several optional registers. These registers are fully described in Section 4. A description of the serial management access protocol follows.
3.2.1 Serial Management Access Protocol
The serial control interface consists of two pins, Management Data Clock (MDC) and Management Data Input/Output (MDIO). MDC has a maximum clock rate of
2.5 MHz and no minimum rate. The MDIO line is bi­directional and may be shared by up to 32 devices. The MDIO frame format is shown in Table I.
The MDIO pin requires a pull-up resistor (1.5KΩ) which, during IDLE and Tur naround, will pull MDIO high. Prior to initiating any transaction, the station management entity sends a sequence of 32 contiguous logic ones on MDIO to provide the DP83840A with a sequence that can be used to establish synchronization. This preamble may be generated either by driving MDIO high for 32 consecutive MDC clock cycles, or by simply allowing the MDIO pull-up resistor to pull the MDIO PHY pin high during which time 32 MDC clock cycles are provided.
The Start code is indicated by a <01> pattern. This assures the MDIO line transitions from the default idle line state.
MDC
MDIO
00011 110000000
(STA)
Idle Start
Opcode
(Read)
PHY Address
(PHYAD = 0Ch)
Register Address
(00h = BMCR)
TA
Register Data
Z
MDIO
(PHY)
Z
Z
Z
0 0 011000100000000
Z
Idle
Z
Z
MDC
MDIO
00011110000000
(STA)
Idle Start
Opcode (Write)
PHY Address
(PHYAD = 0Ch)
Register Address
(00h = BMCR)
TA
Register Data
Z
0 0 0 000 00000000
Z
Idle
1000
ZZ
FIGURE 2. Typical MDC/MDIO Read Operation
FIGURE 3. Typical MDC/MDIO Write Operation
Table I.
MII Management
Serial Protocol
<idle><start><op code><device addr> <reg addr><turnaround><data><idle>
Read Operation <idle><01><10><AAAAA> <RRRRR><Z0><xxxx xxxx xxxx xxxx><idle> Write Operation <idle><01><01><AAAAA> <RRRRR><10><xxxx xxxx xxxx xxxx><idle>
3.0 Functional Description (Continued)
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the second bit of Turnaround and follows this with the required data. Figure 2 shows the timing relationship between MDC and the MDIO as driven/received by the Station Management Entity (STA) and the DP83840A (PHY) for a typical register read access.
For write transactions, the station management entity writes data to an addressed DP83840A eliminating the requirement for MDIO Turnaround. The Turnaround time is filled by the management entity inserting <10> for these two bits. Figure 3 shows the timing relationship for a typical MII register write access.
3.2.1.1 Preamble Suppression
The DP83840A supports a Preamble Suppression mode as indicated by a one in bit 6 of the Basic Mode Status Register (BMSR, address 01h.) If the station management entity (i.e. MAC or other management controller) determines that all PHYs in the system support Preamble Suppression by returning a one in this bit, then the station management entity need not generate preamble for each management transaction.
The DP83840A requires a single initialization sequence of 32 bits of preamble following power-up/hardware reset. This requirement is generally met by the mandatory pull-up resistor on MDIO or the management access made to determine whether Preamble Suppression is supported.
While the DP83840A will respond to management accesses without preamble,
a minimum of one idle bit
between management transactions is required
as specified
in IEEE 802.3u.
3.2.2 PHY Address Sensing
The DP83840A can be set to respond to any of the possible 32 PHY addresses. Each DP83840A connected to a common serial MII must have a unique address. It should be noted that while an address selection of all zeros <00000> will result in PHY Isolate mode, this will not effect serial management access.
The DP83840A provides five PHY address pins, the state of which are latched into the PHY Address Register (PAR) at system power-up/reset. These pins are described in Section 2.8. For further detail relating to the latch-in timing requirements of the PHY Address pins, as well as the other hardware configuration pins, refer to section 3.10.
3.2.3 MII Management
The MII may be used to connect PHY devices to MAC or repeater devices in 10/100 Mb/s systems.
3.2.4 MII Isolate Mode
A 100BASE-X PHY connected to the mechanical MII interface specified in IEEE 802.3u is required to have a default value of one in bit 10 of the Basic Mode Control Register (BMCR, address 00h.) The DP83840A will set this bit to one if the PHY Address is set to 00000 upon power­up/hardware reset. Otherwise, the DP83840A will set this bit to zero upon power-up/hardware reset.
With bit 10 in the BMCR set to one the DP83840A does not respond to packet data present at TXD[3:0], TX_EN, and TX_ER inputs and presents a high impedance on the TX_CLK, RX_CLK, RX_DV, RX_ER, RXD[3:0], COL, and CRS outputs. The CLK_25M output remains active and the DP83840A will continue to respond to all management transactions.
While in Isolate mode, the TD +/-, TXU +/-, and TXS +/­outputs will not transmit packet data. However, the DP83840A will default to 100 Mb/s mode and source 100BASE-X Idles during the Isolate condition. Data present on the RD +/- and RXI +/- inputs is ignored and the link will be forced to disable.
3.3 100BASE-X TRANSMITTER
The 100BASE-X transmitter consists of functional blocks which convert synchronous 4-bit nibble data, as provided by the MII, to a scrambled 125 Mb/s serial data stream. This data stream may be routed either to a twisted pair PMD such as the DP83223 TWISTER for 100BASE-TX signaling, or to an optical PMD for 100BASE-FX applications. The block diagram in Figure 4 provides an overview of each functional block within the 100BASE-X transmit section.
The Transmitter section consists of the following functional blocks:
• code-group Encoder and Injection block (bypass option)
• Scrambler block (bypass option)
• NRZ to NRZI encoder block (bypass option)
3.3.1 100 Mb/s Transmit State Machine
The DP83840A implements the 100BASE-X transmit state machine diagram as given in the IEEE 802.3u Standard, Clause 24.
3.3.2 Code-group Encoding and Injection
The code-group encoder converts 4 bit (4B) nibble data generated by the MAC into 5 bit (5B) code-groups for transmission. This conversion is required to allow control data to be combined with packet data code-groups. Refer to Table II for 4B to 5B code-group mapping details.
The code-group encoder substitutes the first 8 bits of the MAC preamble with a J/K code-group pair (11000 10001). The code-group encoder continues to replace subsequent 4Bdata with corresponding 5B code-groups. At the end of the transmit packet, upon the deassertion of Transmit Enable signal from the MAC or Repeater, the code-group encoder injects the T/R code-group pair (01101 00111) indicating end of frame.
After the T/R code-group pair, the code-group encoder continuously injects IDLEs into the transmit data stream until the next transmit packet is detected (reassertion of Transmit Enable).
3.3.3 Scrambler
The scrambler is required to control the radiated emissions at the media connector and on the twisted pair cable (for
3.0 Functional Description (Continued)
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100BASE-TX applications). By scrambling the data, the total energy launched onto the cable is randomly distributed over a wide frequency range. Without the scrambler, energy levels at the PMD and on the cable would peak beyond FCC limitations at frequencies related to repeating 5B sequences (i.e., continuous transmission of IDLEs).
The scrambler is configured as a closed loop linear feedback shift register (LFSR) with an 11-bit polynomial. The output of the closed loop LFSR is combined with the NRZ 5B data from the code-group encoder via an X-OR logic function. The result is a scrambled data stream with sufficient randomization to decrease radiated emissions at certain frequencies by as much as 20 dB. The DP83840A uses the PHYID as determined by the PHYAD [4:0] pins to set a unique seed value for the scrambler so that the total energy produced by a multi-PHY application (i.e. repeater) distributes the energy across the spectrum and reduces overall EMI.
3.3.4 NRZ to NRZI Encoder
After the transmit data stream has been scrambled and serialized, the data must be NRZI encoded in order to comply with the TP-PMD standard for 100BASE-TX transmission over Category-5 un-shielded twisted pair cable. Normal operation for both twisted pair and fiber applications requires that this encoder remain engaged. This encoder should only be bypassed for system testing and or debug.
3.3.5 TX_ER
3.4 100BASE-X RECEIVER
The 100BASE-X receiver consists of several functional blocks which are required to recover and condition the 125 Mb/s receive data stream as specified by the IEEE 802.3u Standard. The 125 Mb/s receive data stream may originate from a twisted pair transceiver such as the DP83223 TWISTER in a 100BASE-TX application. Alternatively, the receive data stream may be generated by an optical receiver as in a 100BASE-FX application. The block diagram in Figure 5 provides an overview of each functional block within the 100BASE-X receive section.
The Receiver block consists of the following functional blocks:
• Clock Recovery block
• NRZI to NRZ decoder block (bypass option)
• Descrambler block (bypass option)
• code-group Alignment block (bypass option)
• 5B/4B code-group Decoder block (bypass option)
• Collision Detect block
• Carrier Sense block
• 100 Mb/s Receive State Machine
• Far End Fault Indication block
• Link Integrity Monitor block
• Carrier Integrity Monitor Block
3.4.1 Clock Recovery
The Clock Recovery Module (CRM) accepts 125 Mb/s scrambled or unscrambled NRZI data from an external twisted pair or fiber PMD receiver. The CRM locks onto the 125 Mb/s data stream and extracts a 125 MHz reference clock. The extracted and synchronized clock and data are used as required by the synchronous receive operations as generally depicted in Figure 5.
The CRM is implemented using an advanced digital Phase Locked Loop (PLL) architecture that replaces sensitive analog circuits. Using digital PLL circuitry allows the DP83840A to be manufactured and specified to tighter tolerances.
3.4.2 NRZI to NRZ
In a typical application the NRZI to NRZ decoder is required in order to present NRZ formatted data to the descrambler (or to the code-group alignment block if the descrambler is bypassed).
The receive data stream, as recovered by the PMD receiver, is in NRZI format, therefore the data must be decoded to NRZ before further processing.
3.4.3 Descrambler
A 5-bit parallel (code-group wide) descrambler is used to de- scramble the receive NRZ data. To reverse the data scrambling process, the descrambler has to generate an identical data scrambling sequence (N) in order to recover the original unscrambled data (UD) from the scrambled data (SD) as represented in the equations:
Synchronization of the descrambler to the original scrambling sequence (N) is achieved based on the knowledge that the incoming scrambled data stream consists of scrambled IDLE data. After the descrambler has recognized 16 consecutive IDLE code-groups, where an IDLE code-group in 5B NRZ is equal to five consecutive ones (11111), it will synchronize to the receive data stream and generate unscrambled data in the form of unaligned 5B code-groups.
In order to maintain synchronization, the descrambler must continuously monitor the validity of the unscrambled data that it generates. To ensure this, a line state monitor and a hold timer are used to constantly monitor the synchronization status. Upon synchronization of the descrambler the hold timer starts a 722µs countdown. Upon detection of sufficient IDLE code-groups within the 722µs period, the hold timer will reset and begin a new countdown. This monitoring operation will continue indefinitely given a properly operating network connection with good signal integrity. If the line state monitor does not recognize sufficient unscrambled IDLE code-groups within the 722µs period, the entire descrambler will be forced out
UD SD N⊕()=
SD UD N⊕()=
3.0 Functional Description (Continued)
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CODE-GROUP
ENCODER
SCRAMBLER
NRZ TO NRZI
ENCODER
PARALLEL
TO SERIAL
TD +/-
_NRZI_EN
BYP_SCR
BYP_4B5B
TX_CLK TXD[3:0]
FROM CGM
BYP_ALIGN
100BASE-X LOOPBACK
MUX
MUX
MUX
MUX
CARRIER SENSE
COLLISON
DETECTION
FAR END FAULT
INDICATION
100 Mb/s
TX STATE
MACHINE
FIGURE 4. 100BASE-X Transmitter
3.0 Functional Description (Continued)
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Table II. 4B5B code-group Encoding/Decoding.
*Control code-groups I, J, K, T and R in data fields will be mapped as invalid codes, together with RX_ER asserted. **Normally, invalid codes (V) are mapped to 6h on RXD[3:0] with RX_ER asserted. If the CODE_ERR bit in the LBREMR (bit 4, register address 18h) is
set, the invalid codes are mapped to 5h on RXD[3:0] with RX_ER asserted. Refer to section 4.14 for further detail.
Name PCS 5B Code-group MII 4B Nibble Code
DATA CODES
0 11110 0000 1 01001 0001 2 10100 0010 3 10101 0011 4 01010 0100 5 01011 0101 6 01110 0110 7 01111 0111 8 10010 1000 9 10011 1001 A 10110 1010
B 10111 1011 C 11010 1100 D 11011 1101 E 11100 1110 F 11101 1111
IDLE AND CONTROL CODES
H 00100 Halt code-group - Error code
I 11111 Inter-Packet Idle - 0000*
J 11000 First Start of Packet - 0101* K 10001 Second Start of Packet - 0101* T 01101 First End of Packet - 0000* R 00111 Second End of Packet - 0000*
INVALID CODES
V 00000 0110 or 0101* V 00001 0110 or 0101* V 00010 0110 or 0101* V 00011 0110 or 0101* V 00101 0110 or 0101* V 00110 0110 or 0101* V 01000 0110 or 0101* V 01100 0110 or 0101* V 10000 0110 or 0101* V 11001 0110 or 0101*
3.0 Functional Description (Continued)
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CODE-GROUP
DECODER
CODE-GROUP
ALIGNMENT
DESCRAMBLER
NRZI TO NRZ
DECODER
CLOCK RECOVER Y
MODULE
100 Mb/s RX STATE MACHINE
RX_DATA VALID
SSD DETECT
CARRIER SENSE
COLLISON
DETECTION
SERIAL
TO
PARALLEL
RX_CLK RXD[3:0]
BYP_ALIGN
BYP_4B5B
BYP_SCR
NRZI_EN
RD +/-
CLK
DATA
FAR END FAULT
INDICATION
LINK INTEGRITY
MONITOR
CARRIER
INTEGRITY
MONITOR
MUX
MUX
MUX
MUX
100BASE-X
LOOPBACK
FIGURE 5. 100BASE-X Receiver
3.0 Functional Description (Continued)
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DP83840A 10/100 Mb/s Ethernet Physical Layer
of the current state of synchronization and reset in order to re-acquire synchronization.
The value of the time-out for this timer ma y be modified from 722 s to 2 ms by setting bit 14 of the PCR (address 17h) to one. The 2 ms option allows applications with Maximum Transmission Units (packet sizes) larger than IEEE 802.3 to maintain descrambler synchronization (i.e. Token Ring/ Fast-Ethernet switch/router applications).
Additionally, this timer may be disabled entirely by setting bit 13 of the PCR (address 17h) to one. The disabling of the time-out timer is not recommended as this will eventually result in a lack of synchronization between the transmit scrambler and the receive descrambler which will corrupt data.
3.4.4 Code-group Alignment
The code-group alignment module operates on unaligned 5-bit data from the descrambler (or, if the descrambler is bypassed, directly from the NRZI/NRZ decoder) and converts it into 5B code-group data (5 bits). code-group alignment occurs after the J/K code-group pair is detected. Once the J/K code-group pair (11000 10001) is detected, subsequent data is aligned on a fixed boundary.
3.4.5 Code-group Decoder
The code-group decoder functions as a look up table that translates incoming 5B code-groups into 4B nibbles. The code-group decoder first detects the J/K code-group pair preceded by IDLE code-groups and replaces the J/K with MAC preamble. Specifically, the J/K 10-bit code-group pair is replaced by the nibble pair (0101 0101). All subsequent 5B code-groups are converted to the corresponding 4B nibbles for the duration of the entire packet. This conversion ceases upon the detection of the T/R code­group pair denoting the End of Stream Delimiter (ESD) or with the reception of a minimum of two IDLE code-groups.
3.4.6 Collision Detect
Half Duplex collision detection for 100 Mb/s follows the model of 10BASE-T (refer to section 3.7.3). Collision detection is indicated by the COL pin of the MII whenever both the transmit and receive functions within the DP83840A attempt to process packet data simultaneously.
For Full Duplex applications the COL signal is never asserted.
3.4.7 Carrier Sense
Carrier Sense (CRS) is asserted, as a function of receive activity, upon the detection of two non-contiguous zeros occurring within any 10-bit boundary of the receive data stream. CRS is asserted, as a function of transmit activity (depending on the mode of operation), whenever the TX_EN (transmit enable) input to the DP83840A is asserted.
For 100 Mb/s Half Duplex operation (non-repeater mode), CRS is asserted during either packet transmission or reception.
For 100 Mb/s Full Duplex operation, the behavior of CRS depends on bit 6 of the LBREMR (address 18h). If this bit is zero, then CRS is asserted only due to receive activity. If this bit is one, then CRS is asserted only due to transmit
activity. This operation allows flexibility for interfacing a Full Duplex MAC to the DP83840A.
When the IDLE code-group pair is detected in the receive data stream, CRS is deasserted. In modes where transmit activity results in the assertion of CRS, the deassertion of TX_EN results in the immediate deassertion of CRS.
The carrier sense function is independent of code-group alignment.
3.4.8 100 Mb/s Receive State Machine
The DP83840A implements the 100BASE-X receive state machine diagram as given in ANSI/IEEE Standard 802.3u/ D5, Clause 24.
3.4.9 100BASE-X Link Integrity Monitor
The 100BASE-X Link Integrity Monitor function (LIM) allows the receiver to ensure that reliable data is being received. Without reliable data reception, the LIM will halt both transmit and receive operations until such time that a valid link is detected (i.e. good link.)
If Auto-Negotiation is not enabled, then a valid link will be indicated once SD+/- is asserted continuously for 500 µs.
If Auto-Negotiation is enabled, then Auto-Negotiation will further qualify a valid link as follows:
The descrambler must receive a minimum of 15 IDLE code groups for proper link initialization
Auto-Negotiation must determine that the 100BASE-X function should be enabled.
A valid link may be detected externally by either the
LED3 output or by reading bit 2 of the Basic Mode Status Register (address 01h.)
3.4.10 Bad SSD Detection
A Bad Start of Stream Delimiter (Bad SSD) is an error condition that occurs in the 100BASE-X receiver if carrier is detected (CRS asserted) and a valid /J/K/ set of code groups (SSD) is not received.
If this condition is detected, then the DP83840A will assert RX_ER and present RXD[3:0] = 1110 to the MII for the cycles that correspond to received 5B code-groups until at least two IDLE code groups are detected. In addition, the False Carrier Event Counter (address 12h) and the RX_ER Counter (address 15h) will be incremented by one.
Once at least two IDLE code groups are detected, RX_ER and CRS become de-asserted.
3.4.11 Far End Fault Indication
Auto-Negotiation provides a mechanism for transferring information from the Local Station to the Link Partner that a remote fault has occurred for 100BASE-TX. As Auto­Negotiation is not currently specified for operation over fiber, the Far End Fault Indication function (FEFI) provides this capability for 100BASE-FX applications.
3.0 Functional Description (Continued)
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DP83840A 10/100 Mb/s Ethernet Physical Layer
A remote fault is an error in the link that one station can detect while the other cannot. An example of this is a disconnected wire at a station’s transmitter. This station will be receiving valid data and detect that the link is good via the Link Integrity Monitor, but will not be able to detect that its transmission is not propagating to the other station.
A 100BASE-FX station that detects such a remote fault may modify its transmitted IDLE stream from all ones to a group of 84 ones followed by a single zero (i.e. 16 IDLE code groups followed by a single Data 0 code group.) This is referred to as the FEFI IDLE pattern.
If the FEFI function has been enabled via bit 8 of the PAR (address 19h), then the DP83840A will halt all current operations and transmit the FEFI IDLE pattern when SD+/­is de-asserted following a good link indication from the Link Integrity Monitor. Transmission of the FEFI IDLE pattern will continue until SD+/- is asserted.
If three or more FEFI IDLE patterns are detected by the DP83840A, then bit 4 of the Basic Mode Status Register (address 01h) is set to one until read by management. Additionally, upon detection of Far End Fault, all receive and transmit MII activity is disabled/ignored.
This function is optional for 100BASE-FX compliance and should be disabled for 100BASE-TX compliance.
Note: The first FEFI IDLE pattern may contain more than 84 ones as the pattern may have started during IDLE transmission. Also, the FEFI IDLE pattern will not cause carrier detection.
3.4.12 Carrier Integrity Monitor
The Carrier Integrity Monitor function (CIM) protects the repeater from transient conditions that would otherwise cause spurious transmission due to a faulty link. This function is required for repeater applications and is not specified for node applications.
The REPEATER pin (pin # 47) determines the default state of bit 5 of the PCR (Carrier Integrity Monitor Disable, address 17h) to automatically enable or disable the CIM function as required for IEEE 802.3u/D5 compliant applications. After power-up/hardware reset, software may enable or disable this function independent of repeater or node/switch mode.
If the CIM determines that the link is unstable, the DP83840A will not propagate the received data or control signaling to the MII and will ignore data transmitted via the MII. The DP83840A will continue to monitor the receive stream for valid carrier events.
Detection of an unstable link condition will cause bit 5 of the PAR (address 19h) to be set to one. This bit is cleared to zero upon a read operation once a stable link condition is detected by the CIM. Upon detection of a stable link, the DP83840A will resume normal operations.
The Disconnect Counter (address 12h) increments each time the CIM determines that the link is unstable.
3.5 CLOCK GENERATION MODULE
The Clock Generation Module (CGM) within the DP83840A can be configured for several different applications. This offers the flexibility of selecting a clocking scheme that is best suited for a given design.
This section describes the operation of the CGM from both the device perspective as well as at the system level such as in an adapter or repeater. A tolerance of no greater than
50ppm is recommended for all external references driving the CGM.
It is important to note that in order to provide proper device initialization, even when operating the DP83840A in 100BASE-X only mode, the 10BASE-T sections of the device must also be provided with a clock upon device power-up/reset to ensure proper device initialization. This is taken into consideration in the following subsections.
It is also important to note that the state of the internal divide-by-two flip-flop, between OSCIN and CLK25M, is unknown at power-up/reset. Therefore, the phase of CLK25M relative to that of OSCIN can be either 0 degrees or 180 degrees.
3.5.1 Single 50 MHz Reference
This option will support 10BASE-T, 100BASE-X, or combined 10/100.
A 50 MHz oscillator can be used to drive the OSCIN input. This reference is internally divided by two and then routed to the CLK25M output pin. By connecting the CLK25M output directly to the REFIN input pin, the 25 MHz reference is allowed to drive the 100 Mb/s module. The 50 MHz signal is also divided by 2.5 internally to provide the 20 MHz reference directly to the 10 Mb/s module. This option is shown in Figure 6.
CC
(4.7 kΩ pull-up resistor recommended)).
It should be noted that an external 20 MHz reference driving the X1 input will provide the best over all transmit jitter performance from the integrated 10BASE-T transmitter.
3.5.2 50 MHz and 20 MHz References
This option will support 10BASE-T, 100BASE-X, or combined 10/100.
For improved jitter perfor mance in the 10 Mb/s module, an external 20 MHz oscillator can be used to drive the X1 pin. Alternatively, a 20 MHz cr ystal network can be connected across pins X1 and X2 to provide the required reference f or the 10 Mb/s module. The 100 Mb/s module must still receive a 25 MHz reference which can be provided by a 50 MHz oscillator as described in 3.5.1. This option is shown in Figure 7 (20 MHz oscillator module) and Figure 8 (20 MHz crystal).
3.5.3 25 MHz and 20 MHz References
This option will support 10BASE-T, 100BASE-X, or combined 10/100.
A 25 MHz reference, either from an oscillator or a system clock can directly drive the 100 Mb/s module via the REFIN input.
A separate 20 MHz reference from either an oscillator or a crystal network must be provided to the X1 and X2 inputs as described in 3.5.2. This option is shown in Figure 9.
Because the CLK25M output is not used with this clocking scheme, it is recommended that it be disabled by setting bit 7 of the PCS Configuration Register (PCR address 17h).
3.0 Functional Description (Continued)
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National SemiconductorVersion A
DP83840A 10/100 Mb/s Ethernet Physical Layer
3.5.4 Single 25 MHz Reference
This option will support only 100BASE-X as might be required in 100BASE-X repeaters that do not employ Auto­Negotiation. 10BASE-T and Auto-Negotiation will not function when using this clocking scheme.
A 25 MHz reference, either from an oscillator or a system clock can directly drive the 100 Mb/s module via the REFIN input.
The same 25 MHz reference must be also be connected to the OSCIN input in order to meet the requirement for the presence of a clock in the 10BASE-T module to ensure proper device initialization upon power-up/reset. Even though the divide by 2.5 of the 25MHz clock does not yield the typical 20MHz 10BASE-T reference, it is still sufficient for device initialization purposes. This option is shown in Figure 10.
Because the CLK25M output is not used with this clocking scheme, it is recommended that it be disabled by setting bit7 of the PCS Configuration Register (PCR address 17h).
3.5.5 System Clocking
The DP83840A clock options help to simplify single port adapter designs as well as multi-port repeaters. The TX_CLK allows 10 Mb/s MII data to be received in either
parallel or serial modes as described in Section 3.1.3. The standard MII interface clock rate options are as follows:
TX_CLK = 25 MHz for 100 Mb/s nibble mode TX_CLK = 2.5 MHz for 10 Mb/s nibble mode Additionally, the DP83840A provides: TX_CLK = 10 MHz for 10 Mb/s serial mode
3.5.5.1 Adapter Clock Distribution Example
In most single port adapter applications, where only one DP83840A is required, providing a single 50 MHz oscillator reference is sufficient for deriving the required MAC and PHY layer clocks as illustrated in Figure 11. Based on the 50 MHz reference, the DP83840A can generate its own internal 20 MHz reference for the 10 Mb/s module. Additionally, the DP83840A can generate the required 25 MHz reference for its 100 Mb/s module.
During 100 Mb/s operation the 25 MHz reference generated by the DP83840A is available at the TX_CLK output pin. This can be used for synchronization with the MAC layer device. During 10 Mb/s operation the TX_CLK pin sources either a 2.5 MHz or 10 MHz reference to the MAC layer device. Figure 10 provides an example of the clock distribution in a typical node design based on the DP83840A.
FIGURE 6. Single 50 MHz Reference
DIV 2.5
MUX
DIV 2.0
50 MHz
OSC
V
CC
4.7 kΩ
X2
X1
OSCIN
CLK25M
REFIN
TX_CLK
SPEED
SELECT
20 MHz TO 10 Mb/s SECTION
25 MHz TO 100 Mb/s SECTION
25 MHz FROM 100 Mb/s SECTION
2.5 MHz (OR 10 MHz) FROM 10 Mb/s SECTION
 50ppm
3.0 Functional Description (Continued)
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National SemiconductorVersion A
DP83840A 10/100 Mb/s Ethernet Physical Layer
FIGURE 7. 50 MHz and 20 MHz References
MUX
DIV 2.0
50 MHz
OSC
X2
X1
OSCIN
CLK25M
REFIN
TX_CLK
SPEED
SELECT
20 MHz TO 10 Mb/s SECTION
25 MHz TO 100 Mb/s SECTION
25 MHz FROM 100 Mb/s SECTION
2.5 MHz (OR 10 MHz) FROM 10 Mb/s SECTION
 50ppm
20 MHz
OSC
 50ppm
MUX
DIV 2.0
50 MHz
OSC
X2
X1
OSCIN
CLK25M
REFIN
TX_CLK
SPEED
SELECT
20 MHz TO 10 Mb/s SECTION
25 MHz TO 100 Mb/s SECTION
25 MHz FROM 100 Mb/s SECTION
2.5 MHz (OR 10 MHz) FROM 10 Mb/s SECTION
 50ppm
20 MHZ 0.005%
* 33 pF
* 33 pF
* NOTE:
REFER TO CRYSTAL MANUFACTURE FOR RECOMMENDED CRYSTAL LOAD CAPACITANCE
FIGURE 8. 50 MHz Reference and 20 MHz Crystal
3.0 Functional Description (Continued)
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National SemiconductorVersion A
DP83840A 10/100 Mb/s Ethernet Physical Layer
FIGURE 9. 25 MHz and 20 MHz References
MUX
DIV 2.0
20 MHz
OSC
4.7 kΩ
X2
X1
OSCIN
CLK25M
REFIN
TX_CLK
SPEED
SELECT
20 MHz TO 10 Mb/s SECTION
25 MHz TO 100 Mb/s SECTION
25 MHz FROM 100 Mb/s SECTION
2.5 MHz (OR 10 MHz) FROM 10 Mb/s SECTION
 50ppm
25 MHz SYSTEM
REFERENCE
 50ppm
FROM 10 Mb/s SECTION
MUX
DIV 2.0
X2
X1
OSCIN
CLK25M
REFIN
TX_CLK
SPEED
SELECT
25 MHz TO 100 Mb/s SECTION
25 MHz FROM 100 Mb/s SECTION
25 MHz SYSTEM
REFERENCE
 50ppm
V
CC
4.7 kΩ
DIV 2.5
TO 10 Mb/s SECTION
FIGURE 10. Single 25 MHz Reference
3.0 Functional Description (Continued)
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DP83840A 10/100 Mb/s Ethernet Physical Layer
3.5.5.2 Repeater Clock Distribution Example
The clock distribution within a multi-port repeater can be designed in a variety of ways. Figure 12 provides a simplified example of one possible timing distribution scheme in a 100 Mb/s only repeater design. It should be noted that in order to support Auto-Negotiation, a 20 MHz reference would be required for each DP83840A device.
ENDEC
(DP83850
100RIC)
DP83840A (1) DP83840A (2) DP83840A (12)
DP83223
(1)
DP83223
(2)
DP83223
(12)
25 MHz
25
MHz
BUFFER
RX_CLK
MAC PHY
PMD
RXD
TX_CLK
RX_CLK
TXD
TD
RD
50
MHz
FIGURE 12. Typical 100 Mb/s Repeater Clock Interconnection
FIGURE 11. Typical Adapter Clock and Data Typical
Due to the demanding timing constraints required to maintain standards compliance, great care must be taken in the design and layout of a multi-port repeater system. The example provided in Figure 12 illustrates interconnection only and should not be considered as a reference design.
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