NSC DP83815DUJB-AB, DP83815DVNG-AP, DP83815DVNG-AB, DP83815DUJB-PXE, DP83815DUJB-AP Datasheet
DP83815 10/100 Mb/s I ntegrated PCI Ethern et Media Access Control ler and Physical Layer (MacPhyter™)
© 2002 National Semiconductor Corporation www.national.com
1
September 2002
DP83815 10/100 Mb/s Integrated PCI Ethernet Media Access
Controller and Physical Layer (MacPhyter
™
)
General Description
DP83815 is a single-chip 10/100 Mb/s Ethernet Controller
for the PCI bus. It is targeted at low-cost, high volume PC
mother boards, adapter cards, and embedded systems.
The DP83815 fully implements the V2.2 33 MHz PCI bus
interface for host co mm un ica t io ns with power management
support. Packet descriptors and data are transferred via
bus-mastering, reducing the burden on the host CPU. The
DP83815 can support full duplex 10/100 Mb /s transmission
and reception, with minimum interframe gap.
The DP83815 device is an integration of an enhanced
version of the National Semiconductor PCI MAC/BIU
(Media Access Controller/Bus Interface Unit) and a 3.3V
CMOS physical layer interface.
Features
— IEEE 802.3 Compliant, PCI V2.2 MAC/BIU supports
traditional data rates of 10 Mb/s Ethernet and 100 Mb/s
Fast Ethernet (via internal phy)
— Bus master - burst sizes of up to 128 dwords (512 by tes)
— BIU compliant with PC 97 and PC 98 Hardware Design
Guides, PC 99 Hardware Design Guide draft, ACPI v1. 0,
PCI Power Management Specification v1.1, OnNow
Device Class Power Management Reference
Specification - Network Device Class v1.0a
— Wake on LAN (WOL) support compliant with PC98,
PC99, SecureOn, and OnNow, including directed
packets, Magic Packet, VLAN packets, ARP packets,
pattern match packets, and Phy status change
— Clkrun function for PCI Mobile Design Guide
— Virtual LAN (VLAN) and long frame support
— Support for IEEE 802.3x Full duplex flow control
— Extremely flexible Rx packet filtration including: single
address perfect filter with MSb masking, broadcast, 512
entry multicast/unicast hash table, deep packet pattern
matching for up to 4 unique patterns
— Statistics gathered for support of RFC 1213 (MIB II),
RFC 1398 (Ether-like MIB), IEEE 802.3 LME, reducing
CPU overhead for management
— Internal 2 KB Transmit and 2 KB Receive data FIFOs
— Serial EEPROM port with auto-load of configu ration da ta
from EEPROM at power-on
— Flash/PROM interface for remote boot support
— Fully integrated IEEE 802 .3/802.3u 3.3V CMOS physical
layer
— IEEE 802.3 10BASE-T transceiver with integrated filters
— IEEE 802.3u 100BASE-TX transceiver
— Fully integrated ANSI X3.263 compliant TP-PMD
physical sublayer with adaptive equalization and
Baseline Wander compensation
— IEEE 802.3u Auto-Negotiation - advertised features
configurable via EEPROM
— Full Duplex support for 10 and 100 Mb/s data rates
— Single 25 MHz reference clock
— 144-pin LQFP and 160-pin LBGA packages
— Low power 3.3V CMOS d es ign with ty pic al co nsu mp tion
of 561 mW operating, 380 mW during WOL mode, 33
mW sleep mode
— IEEE 802.3u MII for connecting alternative external
Physical Layer Devices
System Diagram
PCI Bus
DP83815
EEPROM
Isolation
10/100 Twisted Pair
BIOS ROM
(optional)
(optional)
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
Magic Packet is a trademark of Advanced Micro Devices, Inc.
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DP83815
Table of Contents
1.0 Connection Diagram . . . . . . . . . . . . . . . . . . 4
1.1 144 LQFP Package (VNG) . . . . . . . . . . . . 4
1.2 160 pin LBGA Package (UJB) . . . . . . . . . . 5
2.0 Pin Description . . . . . . . . . . . . . . . . . . . . . . 6
3.0 Functional Description . . . . . . . . . . . . . . . 13
3.1 MAC/BIU . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.1.1 PCI Bus Interfa ce . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.1.2 T x M A C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
3.1.3 Rx M AC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
3.2 Buffer Management . . . . . . . . . . . . . . . . . 15
3.2.1 Tx Buffer Manager . . . . . . . . . . . . . . . . . . . . . . . . .15
3.2.2 Rx Buffer Manager . . . . . . . . . . . . . . . . . . . . . . . . .15
3.2.3 Packet Recognition . . . . . . . . . . . . . . . . . . . . . . . .15
3.2.4 MI B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
3.3 Interface Definitions . . . . . . . . . . . . . . . . . 16
3.3.1 PCI System Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.3.2 Boo t PROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.3.3 EE PR OM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.3.4 Cl o c k . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
3.4 Physical Layer . . . . . . . . . . . . . . . . . . . . . 18
3.4.1 Auto-Negotiation . . . . . . . . . . . . . . . . . . . . . . . . . .18
3.4.2 Auto-Negotiation Register Control . . . . . . . . . . . . .18
3.4.3 Auto-Negotiation Parallel Detection . . . . . . . . . . . .18
3.4.4 Auto-Negotiation Restart . . . . . . . . . . . . . . . . . . . .19
3.4.5 Enabling Auto-Negotiation via Software . . . . . . . .19
3.4.6 Auto-Negotiation Complete Time . . . . . . . . . . . . . .19
3.5 LED Interfaces . . . . . . . . . . . . . . . . . . . . . 19
3.6 Half Duplex vs. Full Duplex . . . . . . . . . . . 20
3.7 Phy Loopback . . . . . . . . . . . . . . . . . . . . . 20
3.8 Status Information . . . . . . . . . . . . . . . . . . 20
3.9 100BASE-TX TRANSMITTER . . . . . . . . . 20
3.9.1 Code-group Encoding and Injection . . . . . . . . . . .21
3.9.2 Sc r a mb l e r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1
3.9.3 NRZ to NRZI Encoder . . . . . . . . . . . . . . . . . . . . . .22
3.9.4 Binary to MLT-3 Convertor / Common Driver . . . . 22
3.10 100BASE-TX Receiver . . . . . . . . . . . . . . 23
3.10.1 Input and Base Line Wander Compensation . . . .23
3.10.2 Signal Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
3.10.3 Digital Adaptive Equalization . . . . . . . . . . . . . . . .25
3.10.4 Line Quality Monitor . . . . . . . . . . . . . . . . . . . . . . .26
3.10.5 MLT-3 to NRZI Decoder . . . . . . . . . . . . . . . . . . . .26
3.10.6 Clock Recovery Module . . . . . . . . . . . . . . . . . . . .27
3.10.7 NRZI to N R Z . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.10.8 Seria l to Pa r a l l e l . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.10.9 De-scrambler . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.10.10 Code-group Alignment . . . . . . . . . . . . . . . . . . . .27
3.10.11 4B/5B Decoder . . . . . . . . . . . . . . . . . . . . . . . . . .27
3.10.12 100BASE-TX Link Integrity Monitor . . . . . . . . . .27
3.10.13 Bad SSD Detection . . . . . . . . . . . . . . . . . . . . . . 27
3.11 10BASE-T Transceiver Module . . . . . . . . 28
3.11.1 Operational Modes . . . . . . . . . . . . . . . . . . . . . . . .28
3.11.2 Smart Squelch . . . . . . . . . . . . . . . . . . . . . . . . . . .28
3.11.3 Coll i si o n D etection . . . . . . . . . . . . . . . . . . . . . . . . 28
3.11.4 Normal Link Pulse Detection/Generation . . . . . . .28
3.11.5 Jabber Function . . . . . . . . . . . . . . . . . . . . . . . . . .29
3.11.6 Autom a t ic Link Polarit y D e te ction . . . . . . . . . . . . . 29
3.11.7 10BASE-T Internal Loopback . . . . . . . . . . . . . . . .29
3.11.8 Transmit and Receive Filtering . . . . . . . . . . . . . . .29
3.11.9 Tran s m i t te r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 9
3.11.10 Rec e i v e r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
3.11.11 Far End Fault Indication . . . . . . . . . . . . . . . . . . . 29
3.12 802.3u MII . . . . . . . . . . . . . . . . . . . . . . . . 29
3.12.1 MII Access Configuration . . . . . . . . . . . . . . . . . . .29
3.12.2 MII Serial Management . . . . . . . . . . . . . . . . . . . . 29
3.12.3 MII Serial Management Access . . . . . . . . . . . . . 30
3.12.4 Serial Management Access Protocol . . . . . . . . . 30
3.12.5 Nibble-wide MII Data Inter face . . . . . . . . . . . . . . 30
3.12.6 Collision Detection . . . . . . . . . . . . . . . . . . . . . . . 31
3.12.7 Carrier Sense . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.0 Register Set . . . . . . . . . . . . . . . . . . . . . . . . 32
4.1 Configuration Registers . . . . . . . . . . . . . . 32
4.1.1 Configuration Identification Register . . . . . . . . . . . 32
4.1.2 Configuration Command and Status Register . . . 33
4.1.3 Configuration Revision ID Register . . . . . . . . . . . 34
4.1.4 Configuration Latency Timer Register . . . . . . . . . 35
4.1.5 Configuration I/O Base Address Register . . . . . . . 35
4.1.6 Configuration Memory Address Register . . . . . . . 36
4.1.7 Configuration Subsystem Identification Register . 36
4.1.8 Boot ROM Configuration Register . . . . . . . . . . . . 37
4.1.9 Capabilities Pointer Register . . . . . . . . . . . . . . . . 37
4.1.10 Configuration Interrupt Select Register . . . . . . . . 38
4.1.11 Power Management Capabilities Register . . . . . 38
4.1.12 Power Management Control and Status Register 39
4.2 Operational Registers . . . . . . . . . . . . . . . 40
4.2.1 Command Register . . . . . . . . . . . . . . . . . . . . . . . . 41
4.2.2 Configuration and Media Status Register . . . . . . . 42
4.2.3 EEPROM Access Register . . . . . . . . . . . . . . . . . . 44
4.2.4 EEPROM Map . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4.2.5 PCI Test Control Register . . . . . . . . . . . . . . . . . . . 45
4.2.6 Interrupt Status Register . . . . . . . . . . . . . . . . . . . . 46
4.2.7 Interrupt Mask Register . . . . . . . . . . . . . . . . . . . . 47
4.2.8 Interrupt Enable Register . . . . . . . . . . . . . . . . . . . 49
4.2.9 Transmit Descriptor Pointer Regi ster . . . . . . . . . . 49
4.2.10 Transmit Configuration Register . . . . . . . . . . . . . 50
4.2.11 Receive Descriptor Pointer Regis ter . . . . . . . . . . 51
4.2.12 Receive Configuration Register . . . . . . . . . . . . . 52
4.2.13 CLKRUN Control/Status Regis te r . . . . . . . . . . . . 53
4.2.14 Wake Command/Status Register . . . . . . . . . . . . 55
4.2.15 Pause Control/Status Register . . . . . . . . . . . . . . 57
4.2.16 Receive Filter/Match Control Register . . . . . . . . 58
4.2.17 Receive Filter/Mat ch Data Regis ter . . . . . . . . . . 59
4.2.18 Receive Filter Logic . . . . . . . . . . . . . . . . . . . . . . 60
4.2.19 Boot ROM Address Regis te r . . . . . . . . . . . . . . . . 64
4.2.20 Boot ROM Data Register . . . . . . . . . . . . . . . . . . 64
4.2.21 Silicon Revision Registe r . . . . . . . . . . . . . . . . . . 64
4.2.22 Management Information Base Control Register 65
4.2.23 Management Information Base Registers . . . . . . 66
4.3 Internal PHY Registers . . . . . . . . . . . . . . . 67
4.3.1 Basic Mode Control Register . . . . . . . . . . . . . . . . 67
4.3.2 Basic Mode Status Register . . . . . . . . . . . . . . . . . 68
4.3.3 PHY Identifier Register #1 . . . . . . . . . . . . . . . . . . 69
4.3.4 PHY Identifier Register #2 . . . . . . . . . . . . . . . . . . 69
4.3.5 Auto-Negotiation Advertisement Register . . . . . . 69
4.3.6 Auto-Negotiation Link Partner Ability Register . . . 70
4.3.7 Auto-Negotiate Expansion Register . . . . . . . . . . . 71
4.3.8 Auto-Negotiation Next Page Transmit Register . . 71
4.3.9 PHY Status Register . . . . . . . . . . . . . . . . . . . . . . . 72
4.3.10 MII Interrupt Contr o l Regis ter . . . . . . . . . . . . . . . 74
4.3.11 MII Interrupt Status and Misc. Control Register . 74
4.3.12 False Carrier Sense Counter Register . . . . . . . . 75
4.3.13 Receiver Error Counter Register . . . . . . . . . . . . . 75
4.3.14 100 Mb/s PCS Configuration and Status Register 75
4.3.15 PHY Control Register . . . . . . . . . . . . . . . . . . . . . 76
4.3.16 10BASE-T Stat us/Control Register . . . . . . . . . . . 77
4.4 Recommended Registers Configuration .78
5.0 Buffer Management . . . . . . . . . . . . . . . . . .79
5.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . .79
5.1.1 Descriptor Format . . . . . . . . . . . . . . . . . . . . . . . . . 79
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DP83815
5.1.2 Single Descriptor Packets . . . . . . . . . . . . . . . . . . .81
5.1.3 Multiple Descriptor Packets . . . . . . . . . . . . . . . . . .82
5.1.4 De s criptor List s . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
5.2 Transmit Architecture . . . . . . . . . . . . . . . 83
5.2.1 Transmit State Machine . . . . . . . . . . . . . . . . . . . . . 83
5.2.2 Transmit Data Flow . . . . . . . . . . . . . . . . . . . . . . . .85
5.3 Receive Architecture . . . . . . . . . . . . . . . . 86
5.3.1 Receive State Machine . . . . . . . . . . . . . . . . . . . . . 86
5.3.2 Re c e i v e D a t a Fl o w . . . . . . . . . . . . . . . . . . . . . . . . . 88
6.0 Power Management and Wake-On-LAN. . 89
6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . 89
6.2 Definitions (for this document only) . . . . . 89
6.3 Packet Filtering . . . . . . . . . . . . . . . . . . . . 89
6.4 Power Management . . . . . . . . . . . . . . . . 89
6.4.1 D0 S ta t e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
6.4.2 D1 S ta t e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
6.4.3 D2 S ta t e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
6.4.4 D3hot State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
6.4.5 D3 c o l d St a te . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
6.5 Wake-On-LAN (WOL) Mode . . . . . . . . . . 90
6.5.1 Entering WOL Mode . . . . . . . . . . . . . . . . . . . . . . .90
6.5.2 W a ke Ev e n t s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
6.5.3 Exiting WOL Mode . . . . . . . . . . . . . . . . . . . . . . . . 91
6.6 Sleep Mode . . . . . . . . . . . . . . . . . . . . . . .91
6.6.1 Entering Sleep Mode . . . . . . . . . . . . . . . . . . . . . . 91
6.6.2 Exiting Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . 91
6.7 Pin Configuration for Power Management 91
7.0 DC and AC Specifications . . . . . . . . . . . . . 92
7.1 DC Specifications . . . . . . . . . . . . . . . . . . . 92
7.2 AC Specifications . . . . . . . . . . . . . . . . . . . 93
7.2.1 PCI Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . 93
7.2.2 X1 Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 93
7.2.3 Power On Reset (PCI Active) . . . . . . . . . . . . . . . . 94
7.2.4 Non Power On Reset . . . . . . . . . . . . . . . . . . . . . . 94
7.2.5 POR PCI Inactive . . . . . . . . . . . . . . . . . . . . . . . . . 95
7.2.6 PCI Bus Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
7.2.7 EE PR O M Auto-Load . . . . . . . . . . . . . . . . . . . . . 101
7.2.8 Boot PROM/FLASH . . . . . . . . . . . . . . . . . . . . . . 102
7.2.9 100BASE-TX Transmit . . . . . . . . . . . . . . . . . . . 103
7.2.10 10BASE-T Transmit End of Packet . . . . . . . . . 104
7.2.11 10 Mb/s Jabber Timing . . . . . . . . . . . . . . . . . . 104
7.2.12 10BASE-T Normal Link Pulse . . . . . . . . . . . . . 105
7.2.13 Auto-Negotiation Fast Link Pulse (FLP) . . . . . . 105
7.2.14 Media Independent Interface (MII . . . . . . . . . . . 106
List of Figures
Figure 3-1 DP83815 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Figure 3-2 MAC/BIU Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Figure 3-3 Ethernet Packet Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Figure 3-4 DSP Physical Layer Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Figure 3-5 LED Loading Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Figure 3-6 100BASE-TX Transmit Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Figure 3-7 Binary to MLT-3 conversion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Figure 3-8 100 M/bs Receive Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Figure 3-9 100BASE-TX BLW Event Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Figure 3-10 EIA/TIA Attenuation vs. Frequency for 0, 50, 100, 130 & 150 meters of CAT V cable . . . . . . . .26
Figure 3-11 MLT-3 Signal Measured at AII after 0 meters of CAT V cable. . . . . . . . . . . . . . . . . . . . . . . . . . .26
Figure 3-12 MLT-3 Signal Measured at AII after 50 meters of CAT V cable. . . . . . . . . . . . . . . . . . . . . . . . . .26
Figure 3-13 MLT-3 Signal Measured at AII after 100 meters of CAT V cable. . . . . . . . . . . . . . . . . . . . . . . . .26
Figure 3-14 10BASE-T Twisted Pair Smart Squelch Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Figure 3-15 Typical MDC/MDIO Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Figure 3-16 Typical MDC/MDIO Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Figure 4-1 Pattern Buffer Memory - 180h words (word = 18bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Figure 4-2 Hash Table Memory - 40h bytes addressed on word boundaries. . . . . . . . . . . . . . . . . . . . . . . .63
Figure 5-1 Single Descriptor Packets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
Figure 5-2 Multiple Descriptor Packets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
Figure 5-3 List and Ring Descriptor Organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
Figure 5-4 Transmit Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
Figure 5-5 Transmit State Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
Figure 5-6 Receive Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
Figure 5-7 Receive State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
List of Tables
Table 3-1 4B5B Code-Group Encoding/Decoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Table 3-2 Typical MDIO Frame Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Table 4-1 Configuration Register Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Table 4-2 Operational Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Table 4-3 MIB Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Table 5-1 DP83815 Descriptor Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
Table 5-2 cmdsts Common Bit Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
Table 5-3 Transmit Status Bit Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Table 5-4 Receive Status Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Table 5-5 Transmit State Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
Table 5-6 Receive State Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
Table 6-1 Power Management Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
Table 6-2 PM Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
4 www.national.com
DP83815
1.0 Connection Diagram
1.1 144 LQFP Package (VNG)
Order Number DP83815DVNG
See NS Package Number VNG144A
121
122
123
124
125
126
127
128
129
130
131
132
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
123456789
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
30
31
323329
Identification
Pin1
37
38
39
40
120
119
118
117
116
115
114
113
112
110
109
111
DEVSELN
TRDYN
IRDYN
FRAMEN
CBEN2
AD16
AD17
AD18
STOPN
PERRN
SERRN
PAR
CBEN1
AD15
AD14
AD13
AD12
AD11
AD10
AD9
PCIVSS4
AD8
AD19
AD20
AD21
AD22
AD23
IDSEL
PCIVSS2
PCIVDD3
VSSIO4
PCIVDD4
VDDIO4
PCIVSS3
PCIVDD2
CBEN3
AD24
AD25
AD26
CBEN0
MACVSS1
MACVDD1
RESERVED
VREF
PCIVDD1
AD29
AD31
PCIVSS1
REQN
GNTN
RSTN
INTAN
AD28
PCICLK
AD30
PMEN/CLKRUNN
TXIOVSS2
TXIOVSS1
TPTDP
TPTDM
NC
RXAVDD2
RXAVSS2
TPRDP
TPRDM
SUBGND2
AD27
AD7
AD6
AD5
PCIVSS5
MA1/LED10N
MA2/LED100N
MA3/EEDI
MA4/EECLK
MA5
MWRN
MD4/EEDO
MD3
EESEL
AD0
AD1
AD2
AD3
AD4
MD0
MCSN
MD1/CFGDISN
MD2
MD5
MD6
MD7
MA0/LEDACTN
PCIVDD5
VSSIO2
VDDIO2
MACVSS2
MACVDD2
VDDIO5
VSSIO5
MDIO
MDC
RXCLK
RXD0/MA6
RXD1/MA7
RXD2/MA8
RXD3/MA9
RXOE
RXER/MA10
RXDV/MA11
TXD3/MA15
COL/MA16
CRS
TXEN
TXCLK
TXD2/MA14
TXD1/MA13
TXD0/MA12
VSSIO3
VDDIO3
VSSIO1
VDDIO1
X2
X1
DP83815
SUBGND3
PHYVSS1
PHYVDD1
NC
3VAUX
363534
67
68
69
70
71
72
100
101
102
103
104
105
106
107
108
144
143
142
141
140
139
138
137
136
135
134
133
RXAVSS1
RXAVDD1
PWRGOOD
MRDN
TXDVDD
FXVDD
FXVSS
PHYVSS2
PHYVDD2
SUBGND1
RESERVED
NC
NC
RESERVED
TXDVSS
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1.0 Connection Diagram (Continued)
DP83815
1.2 160 pin LBGA Package (UJB)
Top View
Order Number DP83815DUJB
See NS Package Number UJB160A
Identification
Pin A1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
1
2
3
4
5
6
7
8
9
10
11
12
13
14
(Marked on Top)
6 www.national.com
DP83815
2.0 Pin Description
PCI Bus Interface
Symbol
LQFP Pin
No(s)
LBGA Pin
No(s) Dir Description
AD[31-0] 66, 67, 68, 70,
71, 72, 73, 74,
78, 79, 81, 82,
83, 86, 87, 88,
101, 102, 104,
105, 106, 108,
109, 110, 112,
113, 115, 116,
118, 1 19, 120,
121
K3, K2, K4,
L3, L2, M1,
N3, P3, L4
N5, M5, L5,
N6, L6, N7,
P7, N10, L10,
M11, N11,
P12, N12,
M13, M14,
L12, L14,
K13, K14,
K11, J13, J14,
J12
I/O Address and Data: Multiplexed address and data bus. As a bus
master, the DP83815 will drive address during the first bus phase.
During subsequent phases, the DP83815 will either read or write
data expecting the target to increment its address pointer. As a bus
target, the DP83815 will decode each address on the bus and
respond if it is the target being addressed.
CBEN[3-0] 75,
89,
100,
111
N4,
L7,
M10,
L13
I/O Bus Command/Byte Enable: During the address phase these
signals define the “bus command” or the type of bus transaction that
will take place. During the data phase these pins indicate which byte
lanes contain valid data. CBEN[0] applies to byte 0 (bits 7-0) and
CBEN[3] applies to byte 3 (bits 31-24) in the Little Endian Mode. In
Big Endian Mode, CBEN[3] applies to byte 0 (bits 31-24) and
CBEN[0] applies to byte 3 (bits 7-0).
PCICLK 60 H4 I Clock: This PCI Bus clock provides timing for all bus phases. The
rising edge defines the start of each phase. The clock frequency
ranges from 0 to 33 MHz.
DEVSELN 95 P9 I/O Device Select: As a bus master, the DP83815 samples this signal to
insure that the destination address for the data transfer is recognized
by a PCI target. As a target, the DP83815 asserts this signal low
when it recognizes its address after FRAMEN is asserted.
FRAMEN 91 M7 I/O Frame: As a bus master, this signal is asserted low to indicate the
beginning and duration of a bus transaction. Data transfer takes
place when this signal is asserted. It is de-asserted before the
transaction is in its final phase. As a target, the device monitors this
signal before decoding the address to check if the current transaction
is addressed to it.
GNTN 63 J2 I Grant: This signal is asserted low to indicate to the DP83815 that it
has been granted ownership of the bus by the central arbiter. This
input is used when the DP83815 is acting as a bus master.
IDSEL 76 M4 I Initialization Device Select: This pin is sampled by the DP83815 to
identify when configuration read and write accesses are intended for
it.
INTAN 61 J1 O Interrupt A: This signal is asserted low when an interrupt condition
occurs as defined in the Interrupt Status Register, Interrupt Mask,
and Interrupt Enable registers.
IRDYN 92 P8 I/O Initiator Ready: As a bus master, this signal will be asserted low
when the DP83815 is ready to complete the current data phase
transaction. This signal is used in conjunction with the TRYDN
signal. Data transaction takes place at the rising edge of PCICLK
when both IRDYN and TRDYN are asserted low. As a target, this
signal indicates that the master has put the data on the bus.
PAR 99 P10 I/O Parity: This signal indicates even parity across AD[31-0] and
CBEN[3-0] including the PAR pin. As a master, PAR is asserted
during address and write data phases. As a target, PAR is asserted
during read data phases.
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2.0 Pin Description (Continued)
DP83815
PERRN 97 N9 I/O Parity Error: The DP83815 as a master or target will assert this
signal low to indicate a parity error on any incoming data (except for
special cycles). As a bus master, it will monitor this signal on all write
operations (except for special cycles).
REQN 64 J4 O Request: The DP83815 will assert this signal low to request
ownership of the bus from the central arbiter.
RSTN 62 J3 I Reset: When this signal is asserted all outputs of DP83815 will be
tri-stated and the device will be put into a known state.
SERRN 98 L9 I/O System Error: This signal is asserted low by DP83815 during
address parity errors and system errors if enabled.
STOPN 96 M9 I/O Stop: This signal is asserted low by the target device to request the
master device to stop the current transaction.
TRDYN 93 N8 I/O Target Ready: As a master, this signal indicates that the target is
ready for the data during write operation and with the data during
read operation. As a target, this signal will be asserted low when the
(target) device is ready to complete the current data phase
transaction. This signal is used in conjunction with the IRDYN signal.
Data transaction takes place at the rising edge of PCICLK when both
IRDYN and TRDYN are asserted low.
PMEN/
CLKRUNN
59 H2 I/O Power Management Event/Clock Run Function : This pin is a dual
function pin. The function of this pin is determined by the
CLKRUN_EN bit 0 of the CLKRUN Control and Status register
(CCSR). Default operation of this pin is PMEN.
Power Management Eve nt: This signal is asserted low by DP83815
to indicate that a power management event has occurred. For pin
connection please refer to Section 6.7.
Clock Run Function: In this mode, this pin is used to indicate when
the PCICLK will be stopped.
3VAUX 122 J11 I PCI Auxiliary Voltage Sense: This pin is used to sense the
presence of a 3.3V auxiliary supply in order to define the PME
Support available. For pin connection please refer to Section 6.7.
This pin has an internal weak pull down.
PWRGOOD 123 H13 I PCI bus power good: Connected to PCI bus 3.3V power (not
3.3Vaux), this pin is used to sense the presence of PCI bus power.
This pin has an internal weak pull down.
PCI Bus Interface
Symbol
LQFP Pin
No(s)
LBGA Pin
No(s) Dir Description
8 www.national.com
2.0 Pin Description (Continued)
DP83815
Note: MII is normally tri-stated, unless enabled by CFG:EXT_PHY. See Section 4.2.2.
Media Independent Interface (MII)
Symbol
LQFP Pin
No(s)
LBGA Pin
No(s) Dir Description
COL 28 C5 I Collision Det e c t: The COL signal is asserted high asynchronously
by the external PMD upon detection of a collision on the medium. It
will remain asserted as long as the collision condition persists.
CRS 29 B5 I Carrier Sense: This signal is asserted high asynchronously by the
external PMD upon detection of a non-idle medium.
MDC 5 A11 O Management Data Clock: Clock signal with a maximum rate of 2.5
MHz used to transfer management data for the external PMD on the
MDIO pin.
MDIO 4 C11 I/O Management Data I/O: Bidirectional signal used to transfer
management information for the external PMD. (See Section 3.12.4
for details on connections when MII is used.)
RXCLK 6 D11 I Receive Clock: A continuous clock, sourced by an external PMD
device, that is recovered from the incoming data. During 100 Mb/s
operation RXCLK is 25 MHz and during 10 Mb/s this is 2.5 MHz.
RXD3/MA9,
RXD2/MA8,
RXD1/MA7,
RXD0/MA6
12,
11,
10,
7
A9,
B9,
D10,
B10
IOReceive Data: Sourced from an external PMD, that contains data
aligned on nibble boundaries and are driven synchronous to RXCLK.
RXD[3] is the most significant bit and RXD[0] is the least significant
bit.
BIOS ROM Address: During external BIOS ROM access, these
signals become part of the ROM address.
RXDV/MA11 15 B8 IOReceive Data Valid: Indicates that the external PMD is presenting
recovered and decoded nibbles on the RXD signals, and that RXCLK
is synchronous to the recovered data in 100 Mb/s operation. This
signal will encompass the frame, starting with the Start-of-Frame
delimiter (JK) and excluding any End-of-Frame delimiter (TR).
BIOS ROM Address: During external BIOS ROM access, this signal
becomes part of the ROM address.
RXER/MA10 14 D9 IOReceive Error: Asserted high synchronously by the external PMD
whenever it detects a media error and RXDV is asserted in 100 Mb/s
operation.
BIOS ROM Address: During external BIOS ROM access, this signal
becomes part of the ROM address.
RXOE 13 C9 O Receive Output Enable: Used to disable an external PMD while the
BIOS ROM is being accessed.
TXCLK 31 A4 I Transmit Clock: A continuous clock that is sourced by the external
PMD. During 100 Mb/s operation this is 25 MHz +/- 100 ppm. During
10 Mb/s operation this clock is 2.5 MHz +/- 100 ppm.
TXD3/MA15,
TXD2/MA14,
TXD1/MA13,
TXD0/MA12
25,
24,
23,
22
B6,
C6,
A6,
D7
OOTransmit Data: Signals which are driven synchronous to the TXCLK
for transmission to the external PMD. TXD[3] is the most significant
bit and TXD[0] is the least significant bit.
BIOS ROM Address: During external BIOS ROM access, these
signals become part of the ROM address.
TXEN 30 D5 O Transmit Enable: This signal is synchronous to TXCLK and
provides precise framing for data carried on TXD[3-0] for the external
PMD. It is asserted when TXD[3-0] contains valid data to be
transmitted.
9 www.national.com
2.0 Pin Description (Continued)
DP83815
Note: DP83815 supports NM27LV010 for the BIOS ROM interface device.
100BASE-TX/10BASE-T Interface
Symbol
LQFP Pin
No(s)
LBGA Pin
No(s) Dir Description
TPTDP,
TPTDM
54,
53
G1,
F1
A-O Transmit Data: Differential common output driver. This differential
common output is configurable to either 10BASE-T or 100BASE-TX
signaling:
10BASE-T: Transmission of Manchester encoded 10BASE-T packet
data as well as Link Pulses (including Fast Link Pulses for AutoNegotiation purposes).
100BASE-TX: Transmission of ANSI X3T12 compliant MLT-3 data.
The DP83815 will automatically configure this common output driver
for the proper signal type as a result of either forced configuration or
Auto-Negotiation.
TPRDP,
TPRDM
46,
45
D1,
C1
A-I Receive Data: Differential common input buffer. This differential
common input can be configured to accept either 100BASE-TX or
10BASE-T signaling:
10BASE-T: Reception of Manchester encoded 10BASE-T packet
data as well as normal Link Pulses and Fast Link Pulses for AutoNegotiation purposes.
100BASE-TX: Reception of ANSI X3T12 compliant scrambled MLT-3
data.
The DP83815 will automatically configure this common input buffer
to accept the proper signal type as a result of either forced
configuration or Auto-Negotiation.
BIOS ROM/Flash Interface
Symbol
LQFP Pin
No(s)
LBGA Pin
No(s) Dir Description
MCSN 129 G13 O BIOS ROM/Flash Chip Select: During a BIOS ROM/Flash
access, this signal is used to select the ROM device.
MD7, MD6, MD5,
MD4/EEDO, MD3,
MD2,
MD1/CFGDISN,
MD0
141, 140, 139,
138, 135,
134,
133,
132
D13,D12,D14,
E11, E14,
F11,
F13,
F12
I/O BIOS ROM/Flash Data Bus: During a BIOS ROM/Flash access
these signals are used to transfer data to or from the ROM/Flash
device.
MD[5:0] pins have internal weak pull ups.
MD6 and MD7 pins have internal weak pull downs.
MA5,
MA4/EECLK,
MA3/EEDI,
MA2/LED100LNK,
MA1/LED10LNK,
MA0/LEDACT
3,
2,
1,
144,
143,
142
B11,
A12,
B12,
C13,
C12,
C14
O BIOS ROM/Flash Address: During a BIOS ROM/Flash access,
these signals are used to drive the ROM/Flash address.
MWRN 131 F14 O BIOS ROM/Flash Writ e : During a BIOS ROM/Flash access, this
signal is used to enable data to be written to the Flash device.
MRDN 130 G11 O BIOS ROM/Flash Read: During a BIOS ROM/Flash access, this
signal is used to enable data to be read from the Flash device.
10 www.national.com
2.0 Pin Description (Continued)
DP83815
Note: DP83815 supports FM93C46 for the EEPROM device.
Clock Interface
Symbol
LQFP Pin
No(s)
LBGA Pin
No(s) Dir Description
X1 17 D8 I Crystal/Oscillator Input: This pin is the primary clock reference
input for the DP83815 and must be connected to a 25 MHz 0.005%
(50ppm) clock source. The DP83815 device supports either an
external crystal resonator connected across pins X1 and X2, or an
external CMOS-level oscillator source connected to pin X1 only.
X2 18 C7 O Crystal Output: This pin is used in conjunction with the X1 pin to
connect to an external 25 MHz crystal resonator device. This pin
must be left unconnected if an external CMOS oscillator clock source
is utilized. For more information see the definition for pin X1.
LED Interface
Symbol
LQFP Pin
No(s)
LBGA Pin
No(s) Dir Description
LEDACTN/MA0 142 C14 O TX/RX Activity: This pin is an output indicating transmit/receive
activity. This pin is driven low to indicate active transmission or
reception, and can be used to drive a low current LED (<6 mA). The
activity event is stretched to a min duration of approximately 50 ms.
LED100N/MA2 144 C13 O 100 Mb/s Link: This pin is an output indicating the 100 Mb/s Link
status. This pin is driven low to indicate Good Link status for 100
Mb/s operation, and can be used to drive a low current LED (<6 mA).
LED10N/MA1 143 C12 O 10 Mb/s Link: This pin is an output indicating the 10 Mb/s Link
status. This pin is driven low to indicate Good Link status for 10 Mb/s
operation, and can be used to drive a low current LED (<6 mA).
Serial EEPROM Interface
Symbol
LQFP Pin
No(s)
LBGA Pin
No(s) Dir Description
EESEL 128 G14 O EEPROM Chip Select: This signal is used to enable an external
EEPROM device.
EECLK/MA4 2 A12 O EEPROM Clock: During an EEPROM acce ss (E ESE L assert ed),
this pin is an output used to drive the serial clock to an external
EEPROM device.
EEDI/MA3 1 B12 O EEPROM Data In: During an EEPROM access (EESEL asserted),
this pin is an output used to drive opcode, address, and data to an
external serial EEPROM device.
EEDO/MD4 138 E11 I EEPROM Data Out: During an EEPROM access (EESEL asserted),
this pin is an input used to retrieve EEPROM serial read data.
This pin has an internal weak pull up.
MD1/CFGDISN 133 F13 I/O Configuration Disable: When pulled low at power-on time, disables
load of configuration data from the EEPROM. Use 1 KΩ to ground to
disable configuration load.
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2.0 Pin Description (Continued)
DP83815
External Reference Interf ace
Symbol
LQFP Pin
No(s)
LBGA Pin
No(s) Dir Description
VREF 40 A2 I Bandgap Reference: External current reference resistor for internal
Phy bandgap circuitry. The value of this resistor is 9.31 KΩ 1% metal
film (100 ppm/
o
C) which must be connected from the VREF pin to
analog ground.
No Connects
Symbol
LQFP Pin
No(s)
LBGA Pin
No(s) Dir Description
NC 34, 42, 43, 48 A1, A13, A14,
B3, B13, B14,
D4, F3, F4,
G2, M2, M3,
N1, N2, N13,
N14, P1, P2,
P13, P14
No Connect
Reserved 41, 50, 127 D2, E3, H12 These pins are reserved and cannot be connected to any external
logic or net.
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2.0 Pin Description (Continued)
DP83815
Supply Pins
Symbol
LQFP Pin
No(s)
LBGA Pin
No(s) Dir Description
SUBGND1,
SUBGND2,
SUBGND3
37,
49,
126
B2,
E1,
G12
S Substrate GND
RXAVDD1,
RXAVDD2
39,
47
C2,
E2
S RX Analog VDD - connect to isolated Aux 3.3V supply VDD
RXAVSS1,
RXAVSS2
38,
44
B1,
D3
S RX Analog GND
TXIOVSS1,
TXIOVSS2
52,
55
F2,
G4
S TX Output driver VSS
TXDVDD 56 H3 S TX Digital VDD - connect to Aux 3.3V supply VDD
TXDVSS 51 E4 S TX Digital VSS
MACVDD1,
MACVDD2
58,
125
H1,
H11
S Mac/BIU digital core VDD - connect to Aux 3.3V supply VDD
MACVSS1,
MACVSS2
57,
124
G3,
H14
S Mac/BIU digital core VSS
PCIVDD1,
PCIVDD2,
PCIVDD3,
PCIVDD4,
PCIVDD5
69,
80,
94,
107,
117
L1,
P5,
L8,
M12,
K12
S PCI IO VDD - connect to PCI bus 3.3V VDD
PCIVSS1,
PCIVSS2,
PCIVSS3,
PCIVSS4,
PCIVSS5
65,
77,
90,
103,
114
K1,
P4,
M8,
P11,
L11
S PCI IO VSS
VDDIO2,
VDDIO4
19,
85
C8,
M6
S Misc. IO VDD - connect to Aux 3.3V supply VDD
VDDIO1,
VDDIO3,
VDDIO5
9,
27,
137
C10,
A5,
E13
S Misc. IO VDD - connect to Aux 3.3V supply VDD
VSSIO2,
VSSIO4
16,
84
A8,
P6
SMisc. IO VSS
VSSIO1,
VSSIO3,
VSSIO5
8,
26,
136
A10,
D6,
E12
SMisc. IO VSS
PHYVDD1,
PHYVDD2
21,
33
B7,
B4
S Phy digital core VDD - connect to Aux 3.3V supply VDD
PHYVSS1,
PHYVSS2
20,
32
A7,
C4
S Phy digital core VSS
FSVDD 36 C3 S Frequency Synthesizer VDD - connect to isolated Aux 3.3V supply
VDD
FSVSS 35 A3 S Frequency Synthesizer VSS
13 www.national.com
DP83815
3.0 Functional Description
DP83815 consists of a MAC/BIU (Media Access
Controller/Bus Interface Unit), a physical layer interface,
SRAM, and miscellaneous support logic. The MAC/BIU
includes the PCI bus, BIOS ROM a nd EEPROM int erfaces ,
and an 802.3 MAC. The physical layer interface used is a
single-port version of the 3.3V DsPhyter. Internal memory
consists of one - 0.5 KB and two - 2 KB SRAM blocks.
Figure 3-1 DP83815 Functional Block Diagram
MAC/BIU
Interface
SRAM
25 MHz Clk
MII RX
MII TX
MII Mgt
BIOS ROM Cntl
BIOS ROM Data
BROM/EE
PCI AD
PCI CNTL
PCI CLK
3V DSP Physical Layer
Logic
RX-2 KB
SRAM
TX-2 KB
TPRDP/M
EEPROM/LEDs
MII TX
MII RX
MII Mgt
Test data in
Test data out
MII TX
MII RX
MII Mgt
TPTDP/M
DP83815
Tx Addr
Tx wr data
Rx Addr
Rx wr data
Rx rd data
Tx rd data
RAM
BIST
Logic
SRAM
RXFilter
.5 KB
3.0 Functional Description (Continued)
14 www.national.com
DP83815
Figure 3-2 MAC/BIU Functional Block Diagram
3.1 MAC/BIU
The MAC/BIU is a derivative design from the DP83810
(Euphrates). The original MAC/BIU design has been
optimized to improve logic efficiency and enhanced to add
features consistent with current market needs and
specification compliance. The MAC/BIU design blocks are
discussed in this section.
3.1.1 PCI Bus Interfac e
This block implements PCI v2.2 bus protocols, and
configuration space. Supports bus master reads and writes
to CPU memory, and CPU access to on-chip register
space. Additional functions provided include: configuration
control, serial EEPROM access with auto configuration
load, interrupt control, power management control with
support for PME or CLKRUN function.
3.1.1.1 Byte Ordering
The DP83815 can be configured to order the bytes of data
on the AD[31:0] bus to conform to little endian or big
endian ordering through the use of the Configuration
Register, bit 0 (CFG:BEM). By default, the device is in little
endian ordering. Byte ordering only affects data FIFOs.
Register information remains bit aligned (i.e. AD[31] maps
to bit 31 in any register space, AD[0] maps to bit 0, etc.).
Tx Buffer Manager
MIB
Tx MAC
Rx MAC
PCI Bus
Data FIFO
Physical Layer Interface
93C46
Serial
EEPROM
MAC/BIU
32
15
32
32
32
32
32
16
32
32
4
4
32
Rx Filter
Pkt Recog
Logic
SRAM
Rx Buffer Manager
Data FIFO
Boot ROM/
Flash
PCI Bus
Interface
3.0 Functional Description (Continued)
15 www.national.com
DP83815
Little Endian (CFG:BEM=0): The byte orientation for
receive and transmit data in system memory is as follows:
Big Endian (CFG:BEM=1): The byte orientation for
receive and transmit data in system memory is as follows:
3.1.1.2 PCI Bus Interrupt Control
PCI bus interrupts for the DP83815 are asynchronously
performed by asserting pin INTAN. This pin is an open
drain output. The sou rce of th e in terrupt can be determined
by reading the Interrupt Status Register (ISR). One or more
bits in the ISR will be set, denoting all currently pending
interrupts. Caution: Reading of the ISR clears ALL bits.
Masking of specified interrupts can be accomplished by
using the Interrupt Mask Register (IMR).
3.1.1.3 Timer
The Latency Timer described in CFGLAT:LAT defines the
minimum number of bus clocks that the device will hold the
bus. Once the device gains control of the bus and issues
FRAMEN, the Latency Timer will begin counting down. If
GNTN is de-asserted before the DP83815 has finished
with the bus, the device will maintain ownership of the bus
until the timer reaches zero (or has finished the bus
transfer). The timer is an 8-bit counter.
3.1.2 Tx MAC
This block implements the transmit portion of 802.3 Media
Access Control. The Tx MAC retrieves packet data from
the Tx Buffer Manager and sends it out through the
transmit portion. Additionally, the Tx MAC provides MIB
control information for transmit packets.
3.1.3 Rx MAC
This block implements the receive portion of 802.3 Media
Access Control. The Rx MAC retrieves packet data from
the receive portion and sends it to the Rx Buffer Manager.
Additionally, the Rx MAC provides MIB control information
and packet address data for the Rx Filter.
3.2 Buffer Management
The buffer management scheme used on the DP83815
allows quick, simple and efficient use of the frame buffer
memory. Frames are saved in similar formats for both
transmit and receive. T he b uf fer management scheme also
uses separate buffers and descriptors for packet
informatio n. Th is al lows effect ive t ran sfer s of da ta from t he
receive buffer to the transmit buffer by simply transferring
the descriptor from the receive queue to the transmit
queue.
The format of the descriptors allows the packets to be
saved in a number of configurations. A packet can be
stored in memory with a s ingle descr iptor pe r single p ac ket,
or multiple descriptors per single packet. This flexibility
allows the user to configure the DP83815 to maximize
efficiency. Architecture of the specific system’s buffer
memory, as well as the nature of network traffic, will
determine the most suitable configuration of packet
descriptors and fragments. Refer to the Buffer
Management Section (Section 5.0) for more information.
3.2.1 Tx Buffer Manager
This block DMAs packet data from PCI memory space and
places it in the 2 KB transmit FIFO, and pulls data from the
FIFO to send to the Tx MAC. Multiple packets (4) may be
present in the FIFO, all owin g p acket s to be tran smitted w ith
minimum interframe gap. The way in which the FIFO is
emptied and filled is controlled by the FIFO threshold
values in the TXCFG regis ter: FL TH (Tx Fill Threshold) an d
DRTH (Tx Drain Threshold). These values determine how
full or empty the FIFO must be before the device requests
the bus. Additionally, once the DP83815 requests the bus,
it will attempt to empty or fill the FIFO as allowed by the
MXDMA setting in the TXCFG register.
3.2.2 Rx Buffer Manager
This block retrieves packet data from the Rx MAC and
places it in the 2 KB receive data FIFO, and pulls data from
the FIFO for DMA to PCI memory space. The Rx Buffer
Manager maintains a status FIFO, allowing up to 4 packets
to reside in the FIFO at once. Similar to the transmit FIFO,
the receive FIFO is controlled by the FIFO threshold value
in the RXCFG register: DRTH (R x Drain Threshol d). This
value determines the number of long words written into the
FIFO from the MAC unit before a DMA request for system
memory access occurs. Once the D P838 15 gets the bus, it
will continue to transfer the long words from the FIFO until
the data in the FIFO is less than one long word, or has
reached the end of the packet, or the max DMA burst size
is reached (RXCFG:MXDMA).
3.2.3 Packet Recognition
The Receive packet filter and recognition logic allows
software to control which pac kets are accepted based on
destination address and packet type. Address recognition
logic includes support for broadcast, multicast hash, and
unicast addresses. The packet recognition logic includes
support for WOL, Pause, and programmable pattern
recognition.
The standard 802.3 Ethernet packet consists of the
following fields: Preamble (PA), Start of Frame Delimiter
(SFD), Destination Address (DA), Source Address (SA),
Length (LEN), Data and Fra me Chec k Seque nce (FCS). Al l
fields are fixed length except for the data field. During
reception, the PA, SFD and FCS are stripped. During
transmission, the DP83815 generates and appends the
PA, SFD and FCS.
Byte 0Byte 1Byte 2Byte 3
0781516
232431
LSB
C/BE[0]C/BE[1]C/BE[2]C/BE[3]
MSB
Byte 3Byte 2Byte 1Byte 0
0781516
232431
MSB
C/BE[0]C/BE[1]C/BE[2]
C/BE[3]
LSB
3.0 Functional Description (Continued)
16 www.national.com
DP83815
3.2.4 MIB
The MIB block contains counters to track certain media
events required by the management specifications RFC
1213 (MIB II), RFC 1398 (Ether-like MIB), and IEEE 802.3
LME. The counters provided are f or eve nts which are eith er
difficult or impossible to be intercepted directly by software.
Not all counters are implemented, however required
counters can be calculated from the counters provided.
3.3 Interface Definitions
3.3.1 PCI System Bus
This interface allows direct connection of the DP83815 to a
33 MHz PCI system bus. The DP83815 supports zero wait
state data tran sf er s w it h bu rs t s iz es up t o 12 8 dwo rds. The
DP83815 conforms to 3.3V AC/DC specifications, but has
5V tolerant inputs.
3.3.2 Boot PROM
The BIOS ROM interface allows the DP83815 to read from
and write data to an external ROM/Flash device.
3.3.3 EEPROM
The DP83815 supports the attachment of an external
EEPROM. The EEPROM interface provides the ability for
the DP83815 to read from and write data to an external
serial EEPROM device. The DP83815 will auto-load values
from the EEPROM to certain fields in PCI configuration
space and operational space and perform a checksum to
verify that the data is valid. Value s in the e xternal EEPROM
allow default fields in PCI configuration space and I/O
space to be overridden following a hardware reset. If the
EEPROM is not present, the DP83815 initialization uses
default values for the appropriate Configuration and
Operational Registers. Software can read and write to the
EEPROM using “bit-bang” accesses via the EEPROM
Access Register (MEAR).
3.3.4 Clock
The clock interface provides the 25 MHz clock reference
input for the DP83815 IC. The X1 and X2 pin capacitances
are 4.5 +
1.0pF. The X1 input signa l amplitude should be
approximately 1V. This interface supports operation from a
25 MHz, 50 ppm CMOS oscillator, or a 25 MHz, 50 ppm,
parallel, 20 p F l o ad , < 40 Ω E SR c r ysta l re so nat o r. A 20pF
crystal resonator would require C1 and C2 load capacitors
of 27-33pF each.
Figure 3-3 Ethernet Packet Format
60b 4b 6B 2B 46B-1500B
4B
FCSDataLENSADAPA
6B
SFD
Note: B = Bytes
b = bits
3.0 Functional Description (Continued)
17 www.national.com
DP83815
Figure 3-4 DSP Physical Layer Block Diagram
TRANSMIT CHANNELS &
100 MB/S 10 MB/S
NRZ TO
MANCHESTER
ENCODER
STATE MACHINES
TRANSMIT
FILTER
LINK PULSE
GENERATOR
4B/5B
ENCODER
SCRAMBLER
PARALLEL TO
SERIAL
NRZ TO NRZI
ENCODER
BINARY TO
MLT-3
ENCODER
10/100 COMMON
RECEIVE CHANNELS &
100 MB/S 10 MB/S
MANCHESTER
TO NRZ
DECODER
STATE MACHINES
RECEIVE
FILTER
LINK PULSE
DETECTOR
4B/5B
DECODER
DESCRAMBLER
SERIAL TO
PARALLEL
NRZI TO NRZ
DECODER
MLT-3 TO
10/100 COMMON
AUTO-NEGOTIATION
STATE MACHINE
FAR-END-FAULT
STATE MACHINE
REGISTERS
AUTO
100BASE-X
10BASE-T
MII
BASIC MODE
PCS CONTROL
PHY ADDRESS
NEGOTIATION
CLOCK
CLOCK
RECOVERY
CLOCK
RECOVERY
CODE GROUP
ALIGNMENT
SMART
SQUELCH
RX_DATA
RXCLK
RX_DATARXCLK
TX_DATA
TX_DATA
TXCLK
SYSTEM CLOCK
REFERENCE
RD±
TD±
OUTPUT DRIVER
INPUT BUFFER
BINARY
DECODER
ADAPTIVE
EQ
AND
BLW
COMP.
(ALSO FX_RD±)
LED
DRIVERS
LEDS
POWER ON
CONFIGURATION
PINS
GENERATION
CONTROL
NCLK_50M
TXCLK
TXD(3:0)
TXER
TXEN
MDIO
MDC
COL
CRS
RXEN
RXER
RXDV
RXD(3:0)
RXCLK
MAC INTERFACE
SERIAL
MANAGEMENT
3.0 Functional Description (Continued)
18 www.national.com
DP83815
3.4 Physical Layer
The DP83815 has a full featured physical layer device with
integrated PMD sub-layers to support both 10BASE-T and
100BASE-TX Ethernet protocols. The physical layer is
designed fo r eas y impl emen tati on of 10/10 0 Mb/ s Et herne t
home or office solutions. It interfaces directly to twisted pair
media via an external transformer. The physical layer
utilizes on chip Digital Signal Processing (DSP) technology
and digital PLLs for robust performance under all operating
conditions, enhanced noise immunity, and lower external
component count when compared to analog solutions.
3.4.1 Auto-Negotiation
The Auto-Negotiation function provides a mechanism for
exchanging configuration information between two ends of
a link segment and automatically selecting the highest
performance mode of o perat ion su pported by both de vices .
Fast Link Pulse (FLP) Bursts provide the signalling used to
communicate Auto-Negotiation abilities between two
devices at each end of a link segment. For further detail
regarding Auto-Negotiation, refer to Clause 28 of the IEEE
802.3u specification. The DP83815 supports four different
Ethernet protocols (10 Mb/s Half Duplex, 10 Mb/s Full
Duplex, 100 Mb/s Half Duplex, and 100 Mb/s Full Duplex),
so the inclusion of Auto-Negotiation ensures that the
highest performance protocol will be selected based on the
advertised ability of the Link Partner. The Auto-Negotiation
function within the DP83815 is controlled by internal
register access. Auto-Negotiation will be set at powerup/reset, and also when a link status (up/valid) change
occurs.
3.4.2 Auto-Negotiation Register Control
When Auto-Negotiation is enabled, the DP83815 transmits
the abilities programmed into the Auto-Negotiation
Advertisement register (ANAR) via FLP Bursts. Any
combination of 10 Mb/s, 100 Mb/s, Half-Duplex, and Full
Duplex modes may be selected. The default setting of bits
[8:5] in the ANAR and bit 12 in the BMCR register are
determined at power-up.
The BMCR provides software with a mechanism to control
the operation of the DP83815. Bits 1 & 2 of the PHYSTS
register are only valid if Auto-Negotiation is disabled or
after Auto-Negotiation is complete. The Auto-Negotiation
protocol compares the contents of the ANLPAR and ANAR
registers and uses the results to automatically configure to
the highest performance protocol common to the local and
far-end port. The results of Auto-Negotiation may be
accessed in register C0h (PHYSTS), bit 4: AutoNegotiation Complete, bit 2: Duplex Status and bit 1:
Speed Status.
Auto-Negotiation Priority Resolutio n:
— (1) 100BASE-TX Full Duplex (Highest Priority)
— (2) 100BASE-TX Half Duplex
— (3) 10BASE-T Full Duplex
— (4) 10BASE-T Half Duplex (Lowest Priority)
The Basic Mode Control Register (BMCR) provides control
for enabling, disabling, and restarting the Auto-Negotiation
process. When Auto-Negotiation is disabled the Speed
Selection bit in the BCMR (bit 13) controls switching
between 10 Mb/s or 100 Mb/s operation, and the Duplex
Mode bit (bit 8) controls switching between full duplex
operation and half duplex operation. The Speed Selection
and Duplex Mode bits have no effect on the mode of
operation when the Auto-Negotiation Enable bit (bit 12) is
set.
The Basic Mode Status Register (BMSR) indicates the set
of available abilities for technology types, Auto-Negotiation
ability, and Extended Register Capability. These bits are
permanently set to indicate the full functionality of the
DP83815 (only the 100BASE-T4 bit is not set since the
DP83815 does not support that function).
The BMSR also provides status on:
— Auto-Negotiation complete (bit 5)
— Link Partner advertising t hat a remote fa ult has occ urred
(bit 4)
— Valid link has been established (bit 2)
— Support for Management Frame Preamble suppression
(bit 6)
The Auto-Negotiation Advertisement Register (ANAR)
indicates the Auto-Negotiation abilities to be advertised by
the DP83815. All available abilities are transmitted by
default, but any ability can be suppressed by writing to the
ANAR. Updating the ANAR to suppress an ability is one
way for a management agent to change (force) the
technology that is used.
The Auto-Negotiation Link Partner Ability Register
(ANLPAR) is used to r eceive the base li nk code word as
well as all next page code words during the negotiation.
Furthermore, the ANLPAR will be updated to either 0081h
or 0021h for parallel detection to either 100 Mb/s or 10
Mb/s respectively.
The Auto-Negotiation Expansion Register (ANER)
indicates additional Auto-Negotiation status. The ANER
provides status on:
— Parallel Detect Fault occurrence (bit 4)
— Link Partner support of the Next Page function (bit 3)
— DP83815 support of the Next Page function (bit 2). The
DP83815 supports the Next Page function.
— Current page being exc hanged by Auto-Negotia tion has
been received (bit1)
— Link Partner support of Auto-Negotiation (bit 0)
3.4.3 Auto-Negotiation Parallel Detection
The DP83815 supports the Parallel Detection function as
defined in the IEEE 802.3u specifi cat io n. Paral le l Detectio n
requires both the 10 Mb/s and 100 Mb/s receivers to
monitor the receive signal and report link status to the
Auto-Negotiation function. Auto-Negotiation uses this
information to configure the correct technology in the event
that the Link Partner does not support Auto-Negotiation yet
is transmitting link signals that the 100BASE-TX or
10BASE-T PMAs (Physical Medium Attachments)
recognize as valid link signals.
If the DP83815 completes Auto-Negotiation as a result of
Parallel Detection, bits 5 and 7 within the ANLPAR register
will be updated to reflect the mode of operation present in
the Link Partner. Note that bits 4:0 of the ANLPAR will also
be set to 00001 based on a successful parallel detection to
indicate a valid 802.3 selector field. Software may
determine that negotiation completed via Para llel Detection
by reading the ANER (98h) register with bit 0, Link Partner
Auto-Negotiation Able bit, being reset to a zero, once the
Auto-Negotiation Complete bit, bit 5 of the BMSR (84h)
3.0 Functional Description (Continued)
19 www.national.com
DP83815
register is set to a one. If configured for parallel detect
mode, and any condition other than a single good link
occurs, then the parallel detect fault bit will set to a one, bit
4 of the ANER register (98h).
3.4.4 Auto-Negotiati on Restart
Once Auto-Negotiation has completed, it may be restarted
at any time by setting bit 9 (Res tart Auto-Ne gotiat ion) of th e
BMCR to one. If the mode confi gured b y a su ccessfu l AutoNegotiation loses a valid link, then the Auto-Negotiation
process will resume and attempt to determine the
configuration for the link. This function ensures that a valid
configuration is maintained if the cable becomes
disconnected.
A renegotiation request from any entity, such as a
management agent, will cause the DP83815 to halt any
transmit data and link pulse activity until the
break_link_timer expires (~1500 ms). Consequently, the
Link Partner will go into link fail and normal AutoNegotiation resumes. The DP83815 will resume AutoNegotiation after the break_link_timer has expired by
issuing FLP (Fast Link Pulse) bursts.
3.4.5 Enabling Auto-Negotiation via Software
It is important to note that if the DP83815 has been
initialized upon power-up as a non-auto-negotiating device
(forced technology), and it is then required that AutoNegotiation or re-Auto-Neg otiati on be in itiated via s oftware,
bit 12 (Auto-Negotiation Enable) of the Basic Mode Control
Register must first be cleared and then set for any AutoNegotiation function to take effect.
3.4.6 Auto-Negotiation Complete Time
Parallel detection and Auto-Negotiation take approximately
2-3 seconds to comp le te. In addition, Auto-Neg oti atio n wi th
next page should take approximately 2-3 seconds to
complete, depending on the number of next pages sent.
Refer to Clause 28 of the IEEE 802.3u standard for a full
description of the individual timers related to AutoNegotiation.
3.5 LED Interfaces
The DP83815 has parallel outputs to indicate the status of
Activity (Transmit or Receive), 100 Mb/s Link, and 10 Mb/s
Link.
The LEDACTN pin indicates the presence of transmit or
receive ac tiv it y. The stand ard C MOS dri ve r g oes l ow wh en
RX or TX activity is detected in either 10 Mb/s or 100 Mb/s
operation.
The LED100N pin indicates a good link at 100 Mb/s data
rate. The standard CMOS driver goes low when this
occurs. In 100BASE-T mode, link is established as a result
of input receive amplitude compliant with TP-PMD
specifications which will result in internal generation of
signal detect. This s ig nal w ill a ss ert afte r th e i nte rnal Si gna l
Detect has remained asserted for a minimum of 500 us.
The signal will de-assert immediately following the deassertion of the internal signal detect.
The LED10N pin indi ca tes a g ood link at 10 Mb/s data rate.
The standard CMOS driver goes low when this occurs. 10
Mb/s Link is established as a result of the reception of at
least seven consecutive normal Link Pulses or the
reception of a valid 10BASE-T packet. This will cause the
assertion of this signal. the signal will de-assert in
accordance w ith the Link Loss Timer as specifi ed in IEE E
802.3.
The DP83815 LED pins are capable of 6 mA. Connection
of these LED pins should ensure this is not overloaded.
Using 2 mA LED devices the connection for the LEDs
could be as shown in Figure 3-5.
Figure 3-5 LED Loading Example
V
DD
LED10N
453 Ω
LEDACTN
453 Ω
LED100N
453 Ω
3.0 Functional Description (Continued)
20 www.national.com
DP83815
3.6 Half Duplex vs. Full Duplex
The DP83815 supports both half and full duplex operation
at both 10 Mb/s and 100 Mb/s speeds.
Half-duplex is the standard, traditional mode of operation
which relies on the CSMA/CD protocol to handle collisions
and network access. In Hal f-Duplex mode, CRS res ponds
to both transmit and receive activity in order to maintain
compliance with IEEE 802.3 specification .
Since the DP83815 is designed to support simultaneous
transmit and receiv e act ivi ty it is capabl e of su ppor ting full duplex switched ap plications with a thro ug hpu t of up to 200
Mb/s per port when operating in 100BASE-TX mode.
Because the CSMA/CD protocol does not apply to fullduplex operation, the DP83815 disables its own internal
collision sensing and reporting functions.
It is important to un ders tand that while f ull Aut o-Neg oti atio n
with the use of Fast Link Pulse code words can interpret
and configure to support full-duplex, parallel detection can
not recogni ze the difference between full and half-duplex
from a fixed 10 Mb/s or 100 Mb/s link partner over twisted
pair. Therefore, as specified in 802.3u, if a far-end link
partner is transmitting forced full duplex 100BASE-TX for
example, the parallel detection state machine in the
receiving station would be unable to detect the full duplex
capability of the fa r -e nd li nk par tne r an d wou ld ne go ti at e to
a half duplex 100BASE-TX configuration (same scenario
for 10 Mb/s).
For full duplex operation, the following register bits must
also be set:
— TXCFG:CSI (Carrier Sense Ignore)
— TXCFG:HBI (HeartBeat Ignore)
— RXCFG:ATX (Accept Transmit Packets)
Additionally, the Auto-Negotiation Select bits in the
Configuration register must show full duplex support:
— CFG:ANEG_SEL
3.7 Phy Loopback
The DP83815 includes a Phy Loopback Test mode for
easy board diagnostics. The Loopback mode is selected
through bit 14 (Loopback) of the Basic Mode Control
Register (BMCR). Writi ng 1 to this bi t enable s transm it dat a
to be routed to the receive path early in the physical layer
cell. Loopback status may be checked in bit 3 of the PHY
Status Register (C0h). While in Loopback mode the data
will not be trans m itte d o nto the media. This i s true f or e ith er
10 Mb/s as well as 100 Mb/s data.
In 100BASE-TX Loopback mode the data is routed through
the PCS and PMA layers into the PMD sublayer before it is
looped back. Therefore, in addition to serving as a board
diagnostic, this mode serves as qu ick fun ction al verif icatio n
of the device.
Note: A Mac Loopback can be performed via setting bit 29
(Mac Loopback) in the Tx Configuration Register.
3.8 Status Information
There are 3 pins that are available to convey status
information to the user through LEDs to indicate the speed
(10 Mb/s or 100 Mb/s) link status and receive or transmit
activity.
10 Mb/s Link is estab lishe d as a resu lt of the rec eption of at
least seven consecutive Normal Link Pulses or the
reception of a valid 10BASE-T packet. LED10N will deassert in accordance with the Link Loss Timer specified in
IEEE 802.3.
100BASE-T Link is established as a result of an input
receive amplitude compliant with TP-PMD specifications
which will result in internal generation of Signal Detect.
LED100N will assert after the internal Signal Detect has
remained asserted for a minimum of 500 µs. LED100N will
de-assert immediately following the de-assertion of the
internal Signal Detect.
Activity LED status indicates Receive or Transmit activity.
3.9 100BASE-TX TRANSMITTER
The 100BASE-TX transmitter consists of several functional
blocks which convert synchronous 4-bit nibble data, to a
scrambled MLT-3 125 Mb/s serial data stream. Because
the 100BASE-TX TP-PMD is integrated, the differential
output pins, TD±, can be directly routed to the magnetics.
The block dia gram in Figure 3-6 prov ides an overview of
each functional block within the 100BASE-TX transmit
section.
The Transmitter section consists of the following functional
blocks:
— Code-group Encode r and Injecti on block ( bypass optio n)
— Scrambler block (bypass option)
— NRZ to NRZI encoder block
— Binary to MLT-3 converter / Common Driver
The bypass option for the functional blocks within the
100BASE-TX transmitter provides flexibility for applications
such as 100 Mb/s repeaters where data conversion is not
always required. The DP83815 implements the 100BASETX transmit state machine diagram as specified in the
IEEE 802.3u Standard, Clause 24.
3.0 Functional Description (Continued)
21 www.national.com
DP83815
Figure 3-6 100BASE-TX Transmit Block Diagram
3.9.1 Code-group Encoding and Injection
The code-group encoder converts 4-bit (4B) nibble data
generated by the MAC into 5-bit (5B) code-groups for
transmission. This conversion is required to allow control
data to be combined with packet data code-groups. Refer
to Table 3-1 for 4B to 5B code-group mapping details.
The code-group encoder substitutes the first 8-bits of the
MAC preamble with a J/K code-group pair (11000 10001)
upon transmission. The code-group encoder continues to
replace subsequent 4B preamble and data nibbles with
corresponding 5B code-groups. At the end of the transmit
packet, upon the de-assertion of Transmit Enable signal
from the MAC, the code-group encoder injects the T/R
code-group pair (0 1101 00111 ) in dic at ing the en d o f fra me .
After the T/R code-group pair, the code-group encoder
continuously injects IDLEs into the transmit data stream
until the next transmit packet is detected (re-assertion of
Transmit Enable).
3.9.2 Scrambler
The scrambler is required to control the radiated emissions
at the media connector and on the twisted pair cable (for
100BASE-TX applications). By scrambling the data, the
total energy launched onto the cable is randomly
distributed over a wide frequency range. Without the
scrambler, energy levels at the PMD and on the cable
could peak beyond FCC limitations at frequencies related
to repeating 5B sequences (i.e., continuous transmission
of IDLEs).
The scrambler is configured as a closed loop linear
feedback shift register (LFSR) with an 11-bit polynomial.
The output of the closed loop LFSR is X-ORd with the
serial NRZ data from the code-group encoder. The result is
a scrambled data stream with sufficient randomization to
decrease radiated emissions at certain frequencies by as
much as 20 dB.
FROM CGM
BP_4B5B
BP_SCR
4B5B CODE-
MUX
5B PARALLEL
SCRAMBLER
MUX
MUX
NRZ TO NRZI
BINARY
TD +/-
100BASE-TX
GROUP ENABLER
TXD(3:0)/TXER
TXCLK
TO SERIAL
ENCODER
TO MLT-3/
COMMON
DRIVER
LOOPBACK
3.0 Functional Description (Continued)
22 www.national.com
DP83815
3.9.3 NRZ t o NRZI Encoder
After the transmit data stream has been serialized and
scrambled, the data must be NRZI encoded in order to
comply with the TP-PMD standard for 100BASE-TX
transmission over Category-5 un-shielded twisted pair
cable. There is no ability to bypass this block within the
DP83815.
3.9.4 Binary to MLT-3 Convertor / Common Driver
The Binary to MLT-3 conversion is accomplished by
converting the serial binary data stream output from the
NRZI encoder into two binary data streams with alternately
phased logic one events. These two binary streams are
then fed to the twisted pair output dri ve r whic h con ve rt s the
voltage to current and alternately drives either side of the
transmit transformer primary winding, res ultin g in a mini mal
current (20 mA max) MLT-3 signal. Refer to Figure 3-7
Figure 3-7 Binary to MLT-3 conversion
D
Q
Q
binary_in
binary_plus
binary_minus
binary_in
binary_plus
binary_minus
COMMON
DRIVER
MLT-3
differential MLT-3
Table 3-1 4B5B Code-Group Encoding/Decoding
Name PCS 5B Code-group Description/4B Value
DATA CODES
0 11110 0000
1 01001 0001
2 10100 0010
3 10101 0011
4 01010 0100
5 01011 0101
6 01110 0110
7 01111 0111
8 10010 1000
9 10011 1001
A 10110 1010
B 10111 1011
C 11010 1100
D 11011 1101
E 11100 1110
F 11101 1111
IDLE AND CONTROL CODES
H 00100 HALT code-group - Error code
I 11111 Inter-Packet IDLE - 0000
J 11000 First Start of Packet - 0101
K 10001 Second Start of Packet - 0101
T 01101 First End of Packet - 0000
R 00111 Second End of Packet - 0000
3.0 Functional Description (Continued)
23 www.national.com
DP83815
The 100BASE-TX MLT-3 signal sourced by the TD±
common driver output pins is slew rate controlled. This
should be considered when selecting AC coupling
magnetics to ensure TP-PMD Standard compliant
transition times (3 ns < Tr < 5 ns).
The 100BASE-TX transmit TP-PMD function within the
DP83815 is capab le o f sour cing only M LT-3 encoded data.
Binary output from the TD± outputs is not po ssible in 100
Mb/s mode.
3.10 100BASE-TX Receiver
The 100BASE-TX receiver consists of several functional
blocks which convert the scrambled MLT-3 125 Mb/s serial
data stream to synchronous 4-bit nibble data that is
provided to the MAC. Because the 100BASE-TX TP-PMD
is integrated, the differential input pins, RD±, can be
directly routed from the AC coupling magnetics.
See Figure 3-8 for a block diagram of the 100BASE-TX
receive function. This provides an overview of each
functional block within the 100BASE-TX receive section.
The Receive section consists of the following functional
blocks:
—ADC
— Input and BLW Compensation
— Signal Detect
— Digital Adaptive Equalization
— MLT-3 to Binary Decoder
— Clock Recovery Module
— NRZI to NRZ Decoder
— Serial to Parallel
— De-scrambler (bypass option)
— Code Group Alignment
— 4B/5B Decoder (bypass option)
— Link Integrity Monitor
— Bad SSD Detection
The bypass option for the functional blocks within the
100BASE-TX receiver provides flexibility for applications
such as 100 Mb/s repeaters where data conversion is not
always required.
3.10.1 Input and Base Line Wander Compensation
Unlike the DP83223V Twister, the DP83815 requires no
external attenuation circuitry at its receive inputs, RD+/−. It
accepts TP-PMD compliant waveforms directly, requiring
only a 100Ω termination plus a simple 1:1 transformer.
The DP83815 is completely ANSI TP-PMD compliant and
includes Base Line Wander (BLW) compensation. The
BLW compensation block can successfully recover the TPPMD defined “killer” pattern and pass it to the digital
adaptive equalization block.
BLW can generally be defined as the change in the
average DC content, over time, of an AC coupled digital
transmission over a given transmission medium. (i.e.
copper wire).
BLW results from the interaction between the low
frequency components of a transmitted bit stream and the
frequency response of the AC coupling component(s)
within the transmission system. If the low frequency
content of the digital bit stream goes below the low
frequency pole of the AC coupling transformers then the
droop characteristics of the transformers will dominate
resulting in potentially serious BLW.
The digital oscilloscope plot provided in Figure3-9
illustrates the severity of the BLW event that can
theoretically be generated during 100BASE-TX packet
transmission. This event consists of approximately 800 mV
of DC offset for a period of 120 us. Left uncompensated,
events such as this can cause packet loss.
3.10.2 Signal Detect
The signal detect function of the DP83815 is incorporated
to meet the specifications mandated by the A NS I FDD I TPPMD Standard as well as the IEEE 802.3 100BASE-TX
Standard for both voltage thresholds and timing
parameters.
Note that the reception of normal 10BASE-T link pulses
and fast link pulses per IEEE 802.3u Auto-Negotiation by
the 100BASE-TX receiver do not cause the DP83815 to
assert signal detect.
INVALID CODES
V 00000
V 00001
V 00010
V 00011
V 00101
V 00110
V 01000
V 01100
V 10000
V 11001
Table 3-1 4B5B Code-Group Encoding/Decoding
Name PCS 5B Code-group Description/4B Value
3.0 Functional Description (Continued)
24 www.national.com
DP83815
Figure 3-8 100 M/bs Receive Block Diagram
BP_4B5B
BP_SCR
BP_RX
CLOCK
MUX
MUX
4B/5B DECODER
SERIAL TO
CODE GROUP
MUX
DESCRAMBLER
NRZI TO NRZ
MLT-3 TO BINARY
DIGITAL
CLOCK
LINK INTEGRITY
RX_DATA VALID
AGC
INPUT BLW
ADC
SIGNAL
COMPENSATION
ADAPTIVE
EQUALIZATION
DECODER
DECODER
ALIGNMENT
RECOVERY
MODULE
PARALLEL
MONITOR
SSD DETECT
RXCLK
SD
RXD(3:0)/RXER
RD +/-
DETECT
3.0 Functional Description (Continued)
25 www.national.com
DP83815
3.10.3 Digital Adaptive Equalization
When transmitting data at high speeds over copper twisted
pair cable, frequency dependent attenuation becomes a
concern. In high-speed twisted pair signalling, the
frequency content of the trans mitted signal can va ry greatl y
during normal operation based primarily on the
randomness of the scrambled data stream. This variation
in signal attenuation caused by frequency variations must
be compensated for to ensure the integrity of the
transmission.
In order to ensure quality transmission when employing
MLT-3 encoding, the co mpensation mus t be able to adapt
to various cable lengths and cable types depending on the
installed env ironment. The se lection of long cable lengths
for a given implementation, requires significant
compensation which will over-compensate for shorter, less
attenuating lengths. Conversely, the selection of short or
intermediate cable lengths requiring less compensation will
cause serious under-compensation for longer length
cables. Therefore, the compensation or equalization must
be adaptive to en sure proper condi tioning of the recei ved
signal independent of the cable length.
The DP83815 utilizes an extremely robust equalization
scheme referred to herein as ‘Digital Adaptive
Equalization’. Traditional designs use a pseudo adaptive
equalization scheme that determines the approximate
cable length by monitoring signal attenuation at certain
frequencies. This attenuation value was compared to the
internal receive input reference voltage. This comparison
would indicate the amount of equalization to use. Although
this scheme is used successfully on the DP83223V twister,
it is sensitive to transformer mismatch, resistor variation
and process induced offset. The DP83223V also required
an external attenua tio n network to help ma tch the incoming
signal amplitude to the internal reference.
The Digital Equalizer removes ISI (Inter Symbol
Interference) from the receive data stream by continuously
adapting to provide a filter with the inverse frequency
response of the channel. When used in conjunction with a
gain stage, this enables the receive 'eye pattern' to be
opened sufficiently to allow very reliable data recovery.
Traditionally 'adaptive' equalizers selected 1 of N filters in
an attempt to match the cables characteristics. This
approach will typically leave holes at certain cable lengths,
where the performance of the equalizer is not optimized.
The DP83815 equalizer is truly adaptive.
The curves given in Figure 3-10 illustrate attenuation at
certain frequencies for given cable lengths. This is derived
from the worst case frequency vs. attenuation figures as
specified in the EIA/TIA Bulletin TSB-36. These curves
indicate the significant variations in signal attenuation that
must be compensated for by the receive adaptive
equalization circuit.
Figure 3-11 represents a scrambled IDLE transmitted over
zero meters of cable as measured at the AII (Active Input
Interface) of the receiver. Figure 3-12 and Figure 3-13
represent the signal degradation over 50 and 100 meters
of category V
cable respectively, also measured at the AII.
These plots show the extreme degradation of signal
integrity and indicate the requirement for a robust adaptive
equalizer.
Figure 3-9 100BASE-TX BLW Event Diagram
3.0 Functional Description (Continued)
26 www.national.com
DP83815
3.10.4 Line Quality Monitor
It is possible to determine the amount of Equalization being
used by accessing certain test registers with the DSP
engine. This provides a crude indication of connected
cable length. This function allows for a quick and simple
verification of the line quality in that any significant
deviation from an expected register value (based on a
known cable length) would indicate that the signal quality
has deviated from the expected nominal case.
3.10.5 MLT-3 to NRZI Decoder
The DP83815 decodes the MLT-3 information from the
Digital Adaptive Equalizer block to binary NRZI data.
Figure 3-10 EIA/TIA Attenuation vs. Frequenc y for 0, 50,
100, 130 & 150 meters of CAT V
cable
Figure 3-11 MLT-3 Signal Measured at AII after 0 meters
of CAT V
cable
2ns/div
Figure 3-12 MLT-3 Signal Measured at AII after 50
meters of CAT V
cable
Figure 3-13 MLT-3 Signal Measured at AII after 100
meters of CAT V cable
2ns/div
2ns/div
3.0 Functional Description (Continued)
27 www.national.com
DP83815
3.10.6 Clock Recovery Module
The Clock Recovery Module (CRM) accepts 125 Mb/s
MLT3 data from the equalizer. The DPLL locks onto the
125 Mb/s data str eam and extracts a 125 MHz recover ed
clock. The extracted and synchronized clock and data are
used as required by the synchronous re ce iv e o per atio ns a s
generally depicted in Figure3-8.
The CRM is implemented using an advanced all digital
Phase Locked Loop (PLL) architecture that replaces
sensitive analog circuitry. Using digital PLL circuitry allows
the DP83815 to be manufactured and specified to tighter
tolerances.
3.10.7 NRZI to NRZ
In a typical application, the NRZI to NRZ decoder is
required in order to present NRZ formatted data to the descrambler (or to the code-group alignment block, if the descrambler is bypassed, or directly to the PCS, if the
receiver is bypassed).
3.10.8 Serial to Parallel
The 100BASE-TX receiver includes a Serial to Parallel
converter which supplies 5-bit wide data symbols to the
PCS Rx state machine.
3.10.9 De-scrambler
A serial de-scrambler is used to de-scramble the received
NRZ data. The de-scrambler has to generate an identical
data scrambling sequence (N) in order to recover the
original unscrambled data (UD) from the scrambled data
(SD) as represented in the equations:
Synchronization of the de-scrambler to the original
scrambling sequence (N) is achieved based on the
knowledge that the incoming scrambled data stream
consists of scrambled IDLE data. After the de-scrambler
has recognized 12 consecutive IDLE code-groups, where
an unscrambled IDLE code-group in 5B NRZ is equal to
five consecutive ones (11111), it will synchronize to the
receive data stream and generate unscrambled data in the
form of unaligned 5B code-groups.
In order to maintain synchronization, the de-scrambler
must continuo usly monitor the va lidity of the uns crambled
data that it generates. To ensure this, a line state monitor
and a hold timer are used to constantly monitor the
synchronization status. Upon synchronization of the descrambler the hold timer starts a 722 µs countdown. Upon
detection of sufficient IDLE code-groups (58 bit times)
within the 722 µs period, the hold timer will reset and begin
a new countdown . This monitoring op eration will cont inue
indefinitely given a properly operating network connection
with good signal integrity. If the line state monitor does not
recognize sufficient unscrambled IDLE code-groups within
the 722 µs period, the entire de-scrambler will be forced
out of the current state of synchronization and reset in
order to re-acquire synchronization.
3.10.10 Code-group Alignment
The code-group alignment module operates on unaligned
5-bit data f rom th e de-sc rambler (or, if the de -scram bler is
bypassed, directly from the NRZI/NRZ decoder) and
converts it into 5B code-group data (5 bits). Code-group
alignment occurs after the J/K code-group pair is detected.
Once the J/K code-group pair (11000 10001) is detected,
subsequent data is aligned on a fixed boundary.
3.10.11 4B/5B Decoder
The code-group decoder functions as a look up table that
translates incoming 5B code-groups into 4B nibbles. The
code-group decoder first detects the J/K code-group pair
preceded by IDLE code-groups and replaces the J/K with
MAC preamble. Spec ific all y, the J/K 10-bit code- grou p pair
is replaced by the nibble pair (0101 0101). All subsequent
5B code-groups are converted to the corresponding 4B
nibbles for the duration of the entire packet. This
conversion ceases upon the detection of the T/R codegroup pair denoting the End of Stream Delimiter (ESD) or
with the reception of a minimum of two IDLE code-groups.
3.10.12 100BASE-TX Link Integrity Monitor
The 100 Base-TX Link monitor ensures that a valid and
stable link is established before enabling both the Transmit
and Receive PCS layer.
Signal detect must be valid for 395 µs to allow the link
monitor to enter the 'Link Up' state, an d e nab le the transmit
and receive functions.
Signal detect can be forced active by setting Bit 1 of the
PCSR.
Signal detect can be optionally ANDed with the descrambler locked indication by setting bit 8 of the PCSR.
When this option is enabled, then De-scrambler 'locked' is
required to enter the Link Up sta te, but only Signal det ect is
required to maintain the link in the link Up state.
3.10.13 Bad SSD Detection
A Bad Start of Stream Delimiter (Bad SSD) is any transition
from consecutive idle code-groups to non-idle code-groups
which is not prefixed by the code-group pair J/K.
If this condition is detected, the DP83815 will assert RXER
and present RXD[3 :0] = 1110 to the M AC fo r th e cy cl es th at
correspond to received 5B code-groups until at least two
IDLE code groups are detected. In addition, the False
Carrier Event Counter will be incremented by one.
Once at least two IDLE c ode gro up s a r e de tect ed , th e e rror
is reported to the MAC.
UD SD N⊕()=
SD UD N⊕()=
3.0 Functional Description (Continued)
28 www.national.com
DP83815
3.11 10BASE-T Transceiver Module
The 10BASE-T Transceiver Module is IEEE 802.3
compliant. It includes the receiver, transmitter, collision,
heartbeat, loopback, jabber, and link integrity functions, as
defined in the standard. An external filter is not required on
the 10BASE-T interface since this is integrated inside the
DP83815. This section focuses on the general 10BASE-T
system level operation.
3.11.1 Operational Modes
The DP83815 has two basic 10BASE-T operational
modes:
— Half Duplex mode - functions a s a s tan dard IEEE 802 .3
10BASE-T transceiver supporting the CSMA/CD
protocol.
— Full Duplex mode - capable of simultaneously
transmitting and receiving without reporting a collision.
The DP83815's 10 Mb/s ENDE C is des ign ed to enco de
and decode simultaneously.
3.11.2 Smart Squelch
The smart squelch is responsible for determining when
valid data is present on the differential receive inputs
(RD±). The DP83815 implements an intelligent receive
squelch to ensure that impulse noise on the receive inputs
will not be mistaken for a valid signal. Smart squelch
operation is independent of the 10BASE-T operational
mode.
The squelch circuitry employs a combination of amplitude
and timing measurements (as specified in the IEEE 802.3
10BASE-T standard) to determine the validity of data on
the twisted pair inputs (refer to Figure 3-14).
The signal at the start of packet is checked by the smart
squelch and any pulses not exceeding the squelch level
(either positive or negative, depending upon polarity) will
be rejected. Once this first squelch level is overcome
correctly, the opposite squelch level must then be
exceeded within 150 ns. Finally the signal must again
exceed the original squelch level within a 150 ns to ensure
that the input waveform will not be rejected. This checking
procedure result s in the l oss of typic ally t hree preamb le bit s
at the beginning of each packet.
Only after all these conditions have been satisfied will a
control signal be generated to indicate to the remainder of
the circuitry that valid data is present. At this time, the
smart squelch circuitry is reset.
Valid data is considered to be present until the squelch
level has not been g enerated for a time long er th an 150 ns ,
indicating the End of Packet. Once good data has been
detected the squelch levels are reduced to minimize the
effect of noise causing premature End of Packet detection.
3.11.3 Collision Detection
When in Half Duplex, a 10BASE-T collision is detected
when the receive and transmit channels are active
simultaneously. Collisions are reported to the MAC.
Collisions are also reported when a jabber condition is
detected.
If the ENDEC is receiving when a collision is detected it is
reported immediately (through the COL signal).
When heartbeat is enabled, approximately 1 µs after the
transmission of each packet, a Signal Quality Error (SQE)
signal of approximate ly 10 bit tim es is generate d to indi cate
successful transmission.
The SQE test is inhibited when the physical layer is set in
full duplex mode. SQE can also be inhibited by setting the
HEARTBEAT_DIS bit in the TBTSCR register.
3.11.4 Normal Link Pulse Detection/Generation
The link pulse generator produces pulses as defined in the
IEEE 802.3 10BASE-T standard. Each link pulse is
nominally 100 ns in duration and transmitted every 16 ms
in the absence of transmit data.
Link pulses are used to check the integrity of the
connection with the remote end. If valid link pulses are not
received, the link detector disables the 10BASE-T twisted
pair transmitter, receiver and collision detection functions.
When the link integrity function is disabled
(FORCE_LINK_10 of the TBTSCR register), good link is
forced and the 10BASE-T transceiver will operate
regardless of the presence of link pulses.
Figure 3-14 10BASE-T Twisted Pair Smart Squelch Operation
end of packet
start of packet
V
SQ-(reduced)
V
SQ-
V
SQ+(reduced)
V
SQ+
<150 ns
<150 ns
>150 ns
3.0 Functional Description (Continued)
29 www.national.com
DP83815
3.11.5 Jabber Function
The jabber function monitors the DP83815's output and
disables the transmitte r if it att empts to transmit a packet of
longer than legal size. A jabber timer monitors the
transmitter and disables the transmission if the transmitter
is active for approximately 20-30 ms.
Once disabled by the jabber function, the transmitter stays
disabled for the entire time that the ENDEC module's
internal transmit enable is asserted. This signal has to be
de-asserted for approximately 400-600 ms (the “unjab”
time) before the jabber function re-enables the transmit
outputs.
The Jabber function is only me aningf ul in 10 BASE-T mod e.
3.11.6 Automatic Link Polarity Detection
The DP83815's 10BASE-T transceiver module
incorporates an automatic link polarity detection circuit.
When seven consecutive li nk pulses or t hree consec utive
receive packets with inverted End-of-Packet pulses are
received, bad polarity is reported .
A polarity reversal can be cau sed by a wiring error a t either
end of the cable, usually at the Main Distribution Frame
(MDF) or patc h panel in the wiring closet.
The bad polarity condition is latched. The DP83815's
10BASE-T transceiver module corrects for this error
internally and will continue to decode received data
correctly. This eliminates the need to correct the wiring
error immediately.
3.11.7 10BASE-T Internal Loopback
When the LOOPBACK bit in the BMCR register is set,
10BASE-T transmit data is looped back in the ENDEC to
the receive channel. The transmit drivers and receive input
circuitry are disabled in transceiver loopback mode,
isolating the transceiver from the network.
Loopback is used for diagnostic testing of the data path
through the transceiver without transmitting on the network
or being interrupted by receive traffic. This loopback
function causes the data to loopback just prior to the
10BASE-T output driver buffers such that the entire
transceiver path is tested.
3.11.8 Transmit and Receive Filtering
External 10BASE-T filters are not required when using the
DP83815, as the required signal conditioning is integrated
into the device.
Only isolation/step-up transformers and impedance
matching resistors are required for the 10BASE-T transmit
and receive interface. The internal transmit filtering
ensures that all the harmonics in the transmit signal are
attenuated by at least 30 dB.
3.11.9 Transmitter
The encoder begins operation when the transmit enable
input to the physical layer is asserted and converts NRZ
data to pre-emphasized Manchester data for the
transceiver. For the duration of assertion, the serialized
transmit data is encoded for the transmit-driver pair (TD±).
The last transition is always positive; it occurs at the center
of the bit cell if the last bit is a one, or at the end of the bit
cell if the last bit is a zero.
3.11.10 Receiver
The decoder consist s of a di fferential receiver and a PLL to
separate a Manchester encoded data stream into internal
clock signals and data. The differential input must be
externally terminated with a differential 100Ω termination
network to accommodate UTP cable. The internal
impedance of RD± (typically 1.1Kohms) is in parallel with
two 54.9 resistors to approximate the 100Ω termination.
The decoder detect s the end of a fra me whe n no m ore mi dbit transitions are detected.
3.11.11 Far End Fault Indication
Auto-Negotiation provides a mechanism for transferring
information from the Loca l Station to the Link Partner that a
remote fault has occurred for 100BASE-TX.
A remote fault is an error in the link that one station can
detect while the other cannot. An example of this is a
disconnected fiber a t a st a tion’ s tra nsmi tter. This station will
be receiving valid data and detect that the link is good via
the Link Integrity Monitor, but will not be able to detect that
its transmission is not pr opagating to the other station.
If three or more FEFI IDLE patterns are detected by the
DP83815, then bit 4 of the Basic Mode Status register is
set to one until read by management, additionally bit 7 of
the PHY Status register is also set.
The first FEFI IDLE pattern may co nt ain mo re than 84 one s
as the pattern may have started during a normal IDLE
transmission which is actually quite likely to occur.
However, since FEFI is a repeating pattern, this will not
cause a problem with the FEFI function. It should be noted
that receipt of the FEFI IDLE pattern will not cause a
Carrier Sense error to be reported.
If the FEFI function has been disabled via FEFI_EN (bit 3)
of the PCSR Configuration register, then the DP83815 will
not send the FEFI IDLE pattern.
3.12 802.3u MII
The DP83815 incorporates the Media Independent
Interface (MII) as specifi ed in Claus e 22 of the IEEE 80 2.3u
standard. This interface may be used to connect PHY
devices. This section describes the MII configuration steps
as well as the serial MII management interface and nibble
wide MII data interface.
3.12.1 MII Access Configuration
The DP83815 must be specifically configured for
accessing the MII. This is done by first connecting pin 133
(MD1/CFGDISN) to GND through a 1KΩ resistor. Then
setting bit 12 (EXT_PHY) of the CFG regi ster (offset 04h)
to 1. See Section 4.2.2. When this bit is set, the internal
Phy is automatically disabled, as reported by bit 9
(PHY_DIS) of the CFG reg ister. The MII must then be reset
before the external PHY can be detected.
If external MII is not selected as described then the internal
Phy is used and the MII pins of the MacPhyter can be left
unconnected.
3.12.2 MII Serial Management
The MII serial management interface allows for the
configuration and control of PHY registers, gathering of
status, error information, and the determination of the type
and capabilities of the attached PHY(s).
The MII serial management specification defines a set of
thirty-two 16-bit status and control registers that are
accessible through the management interface pins MDC
and MDIO. A description of the serial management
interface access and access protocol follows.
3.0 Functional Description (Continued)
30 www.national.com
DP83815
3.12.3 MII Serial Management Access
Management access to the PHY(s) is done via
Management Data Clock (MDC) and Management Data
Input/Output (MDIO). M DC ha s a m aximum cloc k rate of 25
MHz and no minimum rate. The MDIO line is bi-directional
and may be shared by up to 32 devices. The internal PHY
counts as one of these 32 devices.
The internal PHY has the advantage of having direct
register access but can also be controlled exactly like a
PHY, with a default address of 1Fh, connected to the MII.
Access and control of the MDC and MDIO pins is done via
the MII/EEPROM Access Register (MEAR). The clock
(MDC) is created by alternating writes of 0 then 1 to the
MDC bit (bit 6). Control of data direction is done by the
MDDIR bit (bit 5). Data is either recorded or written by the
MDIO bit (bit 4). Setting the MDDIR bit to a 1 allows the
DP83815 to drive the MDIO pin. Setting the MDDIR bit to a
0 allows the MDIO bit to reflect the value of the MDIO pin.
See Section 4 .2.3
This bit-bang access of the MDC and MDIO pins thus
requires 64 accesses to the MEAR register to complete a
single PHY register transaction. Since a PHY device is
typically self configuring and adaptive this serial
management access is usually only required at
initialization time and therefore is not time critical.
3.12.4 Serial Management Access Protocol
The serial control interface clock (MDC) has a maximum
clock rate of 25 MHz and no minimum rate. The MDIO line
is bi-directional and may be shared by up to 32 devices.
The MDIO frame format is shown in Table 3-2.
If external PHY devices may be attached and removed
from the MII there should be a 15 KΩ pull-down resistor on
the MDIO signal. If the PHY will always be connected then
there should be a 1.5 kΩ pull-up resistor which, during
IDLE and turnaround, will pull MDIO high. In order to
initialize the MDIO interface, the DP83815 sends a
sequence of 32 contiguous logic ones on MDIO provides
the PHY(s) with a sequence that can be used to establish
synchronization. This preamble may be generated either
by driving MDIO high for 32 consecutive MDC clock c yc les,
or by simply allowing the MDIO pull-up resistor to pull the
MDIO pin high du ring which ti me 32 MDC cl ock cycle s ar e
provided. In addition 32 MDC clock cycles should be used
to re-sync the device if an invalid start, opcode, or
turnaround bit is detected.
The St art c ode is in dic ate d by a <01> pattern. This assures
the MDIO line transitions from the default idle line state.
Turnaround is defined as an idle bit time inserted between
the Register Address field and the Data field. To avoid
contention during a read transaction, no device shall
actively drive the MDIO signal during the first bit of
Turnaround. The addressed PHY drives the MDIO with a
zero for the second bit of turnaround and follows this with
the required data. Figure 3-15 shows the timing
relationship between MDC and the MDIO as
driven/received by the DP83815 and a PHY for a typical
register read access.
For write transactions, the DP83815 writes data to the
addressed PHY thus eliminating the requirement for MDIO
Turnaround. The Turnaround time is filled by the DP83815
by inserting <10>. Figure 3-16 shows the timing
relations hip for a typical MII register write access.
3.12.5 Nibble-wide MII Data Interface
Clause 22 of the IEEE 802.3u specification defines the
Media Independent Interface. This interface include
separate dedicated receive and transmit busses. These
two data buses, along with various control and indication
signals, allow for the simultaneous exchange of data
between the DP83815 and PHY(s).
Table 3-2 Typical MDIO Frame Format
MII Management
Serial Protocol
<idle><start><op code><device addr><reg addr><turnaround><data><idle>
Read Operation <idle><01><10><AAAAA><RRRRR><Z0><xxxx xxxx xxxx xxxx><idle>
Write Operation <idle><01><01><AAAAA><RRRRR><10><xxxx xxxx xxxx xxxx><idle>
Figure 3-15 Typical MDC/MDIO Read Operation
MDC
MDIO
00011 110000000
(STA)
Idle Start
Opcode
(Read)
PHY Address
(PHYAD = 0Ch)
Register Address
(00h = BMCR)
TA
Register Data
Z
MDIO
(PHY)
Z
Z
Z
0 0 011000100000000
Z
Idle
Z
Z
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