NSC COP820CJMHEA-3, COP820CJ-XXX-WM Datasheet
COP820CJ/COP840CJ Family
8-Bit CMOS ROM Based Microcontrollers with 1k or 2k
Memory, Comparator and Brown Out Detector
General Description
The COP820CJ/840CJ Family ROM based microcontrollers
are integrated COP8
™
Base core devices with 1k or 2k
memory, an Analog comparator and Brownout detection.
These single-chip CMOS devices are suited for lowerfunctionality applications where power and voltage fluctuations are a consideration. Pin and software compatible (no
Brownout; different Vcc range) 4k/32k OTP versions are
available (COP87LxxCJ/RJ Family) for pre-production, and
for use with a range of COP8 software and hardware development tools.
Family features include an 8-bit memory mapped architecture, 10MHz CKI with 1us instruction cycle, one multifunction 16-bit timer/counter, MICROWIRE/PLUS
™
serial
I/O, one analog comparator, power saving HALT mode,
MIWU, on-chip R/C oscillator capacitor (COP840CJ), high
current outputs, software selectable I/O options, WATCHDOG
™
timer, modulator/timer, Brownout detector, Power on
Reset, 2.5v-6.0v operation, and 16/20/28 pin packages.
In this datasheet, the term COP820CJ refers to packages in-
cluding the COP820CJ, COP822CJ, and COP823CJ; and
COP840CJ refers to COP840CJ, COP842CJ, COP940CJ,
and COP942CJ.
Devices included in this data sheet are:
Device Memory (bytes) RAM (bytes) I/O Pins Packages Temperature Comments
COP820CJ 1k ROM 64 24 28 DIP/SOIC -40 to +85˚C
COP822CJ 1k ROM 54 16 20 DIP/SOIC -40 to +85˚C
COP823CJ 1k ROM 64 12 16 SOIC -40 to +85˚C
COP840CJ 2k ROM 128 24 28 DIP/SOIC -40 to +85˚C Low EMI
COP940CJ 2k ROM 128 24 28 DIP/SOIC -0 to +70˚C 2.5V-4.5V, CJH = 4V-6V
COP842CJ 2k ROM 128 16 20 DIP/SOIC -40 to +85˚C
COP942CJ 2k ROM 128 16 20 DIP/SOIC -0 to +70˚C 2.5V-4.5V, CJH = 4V-6V
Key Features
n Multi-Input Wake Up (on the 8-bit Port L)
n Brown out detector
n Analog comparator
n Modulator/timer (High speed PWM for IR transmission)
n 16-bit multi-function timer supporting
— PWM mode
— External event counter mode
— Input capture mode
n 1024 or 2048 bytes of ROM
n 64 or 128 bytes of RAM
n Quiet design (low radiated emissions)
n Integrated capacitor for the R/C oscillator for COP840CJ
I/O Features
n Software selectable I/O options (TRI-STATE®output,
push-pull output, weak pull-up input, high impedance
input)
n High current outputs (8 pins)
n Packages
— 16 SO with 12 I/O pins for COP820CJ
— 20 DIP/SO with 16 I/O pins
— 28 DIP/SO with 24 I/O pins
n Schmitt trigger inputs on Port G
n MICROWIRE/PLUS serial I/O
CPU/Instruction Set Feature
n 1 µs instruction cycle time
n Three multi-source vectored interrupts servicing
— External interrupt with selectable edge
— Timer interrupt
— Software interrupt
n 8-bit Stack Pointer (SP)—stack in RAM
n Two 8-bit register indirect data memory pointers (B, X)
Fully Static CMOS
n Low current drain (typically<1 µA)
n Single supply operation: 2.5V to 6.0V
n Temperature ranges: −0˚C to +70˚C and −40˚C to +85˚C
Development Support
n Emulation and OTP devices
n Real time emulation and full program debug offered by
MetaLink Development System
TRI-STATE®is a registered trademark of National Semiconductor Corporation.
COP8
™
, MICROWIRE™, MICROWIRE/PLUS™and WATCHDOG™are trademarks of National Semiconductor Corporation.
iceMASTER
®
is a registered trademark of MetaLink Corporation.
September 1999
COP820CJ/COP840CJ Family, 8-Bit CMOS ROM Based Microcontrollers with 1k or 2k Memory,
Comparator and Brown Out Detector
© 2000 National Semiconductor Corporation DS011208 www.national.com
Block Diagram
Connection Diagrams
DS011208-1
2k ROM and 128 Bytes RAM for COP840CJ
FIGURE 1. Block Diagram
DS011208-3
Top View
Order Number COPCJ820-XXX/N or
COPCJ820-XXX/M,
Order Number COPCJ840-XXX/N or
COPCJ840-XXX/M,
Order Number COPCJ940-XXX/N or
COPCJ940-XXX/M
See NS Package Number N28B or
M28B
DS011208-4
Top View
Order Number COPCJ822-XXX/N or
COPCJ822-XXX/M
Order Number COPCJ842-XXX/N or
COPCJ842-XXX/M
Order Number COPCJ942-XXX/N or
COPCJ942-XXX/M
See NS Package Number N20A or
M20B
DS011208-5
Top View
Order Number COPCJ823-XXX/WM
See NS Package Number M16B
FIGURE 2. Connection Diagrams
COP820CJ/COP840CJ Family
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Connection Diagrams (Continued)
COP820CJ/COP840CJ Pin Assignment
Port Pin Typ. ALT Function 16-Pin 20-Pin 28-Pin
L0 I/O MIWU/CMPOUT 5 7 11
L1 I/O MIWU/CMPIN− 6 8 12
L2 I/O MIWU/CMPIN+ 7 9 13
L3 I/O MIWU 8 10 14
L4 I/O MIWU 9 11 15
L5 I/O MIWU 10 12 16
L6 I/O MIWU 11 13 17
L7 I/O MIWU/MODOUT 12 14 18
G0 I/O INTR 17 25
G1 I/O 18 26
G2 I/O 19 27
G3 I/O TIO 15 20 28
G4 I/O SO 1 1
G5 I/O SK 16 2 2
G6 ISI 133
G7 I CKO 2 4 4
I0 I 7
I1 I 8
I2 I 9
I3 I 10
D0 O 19
D1 O 20
D2 O 21
D3 O 22
V
CC
466
GND 13 15 23
CKI 3 5 5
RESET
14 16 24
COP820CJ/COP840CJ Family
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Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
CC
) 7.0V
Voltage at any Pin −0.3V to V
CC
+ 0.3V
Total Current into V
CC
pin (Source) 80 mA
Total Current out of GND pin (sink) 80 mA
Storage Temperature Range −65˚C to +150˚C
Note 1:
Absolute maximum ratings indicate limits beyond which damage to
the device may occur.
DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings.
DC Electrical Characteristics
−0˚C ≤ TA≤ + 70˚C for COP94x and −40˚C ≤ TA≤ +85˚C for all others
Parameter Conditions Min Typ Max Units
Operating Voltage Brown Out Disabled 2.5 6.0 V
COP94xCJ Brown Out Disabled 2.5 4.5 V
COP94xCJH Brown Out Disabled 4.5 6.0 V
Power Supply Ripple 1 (Note 2) Peak to Peak 0.1 V
CC
V
Supply Current (Note 3)
CKI = 10 MHz V
CC
= 6V, tc = 1 µs 6.0 mA
CKI = 4 MHz V
CC
= 6V, tc = 2.5 µs 3.5 mA
CKI = 4 MHz V
CC
= 4.0V, tc = 2.5 µs 2.0 mA
CKI = 1 MHz V
CC
= 4.0V, tc = 10 µs 1.5 mA
HALT Current with Brown Out
Disabled (Note 4)
V
CC
= 6V, CKI = 0 MHz
<
110µA
HALT Current with Brown Out
Enabled
V
CC
= 6V, CKI = 0 MHz
<
50 110 µA
COP840CJ Supply Current (Note
3)
CKI = 10 MHz, R = 2.2k V
CC
= 6V, tc = 1 µs 8.0 mA
CKI = 4 MHz, R = 4.7k V
CC
= 6V, tc = 2.5 µs 6.0 mA
CKI = 4 MHz, R = 4.7k V
CC
= 4.5V, tc = 2.5 µs 2.5 mA
CKI = 1 MHz, R = 20k V
CC
= 4.5V, tc = 10 µs 1.5 mA
HALT Current with Brown Out
Disabled
V
CC
= 6V, CKI = 0 MHz
<
2.2 8 µA
HALT Current with Brown Out
Enabled
V
CC
= 6V, CKI = 0 MHz
<
50 100 µA
Brown Out Trip Level (Brown Out
Enabled)
1.8 3.1 4.2 V
COP840CJ Brown Out Trip Level
(Brown Out Enabled)
1.9 3.1 3.9 V
INPUT LEVELS (V
IH,VIL
)
Reset, CKI:
Logic High 0.8 V
CC
V
Logic Low 0.2 V
CC
V
All Other Inputs
Logic High 0.7 V
CC
V
Logic Low 0.2 V
CC
V
Hi-Z Input Leakage V
CC
= 6.0V −2 +2 µA
Input Pullup Current V
CC
= 6.0V, VIN= 0V −40 −250 µA
L- and G-Port Hysteresis (Note 6) COP840CJ
0.05 V
CC
0.35 V
CC
V
COP820CJ/COP840CJ Family
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DC Electrical Characteristics (Continued)
−0˚C ≤ TA≤ + 70˚C for COP94x and −40˚C ≤ TA≤ +85˚C for all others
Parameter Conditions Min Typ Max Units
Output Current Levels
D Outputs:
Source V
CC
= 4.5V, VOH= 3.8V −0.4 mA
V
CC
= 2.5V, VOH= 1.8V −0.2 mA
Sink V
CC
= 4.5V, VOL= 1.0V 10 mA
V
CC
= 2.5V, VOH= 0.4V 2 mA
L4–L7 Output Sink V
CC
= 4.5V, VOL= 2.5V 15 mA
All Others
Source (Weak Pull-up Mode) V
CC
= 4.5V, VOH= 3.2V −10 −110 µA
V
CC
= 2.5V, VOH= 1.8V −2.5 −33 µA
Source (Push-pull Mode) V
CC
= 4.5V, VOH= 3.8V −0.4 mA
V
CC
= 2.5V, VOH= 1.8V −0.2 mA
Sink (Push-pull Mode) V
CC
= 4.5V, VOL= 0.4V 1.6 mA
V
CC
= 2.5V, VOL= 0.4V 0.7 mA
TRI-STATE Leakage −2.0 +2.0 µA
Allowable Sink/Source
Current Per Pin
D Outputs 15 mA
L4–L7 (Sink) 20 mA
All Others 3mA
Maximum Input Current Room Temperature
±
100 mA
without Latchup (Note 5)
RAM Retention Voltage, V
r
500 ns Rise and 2.0 V
Fall Time (Min)
Input Capacitance 7pF
Load Capacitance on D2 1000 pF
Note 2: Rate of voltage change must be less than 10 V/mS.
Note 3: Supply current is measured after running 2000 cycles with a square wave CKI input, CKO open, inputs at rails and outputs open.
Note 4: The HALT mode will stop CKI from oscillating in the RC and crystal configurations. HALT test conditions: L, and G0..G5 ports configured as outputs and set
high. The D port set to zero. All inputs tied to V
CC
. The comparator and the Brown Out circuits are disabled.
Note 5: Pins G6 and RESET are designed with a high voltage input network. These pins allow input voltages greater than V
CC
and the pins will have sink current
to VCCwhen biased at voltages greater than VCC(the pins do not have source current when biased at a voltage below VCC). The effective resistance to VCCis 750Ω
(typical). These two pins will not latch up. The voltage at the pins must be limited to less than 14V.
COP820CJ/COP840CJ Family
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AC Electrical Characteristics
−40˚C ≤ TA≤ +85˚C unless otherwise specified
Parameter Conditions Min Typ Max Units
Instruction Cycle Time (tc)
Crystal/Resonator 4.5V ≤ V
CC
≤ 6.0V 1 DC µs
2.5V ≤ V
CC
≤ 4.5V 2.5 DC µs
R/C Oscillator 4.5V ≤ V
CC
≤ 6.0V 3 DC µs
COP840CJ 2 DC µs
2.5V ≤ V
CC
≤ 4.5V 7.5 DC µs
COP840CJ 5 DC µs
V
CC
Rise Time when Using Brown
Out
VCC=0Vto6V 50 µs
Frequency at Brown Out Reset 4 MHz
CKI Frequency For Modular Output 4 MHz
CKI Clock Duty Cycle (Note 6) fr = Max 40 60 %
Rise Time (Note 6) fr = 10 MHz ext. Clock 12 ns
Fall Time (Note 6) fr = 10 MHz ext. Clock 8 ns
Inputs
t
Setup
4.5V ≤ VCC≤ 6.0V 200 ns
2.5V ≤ V
CC
≤ 4.5V 500 ns
t
Hold
4.5V ≤ VCC≤ 6.0V 60 ns
2.5V ≤ V
CC
≤ 4.5V 150 ns
Output Propagation Delay R
L
= 2.2k, CL = 100 pF
t
PD1,tPD0
SO, SK 4.5V ≤ VCC≤ 6.0V 0.7 µs
2.5V ≤ V
CC
≤ 4.5V 1.75 µs
All Others 4.5V ≤ V
CC
≤ 6.0V 1 µs
2.5V ≤ V
CC
≤ 4.5V 5 µs
Input Pulse Width
Interrupt Input High Time 1 tc
Interrupt Input Low Time 1 tc
Timer Input High Time 1 tc
Timer Input Low Time 1 tc
MICROWIRE Setup Time (t
µWS
)20ns
MICROWIRE Hold Time (t
µWH
)56ns
MICROWIRE Output 220 ns
Propagation Delay (t
µPD
)
Reset Pulse Width 1.0 µs
Note 6: Parameter characterized but not production tested.
DS011208-2
FIGURE 3. MICROWIRE/PLUS Timing
COP820CJ/COP840CJ Family
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Comparator DC and AC Characteristics
4V ≤ VCC≤ 6V, −40˚C ≤ TA≤ + 85˚C (Note 7)
Parameters Conditions Min Type Max Units
Input Offset Voltage 0.4V
<
V
IN
<
VCC− 1.5V
±
10
±
25 mV
Input Common Mode Voltage Range 0.4 V
CC
− 1.5 V
Voltage Gain 300k V/V
DC Supply Current (when enabled) V
CC
= 6.0V 250 µA
Response Time 100 mV Overdrive 60 100 140 ns
500 mV Overdrive 80 125 165 ns
1000 mV Overdrive 135 215 300 ns
Note 7: For comparator output current characteristics see L-Port specs.
Typical Performance Characteristics for COP820CJ
Dynamic—IDDvs V
CC
(Crystal Clock Option)
DS011208-32
Halt—IDDvs V
CC
(Brown Out Disabled)
DS011208-33
Halt—IDDvs V
CC
(Brown Out Enabled)
DS011208-34
Ports L/G Weak
Pull-Up Source Current
DS011208-35
Ports L/G Push-Pull
Source Current
DS011208-36
Ports L/G Push-Pull
Sink Current
DS011208-37
COP820CJ/COP840CJ Family
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Typical Performance Characteristics for COP820CJ (Continued)
Typical Performance Characteristics for COP840CJ
Ports L4–L7
Sink Current
DS011208-38
Port D Source Current
DS011208-39
Port D Sink Current
DS011208-40
Brown Out Voltage
vs Temperature
DS011208-41
Port D Sink current
DS011208-42
Halt Current with
Brown Out Disabled
DS011208-43
Halt Current with
Brown Out Enabled
DS011208-44
COP820CJ/COP840CJ Family
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Typical Performance Characteristics for COP840CJ (Continued)
Halt Current with
Comparator Enabled
DS011208-45
Ports L/G Push-Pull
Source Current
DS011208-46
Ports L/G Push-Pull
Sink Current
DS011208-47
Port D Source Current
DS011208-48
Port D Sink Current
DS011208-49
Brown Out Voltage
vs Temperature
DS011208-50
COP820CJ/COP840CJ Family
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Pin Description
VCCand GND are the power supply pins.
CKI is the clock input. This can come from an external
source, a R/C generated oscillator or a crystal (in conjunction with CKO). See Oscillator description.
RESET is the master reset input. See Reset description.
PORT I is a 4-bit Hi-Z input port.
PORT L is an 8-bit I/O port.
There are two registers associated with the L port: a data
register and a configuration register. Therefore, each L I/O
bit can be individually configured under software control as
shown below:
Port L Port L Port L
Config. Data Setup
0 0 Hi-Z Input (TRI-STATE)
0 1 Input with Weak Pull-up
1 0 Push-pull Zero Output
1 1 Push-pull One Output
Three data memory address locations are allocated for this
port, one each for data register [00D0], configuration register
[00D1] and the input pins [00D2].
Port L has the following alternate features:
L7 MIWU or MODOUT (high sink current capability)
L6 MIWU (high sink current capability)
L5 MIWU (high sink current capability)
L4 MIWU (high sink current capability)
L3 MIWU
L2 MIWU or CMPIN+
L1 MIWU or CMPIN−
L0 MIWU or CMPOUT
The selection of alternate Port L functions is done through
registers WKEN [00C9] to enable MIWU and CNTRL2
[00CC] to enable comparator and modulator.
All eight L-pins have Schmitt Triggers on their inputs.
PORT G is an 8-bit port with 6 I/O pins (G0–G5) and 2 input
pins (G6, G7).
All eight G-pins have Schmitt Triggers on the inputs.
There are two registers associated with the G port: a data
register and a configuration register. Therefore each G port
bit can be individually configured under software control as
shown below:
Port G Port G Port G
Config. Data Setup
0 0 Hi-Z Input (TRI-STATE)
0 1 Input with Weak Pull-up
1 0 Push-pull Zero Output
1 1 Push-pull One Output
Three data memory address locations are allocated for this
port, one for data register [00D4], one for configuration register [00D5] and one for the input pins [00D6]. Since G6 and
G7 are Hi-Z input only pins, any attempt by the user to configure them as outputs by writing a one to the configuration
register will be disregarded. Reading the G6 and G7 configuration bits will return zeros. Note that the device will be
placed in the Halt mode by writing a “1” to the G7 data bit.
Six pins of Port G have alternate features:
G7 CKO crystal oscillator output (selected by mask option)
or HALT restart input/general purpose input (if clock
option is R/C or external clock)
G6 SI (MICROWIRE serial data input)
G5 SK (MICROWIRE clock I/O)
G4 SO (MICROWIRE serial data output)
G3 TIO (timer/counter input/output)
G0 INTR (an external interrupt)
Pins G2 and G1 currently do not have any alternate func-
tions.
The selection of alternate Port G functions are done through
registers PSW [00EF] to enable external interrupt and CNTRL1 [00EE] to select TIO and MICROWIRE operations.
PORT D is a four bit output port that is preset when RESET
goes low. One data memory address location is allocated for
the data register [00DC].
Note: Care must be exercised with the D2 pin operation. At RESET, the ex-
ternal loads on this pin must ensure that the output voltages stay
above 0.8 V
CC
to prevent the chip from entering special modes. Also
keep the external loading on D2 to less than 1000 pF.
Functional Description
The internal architecture is shown in the block diagram. Data
paths are illustrated in simplified form to depict how the various logic elements communicate with each other in implementing the instruction set of the device.
ALU and CPU Registers
The ALU can do an 8-bit addition, subtraction, logical or shift
operations in one cycle time. There are five CPU registers:
A is the 8-bit Accumulator register
PC is the 15-bit Program Counter register
PU is the upper 7 bits of the program counter (PC)
PL is the lower 8 bits of the program counter (PC)
B is the 8-bit address register and can be auto incre-
mented or decremented.
X is the 8-bit alternate address register and can be auto
incremented or decremented.
SP is the 8-bit stack pointer which points to the subroutine
stack (in RAM).
B, X and SP registers are mapped into the on chip RAM. The
B and X registers are used to address the on chip RAM. The
SP register is used to address the stack in RAM during subroutine calls and returns. The SP must be preset by software
upon initialization.
Memory
The memory is separated into two memory spaces: program
and data.
PROGRAM MEMORY
Program memory consists of 1024 x 8 ROM or 2048 x 8
ROM. These bytes of ROM may be instructions or constant
data. The memory is addressed by the 15-bit program
counter (PC). ROM can be indirectly read by the LAID instruction for table lookup.
DATA MEMORY
The data memory address space includes on chip RAM, I/O
and registers. Data memory is addressed directly by the instruction or indirectly through B, X and SP registers. The device has 64 or 128 bytes of RAM. Sixteen bytes of RAM are
COP820CJ/COP840CJ Family
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Memory (Continued)
mapped as “registers”, these can be loaded immediately,
decremented and tested. Three specific registers: X, B, and
SP are mapped into this space, the other registers are available for general usage.
Any bit of data memory can be directly set, reset or tested.
All I/O and registers (except Aand PC) are memory mapped;
therefore, I/O bits and register bits can be directly and individually set, reset and tested, except the write once only bit
(WDREN, WATCHDOG Reset Enable), and the unused and
read only bits in CNTRL2 and WDREG registers.
Note: RAM contents are undefined upon power-up.
Reset
EXTERNAL RESET
The RESET input pin when pulled low initializes the
micro-controller.The user must insure that the RESET pin is
held low until V
CC
is within the specified voltage range and
the clock is stabilized. An R/C circuit with a delay 5x greater
than the power supply rise time is recommended (
Figure 4
).
The device immediately goes into reset state when the RESET input goes low. When the RESET pin goes high the device comes out of reset state synchronously. The device will
be running within two instruction cycles of the RESET pin going high. The following actions occur upon reset:
Port L TRI-STATE
Port G TRI-STATE
Port D HIGH
PC CLEARED
RAM Contents RANDOM with Power-On-
Reset
UNAFFECTED with external
Reset (power already applied)
B, X, SP Same as RAM
PSW, CNTRL1,
CNTRL2
and WDREG Reg. CLEARED
Multi-Input Wakeup
Reg.
WKEDG, WKEN CLEARED
WKPND UNKNOWN
Data and Configuration
Registers forL&G CLEARED
WATCHDOG Timer Prescaler/Counter each
loaded with FF
The device comes out of the HALT mode when the RESET
pin is pulled low. In this case, the user has to ensure that the
RESET signal is low long enough to allow the oscillator to restart. An internal 256 t
c
delay is normally used in conjunction
with the two pin crystal oscillator. When the device comes
out of the HALT mode through Multi-Input Wakeup, this delay allows the oscillator to stabilize.
The following additional actions occur after the device
comes out of the HALT mode through the RESET pin.
If a two pin crystal/resonator oscillator is being used:
RAM Contents UNCHANGED
Timer T1 and A Contents UNKNOWN
WATCHDOG Timer Prescaler/Counter ALTERED
If the external or RC Clock option is being used:
RAM Contents UNCHANGED
Timer T1 and A Contents UNCHANGED
WATCHDOG Timer Prescaler/Counter ALTERED
The external RESET takes priority over the Brown Out Reset.
Note: If the RESET pin is pulled low while Brown Out occurs (Brown Out cir-
cuit has detected Brown Out condition), the external reset will not occur until the Brown Out condition is removed. External reset has priority only if V
CC
is greater than the Brown Out voltage.
WATCHDOG RESET
With WATCHDOG enabled, the WATCHDOG logic resets
the device if the user program does not service the WATCHDOG timer within the selected service window.The WATCHDOG reset does not disable the WATCHDOG. Upon
WATCHDOG reset, the WATCHDOGPrescaler and Counter
are each initialized with FF Hex.
The following actions occur upon WATCHDOGreset that are
different from external reset.
WDREN WATCHDOG Reset Enable bit UNCHANGED
WDUDFWATCHDOG Underflow bitUNCHANGED
Additional initialization actions that occur as a result of
WATCHDOG reset are as follows:
Port L TRI-STATE
Port G TRI-STATE
Port D HIGH
PC CLEARED
RAM Contents UNCHANGED/RANDOM
B, X, SP UNCHANGED
PSW, CNTRL1 and
CNTRL2 (except WDUDF
Bit) Registers
CLEARED
Multi-Input Wakeup
Registers
WKEDG, WKEN CLEARED
WKPND UNKNOWN
Data and Configuration
Registers forL&G CLEARED
WATCHDOG Timer Prescalar/Counter
each loaded with FF
DS011208-51
RC>5 x Power Supply Rise Time
FIGURE 4. Recommended Reset Circuit
COP820CJ/COP840CJ Family
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