NSC CLC402AJP Datasheet
Features
■
0.0025% settling in 25ns (32ns max)
■
0.5mV input offset voltage, 3µV/°C drift
■
±1 to ±8 closed-loop gain range
■
Low power, 150mW
■
0.01%/0.05° differential gain/phase
Applications
■
High-accuracy A/D systems (12-14 bits)
■
High-accuracy D/A converters
■
High-speed communications
■
IF processors
■
Video distribution
General Description
CLC402
Low-Gain Op Amp with Fast 14-Bit Settling
N
June 1999
CLC402
Low-Gain Op Amp with Fast 14-Bit Settling
Pinout
DIP & SOIC
The CLC402 is available in several versions to meet a variety of
requirements. A three-letter suffix determines the version:
CLC402AJP -40°C to +85°C 8-pin plastic DIP
CLC402AJE -40°C to +85°C 8-pin plastic SOIC
CLC402A8B -55°C to +125°C 8-pin hermetic CERDIP,
MIL-STD-833, Level B
CLC402ALC
-40°C to +85°C dice
CLC402AMC -55°C to +125°C dice qualified to Method 5008,
MIL-STD-883, Level B
DESC SMD number: 5962-92033
© 1998 National Semiconductor Corporation http://www.national.com
Printed in the U.S.A.
Non-Inverting Frequency Response
V
= 0.5V
out
pp
Magnitude (1dB/div)
Av = 8
Rf = 200Ω
1
Av = 1
Rf = 274Ω
Av = 4
Rf = 221Ω
10
Av = 2
Rf = 249Ω
100
Phase (deg)
0
-90
-180
-270
-360
-450
CLC402 Electrical Characteristics
(Av= +2,Vcc= ±5V, RL= 100Ω,Rf= 250Ω; unless specified)
Absolute Maximum Ratings Miscellaneous Ratings
Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are
determined from tested parameters.
http://www.national.com 2
Pac kage Thermal Resistance
Package θ
JC
θ
JA
AJP 70°C/W 125°C/W
AJE 65°C/W 145°C/W
CERDIP 45°C/W 135°C/W
Reliability Information
Transistor count 37
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