NSC CLC011BCQ Datasheet

CLC011
Serial Digital Video Decoder

General Description

National’s Comlinear CLC011, Serial Digital Video Decoder,
decodes and descrambles SMPTE 259M standard Serial
Digital Videodatastreams with serial clockinto 10-bit parallel
words and a corresponding word-rate clock. SMPTE 259M
standard parallel data is encoded and scrambled using a
9-bit shift register and is also converted from NRZ to NRZI.
The CLC011 restores the original parallel data by reversing
the encoding process. The CLC011 also extracts timing in­formation embedded in the SDV data. These reserved code
words, known as Timing Reference Signals (TRS), indicate
the start and end of each active video line. By decoding the
TRS, the CLC011 correctly identifies the word boundaries of
the encoded input data. Detection of the TRS reserved
codes is indicated by low-true signals at the TRS and End of
Active Video (EAV) outputs.

The CLC011’s design using current-mode logic (CML) re­duces noise injection into the power supply thereby easing
board layout and interfacing. The CMOS compatible outputs,

Block Diagram

CLC011 Serial Digital Video Decoder

January 1999

which feature controlled riseand fall times, may be set forei­ther 3.3V or 5V swings with the VDP and VCP inputs.

The CLC011 Serial Digital Video Decoder, CLC014Adaptive
Cable Equalizer and the CLC016 Data Retiming PLL com­bine to provide a complete Serial Digital Video receiver sys­tem.

The CLC011 is packaged in a 28-pin PLCC.

Features

n Data decoding and deserializing
n CLC011B operates to 360Mbps
n CLC011A operates to 300Mbps
n Low noise injection to power supplies
n Single +5V or −5.2V supply operation
n Output levels programmable for interface to 5V or 3.3V

logic

n Low power
n Low cost

DS100086-1

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Connection Diagram

DS100086-2

28-Pin PLCC

Order Number CLC011ACQ, or CLC011BCQ

See NS Package Number V28A

Pin Descriptions

Name Pin No. Description

EAV 1 End of active video flag. For component video, a logic low is output for one cycle of the

V

EE

2, 4, 26 Negative supply pins.
NC 3 Unused pin.
SDI+, SDI− 5, 6 Differential serial data inputs.
SCI+, SCI− 7, 8 Differential serial clock inputs.
NRZI 9 A logic high at this pin enables NRZI-to-NRZ conversion.
DESC 10 A logic high at this pin enables descrambling.
FE 11 Frame enable. Enables resynchronization of the parallel word at the next TRS.
V

CC

12 Positive supply pin.

VCP 13 Parallel clock high level programming pin. The voltage at this supply pin defines the logic high

NSP 14 New sync position. Indicates that the most recent TRS is in a new position relative to the

TRS 15 Timing reference flag. A logic low is output for the duration of the TRS.
PCLK 16 Parallel clock output. The rising edge of this clock is located at the center of the parallel data

PD0–9 17,

19–25,

27, 28

VDP 18 Parallel data high level programming pin. The voltage at this supply pin defines the logic high

parallel clock every time an EAV timing reference is detected. The pulse is aligned with the
fourth word of the timing reference (the XYZ word). For composite video, this line is always
asserted high.

level for the parallel clock output.

previous TRS. Remains high until the parallel rate clock is aligned properly with the TRS.

window.
Parallel data outputs.

level for the data outputs.

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Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor SalesOffice/

θ

28-Pin PLCC 35˚C/W

JC

Reliability Information

Transistor Count 3076

Distributors for availability and specifications.

Supply Voltage (V

) +6V

CC–VEE

Storage Temperature Range −65˚C to +150˚C
Junction Temperature +150˚C

ESD Rating (HBM)

PDx 500V
other 2kV

Package Thermal Resistance

28-Pin PLCC 85˚C/W

θ

JA

Recommended Operating
Conditions

Supply Voltage (VCC–VEE) 4.5V to 5.5V
Logic High Voltage

(V

Operating Temperature 0˚C to +70˚C

and VDP–VEE) 3.0V to 5.5V

CP–VEE

Electrical Characteristics

(VCC= +5V, VEE= 0V, CL= 10 pF; unless specified).

Parameter Conditions

Typ

+25˚C

Min/Max

+25˚C

DYNAMIC PERFORMANCE

Minimum Serial Data Rate 0 Mbps
Maximum Serial Data Rate CLC011B 400 360 360 Mbps

CLC011A 300 300 Mbps
PDn and PCLK Rise/Fall Time C
PDn and PCLK Rise/Fall Time C

= 2 pF,(Note 9) 2.0 ns

L

= 20 pF,(Note 9) 4.0 ns

L

PCLK Rising Edge Residual Jitter (Note 9) 50 ps

TIMING PERFORMANCE

SD to SC Setup Time 0.2 0.2 ns
SC to SD Hold Time 00ns
PDn to PCLK Skew (Note 9)
PDn Valid to PCLK
PCLK

to PDn Invalid PCLK = 27 MHz, (Note 9) 18 ns

↑

↑

PCLK = 27 MHz, (Note 9) 18 ns

±

0.8 ns

Digital Latency (Notes 6, 7, 9) 42 sclk

Output Buffer Latency (Notes 7, 9) 10 ns

STATIC PERFORMANCE

I

Supply Current (Note 9) VCCPin 44 mA

CC

VDP and VCP Supply Current PCLK = 0 MHz, (Note 9) 2 mA
VDP and VCP Supply Current PCLK = 27 MHz, (Note 9) 12 mA
SD and SC Inputs

Input Range Upper Limit V
Input Range Lower Limit V

EE

Minimum Differential Input 200 200 mV
I

IH

10 15 µA

FE, NRZI, and DESC Inputs

V

IL

V

IH

VEE+0.8 VEE+0.8 V
VEE+2.0 VEE+2.0 V

Outputs

V

OL

V

OH

IOL=10mA VEE+0.5 VEE+0.5 V

IOH=10mA VCC−0.5 VCC−0.5 V

MISCELLANEOUS PERFORMANCE

SD and SC Input Capacitance (Note 9) 2.0 pF
SD and SC Input Resistance (Note 9) 20 kΩ

Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation.

Min/Max

0˚C to
+70˚C

cycles

CC

V

CC

+2.5 VEE+2.5 V

Units

pp

V

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