NSC ADCV08832CIM Datasheet

May 2001

ADCV08832
Low Voltage, 8-Bit Serial I/O CMOS A/D Converter with
Sample/Hold Function

General Description

The ADCV08832 is a low voltage, 8-Bit successive approxi­mation analog-to-digital converter with a 3-wire serial inter­face. The serial I/O will interface to microcontrollers, PLD’s,
microprocessors, DSPs or shift registers. The serial I/O is
configured to comply with the NSC MICROWIRE
data exchange standard.

To minimize total power consumption, the ADCV08832 can
be set to go into low power mode whenever it is not perform­ing conversions.

A sample/hold function allows the analog voltage at the
positive input to vary during the actual A/D conversion. The
analog inputs can be configured to operate in various com­binations of single-ended, differential, or pseudo-differential
modes.

™

serial

Features

n 3-wire serial digital data link requires few I/O pins
n Single supply 2.7V to 5V
n Analog input track/hold function
n Analog input voltage range from GND to V
n No zero or full scale adjustment required

CC

n TTL/CMOS input/output compatible
n Superior pin compatible replacement for TLV0832 and

ADC0832

Applications

n Digitizing sensors and waveforms
n Process control monitoring
n Remote sensing in noisy environments
n Instrumentation
n Embedded systems
n Low power circuits

Key Specifications

(For 3.3V supply, typical, unless otherwise noted)

n Resolution 8 bits
n Conversion time (f
n Power dissipation 1.7 mW
n Power down mode
n Total Unadjusted Error
n No missing codes over temperature (−40˚C to +125˚C)

= 500 kHz) 16 µs (max)

CLK

<

±

0.8 LSB

ADCV08832 Low Voltage, 8-Bit Serial I/O CMOS A/D Converter with Sample/Hold Function

0.1 µW

Connection Diagram

Ordering Information

Temperature Range

Industrial (−40˚C ≤ T

ADCV08832CIM M08A ADC08832I 95 Units in Rail
ADCV08832CIMX M08A ADC08832I 2500 Units in

≤ +125˚C)

J

ADCV08832

SOIC-8 Package

Package

DS200084-1

Package

Marking

Transport

Media

Tape and Reel

COPS™and MICROWIRE™are trademarks of National Semiconductor Corporation.

© 2001 National Semiconductor Corporation DS200084 www.national.com

Absolute Maximum Ratings (Notes 1, 3)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.

ADCV08832

Supply Voltage (V
Voltage at Inputs and Outputs −0.3V to V
Input Current at Any Pin (Note 4)
Package Input Current (Note 4)
ESD Susceptibility (Note 6)

Human Body Model 2500V
Machine Model 250V

) 6.5V

CC

CC

+ 0.3V

±

5mA

±

20 mA

Storage Temperature Range −65˚C to +150˚C
Mounting Temperature

Infrared 235˚C

Operating Ratings (Notes 2, 3)

Temperature Range −40˚C
Supply Voltage 2.7V to 5.5V
Thermal Resistance (θ

SO Package,

8-pin Surface Mount 190˚C/W

Clock Frequency 10 kHz ≤ f

Junction Temperature (Note 5) 150˚C

Electrical Characteristics

The following specifications apply for VCC= 3.3VDCand f

face limits apply for T

A=TJ=TMIN

to T

; all other limits TA=TJ= 25˚C.

MAX

Symbol Parameter Conditions Typical

CONVERTER AND MULTIPLEXED CHARACTERISTICS

TUE Total Unadjusted Error (Note 9)
V

OFF

Offset Error 0.03
DNL Differential Nonlinearity 0.1
INL Integral Nonlinearity 0.1
FS Full Scale Error 0.06
V

IN

Analog Input Voltage (Note 10) (VCC+ 0.05)

DC Common Mode Error

Analog Input Leakage Current

(Note 11)

On Channel
Off Channel

DC CHARACTERISTICS

V

IN(1)

V

IN(0)

I

IN

V

OUT(1)

V

OUT(0)

I

OUT

I

SOURCE

Logical “1” Input Voltage 1.0 2.0 V (min)

Logical “0” Input Voltage 1.1 0.8 V (max)

Digital Input Current

Logical “1” Output Voltage VCC= 2.7V

I

OUT

Logical “0” Output Voltage VCC= 2.7V

I

OUT

TRI-STATE Output Current V

Digital Output Short Circuit

V
V

OUT
OUT

OUT

Current
I
I

SINK
CC

Digital Output Sink Circuit V

OUT=VCC

Supply Current (Note 15) CS = V

CS = Low,
CLK=V

= 500 kHz, 50% Duty Cycle, unless otherwise specified. Bold-

CLK

= −360 µA 3.3 2.4 V (min)

= 1.6 mA

=0V
= 3.3V

= 0V −13 mA

CC

CC

<

T

J

)

jA

≤ 1000 kHz

CLK

(Note 7)

±

0.1

Limits

(Note 8)

±

0.8 LSB (max)

±

0.5 LSB

±

0.5 LSB

±

0.5 LSB

±

0.8 LSB

Units

V (max)

(GND − 0.05)

±

0.02 LSB (max)

±

11.0 nA

±

3.0 nA

±

2 µA (max)

V (min)

0.2 0.4 V (max)

−2.0

2.0

9.6 mA

0.1 nA

330 500 µA (max)

<

+125˚C

µA
µA

Electrical Characteristics

The following specifications apply for VCC= 3.3V, 50% Duty Cycle, and tr=tf= 20 ns unless otherwise specified. Boldface
limits apply for T

A=TJ=TMIN

Symbol Parameter Conditions Typical Limits Units

f

CLK

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Max Clock Frequency VCC= 5 1000 kHz

to T

; all other limits TA=TJ= 25˚C.

MAX

V

= 3.3 700 500 kHz

CC

V

= 2.7 400 kHz

CC

Electrical Characteristics (Continued)

The following specifications apply for VCC= 3.3V, 50% Duty Cycle, and tr=tf= 20 ns unless otherwise specified. Boldface
limits apply for T

A=TJ=TMIN

Symbol Parameter Conditions Typical Limits Units

Clock Duty Cycle
(Note 12)

t

CONV

Conversion Time (Not Including MUX
Addressing Time) f

t

ca

t

SET-UP

Acquisition Time
Set Up Time Required from Falling CS

to Rising Clock Edge

t

HOLD

Data Input Valid after CLK
Rising Edge

t

pd1,tpd0

CLK Falling Edge to Output
Data Valid (Note 13)

t

1H,t0H

TRI-STATE Delay from Rising Edge
of CS to Data Output and SARS Hi-Z

C

IN

Input Capacitance of CH0,CH
(Note 14)

C

IN

C

OUT

Input Capacitance of CLK, D1 5 pF
Output Capacitance of Logic Outputs

D0 (in TRI-STATE)

to T

; all other limits TA=TJ= 25˚C.

MAX

= 500 kHz

CLK

CL= 100 pF:
Data MSB First
Data LSB First

CL= 100 pF, RL=10kΩ
(see TRI-STATE Test Circuit)

1

40
60

8

% (min)

% (max)

1/f

16

1

⁄

2

1/f

CLK

15 ns (min)

20 ns (min)

150
100

ns (max)
ns (max)

35 ns

13 pF

5pF

ADCV08832

CLK

µs

(max)

Dynamic Characteristics

The following specifications apply for VCC= 3.3V, f
non-coherent 2048 samples.

Symbol Parameter Conditions Typical Limits Units

f

S

Sampling Rate f
SNR Signal-to-Noise Ratio (Note 16) 49.5 dB
THD Total Harmonic Distortion (Note 17) −66 dB
SINAD Signal-to-Noise and Distortion 49.4 dB
ENOB Effective Number Of Bits (Note 15) 7.9 Bits
SFDR Spurious Free Dynamic Range −67.6 dB

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.
Note 2: Operating Ratings indicate conditions for which the device is functional. These ratings do not guarantee specific performance limits. For guaranteed

specifications and test conditions, see Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance
characteristics may degrade when the device is not operated under the listed test conditions.

Note 3: All voltages are measured with respect to GND = 0 V
Note 4: Whenthe input voltage V

maximum package input current rating limits the number of pins that can safely exceed V
Note 5: The maximum power dissipation must be derated at elevated temperatures and is dictated by T

allowable power dissipation at any temperature is P

Note 6: Human body model, 100 pF capacitor discharged through a 1.5 kΩ resistor. The machine mode is a 200 pF capacitor discharged directly into each pin.
Note 7: Typical are at T
Note 8: Guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 9: Total unadjusted error includes offset, full-scale, linearity, and multiplexer errors.
Note 10: For V

forward-conduct for analog input voltages one diode drop below ground or one diode drop greater than V
analog inputs (e.g., 3.3V) can cause an input diode to conduct, especially at elevated temperatures, which will cause errors for analog inputs near full-scale. The
spec allows 50 mV forward bias of either diode; this means that as long as the analog V
will be correct. Exceeding the range on an unselected channel will corrupt the reading of a selected channel. Achievement of an absolute 0 V
voltage range will therefore require a minimum supply voltage of 3.25 V

Note 11: Channel leakage current is measured after a single-ended channel is selected and the clock is turned off. For off channel leakage current the following
two cases are considered: one, with the selected channel tied high (3.3V
is measured; two, with the selected channel tied low and the off channels tied high, total current flow through the off channel is again measured. The two cases
considered for determining the on channel leakage current are the same except total current flow through the selected channel is measured.

Note 12: A 40% to 60% duty cycle range insures proper operation at all clock frequencies.
Note 13: Since data, MSB first, is the output of the comparator used in the successive approximation loop, an additional delay is built in to allow for comparator

response time.

IN(−)

≥ V

J

IN(+)

at any pin exceeds the power supplies (V

IN

=(T

D

JMAX−TA

= 25˚C and represent the most likely parametric norm.

the digital output will be 0000 0000. Two on-chip diodes are tied to each analog input (see Functional Block Diagram) which will

= 500 kHz, TA= 25˚C, R

CLK

, unless otherwise specified.

DC

)/θJAor the number given in the Absolute Maximum Ratings, whichever is lower.

<

(GND) or V

IN

over temperature variations, initial tolerance and loading.

DC

) and the remaining off channel tied low (0 VDC), total current flow through the off channel

DC

CC

does not exceed the supply voltage by more than 50 mV,the output code

IN

SOURCE

>

VCC,) the current at that pin should be limited to 5 mA. The 20 mA

IN

with an input current of 5 mA to four pins.

=25Ω,fIN= 9.6 kHz, VIN= 3.3V

/13 ksps

CLK

, θJAand the ambient temperature, TA. The maximum

JMAX

. During testing at low VCClevels (e.g., 2.7V), high level

CC

to 3.30 VDCinput

DC

P-P

,

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Dynamic Characteristics (Continued)

Note 14: Analog inputs are typically 300Ω input resistance in series with a 13 pF sample and hold.
Note 15: Effective Number Of Bits (ENOB) is calculated from the measured signal-to-noise plus distortion ratio (SINAD) using the equation ENOB = (SINAD

−1.76)/6.02.

ADCV08832

Note 16: The signal-to-noise ratio is the ratio of the signal amplitude to the background noise level. Harmonics of the input signal are not included in its calculation.
Note 17: The contributions of the first 6 harmonics are to calculate THD.

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ADCV08832 Functional Block Diagram

ADCV08832

DS200084-12

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