NSC ADC12L063EVAL Datasheet

November 2002

ADC12L063
12-Bit, 62 MSPS, 354 mW A/D Converter with Internal
Sample-and-Hold

ADC12L063 12-Bit, 62 MSPS, 354 mW A/D Converter with Internal Sample-and-Hold

General Description

The ADC12L063 is a monolithic CMOS analog-to-digital con­verter capable of converting analog input signals into 12-bit
digital words at 62 Megasamples per second (MSPS), mini­mum. This converter uses a differential, pipelined architec­ture with digital error correction and an on-chip sample-and­hold circuit to minimize die size and power consumption
while providing excellent dynamic performance. Operating
on a single 3.3V power supply, this device consumes just
354 mW at 62 MSPS, including the reference current. The
Power Down feature reduces power consumption to just 50
mW.

The differential inputs provide a full scale input swing equal

±

V

to
of the differential input is recommended for optimum perfor­mance. For ease of use, the buffered, high impedance,
single-ended reference input is converted on-chip to a differ­ential reference for use by the processing circuitry. Output
data format is 12-bit offset binary.

This device is available in the 32-lead LQFP package and
will operate over the industrial temperature range of −40˚C to
+85˚C.

with the possibility of a single-ended input. Full use

REF

Features

n Single supply operation
n Low power consumption
n Power down mode
n On-chip reference buffer

Key Specifications

n Resolution 12 Bits
n Conversion Rate 62 MSPS(min)
n Bandwidth 170MHz
n DNL
n INL
n SNR 66 dB(typ)
n SFDR 78 dB(typ)
n Data Latency 6 Clock Cycles
n Supply Voltage +3.3V
n Power Consumption, 62 MHz 354 mW(typ)

±

0.5 LSB(typ)

±

1.0 LSB(typ)

±

300 mV

Applications

n Ultrasound and Imaging
n Instrumentation
n Cellular Base Stations/Communications Receivers
n Sonar/Radar
n xDSL
n Wireless Local Loops
n Data Acquisition Systems
n DSP Front Ends

Connection Diagram

20026301

© 2002 National Semiconductor Corporation DS200263 www.national.com

Ordering Information

ADC12L063

Block Diagram

Industrial (−40˚C ≤ TA≤ +85˚C) Package

ADC12L063CIVY 32 Pin LQFP

ADC12L063CIVYX 32 Pin LQFP Tape and Reel

ADC12L063EVAL Evaluation Board

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20026302

Pin Descriptions and Equivalent Circuits

Pin No. Symbol Equivalent Circuit Description

ANALOG I/O

Non-Inverting analog signal Input. With a 1.0V reference
voltage the input signal level is 1.0 V

Inverting analog signal Input. With a 1.0V reference voltage
the input signal level is 1.0 V

for single-ended operation, but a differential input

to V

CM

P-P

signal is required for best performance.

Reference input. This pin should be bypassed to AGND with
a 0.1 µF monolithic capacitor. V
should be between 0.8V and 1.2V.

2V

3V

1V

IN

IN

REF

+

−

.

P-P

. This pin may be connected

is 1.0V nominal and

REF

ADC12L063

31 V

32 V

30 V

DIGITAL I/O

10 CLK

11 OE

RP

RM

RN

These pins are high impedance reference bypass pins only.
Connect a 0.1 µF capacitor from each of these pins to AGND.
DO NOT connect anything else to these pins.

Digital clock input. The range of frequencies for this input is 1
MHz to 70 MHz (typical) with guaranteed performance at 62
MHz. The input is sampled on the rising edge of this input.

OE is the output enable pin that, when low, enables the
TRI-STATE data output pins. When this pin is high, the
outputs are in a high impedance state.

8PD

PD is the Power Down input pin. When high, this input puts
the converter into the power down mode. When this pin is
low, the converter is in the active mode.

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Pin Descriptions and Equivalent Circuits (Continued)

Pin No. Symbol Equivalent Circuit Description

ADC12L063

14–19,

22–27

D0–D11

Digital data output pins that make up the 12-bit conversion
results. D0 is the LSB, while D11 is the MSB of the offset
binary output word.

ANALOG POWER

Positive analog supply pins. These pins should be connected

5, 6, 29 V

A

to a quiet +3.3V source and bypassed to AGND with 0.1 µF
monolithic capacitors located within 1 cm of these power pins,
and with a 10 µF capacitor.

4, 7, 28 AGND The ground return for the analog supply.

DIGITAL POWER

Positive digital supply pin. This pin should be connected to
the same quiet +3.3V source as is V

13 V

D

DGND with a 0.1 µF monolithic capacitor in parallel with a 10
µF capacitor, both located within 1 cm of the power pin.
Decouple this pin from the V

A

pins.

9, 12 DGND The ground return for the digital supply.

Positive digital supply pin for the ADC12L063’s output drivers.
This pin should be connected to a voltage source of +2.5V to

and bypassed to DR GND with a 0.1 µF monolithic

V

D

21 V

DR

capacitor. If the supply for this pin is different from the supply
used for V

and VD, it should also be bypassed with a 10 µF

A

tantalum capacitor. The voltage at this pin should never
exceed the voltage on V

. All bypass capacitors should be

D

located within 1 cm of the supply pin.

The ground return for the digital supply for the ADC12L063’s
output drivers. This pin should be connected to the system

20 DR GND

digital ground, but not be connected in close proximity to the
ADC12L063’s DGND or AGND pins. See Section 5.0 (Layout
and Grounding) for more details.

and bypassed to

A

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ADC12L063

Absolute Maximum Ratings (Notes 1,

2)

If Military/Aerospace specified devices are required,

Soldering Temperature,

Infrared, 10 sec. (Note 6) 235˚C

Storage Temperature −65˚C to +150˚C

please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.

V

A,VD,VDR

|V

| ≤ 100 mV

A–VD

Voltage on Any Input or Output Pin −0.3V to V

Input Current at Any Pin (Note 3)

Package Input Current (Note 3)

Package Dissipation at T

= 25˚C See (Note 4)

A

ESD Susceptibility

or V

A

+0.3V

±

25 mA

±

50 mA

4.2V

D

Operating Ratings (Notes 1, 2)

Operating Temperature −40˚C ≤ T

Supply Voltage (V

Output Driver Supply (V

V

Input 0.8V to 1.2V

REF

CLK, PD, OE

V

Input −0V to (VA− 0.5V)

IN

) +3.0V to +3.60V

A,VD

) +2.5V to V

DR

−0.05V to VD+ 0.05V

|AGND–DGND| ≤100mV

≤ +85˚C

A

Human Body Model (Note 5) 2500V

Machine Model (Note 5) 250V

Converter Electrical Characteristics

Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA=VD=VDR= +3.3V,
PD = 0V, V
other limits T

REF

A=TJ

= +1.0V, f

= 25˚C (Notes 7, 8, 9)

Symbol Parameter Conditions

STATIC CONVERTER CHARACTERISTICS

Resolution with No Missing Codes 12 Bits

INL Integral Non Linearity (Note 11)

DNL Differential Non Linearity

GE Gain Error Positive Error −0.8 %FS(max)

Offset Error (V

Under Range Output Code 0 0

Over Range Output Code 4095 4095

REFERENCE AND ANALOG INPUT CHARACTERISTICS

V

CM

C

IN

V

REF

Common Mode Input Voltage 1.0 V

VINInput Capacitance (each pin to
GND)

Reference Voltage (Note 13) 1.00

Reference Input Resistance 100 MΩ(min)

= 62 MHz, tr=tf= 2 ns, CL= 20 pF/pin. Boldface limits apply for TA=TJ=T

CLK

Typical

(Note 10)

±

1.0

±

0.5 LSB(max)

Negative Error +0.1

+=VIN−) +0.1

IN

VIN= 1.0 Vdc
+1V

P-P

(CLK LOW) 8 pF

(CLK HIGH) 7 pF

to T

MIN

Limits

(Note 10)

±

2.4 LSB(max)

±

3 %FS(max)

±

0.9 %FS(max)

0.8 V(min)

1.2 V(max)

MAX

Units

(Limits)

: all

D

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DC and Logic Electrical Characteristics

Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA=VD=VDR= +3.3V, PD

REF

= +1.0V, f

A=TJ

= 0V, V
other limits T

ADC12L063

Symbol Parameter Conditions

CLK, PD, OE DIGITAL INPUT CHARACTERISTICS

V

V

I

IN(1)

I

IN(0)

C

IN(1)

IN(0)

IN

Logical “1” Input Voltage VD= 3.3V 2.0 V(min)

Logical “0” Input Voltage VD= 3.0V 0.8 V(max)

Logical “1” Input Current V

Logical “0” Input Current V

Digital Input Capacitance 5 pF

D0–D11 DIGITAL OUTPUT CHARACTERISTICS

V

V

I

OZ

+I

OUT(1)

OUT(0)

SC

Logical “1” Output Voltage I

Logical “0” Output Voltage I

TRI-STATE Output Current

Output Short Circuit Source
Current

−I

SC

Output Short Circuit Sink Current V

POWER SUPPLY CHARACTERISTICS

I

A

I

D

I

DR

Analog Supply Current

Digital Supply Current

Digital Output Supply Current

Total Power Consumption

PSRR1 Power Supply Rejection

PSRR2 Power Supply Rejection

DYNAMIC CONVERTER CHARACTERISTICS

BW Full Power Bandwidth 0 dBFS Input, Output at −3 dB 170 MHz

SNR Signal-to-Noise Ratio

SINAD Signal-to-Noise and Distortion

ENOB Effective Number of Bits

THD Total Hamonic Distortion

= 62 MHz, tr=tf= 2 ns, CL= 20 pF/pin. Boldface limits apply for TA=TJ=T

CLK

= 25˚C (Notes 7, 8, 9)

Typical

(Note 10)

+

−

,V

IN

IN

OUT

OUT

V

OUT

V

OUT

V

OUT

OUT=VDR

PD Pin = DGND, V
PD Pin = V

= 3.3V 10 µA

IN

+

−

,V

= 0V −10 µA

IN

= −0.5 mA 2.7 V(min)

= 1.6 mA 0.4 V(max)

= 3.3V 100 nA

= 0V −100 nA

= 0V −20 mA(min)

= 1.0V

REF

DR

102

PD Pin = DGND
PD Pin = V

DR,fCLK

=0

PD Pin = DGND, (Note 14)
PD Pin = V

DR,fCLK

PD Pin = DGND, C
PD Pin = V

DR,fCLK

=0

= 0 pF (Note 15)

L

=0

354

Rejection of Full-Scale Error with

= 3.0V vs 3.6V

V

A

SNR Degradation w/10 MHz,
250 mV

f

= 1 MHz, Differential VIN=

IN

riding on V

P-P

A

−53 dB

−0.5 dBFS

fIN= 10 MHz, Differential VIN=

−0.5 dBFS

= 1 MHz, Differential VIN=

f

IN

−0.5 dBFS

= 10 MHz, Differential VIN=

f

IN

−0.5 dBFS

fIN= 1 MHz, Differential VIN=

−0.5 dBFS

= 10 MHz, Differential VIN=

f

IN

−0.5 dBFS

fIN= 1 MHz, Differential VIN=

−0.5 dBFS

= 10 MHz, Differential VIN=

f

IN

−0.5 dBFS

10.6 Bits

10.3 10.0 Bits

−80 dB

−74 −65 dB(max)

to T

MIN

Limits

(Note 10)

20 mA(min)

140 mA(max)

4

5.3

7 mA(max)

2

<

1

0

485 mW

50

58 dB

66 dB

66 63.3 dB(min)

65 dB

65 62 dB

: all

MAX

Units

(Limits)

mA

mA

mA(max)

mA

mW

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DC and Logic Electrical Characteristics (Continued)

Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA=VD=VDR= +3.3V, PD

REF

= +1.0V, f

A=TJ

= 0V, V
other limits T

Symbol Parameter Conditions

SFDR Spurious Free Dynamic Range

IMD Intermodulation Distortion

= 62 MHz, tr=tf= 2 ns, CL= 20 pF/pin. Boldface limits apply for TA=TJ=T

CLK

= 25˚C (Notes 7, 8, 9)

Typical

(Note 10)

= 1 MHz, Differential VIN=

f

IN

−0.5 dBFS

= 10 MHz, Differential VIN=

f

IN

−0.5 dBFS

= 9.5 MHz and 10.5 MHz,

f

IN

each = −7 dBFS

MIN

Limits

(Note 10)

to T

: all

MAX

Units

(Limits)

82 dB

78 dB(min)

−75 dBFS

AC Electrical Characteristics

Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA=VD,VDR= +3.3V, PD

REF

= +1.0V, f

A=TJ

= 0V, V

other limits T

Symbol Parameter Conditions

1

f

CLK

f

CLK

Maximum Clock Frequency 70 62 MHz(min)

2

Minimum Clock Frequency 1 MHz

Recommended Clock Duty Cycle 50 40 %(min)

t

CH

t

CL

t

CONV

t

OD

t

AD

t

AJ

t

DIS

Clock High Time 6.5 ns(min)

Clock Low Time 6.5 ns(min)

Conversion Latency 6

Data Output Delay after Rising
CLK Edge

Aperture Delay 2 ns

Aperture Jitter 1.2 ps rms

Data outputs into TRI-STATE
Mode

t

EN

Data Outputs Active after
TRI-STATE

t

PD

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.

Note 2: All voltages are measured with respect to GND = AGND = DGND = 0V, unless otherwise specified.

Note 3: When the input voltage at any pin exceeds the power supplies (that is, V

25 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 25 mA to two.

Note 4: The absolute maximum junction temperature (T
junction-to-ambient thermal resistance (θ
LQFP, θ
this device under normal operation will typically be about 374 mW (354 typical power consumption + 20 mW TTL output loading). The values for maximum power
dissipation listed above will be reached only when the device is operated in a severe fault condition (e.g. when input or output pins are driven beyond the power
supply voltages, or the power supply polarity is reversed). Obviously, such conditions should always be avoided.

Note 5: Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through 0Ω.

Note 6: The 235˚C reflow temperature refers to infrared reflow. For Vapor Phase Reflow (VPR), the following Conditions apply: Maintain the temperature at the top

of the package body above 183˚C for a minimum 60 seconds. The temperature measured on the package body must not exceed 220˚C. Only one excursion above
183˚C is allowed per reflow cycle.

Note 7: The inputs are protected as shown below. Input voltages above V
However, errors in the A/D conversion can occur if the input goes above V
voltage must be ≤3.4V to ensure accurate conversions.

Power Down Mode Exit Cycle 20 t

is 79˚C/W, so PDMAX = 1,582 mW at 25˚C and 823 mW at the maximum operating ambient temperature of 85˚C. Note that the power consumption of

JA

= 62 MHz, tr=tf= 2 ns, CL= 20 pF/pin. Boldface limits apply for TA=TJ=T

CLK

= 25˚C (Notes 7, 8, 9, 12)

Typical

(Note 10)

= 2.5V 12 ns

V

DR

V

= 3.3V 9 13 ns(max)

DR

10 ns

10 ns

<

AGND, or V

IN

max) for this device is 150˚C. The maximum allowable power dissipation is dictated by TJmax, the

), and the ambient temperature, (TA), and can be calculated using the formula PDMAX=(TJmax - TA)/θJA. In the 32-pin

JA

J

or below GND will not damage this device, provided current is limited per (Note 3).

A

or below GND by more than 100 mV. As an example, if VAis 3.3V, the full-scale input

A

>

VA,VDor VDR), the current at that pin should be limited to

IN

to T

MIN

Limits

(Note 10)

60 %(max)

: all

MAX

Units

(Limits)

Clock

Cycles

CLK

ADC12L063

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