NSC ADC12L038CIWM, ADC12L034CIWM, ADC12L032CIWM, ADC12L030CIWM Datasheet
ADC12L030/ADC12L032/ADC12L034/ADC12L038
3.3V Self-Calibrating 12-Bit Plus Sign Serial I/O A/D
Converters with MUX and Sample/Hold
June 1999
ADC12L030/ADC12L032/ADC12L034/ADC12L038 3.3V Self-Calibrating 12-Bit Plus Sign Serial I/O
A/D Converters with MUX and Sample/Hold
General Description
The ADC12L030 family is 12-bit plus sign successive approximation A/D converters with serial I/O and configurable
input multiplexers. These devices are fully tested with a
single 3.3Vpowersupply. TheADC12L032,ADC12L034 and
ADC12L038 have 2, 4 and 8 channel multiplexers, respectively. Differential multiplexer outputs and A/D inputs are
available on the MUXOUT1, MUXOUT2, A/DIN1 and A/DIN2
pins. The ADC12L030 has a two channel multiplexer withthe
multiplexer outputs and A/D inputs internally connected. On
request, these A/Ds go through a self calibration process
that adjusts linearity, zero and full-scale errors to less than
1
±
⁄2LSB each.
The analog inputs can be configured to operate in various
combinations of single-ended, differential, or
pseudo-differential modes.A fully differential unipolar analog
input range (0V to +3.3V) can be accommodated with a
single +3.3V supply. In the differential modes, valid outputs
are obtained even when the negative inputs are greater than
the positive because of the 12-bit plus sign two’s compliment
output data format.
The serial I/O is configured to comply with NSC’s
MICROWIRE
references, see the LM4040 or LM4041 data sheets.
™
and Motorola’s SPI standards. For voltage
ADC12L038 Simplified Block Diagram
Features
n 0V to 3.3V analog input range with single 3.3V power
supply
n Serial I/O ( MICROWIRE and SPI Compatible)
n 2, 4, or 8 channel differential or single-ended multiplexer
n Analog input sample/hold function
n Power down mode
n Variable resolution and conversion rate
n Programmable acquisition time
n Variable digital output word length and format
n No zero or full scale adjustment required
n Fully tested and guaranteed with a 2.5V reference
n No Missing Codes over temperature
Key Specifications
n Resolution 12-bit plus sign
n 12-bit plus sign conversion time 8.8 µs (min)
n 12-bit plus sign sampling rate 73 kHz (max)
n Integral linearity error
n Single supply 3.3V
n Power dissipation 15 mW (max)
n Power down 40 µW (typ)
±
1 LSB (max)
±
10
Applications
n Portable Medical instruments
n Portable computing
n Portable Test equipment
%
DS011830-1
TRI-STATE®is a registered trademark of National Semiconductor Corporation.
™
COPS
microcontrollers, HPC™and MICROWIRE™are trademarks of National Semiconductor Corporation.
™
Microsoft
is a trademark of Microsoft Corporation.
© 1999 National Semiconductor Corporation DS011830 www.national.com
Ordering Information
Industrial Temperature Range NS Package
−40˚C ≤ T
≤ +85˚C Number
A
ADC12L030CIWM M16B
ADC12L032CIWM M20B
ADC12L034CIWM M24B
ADC12L038CIWM M28B
Connection Diagrams
16-Pin Wide Body
SO Packages
Top View
20-Pin Wide Body
SO Packages
24-Pin Wide Body
SO Packages
DS011830-2
DS011830-4
Top View
248-Pin Wide Body
SO Packages
DS011830-3
Top View
www.national.com 2
DS011830-5
Top View
Pin Descriptions
CCLK The clock applied to this input controls the su-
SCLK This is the serial data clock input. The clock
DI This is the serial data input pin. The data ap-
DO The data output pin. This pin is an active push/
EOC This pin is an active push/pull output and indi-
CS
cessive approximation conversion time interval
and the acquisition time. The rise and fall times
of the clock edges should not exceed 1 µs.
applied to this input controls the rate at which
the serial data exchange occurs. The rising
edge loads the information on the DI pin into
the multiplexer address and mode select shift
register. This address controls which channel
of the analog input multiplexer (MUX) is selected and the mode of operation for the A/D.
With CS low the falling edge of SCLK shifts the
data resulting from the previous ADC conversion out on DO, with the exception of the first
bit of data. When CS is low continuously, the
first bit of the data is clocked out on the rising
edge of EOC (end of conversion). When CS is
toggled the falling edge of CS always clocks
out the first bit of data. CS should be brought
low when SCLK is low. The rise and fall times
of the clock edges should not exceed 1 µs.
plied to this pin is shifted by the rising edge of
SCLK into the multiplexer address and mode
select register.
Tables 2, 3, 4, 5
show the assignment of the multiplexer address and the
mode select data.
pull output when CS is Low. When CS is High
this output is in TRI-STATE. The A/D conversion result(D0–D12) and converter status data
are clocked out by the falling edge of SCLK on
this pin. The word length and format of this result can vary (see
Table 1
). The word length
and format are controlled by the data shifted
into the multiplexer address and mode select
register (see
Table 5
).
cates the status of the ADC12L030/2/4/8.
When low, it signals that the A/D is busy with a
conversion, auto-calibration, auto-zero or
power down cycle. The rising edge of EOC signals the end of one of these cycles.
This is the chip select pin. When a logic low is
applied to this pin, the rising edge of SCLK
shifts the data on DI into the address register.
This low also brings DO out of TRI-STATE.
With CS low the falling edge of SCLK shifts the
data resulting from the previous ADC conversion out on DO, with the exception of the first
bit of data. When CS is low continuously, the
first bit of the data is clocked out on the rising
edge of EOC (end of conversion). When CS is
toggled the falling edge of CS always clocks
out the first bit of data. CS should be brought
low when SCLK is low. The falling edge of CS
resets a conversion in progress and starts the
sequence for a new conversion. When CS is
brought back low during a conversion, that
conversion is prematurely ended. The data in
the output latches may be corrupted. Therefore, when CS is brought back low during a
conversion in progress the data output at that
time should be ignored. CS may also be left
continuously low. In this case it is imperative
that the correct number of SCLK pulses be applied to the ADC in order to remain synchronous. After theADC supply power is applied, it
expects to see 13 clock pulses for each I/O sequence. The number of clock pulses the ADC
expects is the same as the digital output word
length. This word length can be modified by
the data shifted in on the DO pin.
Table 5
de-
tails the data required.
DOR
This is the data output ready pin. This pin is an
active push/pull output. It is low when the conversion result is being shifted out and goes
high to signal that all the data has been shifted
out.
CONV
A logic low is required on this pin to program
any mode or change the ADC’s configuration
as listed in the Mode Programming Table
(
Table 5
) such as 12-bit conversion, 8-bit conversion,Auto Cal, Auto Zero etc. When this pin
is high the ADC is placed in the read data only
mode. While in the read data only mode, bringing CS low and pulsing SCLK will only clock
out on DO any data stored in the ADCs output
shift register. The data on DI will be neglected.
A new conversion will not be started and the
ADC will remain in the mode and/or configuration previously programmed. Read data only
cannot be performed while a conversion,
Auto-Cal or Auto-Zero are in progress.
PD This is the power down pin. When PD is high
the A/D is powered down; when PD is low the
A/D is powered up. The A/D takes a maximum
of 700 µs to power up after the command is
given.
CH0–CH7 These are the analog inputs of the MUX. A
channel input is selected by the address information at the DI pin, which is loaded on the rising edge of SCLK into the address register
(see
Tables 2, 3, 4
).
The voltage applied to these inputs should not
exceed V
range on an unselected channel will corrupt
+ or go below GND. Exceeding this
A
the reading of a selected channel.
COM This pin is another analog input pin. It is used
as a pseudo ground when the analog multiplexer is single-ended.
MUXOUT1,
MUXOUT2
A/DIN1,
A/DIN2
These are the multiplexer output
pins.
These are the converter input pins. MUXOUT1
is usually tied to A/DIN1. MUXOUT2 is usually
tied toA/DIN2. If external circuitry is placed between MUXOUT1 and A/DIN1, or MUXOUT2
and A/DIN2 it may be necessary to protect
these pins. The voltage at these pins should
not exceed V
5
).
+ This is the positive analog voltage reference
V
REF
input. In order to maintain accuracy the voltage
range of V
+
or go belowAGND (see
A
=
REF(VREF
V
REF
+−V
REF
Figure
−) is
www.national.com3
Pin Descriptions (Continued)
1V
to 3.3 VDCand the voltage at V
DC
not exceed V
mended bypassing.
V
− The negative voltage reference input. In order
REF
to maintain accuracy the voltage at this pin
+. See
A
Figure 6
must not go below GND or exceed V
Figure 6
).
+, VD+ These are the analog and digital power supply
V
A
+
pins. V
A
on the chip. These pins should be tied to the
+
and V
are not connected together
D
same power supply and bypassed separately
(see
Figure 6
V
+ and VD+ is 3.0 VDCto 5.5 VDC.
A
). The operating voltage range of
DGND This is the digital ground pin (see
AGND This is the analog ground pin (see
REF
for recom-
A
Figure 6
Figure 6
+ can-
+. (See
).
).
www.national.com 4
Absolute Maximum Ratings (Notes 1, 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Positive Supply Voltage
+
=
+=VD+) 6.5V
V
(V
Voltage at Inputs and Outputs
Voltage at Analog Inputs
|V
Input Current at Any Pin (Note 3)
Package Input Current (Note 3)
Package Dissipation at
A
+
except CH0–CH7 and COM −0.3V to V
CH0–CH7 and COM GND −5V to V
+−VD+| 300 mV
A
=
25˚C (Note 4) 500 mW
T
A
+0.3V
+
±
30 mA
±
120 mA
+5V
Operating Ratings (Notes 1, 2)
Operating Temperature Range T
ADC12L030CIWM,
ADC12L032CIWM,
ADC12L034CIWM,
ADC12L038CIWM −40˚C ≤ T
Supply Voltage
+
=
+=VD+) +3.0V to +5.5V
V
(V
A
+−VD+| ≤ 100 mV
|V
A
+ 0VtoVA+
V
REF
− 0VtoV
V
REF
V
REF(VREF
V
REF
+−V
−) 1V to VA+
REF
Common Mode Voltage Range
ESD Susceptability (Note 5)
Human Body Model 1500V
Soldering Information
N Packages (10 seconds) 260˚C
SO Package (Note 6):
A/DIN1, A/DIN2, MUXOUT1
and MUXOUT2 Voltage Range 0V to V
A/D IN Common Mode Voltage Range
Vapor Phase (60 seconds) 215˚C
Infrared (15 seconds) 220˚C
Storage Temperature −65˚C to +150˚C
Converter Electrical Characteristics
The following specifications apply for V
sion mode, f
1.250V common-mode voltage, and 10(t
to T
T
MIN
Symbol Parameter Conditions Typical
=
f
CK
SK
; all other limits T
MAX
=
5 MHz, R
+
=
+=VD+=+3.3 VDC,V
V
A
=
25Ω, source impedance for V
S
) acquisition time unless otherwise specified. Boldface limits apply for T
CK
=
=
T
25˚C. (Notes 7, 8, 9)
A
J
+=+2.500 VDC,V
REF
+ and V
REF
REF
− ≤ 25Ω, fully-differential input with fixed
REF
(Note 10)
STATIC CONVERTER CHARACTERISTICS
Resolution with No Missing Codes 12 + sign Bits (min)
+ILE Positive Integral Linearity Error After Auto-Cal (Notes 12, 18)
−ILE Negative Integral Linearity Error After Auto-Cal (Notes 12, 18)
±
1/2
±
1/2
DNL Differential Non-Linearity After Auto-Cal
Positive Full-Scale Error After Auto-Cal (Notes 12, 18)
Negative Full-Scale Error After Auto-Cal (Notes 12, 18)
Offset Error After Auto-Cal (Notes 5, 18)
V
(+)=VIN(−)=1.250V
IN
DC Common Mode Error After Auto-Cal (Note 15)
TUE Total Unadjusted Error After Auto-Cal
±
1/2
±
1/2
±
1/2
±
2
±
1 LSB
(Notes 12, 13, 14)
Resolution with No Missing Codes 8-bit + sign mode 8 + sign Bits (min)
+INL Positive Integral Linearity Error 8-bit + sign mode (Note 12)
−INL Negative Integral Linearity Error 8-bit + sign mode (Note 12)
DNL Differential Non-Linearity 8-bit + sign mode
Positive Full-Scale Error 8-bit + sign mode (Note 12)
Negative Full-Scale Error 8-bit + sign mode (Note 12)
Offset Error 8-bit + sign mode,
after Auto-Zero (Note 13)
V
(+)=VIN(−)=+ 1.250V
IN
TUE Total Unadjusted Error 8-bit + sign mode
after Auto-Zero
(Notes 12, 13, 14)
≤ TA≤ T
MIN
≤ +85˚C
A
MAX
REF
−=0VDC, 12-bit + sign conver-
=
=
T
A
J
Limits Units
(Note 11)
±
1 LSB (max)
±
1 LSB (max)
±
1 LSB (max)
±
2 LSB (max)
±
2 LSB (max)
±
2 LSB (max)
±
3.5 LSB (max)
±
1/2 LSB (max)
±
1/2 LSB (max)
±
3/4 LSB (max)
±
1/2 LSB (max)
±
1/2 LSB (max)
±
1/2 LSB (max)
±
3/4 LSB (max)
(Limits)
+
+
A
www.national.com5
Converter Electrical Characteristics (Continued)
+
The following specifications apply for V
sion mode, f
1.250V common-mode voltage, and 10(t
to T
T
MIN
=
f
CK
SK
; all other limits T
MAX
=
5 MHz, R
A
Symbol Parameter Conditions Typical
STATIC CONVERTER CHARACTERISTICS
Multiplexer Channel to Channel
Matching
Power Supply Sensitivity V
+ Full-Scale Error
− Full-Scale Error
+ Integral Linearity Error
− Integral Linearity Error
Output Data from (Note 20) +10 LSB (max)
“12-Bit Conversion of Offset” −10 LSB (min)
(see
Table 5
)
Output Data from (Note 20) 4095 LSB (max)
“12-Bit Conversion of Full-Scale” 4093 LSB (min)
(see
Table 5
)
UNIPOLAR DYNAMIC CONVERTER CHARACTERISTICS
S/(N+D) Signal-to-Noise Plus f
Distortion Ratio f
−3 dB Full Power Bandwidth V
DIFFERENTIAL DYNAMIC CONVERTER CHARACTERISTICS
S/(N+D) Signal-to-Noise Plus f
Distortion Ratio f
−3 dB Full Power Bandwidth V
REFERENCE INPUT, ANALOG INPUTS AND MULTIPLEXER CHARACTERISTICS
C
REF
C
A/D
Reference Input Capacitance 85 pF
A/DIN1 and A/DIN2 Analog Input 75 pF
Capacitance
A/DIN1 and A/DIN2 Analog Input V
Leakage Current V
CH0–CH7 and COM Input Voltage GND − 0.05 V (min)
C
CH
C
MUXOUT
CH0–CH7 and COM Input
Capacitance
MUX Output Capacitance 20 pF
Off Channel Leakage (Note 16) On Channel=3.3V and −0.01 −0.3 µA (min)
CH0–CH7 and COM Pins Off Channel=0V
On Channel Leakage (Note 16) On Channel=3.3V and 0.01 0.3 µA (max)
CH0–CH7 and COM Pins Off Channel=0V
=
+=VD+=+3.3 VDC,V
V
A
=
25Ω, source impedance for V
S
) acquisition time unless otherwise specified. Boldface limits apply for T
CK
=
=
T
25˚C. (Notes 7, 8, 9)
J
+
=
Offset Error
=
IN
=
IN
=
f
IN
IN
drops 3 dB
=
IN
=
IN
=
f
IN
IN
drops 3 dB
IN
IN
On Channel=0V and 0.01 0.3 µA (max)
Off Channel=3.3V
On Channel=0V and −0.01 −0.3 µA (min)
Off Channel=3.3V
REF
REF
±
%
10
+3.3V
1 kHz, V
20 kHz, V
40 kHz, V
=
2.5 V
1 kHz, V
20 kHz, V
40 kHz, V
=
±
=
+3.3V or
=
0V
=
IN
=
IN
=
IN
, where S/(N+D)
PP
=
IN
=
IN
=
IN
2.5V, where S/(N+D)
+=+2.500 VDC,V
+ and V
− ≤ 25Ω, fully-differential input with fixed
REF
REF
(Note 10)
±
0.05 LSB
±
0.5
±
0.5
±
0.5
±
0.5 LSB
±
0.5 LSB
2.5 V
2.5 V
2.5 V
PP
PP
PP
69.4 dB
68.3 dB
65.7 dB
31 kHz
±
2.5V 77.0 dB
±
2.5V 73.9 dB
±
2.5V 67.0 dB
40 kHz
±
0.1
10 pF
−=0VDC, 12-bit + sign conver-
=
=
T
A
J
Limits Units
(Note 11)
±
1 LSB (max)
±
1.5 LSB (max)
±
1.5 LSB (max)
±
1.0 µA (max)
V
+ + 0.05 V (max)
A
(Limits)
www.national.com 6
Converter Electrical Characteristics (Continued)
+
The following specifications apply for V
sion mode, f
1.250V common-mode voltage, and 10(t
to T
T
MIN
=
f
CK
SK
; all other limits T
MAX
=
5 MHz, R
A
Symbol Parameter Conditions Typical
REFERENCE INPUT, ANALOG INPUTS AND MULTIPLEXER CHARACTERISTICS
MUXOUT1 and MUXOUT2 V
Leakage Current V
R
ON
MUX On Resistance V
R
Matching Channel to Channel V
ON
Channel to Channel Crosstalk V
MUX Bandwidth 90 kHz
=
+=VD+=+3.3 VDC,V
V
A
=
25Ω, source impedance for V
S
) acquisition time unless otherwise specified. Boldface limits apply for T
CK
=
=
T
25˚C. (Notes 7, 8, 9)
J
MUXOUT
MUXOUT
IN
V
MUXOUT
IN
V
MUXOUT
IN
+=+2.500 VDC,V
REF
REF
+ and V
REF
REF
− ≤ 25Ω, fully-differential input with fixed
(Note 10)
=
3.3V or 0.01 0.3 µA (max)
=
0V
=
1.65V and 1300 1900 Ω (max)
=
1.55V
=
1.65V and 5
=
1.55V
=
3.3 V
=
40 kHz −72 dB
PP,fIN
−=0VDC, 12-bit + sign conver-
=
=
T
A
J
Limits Units
(Note 11)
(Limits)
%
DC and Logic Electrical Characteristics
The following specifications apply for V
sion mode, f
1.250V common-mode voltage, and 10(tCK) acquisition time unless otherwise specified. Boldface limits apply for T
to T
T
MIN
=
f
CK
SK
; all other limits T
MAX
=
5 MHz, R
+
=
+=VD+=+3.3 VDC,V
V
A
=
25Ω, source impedance for V
S
=
=
T
25˚C. (Notes 7, 8, 9)
A
J
+=+2.500 VDC,V
REF
+ and V
REF
−=0VDC, 12-bit + sign conver-
REF
− ≤ 25Ω, fully-differential input with fixed
REF
=
=
T
A
J
Symbol Parameter Conditions Typical Limits Units
(Note 10) (Note 11) (Limits)
CCLK, CS, CONV, DI, PD AND SCLK INPUT CHARACTERISTICS
+
V
V
I
I
IN(1)
IN(0)
Logical “1” Input Voltage V
IN(1)
Logical “0” Input Voltage V
IN(0)
Logical “1” Input Current V
Logical “0” Input Current V
=
3.6V 2.0 V (min)
+
=
3.0V 0.8 V (max)
=
3.3V 0.005 1.0 µA (max)
IN
=
0V −0.005 −1.0 µA (min)
IN
DO, EOC AND DOR DIGITAL OUTPUT CHARACTERISTICS
V
V
I
+I
−I
OUT
Logical “1” Output Voltage V
OUT(1)
Logical “0” Output Voltage V
OUT(0)
TRI-STATE®Output Current V
Output Short Circuit Source Current V
SC
Output Short Circuit Sink Current V
SC
=
3.0V, I
+
=
V
3.0V, I
+
=
3.0V, I
=
OUT
=
V
OUT
=
OUT
=
OUT
=
−360 µA 2.4 V (min)
OUT
=
−10µA 2.9 V (min)
OUT
=
1.6 mA 0.4 V (max)
OUT
0V −0.1 −3.0 µA (max)
3.3V 0.1 3.0 µA (max)
0V 14 6.5 mA (min)
+168.0 mA (min)
V
D
+
POWER SUPPLY CHARACTERISTICS
I
+ Digital Supply Current Awake 1.1 1.5 mA (max)
D
I
+ Positive Analog Supply Current Awake 2.2 3.0 mA (max)
A
I
REF
Reference Input Current Awake 70 µA
CS=HIGH, Powered Down, CCLK on
CS=HIGH, Powered Down, CCLK off
CS=HIGH, Powered Down, CCLK on
CS=HIGH, Powered Down, CCLK off
CS=HIGH, Powered Down
600 µA
12 µA
10 µA
0.1 µA
0.1 µA
www.national.com7
AC Electrical Characteristics
The following specifications apply for V
sion mode, t
with fixed 1.250V common-mode voltage, and 10(t
=
T
J
=
=
t
3 ns, f
r
f
=
to T
T
MIN
CK
; all other limits T
MAX
+
=
=
5 MHz, R
=
A
A
=
25Ω, source impedance for V
S
) acquisition time unless otherwise specified. Boldface limits apply for T
CK
=
T
25˚C. (Note 17)
J
=
f
SK
+=VD+=+3.3 VDC,V
V
+=+2.500 VDC,V
REF
REF
+ and V
−=0VDC, 12-bit + sign conver-
REF
− ≤ 25Ω, fully-differential input
REF
Symbol Parameter Conditions Typical Limits Units
(Note 10) (Note 11) (Limits)
f
CK
Conversion Clock (CCLK) Frequency 10 5 MHz (max)
1 MHz (min)
f
SK
Serial Data Clock SCLK Frequency 10 5 MHz (max)
0 Hz (min)
Conversion Clock Duty Cycle 40
60
Serial Data Clock Duty Cycle 40
60
t
C
Conversion Time 12-Bit + Sign or 12-Bit 44(tCK) 44(tCK) (max)
%
%
%
%
(min)
(max)
(min)
(max)
8.8 µs (max)
8-Bit + Sign or 8-Bit 21(t
) 21(tCK) (max)
CK
4.2 µs (max)
t
A
Acquisition Time 6 Cycles Programmed 6(tCK) 6(tCK) (min)
(Note 19) 7(t
) (max)
CK
1.2 µs (min)
1.4 µs (max)
10 Cycles Programmed 10(t
) 10(tCK) (min)
CK
11(t
) (max)
CK
2.0 µs (min)
2.2 µs (max)
18 Cycles Programmed 18(t
) 18(tCK) (min)
CK
19(t
) (max)
CK
3.6 µs (min)
3.8 µs (max)
34 Cycles Programmed 34(t
) 34(tCK) (min)
CK
35(t
) (max)
CK
6.8 µs (min)
7.0 µs (max)
t
CAL
Self-Calibration Time 4944(tCK) 4944(tCK) (max)
988.8 µs (max)
t
AZ
Auto-Zero Time 76(tCK) 76(tCK) (max)
15.2 µs (max)
t
SYNC
Self-Calibration or Auto-Zero 2(tCK) 2(tCK) (min)
Synchronization Time 3(t
) (max)
CK
from DOR 0.40 µs (min)
0.60 µs (max)
t
DOR
DOR High Time when CS is Low
Continuously
for Read Data and Software Power
9(t
) 9(tSK) (max)
SK
1.8 µs (max)
Up/Down
t
CONV
CONV Valid Data Time 8(tSK) 8(tSK) (max)
1.6 µs (max)
t
HPU
Hardware Power-Up Time, Time from 250 700 µs (max)
PD Falling Edge to EOC Rising Edge
A
www.national.com 8
AC Electrical Characteristics (Continued)
+
The following specifications apply for V
sion mode, t
with fixed 1.250V common-mode voltage, and 10(t
=
T
J
=
=
t
r
f
=
to T
T
MIN
MAX
=
3 ns, f
CK
; all other limits T
Symbol Parameter Conditions Typical Limits Units
t
SPU
Software Power-Up Time, Time from
EOC Rising Edge
t
ACC
Access Time Delay from 25 60 ns (max)
CS Falling Edge to DO Data Valid
t
SET-UP
Set-Up Time of CS Falling Edge to 50 ns (min)
Serial Data Clock Rising Edge
t
DELAY
Delay from SCLK Falling 0 5 ns (min)
Edge to CS Falling Edge
t1H,t0HDelay from CS Rising Edge to R
DO TRI-STATE
t
HDI
DI Hold Time from Serial Data 5 15 ns (min)
Clock Rising Edge
t
SDI
DI Set-Up Time from Serial Data 5 10 ns (min)
Clock Rising Edge
t
HDO
DO Hold Time from Serial Data R
Clock Falling Edge 5 ns (min)
t
DDO
Delay from Serial Data Clock 50 90 ns (max)
Falling Edge to DO Data Valid
t
RDO
DO Rise Time, TRI-STATE to High R
DO Rise Time, Low to High 10 40 ns (max)
t
FDO
DO Fall Time, TRI-STATE to Low R
DO Fall Time, High to Low 15 40 ns (max)
t
CD
Delay from CS Falling Edge 50 80 ns (max)
to DOR Falling Edge
t
SD
Delay from Serial Data Clock Falling 45 80 ns (max)
Edge to DOR Rising Edge
C
IN
C
OUT
Note 1: Absolute Maximum Ratingsindicate limits beyond which damageto the device may occur.Operating Ratings indicate conditions for which the deviceis functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions.
Note 2: All voltages are measured with respect to GND, unless otherwise specified.
Note 3: When the input voltage (V
The 120 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 20 mA to four.
Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by T
allowable power dissipation at any temperature is P
T
Capacitance of Logic Inputs 10 pF
Capacitance of Logic Outputs 20 pF
) at any pin exceeds the power supplies (V
IN
max=150˚C. The typical thermal resistance (θJA) of these parts when board mounted follow:
J
f
SK
=
5 MHz, R
A
D
=
+=VD+=+3.3 VDC,V
V
A
=
25Ω, source impedance for V
S
) acquisition time unless otherwise specified. Boldface limits apply for T
=
T
25˚C. (Note 17)
J
CK
=
+=+2.500 VDC,V
REF
REF
+ and V
−=0VDC, 12-bit + sign conver-
REF
− ≤ 25Ω, fully-differential input
REF
(Note 10) (Note 11) (Limits)
500 700 µs (max)Serial Data Clock Falling Edge to
=
=
3k, C
L
=
L
=
L
=
L
=
max − TA)/θJAor the number given in the Absolute Maximum Ratings, whichever is lower. For this device,
(T
J
100 pF 70 100 ns (max)
L
=
3k, C
100 pF 35 65 ns (max)
L
=
3k, C
100 pF 10 40 ns (max)
L
=
3k, C
100 pF 15 40 ns (max)
L
IN
<
GND or V
>
VA+orVD+), the current at that pin should be limited to 20 mA.
IN
max, θJAand the ambient temperature, TA. The maximum
J
A
www.national.com9
AC Electrical Characteristics (Continued)
Thermal
Part Number Resistance
θ
ADC12L030CIWM 70˚C/W
ADC12L032CIWM 64˚C/W
ADC12L034CIWM 57˚C/W
ADC12L038CIWM 50˚C/W
Note 5: The human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin.
Note 6: SeeAN450 “Surface Mounting Methods and Their Effect on Product Reliability” or the section titled “Surface Mount” found in any post 1986 National Semi-
conductor Linear Data Book for other methods of soldering surface mount devices.
Note 7: Twoon-chip diodes are tied to each analog input through a series resistor as shown below. Input voltage magnitude up to 5V above V
will not damage this device. However, errors in theA/D conversion can occur (if these diodes are forward biased by more than 50 mV) if the input voltage magnitude
of selected or unselected analog input go above V
to ensure accurate conversions.
V
DC
Note 8: Toguarantee accuracy, it is required that the V
pin.
Note 9: With the test condition for V
Note 10: Typicals are at T
Note 11: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 12: Positive integral linearity error is defined as the deviation of the analog value, expressed in LSBs, from the straight line that passes through positive
full-scale and zero. For negative integral linearity error, the straight line passes through negative full-scale and zero (see
Note 13: Zero error is a measure of the deviation from the mid-scale voltage (a code of zero), expressed in LSB. It is the worst-case value of the code transitions
between 1 to 0 and 0 to +1 (see
Note 14: Total unadjusted error includes offset, full-scale, linearity and multiplexer errors.
Note 15: The DC common-mode error is measured in the differential multiplexer mode with the assigned positive and negative input channels shorted together.
Note 16: Channel leakage current is measured after the channel selection.
Note 17: Timing specifications are tested at the TTL logic levels, V
to 1.4V.
Note 18: TheADC12L030 family’s self-calibration technique ensures linearity and offseterrors as specified, but noise inherent in the self-calibration process will re-
sult in a maximum repeatability uncertainty of 0.2 LSB.
Note 19: If SCLK and CCLK are driven from the same clock source, then t
Note 20: The “12-Bit Conversion of Offset” and “12-Bit Conversion of Full-Scale” modes are intended to test the functionality of the device. Therefore, the output
data from these modes are not an indication of the accuracy of a conversion result.
REF(VREF
=
=
T
25˚C and represent most likely parametric norm.
J
A
Figure 4
+ or below GND by more than 50 mV. As an example, if VA+ is 3.0 VDC, full-scale input voltage must be ≤3.05
A
+ and VD+ be connected together to the same power supply with separate bypass capacitors at each V
A
+−V
−) given as +2.500V the 12-bit LSB is 610 µV and the 8-bit LSB is 9.8 mV.
REF
).
=
0.4V for a falling edge and V
IL
is 6, 10, 18 or 34 clock periods minimum and maximum.
A
JA
+ or 5V below GND
A
DS011830-6
Figure 2
and
Figure 3
).
=
2.4V for a rising edge. TRI-STATE output voltage is forced
IH
+
www.national.com 10
AC Electrical Characteristics (Continued)
FIGURE 1. Transfer Characteristic
DS011830-7
DS011830-8
FIGURE 2. Simplified Error Curve vs Output Code without Auto-Calibration or Auto-Zero Cycles
www.national.com11
Loading...