NSC ADC12D040EVAL, ADC12D040CIVS Datasheet
ADC12D040
Dual 12-Bit, 40 MSPS, 600 mW A/D Converter with
Internal/External Reference and Sample-and-Hold
December 2002
ADC12D040 Dual 12-Bit, 40 MSPS, 600 mW A/D Converter with Internal/External Reference and
Sample-and-Hold
General Description
The ADC12D040 is a dual, low power monolithic CMOS
analog-to-digital converter capable of converting analog input signals into 12-bit digital words at 40 Megasamples per
second (MSPS), minimum. This converter uses a differential,
pipelined architecture with digital error correction and an
on-chip sample-and-hold circuit to minimize die size and
power consumption while providing excellent dynamic performance. Operating on a single 5V power supply, the
ADC12D040 achieves 10.9 effective bits at 10 MHz input
and consumes just 600 mW at 40 MSPS, including the
reference current. The Power Down feature reduces power
consumption to 75 mW.
The differential inputs provide a full scale input swing equal
to V
of the differential input is recommended for optimum performance. For ease of use, the buffered, high impedance,
single-ended reference input is converted on-chip to a differential reference for use by the processing circuitry. The
digital outputs for the two ADCs are available on separate
12-bit buses with an output data format choice of offset
binary or 2’s complement.
For ease of interface, the digital output driver power pins of
the ADC12D040 can be connected to a separate supply
voltage in the range of 2.5V to the digital supply voltage,
making the outputs compatible with low voltage systems.
When not converting, power consumption can be reduced by
pulling the PD pin high, placing the converter into the powerdown state where it typically consumes just 75 mW. The
ADC12D040’s speed, resolution and single supply operation
make it well suited for a variety of applications.
This device is available in the 64-lead TQFP package and
will operate over the industrial temperature range of −40˚C to
+85˚C.
with the possibility of a single-ended input. Full use
REF
Features
n Binary/2’s comp output format
n Single supply operation
n Internal sample-and-hold
n Outputs 2.5V to 5V compatible
n TTL/CMOS compatible input/outputs
n Low power consumption
n Power down mode
n On-chip reference buffer
n Internal/External 2V reference
Key Specifications
n Resolution 12 Bits
n Conversion Rate 40 MSPS(min)
n DNL
n INL
n SNR (f
n ENOB (f
n THD (f
n SFDR (f
n Data Latency 6 Clock Cycles
n Supply Voltage +5V
n Power Consumption, Operating 600 mW(typ)
n Power Down 75 mW(typ)
n Crosstalk 80 dB(typ)
= 10MHz) 68 dB(typ)
IN
= 10MHz) 10.9 bits(typ)
IN
= 10 MHz) −78 dB (typ)
IN
= 10 MHz) 80 dB (typ)
IN
±
0.4 LSB(typ)
±
0.7 LSB(typ)
±
5%
Applications
n Ultrasound and Imaging
n Instrumentation
n Communications Receivers
n Sonar/Radar
n xDSL
n Cable Modems
n DSP Front Ends
© 2002 National Semiconductor Corporation DS200460 www.national.com
Connection Diagram
ADC12D040
20046001
Ordering Information
Industrial (−40˚C ≤ TA≤ +85˚C) Package
ADC12D040CIVS 64 Pin TQFP
ADC12D040CIVSX 64 Pin TQFP Tape and Reel
ADC12D040EVAL Evaluation Board
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Block Diagram
ADC12D040
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20046002
Pin Descriptions and Equivalent Circuits
Pin No. Symbol Equivalent Circuit Description
ANALOG I/O
ADC12D040
15
2
16
1
7V
11 INT/EXT REF
A+
V
IN
B+
V
IN
A−
V
IN
B−
V
IN
REF
Non-Inverting analog signal Inputs. With a 2.0V reference
voltage each input signal level is 2.0 V
Inverting analog signal Input. With a 2.0V reference voltage
the input signal level is from 2.0 V
pin may be connected to V
a differential input signal is required for best performance.
Reference input. This pin should be bypassed to AGND with
a 0.1 µF monolithic capacitor. V
should be between 1.0V to 2.4V.
V
select pin. With a logic low at this pin the internal 2.0V
REF
reference is selected. With a logic high on this pin an external
reference voltage should be applied to V
centered on VCM.
P-P
centered on VCM. This
P-P
for single-ended operation, but
CM
is 2.0V nominal and
REF
input pin 7.
REF
13
5
12
6
14
4
DIGITAL I/O
60 CLK
22
41
59 PD
21 OF
V
RP
V
RP
V
RN
V
RN
V
RM
V
RM
OEA
OEB
A
B
A
B
A
B
These pins are high impedance reference bypass pins only.
Connect a 0.1 µF capacitor from each of these pins to AGND.
DO NOT connect anything else to these pins.
Digital clock input. The range of frequencies for this input is
100 kHz to 50 MHz (typical) with guaranteed performance at
40 MHz. The input is sampled on the rising edge of this input.
OEA and OEB are the output enable pins that, when low,
enables their respective TRI-STATE data output pins. When
either of these pins is high, the corresponding outputs are in a
high impedance state.
PD is the Power Down input pin. When high, this input puts
the converter into the power down mode. When this pin is
low, the converter is in the active mode.
Output Format pin. A logic low on this pin causes output data
to be in straight binary. A logic high on this pin causes the
output data to be in 2’s complement format.
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Pin Descriptions and Equivalent Circuits (Continued)
Pin No. Symbol Equivalent Circuit Description
ADC12D040
24–29
34–39
DA0–DA11
Digital data output pins that make up the 12-bit conversion
results of their respective converters. DA0 and DB0 are the
LSBs, while DA11 and DB11 are the MSBs of the output
word. Output levels are TTL/CMOS compatible.
42–47
52–57
DB0–DB11
ANALOG POWER
Positive analog supply pins. These pins should be connected
9, 18, 19,
62, 63
V
A
to a quiet +5V source and bypassed to AGND with 0.1 µF
monolithic capacitors located within 1 cm of these power pins,
and with a 10 µF capacitor.
3, 8, 10,
17, 20, 61,
AGND The ground return for the analog supply.
64
DIGITAL POWER
Positive digital supply pin. This pin should be connected to
33, 48 V
D
the same quiet +5V source as is V
DGND with a 0.1 µF monolithic capacitor located within 1 cm
of the power pin and with a 10 µF capacitor.
32, 49 DGND The ground return for the digital supply.
Positive digital supply pins for the ADC12D040’s output
drivers. These pins should be connected to a voltage source
of +2.5V to +5V and bypassed to DR GND with a 0.1 µF
30, 51 V
DR
monolithic capacitor. If the supply for these pins are different
from the supply used for V
and VD, they should also be
A
bypassed with a 10 µF tantalum capacitor. V
exceed the voltage on V
. All bypass capacitors should be
D
located within 1 cm of the supply pin.
The ground return for the digital supply for the ADC12D040’s
23, 31, 40,
50, 58
DR GND
output drivers. These pins should be connected to the system
digital ground, but not be connected in close proximity to the
ADC12D040’s DGND or AGND pins. See Section 5 (Layout
and Grounding) for more details.
and be bypassed to
A
should never
DR
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Absolute Maximum Ratings (Notes 1,
2)
If Military/Aerospace specified devices are required,
ADC12D040
please contact the National Semiconductor Sales Office/
Machine Model (Note 5) 250V
Soldering Temperature,
Infrared, 10 sec. (Note 6) 235˚C
Storage Temperature −65˚C to +150˚C
Distributors for availability and specifications.
V
A,VD,VDR
V
DR
|V
| ≤ 100 mV
A–VD
Voltage on Any Input or Output Pin −0.3V to V
Input Current at Any Pin (Note 3)
Package Input Current (Note 3)
Package Dissipation at T
= 25˚C See (Note 4)
A
ESD Susceptibility
6.5V
VD+ 0.3V
or V
A
+0.3V
±
25 mA
±
50 mA
Operating Ratings (Notes 1, 2)
Operating Temperature −40˚C ≤ T
D
Output Driver Supply (V
V
Input 1.0V to 2.2V
REF
CLK, PD, OE
Analog Input Pins −0V to (V
|AGND–DGND| ≤100mV
Supply Voltage (V
) +4.75V to +5.25V
A,VD
) +2.35V to V
DR
−0.05V to VD+ 0.05V
Human Body Model (Note 5) 2500V
Converter Electrical Characteristics
Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA=VD= +5V, VDR=
+3.0V, PD = 0V, INT/EXT = V
its apply for TA=TJ=T
MIN
D,VREF
to T
= +2.0V, OEA, OEB = 0V, f
: all other limits TA=TJ= 25˚C (Notes 7, 8, 9)
MAX
Symbol Parameter Conditions
STATIC CONVERTER CHARACTERISTICS
Resolution with No Missing Codes 12 Bits(min)
INL Integral Non Linearity (Note 11)
DNL Differential Non Linearity
GE Gain Error
Offset Error (V
+=VIN−) −0.1
IN
Positive Error 0.51 +2.8/−1.9 %FS
Negative Error 0.68 +4/−2.7 %FS
Under Range Output Code 0 0
Over Range Output Code 4095 4095
DYNAMIC CONVERTER CHARACTERISTICS
FPBW Full Power Bandwidth 0 dBFS Input, Output at −3 dB 100 MHz
f
= 1 MHz, VIN= −0.5 dBFS 69 dB
SNR Signal-to-Noise Ratio
SINAD Signal-to-Noise and Distortion
ENOB Effective Number of Bits
THD Total Hamonic Distortion
H2 Second Harmonic
H3 Third Harmonic
SFDR Spurious Free Dynamic Range
IMD Intermodulation Distortion
IN
f
= 10 MHz, VIN= −0.5 dBFS 68 66.5 dB(min)
IN
f
= 1 MHz, VIN= −0.5 dBFS 69 dB
IN
f
= 10 MHz, VIN= −0.5 dBFS 68 65.6 dB(min)
IN
f
= 1 MHz, VIN= −0.5 dBFS 11.1 Bits
IN
f
= 10 MHz, VIN= −0.5 dBFS 10.9 10.6 Bits(min)
IN
f
= 1 MHz, VIN= −0.5 dBFS −80 dB
IN
f
= 10 MHz, VIN= −0.5 dBFS −78 −69 dB(max)
IN
f
= 1 MHz, VIN= −0.5 dBFS −84 dB
IN
f
= 10 MHz, VIN= −0.5 dBFS −80 −73 dB(max)
IN
f
= 1 MHz, VIN= −0.5 dBFS −84 dB
IN
f
= 10 MHz, VIN= −0.5 dBFS −82 −69.5 dB(max)
IN
f
= 1 MHz, VIN= −0.5 dBFS 84 dB
IN
f
= 10 MHz, VIN= −0.5 dBFS 80 69.5 dB(min)
IN
f
= 9.6 MHz and 10.2 MHz,
IN
each = −6.0 dBFS
INTER-CHANNEL CHARACTERISTICS
Channel —Channel Offset Match
= 40 MHz, tr=tf= 3 ns, CL= 20 pF/pin. Boldface lim-
CLK
Typical
(Note 10)
±
0.7
±
0.4
Limits
(Note 10)
±
2.0 LSB(max)
±
1.0 LSB(max)
±
1.2 %FS(max)
−80 dBFS
±
0.02 %FS
≤ +85˚C
A
− 0.5V)
A
Units
(Limits)
D
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Converter Electrical Characteristics (Continued)
Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA=VD= +5V, VDR=
+3.0V, PD = 0V, INT/EXT = V
its apply for TA=TJ=T
MIN
D,VREF
to T
= +2.0V, OEA, OEB = 0V, f
: all other limits TA=TJ= 25˚C (Notes 7, 8, 9)
MAX
Symbol Parameter Conditions
Channel — Channel Gain Error
Match
Crosstalk
10 MHz Tested Channel. 15 MHz
Other Channel
= 40 MHz, tr=tf= 3 ns, CL= 20 pF/pin. Boldface lim-
CLK
Typical
(Note 10)
±
0.05 %FS
Limits
(Note 10)
−80 dB
(Limits)
REFERENCE AND ANALOG INPUT CHARACTERISTICS
V
CM
C
IN
V
REF
R
REF
Common Mode Input Voltage VA/2 V
VINInput Capacitance (each pin to
GND)
VIN= 2.5 Vdc
+ 0.7 V
rms
(CLK LOW) 8 pF
(CLK HIGH) 7 pF
Input Reference Voltage (Note 13) 2.00 V
Reference Input Resistance 100 MΩ(min)
DC and Logic Electrical Characteristics
Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA=VD= +5V, VDR=
+3.0V, PD = 0V, INT/EXT = V
its apply for TA=TJ=T
MIN
D,VREF
to T
= +2.0V, OEA, OEB = 0V, f
: all other limits TA=TJ= 25˚C (Notes 7, 8, 9)
MAX
Symbol Parameter Conditions
CLK, PD, OE DIGITAL INPUT CHARACTERISTICS
V
V
I
I
C
IN(1)
IN(0)
IN(1)
IN(0)
IN
Logical “1” Input Voltage VD= 5.25V 2.0 V(min)
Logical “0” Input Voltage VD= 4.75V 1.0 V(max)
Logical “1” Input Current VIN= 5.0V 10 µA
Logical “0” Input Current VIN= 0V −10 µA
Digital Input Capacitance 5 pF
D0–D11 DIGITAL OUTPUT CHARACTERISTICS
V
V
I
OZ
+I
−I
C
OUT(1)
OUT(0)
SC
SC
OUT
Logical “1” Output Voltage I
Logical “0” Output Voltage I
TRI-STATE Output Current
Output Short Circuit Source
Current
Output Short Circuit Sink Current V
= −0.5 mA
OUT
= 1.6 mA, VDR=3V 0.4 V(max)
OUT
= 2.5V or 5V 100 nA
V
OUT
V
= 0V −100 nA
OUT
= 0V −20 mA(min)
V
OUT
OUT=VDR
Digital Output Capacitance 5 pF
POWER SUPPLY CHARACTERISTICS
I
A
I
D
I
DR
Analog Supply Current
Digital Supply Current
Digital Output Supply Current
Total Power Consumption
PSRR1 Power Supply Rejection
PD Pin = DGND, V
PD Pin = V
DR
PD Pin = DGND
PD Pin = V
DR
PD Pin = DGND, C
PD Pin = V
DR
PD Pin = DGND, C
PD Pin = V
DR
Rejection of Full-Scale Error with
= 4.75V vs 5.25V
V
A
= 40 MHz, tr=tf= 3 ns, CL= 20 pF/pin. Boldface lim-
CLK
Typical
(Note 10)
= 2.5V 2.3 V(min)
V
DR
V
=3V 2.7 V(min)
DR
Limits
(Note 10)
20 mA(min)
REF
= 2.0V
93
110 mA(max)
15
16
18 mA(max)
0
= 0 pF (Note 14)
L
10.5
12 mA(max)
0
= 0 pF (Note 15)
L
600
700 mW
75
56 dB
(Limits)
ADC12D040
Units
Units
mA
mA
mA
mW
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