NSC ADC12762CCV Datasheet
ADC12762
12-Bit, 1.4 MHz, 300 mW A/D Converter
with Input Multiplexer and Sample/Hold
ADC12762 12-Bit, 1.4 MHz, 300 mW A/D Converter with Input Multiplexer and Sample/Hold
June 1999
General Description
Using an innovative multistep conversion technique, the
12-bit ADC12762 CMOS analog-to-digital converter digitizes
signals at a 1.4 MHz sampling rate while consuming a maximum of only 300 mW on a single +5V supply. The
ADC12762 performs a 12-bit conversion in three
lower-resolution “flash” conversions, yielding a fast A/D without the cost and power dissipation associated with true flash
approaches.
The analog input voltage to the ADC12762 is tracked and
held by an internal sampling circuit, allowing high frequency
input signals to be accurately digitized without the need for
an external sample-and-hold circuit. The ADC12762 features
two sample-and-hold/flash comparator sections which allow
the converter to acquire one sample while converting the
previous. This pipelining technique increases conversion
speed without sacrificing performance. The multiplexer output is available to the user in order to perform additional external signal processing before the signal is digitized.
When the converter is not digitizing signals, it can be placed
in the Standby mode; typical power consumption in this
mode is 250 µW.
ADC12762 Block Diagram
Features
n Built-in sample-and-hold
n Single +5V supply
n Single channel or 2 channel multiplexer operation
Key Specifications
n Sampling rate 1.4 MHz (min)
n Conversion time 593 ns (typ)
n SNR, f
n Power dissipation (f
n No missing codes over temperature Guaranteed
=
100 kHz 67.5 dB (min)
IN
=
1.4 MHz) 300 mW (max)
s
Applications
n CCD image scanners
n Digital signal processor front ends
n Instrumentation
n Disk drives
n Mobile telecommunications
n Waveform digitizers
DS012811-1
Ordering Information
Commercial (0˚C ≤ TA≤ +70˚C) Package
ADC12762CCV V44 Plastic Leaded Chip Carrier
ADC12062EVAL Evaluation Board
TRI-STATE®is a registered trademark of National Semiconductor Corporation.
© 1999 National Semiconductor Corporation DS012811 www.national.com
Absolute Maximum Ratings (Notes 1, 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
=
Supply Voltage (V
CC
Voltage at Any Input or Output −0.3V to V
Input Current at Any Pin (Note 3) 25 mA
Package Input Current (Note 3) 50 mA
Power Dissipation (Note 4)
ADC12762CCV 875 mW
ESD Susceptibility (Note 5) 2000V
DV
=
) −0.3V to +6V
AV
CC
CC
CC
+ 0.3V
Soldering Information (Note 6)
V Package, Infrared, 15 seconds +300˚C
Storage Temperature Range −65˚C to +150˚C
Maximum Junction Temperature (T
) 150˚C
JMAX
Operating Ratings (Notes 1, 2)
Temperature Range T
ADC12762CCV −0˚C ≤ TA≤ +70˚C
=
) 4.75V to 5.25V
Supply Voltage Range (DV
AV
CC
CC
MIN
≤ TA≤ T
MAX
Converter Characteristics
=
The following specifications apply for DV
1.4 MHz, unless otherwise specified. Boldface limits apply for T
CC
AV
=
+5V, V
CC
REF+(SENSE)
=
+4.096V, V
=
from T
T
A
J
MIN
REF−(SENSE)
to T
MAX
=
AGND, and f
; all other limits T
=
s
=
=
T
+25˚C.
A
J
Symbol Parameter Conditions Typ Limit Units
(Note 7) (Note 8) (Limit)
Resolution 12 Bits
Differential Linearity Error T
Integral Linearity Error T
MIN
MIN
to T
to T
MAX
MAX
±
0.4
±
0.4
±
0.95 LSB (max)
±
2.0 LSB (max)
(Note 9)
R
V
V
V
C
C
REF
REF(+)
REF(−)
IN
ADC
MUX
Offset Error T
Full-Scale Error T
Power Supply Sensitivity
(Note 15)
DV
MIN
MIN
to T
MAX
to T
MAX
=
=
±
%
5V
5
AV
CC
CC
±
0.3
±
0.3
Reference Resistance 940
V
REF+(SENSE)
V
REF−(SENSE)
Input Voltage Range To V
ADC IN Input Leakage AGND to AV
Input Voltage AV
Input Voltage AGND V (min)
, or ADC IN
IN1,VIN2
− 0.3V 0.1 3 µA (max)
CC
ADC IN Input Capacitance 25 pF
MUX On-Channel Leakage AGND to AV
MUX Off-Channel Leakage AGND to AV
− 0.3V 0.1 3 µA (max)
CC
− 0.3V 0.1 3 µA (max)
CC
Multiplexer Input Cap 7 pF
MUX Off Isolation f
=
100 kHz 92 dB
IN
±
4.0 LSB (max)
±
4.0 LSB (max)
±
0.75 LSB (max)
500 Ω (min)
1300 Ω (max)
CC
AV
+0.05V V (max)
CC
V (max)
AGND − 0.05V V (min)
Dynamic Characteristics (Note 10)
=
The following specifications apply for DV
100 kHz, 0 dB from fullscale, and f
; all other limits T
T
MAX
=
A
=
s
=
T
+25˚C.
J
CC
1.4 MHz, unless otherwise specified. Boldface limits apply for T
AV
=
+5V, V
CC
REF+(SENSE)
Symbol Parameter Conditions Typ Limit Units
SINAD
SNR
THD
ENOB
Signal-to-Noise Plus
Distortion Ratio
Signal-to-Noise Ratio
(Note 11)
Total Harmonic Distortion
(Note 12)
Effective Number of Bits
(Note 13)
IMD Intermodulation Distortion f
to T
T
MIN
MAX
to T
T
MIN
MAX
to T
T
MIN
MAX
to t
T
MIN
MAX
=
88.7 kHz, 89.5 kHz −80 dBc
IN
=
+4.096V, V
REF−(SENSE)
=
AGND, R
=
25Ω,f
S
=
from T
T
A
J
MIN
(Note 7) (Note 8) (Limit)
70 67.0 dB (min)
70 67.5 dB (min)
−80 −70 dBc (max)
11.3 10.8 Bits (min)
=
IN
to
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DC Electrical Characteristics
=
The following specifications apply for DV
1.4 MHz, unless otherwise specified. Boldface limits apply for T
CC
AV
=
+5V, V
CC
REF+(SENSE)
Symbol Parameter Conditions Typ Limit Units
V
IN(1)
V
IN(0)
I
IN(1)
I
IN(0)
V
OUT(1)
V
OUT(0)
I
OUT
C
OUT
C
IN
DI
CC
AI
CC
I
STANDBY
Logical “1” Input Voltage DV
Logical “0” Input Voltage DV
Logical “1” Input Current 0.1 1.0 µA (max)
Logical “0” Input Current 0.1 1.0 µA (max)
Logical “1” Output Voltage
Logical “0” Output Voltage
TRI-STATE®Output
Leakage Current
TRI-STATE Output Capacitance Pins DB0–DB11 5 pF
Digital Input Capacitance 4 pF
DVCCSupply Current 2 10 mA (max)
AVCCSupply Current 32 50 mA (max)
Standby Current (DICC+AICC)PD
=
AV
CC
=
AV
CC
=
AV
DV
CC
=
I
−360 µA 2.4 V (min)
OUT
=
I
−100 µA 4.25 V (min)
OUT
=
DV
AV
CC
=
1.6 mA
I
OUT
Pins DB0–DB11 0.1 3 µA (max)
=
0V 50 µA
=
+4.096V, V
=
from T
T
A
J
MIN
REF−(SENSE)
to T
MAX
=
; all other limits T
AGND, and f
=
A
(Note 7) (Note 8) (Limit)
=
+5.5V 2.0 V (min)
CC
=
+4.5V 0.8 V (max)
CC
=
+4.5V,
CC
=
+4.5V,
CC
0.4 V (max)
=
s
=
T
J
+25˚C.
AC Electrical Characteristics
=
The following specifications apply for DV
1.4 MHz, unless otherwise specified. Boldface limits apply for T
CC
AV
=
+5V, V
CC
REF+(SENSE)
Symbol Parameter Conditions Typ Limit Units
f
s
t
CONV
t
AD
t
S/H
t
EOC
t
ACC
t1H,t
t
INTH
t
INTL
t
UPDATE
t
MS
t
MH
t
CSS
Maximum Sampling Rate
(1/t
THROUGHPUT
)
Conversion Time
(S/H Low to EOC High)
Aperture Delay
(S/H Low to Input Voltage Held)
S/H Pulse Width 10
S/H Low to EOC Low 90
Access Time
(RD Low or OE High to Data Valid)
TRI-STATE Control
0H
(RD High or OE Low to Databus TRI-STATE)
C
R
Delay from RD Low to INT High C
Delay from EOC High to INT Low C
EOC High to New Data Valid 5 15 ns (max)
Multiplexer Address Setup Time
(MUX Address Valid to EOC Low)
Multiplexer Address Hold Time
(EOC Low to MUX Address Invalid)
CS Setup Time
(CS Low to RD Low, S/H Low, or OE High)
=
+4.096V, V
=
from T
T
A
J
MIN
REF−(SENSE)
to T
MAX
=
; all other limits T
AGND, and f
s
=
T
A
J
(Note 7) (Note 8) (Limits)
1.5 MHz (min)
593
560 ns (min)
710 ns (max)
20 ns
5 ns (min)
400 ns (max)
60 ns (min)
126 ns (max)
=
100 pF 10 20 ns (max)
L
=
=
1k, C
L
=
L
=
L
10 pF 25 40 ns (max)
L
100 pF 35 60 ns (max)
100 pF −25
−35 ns (min)
−10 ns (max)
50 ns (min)
50 ns (min)
20 ns (min)
=
=
+25˚C.
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AC Electrical Characteristics (Continued)
=
The following specifications apply for DV
1.4 MHz, unless otherwise specified. Boldface limits apply for T
CC
AV
=
+5V, V
CC
REF+(SENSE)
Symbol Parameter Conditions Typ Limit Units
t
CSH
t
WU
Note 1: Absolute Maximum Ratingsindicatelimitsbeyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional. These ratings do not guarantee specific performance limits, however.For guaranteed specifications and test conditions, see the Electrical Characteristics. The
guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed
test conditions.
Note 2: All voltages are measured with respect to GND (GND=AGND=DGND), unless otherwise specified.
Note 3: When the input voltage (V
to 25 mA or less. The 50 mA package input current limits the number of pins that can safely exceed the power supplies with an input current of 25 mA to two.
Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by T
allowable power dissipation at any temperature is P
(PLCC) package is 55˚C/W. In most cases the maximum derated power dissipation will be reached only during fault conditions.
Note 5: Human body model, 100 pF discharged through a 1.5 kΩ resistor. Machine model ESD rating is 200V.
Note 6: See AN-450 “Surface Mounting Methods and Their Effect on Product Reliability” or the section titled “Surface Mount” found in a current National Semicon-
ductor Linear Data Book for other methods of soldering surface mount devices.
Note 7: Typicals are at +25˚C and represent most likely parametric norm.
Note 8: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 9: Integral Linearity Error is the maximum deviation from a straight line between the measured offset and full scale endpoints.
Note 10: Dynamic testing of theADC12762 is done using the ADC IN input. The input multiplexer adds harmonic distortion at high frequencies. See the graph in the
Typical Performance Characteristics section for a typical graph of THD performance vs input frequency with and without the input multiplexer.
Note 11: The signal-to-noise ratio is the ratio of the signal amplitude to the background noise level. Harmonics of the input signal are not included in its calculation.
Note 12: The contributions from the first nine harmonics are used in the calculation of the THD.
Note 13: Effective Number of Bits (ENOB) is calculated from the measured signal-to-noise plus distortion ratio (SINAD) using the equation ENOB=(SINAD − 1.76)/
6.02.
Note 14: The digital power supply current takes up to 10 seconds to decay to its final value after PD is pulled low. This prohibits production testing of the standby
current. Some parts may exhibit significantly higher standby currents than the 50 µA typical.
Note 15: Power Supply Sensitivity is defined as the change in the Offset Error or the Full Scale Error due to a change in the supply voltage.
CS Hold Time
(CS High after RD High, S/H High, or OE Low)
Wake-Up Time
(PD High to First S/H Low)
) at any pin exceeds the power supply rails (V
IN
=
(T
D
)/θJAor the number given in the Absolute Maximum Ratings, whichever is lower. θJAfor the V
JMAX−TA
IN
=
A
<
GND or V
T
J
=
+4.096V, V
from T
MIN
REF−(SENSE)
to T
MAX
=
; all other limits T
AGND, and f
(Note 7) (Note 8) (Limits)
20 ns (min)
1µs
>
VCC) the absolute value of current at that pin should be limited
IN
, θJAand the ambient temperature TA. The maximum
JMAX
=
s
=
=
T
+25˚C.
A
J
TRI-STATE Test Circuit and Waveforms
DS012811-2
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DS012811-3
TRI-STATE Test Circuit and Waveforms (Continued)
DS012811-4
Typical Performance Characteristics
DS012811-5
Offset and Fullscale
Error Change vs
Reference Voltage
Digital Supply Current
vs Temperature
DS012811-6
DS012811-9
Linearity Error Change
vs Reference Voltage
Analog Supply Current
vs Temperature
DS012811-7
DS012811-10
Mux ON Resistance
vs Input Voltage
DS012811-8
Current Consumption in
Standby Mode vs Voltage
on Digital Input Pins
DS012811-11
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Typical Performance Characteristics (Continued)
Conversion Time (t
vs Temperature
CONV
)
SINAD vs Input Frequency
(ADC In)
SINAD vs Input Frequency
(Through Mux)
DS012811-12
DS012811-15
EOC Delay Time (t
vs Temperature
EOC
)
SNR vs Input Frequency
(ADC In)
SNR vs Input Frequency
(Through Mux)
DS012811-13
DS012811-16
Spectral Response
DS012811-14
THD vs Input Frequency
(ADC In)
DS012811-17
THD vs Input Frequency
(Through Mux)
DS012811-18
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DS012811-19
DS012811-20
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