NSC ADC1251CIJ Datasheet

ADC1251 Self-Calibrating 12-Bit Plus Sign
A/D Converter with Sample-and-Hold

Y

General Description

The ADC1251 is a CMOS 12-bit plus sign successive ap­proximation analog-to-digital converter. On request, the
ADC1251 goes through a self-calibration cycle that adjusts
for any zero, full scale, or linearity errors. The ADC1251 also
has the ability to go through an Auto-Zero cycle that cor­rects the zero error during every conversion.

The analog input to the ADC1251 is tracked and held by the
internal circuitry, so an external sample-and-hold is not re­quired. The ADC1251 has an S
ly controls the track-and-hold state of the A/D. A unipolar
analog input voltage range (0 to

b

(

5V toa5V) can be accommodated withg5V supplies.

/H control input which direct-

a

5V) or a bipolar range

The 13-bit data result is available on the eight outputs of the
ADC1251 in two bytes, high-byte first and sign extended.
The digital inputs and outputs are compatible with TTL or
CMOS logic levels.

Features

Y

Self-calibration provides excellent temperature stability

Y

Internal sample-and-hold

8-bit mP/DSP interface

Y

Bipolar input range with a singlea5V reference

Y

No missing codes over temperature

Y

TTL/MOS input/output compatible

Key Specifications

Y

Resolution 12 bits plus sign

Y

Conversion Time 8 ms (max)

Y

Sampling Rate 83 kHz (max)

Y

Linearity Error

Y

Zero Error

Y

Full Scale Error

Y

Power Consumption

Applications

Y

Digital signal processing

Y

High resolution process control

Y

Instrumentation

December 1994

g

0.6 LSB (g0.0146%) (max)

@

g

5V 113 mW (max)

g

1 LSB (max)

g

1.5 LSB (max)

ADC1251 Self-Calibrating 12-Bit Plus Sign A/D Converter with Sample-and-Hold

Simplified Block Diagram

Connection Diagram

Dual-In-Line Package

Top View

TL/H/11024– 2

Ordering Information

Industrial

b

(

40§CsT

s

a

A

ADC1251BIJ,

ADC1251CIJ

TL/H/11024– 1

b

(

55§CsT

Military

s

A

a

ADC1251CMJ, J24A

ADC1251CMJ/883

TRI-STATEÉis a registered trademark of National Semiconductor Corporation.

C

1995 National Semiconductor Corporation RRD-B30M115/Printed in U. S. A.

TL/H/11024

85§C)

125§C)

Package

J24A

Package

Absolute Maximum Ratings (Notes1&2)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.

Supply Voltage (V

Negative Supply Voltage (Vb)

Voltage at Logic Control Inputs

Voltage at Analog Inputs

(V

REF,VIN

AVCC-DVCC(Note 7) 0.3V

Input Current at Any Pin (Note 3)

Package Input Current (Note 3)

Power Dissipation at 25

Storage Temperature Range

ESD Susceptability (Note 5) 2000V

Soldering Information

J Package (10 sec.) 300

e

e

DV

CC

)(V

AVCC) 6.5V

CC

b

0.3V to (V

b

b

0.3V) to (V

C (Note 4) 875 mW

§

CC

CC

g

b

65§Ctoa150§C

b

a

0.3V)

a

0.3V)

g

5mA

20 mA

6.5V

§

Operating Ratings (Notes1&2)

Temperature Range T

ADC1251BIJ, ADC1251CIJ
ADC1251CMJ
ADC1251CMJ/883

DVCCand AVCCVoltage

(Notes6&7) 4.5V to 5.5V

Negative Supply Voltage (V

Reference Voltage

(V

, Notes6&7) 3.5V to AV

REF

C

s

s

T

MIN

b

40§CsT

b

55§CsT

b

55§CsT

b

)

b

T

A

MAX

s

a

85§C

A

s

a

125§C

A

s

a

125§C

A

4.5V tob5.5V

a

50 mV

CC

Converter Electrical Characteristics

The following specifications apply for V

3.5 MHz and tested using WR control unless otherwise specified. Boldface limits apply for T

e

limits T

e

T

A

25§C. (Notes 6, 7 and 8)

J

CC

e

DV

CC

e

AV

CC

ea

5.0V, V

b

eb

5.0V, V

Symbol Parameter Conditions

STATIC CHARACTERISTICS

Positive Integral ADC1251BIJ After Auto-Cal
Linearity Error

ADC1251CIJ

(Notes 11 & 12)

ADC1251CMJ

Negative Integral ADC1251BIJ After Auto-Cal
Linearity Error

ADC1251CIJ

(Notes 11 and 12)

ADC1251CMJ

Missing Codes After Auto-Cal (Notes 11 and 12) 0

Zero Error (Notes 12 and 13) AZe‘‘0’’ and f

CLK

e

1.75 MHz

After Auto-Cal Only

Positive Full-Scale Error (Note 12) AZe‘‘0’’ and f

CLK

e

1.75 MHz

After Auto-Cal Only

Negative Full-Scale Error (Note 12) AZe‘‘0’’ and f

CLK

e

1.75 MHz

After Auto-Cal Only

C

REFVREF

C

IN

V

IN

Input Capacitance (Note 18) 80 pF

Analog Input Capacitance 65 pF

Analog Input Voltage V

e

Power Supply Sensitivity Zero Error (Note 14) AV

Full-Scale Error

V

CC

REF

e

4.75V, V

DV

CC

e

5Vg5%,

b

eb

5Vg5%

Linearity Error

ea

e

T

A

J

5.0V, AZe‘‘1’’, f

e

T

to T

MIN

MAX

CLK

; all other

REF

Typical Limit Units
(Note 9) (Notes 10, 19) (Limit)

g

0.6 LSB(max)

g

1 LSB(max)

g

1 LSB(max)

g

0.6 LSB(max)

g

1 LSB(max)

g

1 LSB(max)

g

2 LSB(max)

g

2.0/g3.0 LSB(max)

g

1.5 LSB(max)

g

1.5/g2.0 LSB(max)

g

1.5 LSB(max)

g

1.5/g2.0 LSB(max)

b

b

0.05 V(min)

a

V

0.05 V(max)

CC

g

(/8 LSB

g

(/8 LSB

g

(/8 LSB

e

2

Converter Electrical Characteristics (Continued)

The following specifications apply for V

e

3.5 MHz unless otherwise specified. Boldface limits apply for T

CC

e

DV

CC

e

ea

AV

CC

(Notes 6, 7 and 8)

5.0V, V

e

A

b

T

J

Symbol Parameter Conditions

DYNAMIC CHARACTERISTICS

S/(NaD) Unipolar Signal-to-NoiseaDistortion f

Ratio (Note 17)

S/(NaD) Bipolar Signal-to-NoiseaDistortion f

Ratio (Note 17)

b

3 dB Unipolar Full Power Bandwidth V

b

3 dB Bipolar Full Power Bandwidth V

t

Ap

Aperture Time 100 ns

e

1 kHz, V

IN

e

f

IN

e

IN

e

f

IN

e

IN

e

IN

IN

20 kHz, V

1 kHz, V

IN

20 kHz, V

4.85V, (Note 17) 32 kHz

g

4.85V, (Note 17) 25 kHz

Aperture Jitter 100 ps

e

eb

T

MIN

5.0V, V

to T

ea

REF

; all other limits T

MAX

5.0V, AZe‘‘1’’ and f

A

Typical Limit Units

(Note 9) (Notes 10, 19) (Limit)

e

4.85 V

e

4.85 V

IN

e

g

4.85V 76 dB

e

g

4.85V 76 dB

IN

72 dB

p-p

72 dB

p-p

e

CLK

e

T

25§C.

J

rms

Digital and DC Electrical Characteristics

The following specifications apply for DV
otherwise specified. Boldface limits apply for T

CC

e

ea

AV

A

CC

5.0V, V

e

e

T

T

J

MIN

Symbol Parameter Conditions

V

IN(1)

V

IN(0)

I

IN(1)

I

IN(0)

a

V

T

b

V

T

V

H

V

OUT(1)

V

OUT(0)

I

OUT

I

SOURCE

I

SINK

DI

CC

AI

CC

b

I

Logical ‘‘1’’ Input Voltage for V
All Inputs except CLK IN

Logical ‘‘0’’ Input Voltage for V
All Inputs except CLK IN

Logical ‘‘1’’ Input Current V

Logical ‘‘0’’ Input Current V

CLK IN Positive-Going
Threshold Voltage

CLK IN Negative-Going
Threshold Voltage

CLK IN Hysteresis

[

V

a

(min)bV

T

b

]

(max)

T

Logical ‘‘1’’ Output Voltage V

Logical ‘‘0’’ Output Voltage V

TRI-STATEÉOutput Leakage V
Current

Output Source Current V

Output Sink Current V

DVCCSupply Current CSe‘‘1’’ 1 2.5 mA(max)

AVCCSupply Current CSe‘‘1’’ 4 10 mA(max)

VbSupply Current CS

e

5.25V

CC

e

4.75V

CC

e

5V 0.005 1 mA(max)

IN

e

0V

IN

e

4.75V:

CC

eb

I

OUT

I

OUT

I

OUT

V

360 mA 2.4 V(min)

eb

10 mA 4.5 V(min)

e

4.75V,

CC

e

1.6 mA

e

0V

OUT

e

5V 0.01 3 mA(max)

OUT

e

0V

OUT

e

5V 20 8.0 mA(min)

OUT

e

‘‘1’’ 2.8 10 mA(max)

b

to T

eb

MAX

REF

ea

5.0V, V
; all other limits T

5.0V, and f

e

T

A

e

3.5 MHz unless

CLK

e

25§C. (Notes 6 and 7)

J

Typical Limit Units

(Note 9) (Notes 10, 19) (Limit)

2.0 V(min)

0.8 V(max)

b

0.005

b

1 mA(max)

2.8 2.7 V(min)

2.1 2.3 V(max)

0.7 0.4 V(min)

0.4 V(max)

b

0.01

b

20

b

3 mA(max)

b

6.0 mA(min)

3

AC Electrical Characteristics

The following specifications apply for DV

Boldface limits apply for T

e

T

A

J

e

CC

e

T

MIN

to T

AV

CC

MAX

ea

; all other limits T

Symbol Parameter Conditions

f

Clock Frequency MHz

CLK

5.0V, V

b

eb

e

A

e

5.0V, t
T

t

r

f

e

25§C. (Notes 6 and 7)

J

e

20 ns unless otherwise specified.

Typical Limit Units

(Note 9) (Notes 10, 19) (Limit)

0.5 MHz(min)

6.0 3.5 MHz(max)

Clock Duty Cycle 50 %

40 %(min)
60 %(max)

t

t

t

t

t

t

t

t

t

t

t0H,t1HTRI-STATE Control R

t

t

Conversion Time Using WR 27(1/f

C

to Start a Conversion

Conversion Time Using S/H AZe‘‘1’’ 34(1/f

C

to Start a Conversion

Acquisition Time (Note 15) R

A

Internal Acquisition Time

IA

(When Using WR

Auto Zero TimeaAcquisition Time 33(1/f

ZA

Delay from Hold Command Using WR Control 200 350 ns(max)

D(EOC)L

to Falling Edge of EOC

Calibration Time 1399(1/f

CAL

Calibration Pulse Width (Note 16) 60 200 ns(min)

W(CAL)L

Minimum WR Pulse Width 60 200 ns(min)

W(WR)L

Maximum Access Time C

ACC

(Delay from Falling Edge of 50 95 ns(max)
RD

to Output Data Valid)

Control Only)

(Delay from Rising Edge of 30 70 ns(max)
RD

to Hi-Z State)

Maximum Delay from Falling Edge

PD(INT)

of RD

or WR to Reset of INT

Delay between Successive RD Pulses 30 60 ns(min)

RR

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.

Note 2: All voltages are measured with respect to AGND and DGND, unless otherwise specified.

Note 3: When the input voltage (V

5 mA. The 20 mA maximum package input current rating allows the voltage at any four pins, with an input current limit of 5 mA, to simultaneously exceed the power
supply voltages.

Note 4: The power dissipation of this device under normal operation should never exceed 191 mW (Quiescent Power Dissipation
output). Caution should be taken not to exceed absolute maximum power rating when the device is operating in severe fault condition (ex. when any inputs or
outputs exceed the power supply). The maximum power dissipation must be derated at elevated temperatures and is dictated by T
temperature), i
is P

Dmax

resistance (i

Note 5: Human body model, 100 pF discharged through a 1.5 kX resistor.

(package junction to ambient thermal resistance), and TA(ambient temperature). The maximum allowable power dissipation at any temperature

JA

e

b

(T

TA)/iJAor the number given in the Absolute Maximum Ratings, whichever is lower. For this device, T

Jmax

) of the ADC1251 with CMJ, BIJ, and CIJ suffixes when board mounted is 51§C/W.

JA

) at any pin exceeds the power supply rails (V

IN

e

3.5 MHz, AZe‘‘1’’ 7.7 7.95 ms(max)

f

CLK

e

f

1.75 MHz, AZe‘‘0’’ 15.4 15.65 ms(max)

CLK

e

f

3.5 MHz, AZe‘‘1’’ 9.7 9.95 ms(max)

CLK

e

SOURCE

f

CLK

50X 3.5 3.5 ms(min)

e

1.75 MHz 18.8 19.05 m s(max)

Using S/H Control 100 150 ns(max)

e

f

3.5 MHz 399 400 ms(max)

CLK

e

100 pF

L

e

L

1kX,C

e

100 pF

L

k

IN

Vbor V

l

IN

7(1/f

CLK

CLK

CLK

CLK

) 27(1/f

) 34(1/f

) 7(1/f

) 33(1/f

) 1399 (1/f

CLK

)a250 ns (max)

CLK

)a250 ns (max)

CLK

) (max)

CLK

)a250 ns (max)

CLK

) (max)

CLK

100 175 ns(max)

(AVCCor DVCC), the current at that pin should be limited to

a

1 TTL Load on each digital

(maximum junction

Jmax

e

150§C, and the typical thermal

Jmax

4

Electrical Characteristics (Continued)

Note 6: Two on-chip diodes are tied to the analog input as shown below. Errors in the A/D conversion can occur if these diodes are forward biased more than

50 mV. This means that if AV

and DVCCare minimum (4.75 VDC) and Vbis maximum (b4.75 VDC), the analog input full-scale voltage must be

CC

s

g

4.8 VDC.

Note 7: A diode exists between AVCCand DVCCas shown below.

To guarantee accuracy, it is required that the AVCCand DVCCbe connected together to a power supply with separate bypass filters at each VCCpin.

Note 8: Accuracy is guaranteed at f
curves.

Note 9: Typicals are at T

Note 10: Limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).

Note 11: Positive linearity error is defined as the deviation of the analog value, expressed in LSBs, from the straight line that passes through positive full scale and

zero. For negative linearity error the straight line passes through negative full scale and zero. (See

Note 12: The ADC1251’s self-calibration technique ensures linearity, full scale, and offset errors as specified, but noise inherent in the self-calibration process will
result in a repeatability uncertainty of

Note 13: If T

Note 14: After an Auto-Zero or Auto-Cal cycle at the specified power supply extremes.

Note 15: When using the WR

end of the interval t
is synchronous to the rising edge of WR

Note 16: The CAL

Note 17: The specifications for these parameters are valid after an Auto-Cal cycle has been completed.

Note 18: The ADC1251 reference ladder is composed solely of capacitors.

Note 19: A Military RETS Electrical Test Specification is available on request. At time of printing the ADC1251CMJ/883 RETS specification complies fully with the
boldface limits in this column.

changes then an Auto-Zero or Auto-Cal cycle will have to be re-started. See the typical performance characteristic curves.

A

e

J

, therefore making tAend a minimum 6 clock periods or a maximum 7 clock periods after the rising edge of WR. If the falling edge of the clock

A

line must be high before a conversion is started.

e

3.5 MHz. At higher or lower clock frequencies accuracy may degrade. See the Typical Performance Characteristics

CLK

25§C and represent most likely parametric norm.

g

0.20 LSB.

control to start a conversion if the clock is asynchronous to the rising edge of WR an uncertainty of one clock period will exist in the

then tAwill end exactly 6.5 clock periods after the rising edge of WR. This does not occur when S/H control is used.

TL/H/11024– 4

TL/H/11024– 5

Figures 1b

and1c).

FIGURE 1a. Transfer Characteristic

5

TL/H/11024– 6