NSC ADC12441CIJ Datasheet
November 1994
ADC12441 Dynamically-Tested Self-Calibrating 12-Bit
Plus Sign A/D Converter with Sample-and-Hold
ADC12441 Dynamically-Tested Self-Calibrating 12-Bit
Plus Sign A/D Converter with Sample-and-Hold
General Description
The ADC12441 is a CMOS 12-bit plus sign successive approximation analog-to-digital converter whose dynamic
specifications (S/N, THD, etc.) are tested and guaranteed.
On request, the ADC12441 goes through a self-calibration
cycle that adjusts positive linearity and full-scale errors to
less than
g
g
(/2 LSB each and zero error to less than
1 LSB. The ADC12441 also has the ability to go through
an Auto-Zero cycle that corrects the zero error during every
conversion.
The analog input to the ADC12441 is tracked and held by
the internal circuitry, and therefore does not require an external sample-and-hold. A unipolar analog input voltage
range (0V to
accommodated with
a
5V) or a bipolar range (b5V toa5V) can be
g
5V supplies.
The 13-bit word on the outputs of the ADC12441 gives a 2’s
complement representation of negative numbers. The digital inputs and outputs are compatible with TTL or CMOS
logic levels.
Features
Y
Self-calibration provides excellent temperature stability
Y
Internal sample-and-hold
Y
Bipolar input range with singlea5V reference
Simplified Block Diagram
Applications
Y
Digital signal processing
Y
Telecommunications
Y
Audio
Y
High resolution process control
Y
Instrumentation
Key Specifications
Y
Resolution 12 bits plus sign
Y
Conversion Time 13.8 ms (max)
Y
Bipolar Signal/Noise 76.5 dB (min)
Y
Total Harmonic Distortion
Y
Aperture Time 100 ns
Y
Aperture Jitter 100 ps
Y
Zero Error
Y
Positive Full Scale Error
Y
Power Consumption
Y
Sampling rate 55 kHz (max)
TRI-STATEÉis a registered trademark of National Semiconductor Corporation.
@
g
5V 70 mW (max)
b
75 dB (max)
g
1 LSB (max)
g
1 LSB (max)
Connection Diagram
Dual-In-Line Package
rms
Top View
TL/H/11017– 2
Order Number
ADC12441CMJ, ADC12441CMJ/883
or ADC12441CIJ
See NS Package Number J28A
TL/H/11017– 1
C
1995 National Semiconductor Corporation RRD-B30M115/Printed in U. S. A.
TL/H/11017
Absolute Maximum Ratings (Notes1&2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (V
Negative Supply Voltage (Vb)
Voltage at Logic Control Inputs
Voltage at Analog Inputs
(V
and V
IN
AVCC–DVCC(Note 7) 0.3V
Input Current at Any Pin (Note 3)
Package Input Current (Note 3)
Power Dissipation at 25
Storage Temperature Range
ESD Susceptability (Note 5) 2000V
Soldering Information
J Package (10 sec.) 300
e
e
DV
CC
)(V
REF
AVCC) 6.5V
CC
b
0.3V to (V
b
b
0.3V) to (V
C (Note 4) 875 mW
§
a
CC
a
CC
g
g
b
65§Ctoa150§C
b
6.5V
0.3V)
0.3V)
5mA
20 mA
§
Operating Ratings (Notes1&2)
Temperature Range T
ADC12441CIJ
ADC12441CMJ,
ADC12441CMJ/883
DVCCand AVCCVoltage
(Notes6&7) 4.5V to 5.5V
Negative Supply Voltage (V
Reference Voltage
(V
, Notes6&7) 3.5V to AV
REF
C
s
s
T
MIN
b
40§CsT
b
55§CsT
b
)
b
T
A
MAX
s
a
85§C
A
s
a
125§C
A
4.5V tob5.5V
a
50 mV
CC
Converter Electrical Characteristics
The following specifications apply for V
Impedance
all other limits T
e
600X, and f
e
A
e
CLK
e
T
25§C. (Notes 6, 7 and 8)
J
e
e
AV
CC
ea
DV
CC
2.0 MHz unless otherwise specified. Boldface limits apply for T
CC
Symbol Parameter Conditions
5.0V, V
b
eb
5.0V, V
ea
REF
5.0V, Analog Input Source
e
A
Typical Limit Units
(Note 9) (Note 10) (Limit)
STATIC CHARACTERISTICS
Positive Integral Linearity Error After Auto-Cal (Notes 11 & 12)
Negative Integral Linearity Error After Auto-Cal (Notes 11 & 12)
g
(/2 LSB
g
*/4 LSB
Positive or Negative Differential Linearity After Auto-Cal (Notes 11 & 12) 12 Bits
Zero Error After Auto-Zero or Auto-Cal
(Notes 12 & 13)
Positive Full-Scale Error After Auto-Cal (Note 12)
g
(/2
Negative Full-Scale Error After Auto-Cal (Note 12)
V
Analog Input Voltage V
IN
e
Power Supply Zero Error (Note 14) AV
Sensitivity
Full-Scale Error
V
CC
REF
e
4.75V, V
DV
CC
e
5Vg5%,
b
eb
5Vg5%
Linearity Error
C
REFVREF
C
IN
Input Capacitance (Note 18) 80 pF
Analog Input Capacitance 65 pF
V
g
(/8 LSB
g
(/8 LSB
g
(/8 LSB
DYNAMIC CHARACTERISTICS
Bipolar Effective Bits f
(Note 17)
Unipolar Effective Bits f
(Note 17)
S/N Bipolar Signal-to-Noise Ratio f
(Note 17)
S/N Unipolar Signal-to-Noise Ratio f
(Note 17)
IN
f
IN
IN
f
IN
IN
f
IN
f
IN
IN
f
IN
f
IN
e
1 kHz, V
e
20 kHz, V
e
1 kHz, V
e
20 kHz, V
e
1 kHz, V
e
10 kHz, V
e
20 kHz, V
e
1 kHz, V
e
10 kHz, V
e
20 kHz, V
e
g
4.85V 12.6 Bits
IN
e
g
4.85V 12.6 12.4 Bits (min)
IN
e
4.85 V
IN
IN
IN
IN
IN
IN
IN
IN
p-p
e
4.85 V
e
g
4.85V 78 dB
e
g
4.85V 78 dB
e
g
4.85V 78 76.5 dB (min)
e
4.85 V
p-p
e
4.85 V
e
4.85 V
11.8 Bits
11.8 11.6 Bits (min)
p-p
73 dB
p-p
p-p
73 dB
73 71.5 dB (min)
e
T
T
J
MIN
g
1 LSB (max)
g
1 LSB (max)
g1/g
2 LSB (max)
b
b
0.05 V(min)
a
0.05 V(max)
CC
to T
MAX
;
2
Converter Electrical Characteristics
The following specifications apply for V
Impedance
all other limits T
e
600X, and f
e
A
e
CLK
e
T
25§C. (Notes 6, 7 and 8) (Continued)
J
e
e
DV
CC
2.0 MHz unless otherwise specified. Boldface limits apply for T
CC
AV
CC
ea
5.0V, V
b
Symbol Parameter Conditions
DYNAMIC CHARACTERISTICS (Continued)
THD Bipolar Total Harmonic Distortion f
(Note 17)
THD Unipolar Total Harmonic Distortion f
(Note 17)
Bipolar Peak Harmonic or f
Spurious Noise (Note 17)
Unipolar Peak Harmonic or f
Spurious Noise (Note 17)
Bipolar Two Tone Intermodulation V
Distortion (Note 17) f
Unipolar Two Tone Intermodulation V
Distortion (Note 17) f
b
3 dB Bipolar Full Power Bandwidth V
b
3 dB Unipolar Full Power Bandwidth V
e
IN
e
f
IN
e
IN
e
f
IN
e
IN
e
f
IN
e
f
IN
e
IN
e
f
IN
e
f
IN
e
IN
e
IN2
e
IN
e
IN2
e
IN
e
IN
1 kHz, V
19.688 kHz, V
1 kHz, V
19.688 kHz, V
1 kHz, V
10 kHz, V
20 kHz, V
1 kHz, V
10 kHz, V
20 kHz, V
g
20.625 kHz
4.85 V
20.625 kHz
g
4.85 V
e
g
IN
IN
e
4.85 V
IN
IN
e
g
IN
e
IN
e
IN
e
4.85 V
IN
e
IN
e
IN
IN1
p-p,fIN1
e
4.85V, f
4.85V (Note 17) 25 20 kHz (Min)
(Note 17) 30 20 kHz (Min)
p-p
Aperture Time 100 ns
Aperture Jitter 100 ps
eb
5.0V, V
4.85V
e
g
4.85V
p-p
e
4.85 V
4.85V
g
4.85V
g
4.85V
p-p
4.85 V
p-p
4.85 V
p-p
19.375 kHz,
e
19.375 kHz,
ea
REF
5.0V, Analog Input Source
e
e
T
A
T
J
MIN
Typical Limit Units
(Note 9) (Notes 10, 19) (Limit)
b
82 dB
p-p
b
80
b
82 dB
b
80
b
88 dB
b
84 dB
b
80 dB
b
90 dB
b
86 dB
b
82 dB
b
78
b
78
b
75 dB (max)
b
75 dB (max)
b
74 dB (max)
b
73 dB (max)
to T
MAX
;
rms
Digital and DC Electrical Characteristics
The following specifications apply for DV
otherwise specified. Boldface limits apply for T
(Notes 6 and 7)
CC
e
ea
AV
A
CC
5.0V, V
e
e
T
T
J
MIN
Symbol Parameter Conditions
V
IN(1)
V
IN(0)
I
IN(1)
I
IN(0)
V
T
V
T
V
H
V
OUT(1)
V
OUT(0)
Logical ‘‘1’’ Input Voltage for V
All Inputs except CLK IN
Logical ‘‘0’’ Input Voltage for V
All Inputs except CLK IN
Logical ‘‘1’’ Input Current V
Logical ‘‘0’’ Input Current V
a
CLK IN Positive-Going
Threshold Voltage
b
CLK IN Negative-Going
Threshold Voltage
CLK IN Hysteresis
[
V
a
(min)bV
T
b
]
(max)
T
Logical ‘‘1’’ Output Voltage V
Logical ‘‘0’’ Output Voltage V
e
5.25V
CC
e
4.75V
CC
e
5V 0.005 1 mA (max)
IN
e
0V
IN
e
4.75V:
CC
eb
I
I
CC
360 mA 2.4 V (min)
OUT
eb
10 mA 4.5 V (min)
OUT
e
4.75V, I
OUT
3
b
to T
eb
MAX
5.0V, V
; all other limits T
REF
ea
5.0V, and f
e
T
A
J
e
CLK
25§C.
e
2.0 MHz unless
Typical Limit Units
(Note 9) (Notes 10, 19) (Limits)
2.0 V (min)
0.8 V (max)
b
0.005
b
1 mA (max)
2.8 2.7 V (min)
2.1 2.3 V (max)
0.7 0.4 V (min)
e
1.6 mA 0.4 V (max)
Digital and DC Electrical Characteristics
The following specifications apply for DV
otherwise specified. Boldface limits apply for T
(Notes 6 and 7) (Continued)
CC
e
ea
AV
A
CC
5.0V, V
e
e
T
T
J
MIN
Symbol Parameter Conditions
I
OUT
I
SOURCE
I
SINK
DI
CC
AI
CC
b
I
TRI-STATEÉOutput Leakage V
Current
Output Source Current V
Output Sink Current V
DVCCSupply Current f
AVCCSupply Current f
VbSupply Current f
e
0V
OUT
e
V
5V 0.01 3 mA (max)
OUT
e
0V
OUT
e
5V 20 8.0 mA (min)
OUT
e
2 MHz, CSe‘‘1’’ 1 2 mA (max)
CLK
e
2 MHz, CSe‘‘1’’ 2.8 6 mA (max)
CLK
e
2 MHz, CSe‘‘1’’ 2.8 6 mA (max)
CLK
b
to T
eb
MAX
REF
ea
5.0V, V
; all other limits T
5.0V, and f
e
T
A
e
CLK
e
25§C.
J
Typical Limit Units
(Note 9) (Notes 10, 19) (Limits)
b
0.01
b
20
b
3 mA (max)
b
6.0 mA (min)
2.0 MHz unless
AC Electrical Characteristics
The following specifications apply for DV
Boldface limits apply for T
e
T
A
J
e
ea
AV
CC
e
T
MIN
to T
CC
MAX
; all other limits T
Symbol Parameter Conditions
f
CLK
Clock Frequency
5.0V, V
b
eb
e
A
e
5.0V, t
T
t
r
e
25§C. (Notes 6 and 7)
J
e
20 ns unless otherwise specified.
f
Typical Limit Units
(Note 9) (Notes 10, 19) (Limits)
0.5 MHz (min)
4.0 2.0 MHz (max)
Clock Duty Cycle 50 %
40 % (min)
60 % (max)
t
C
t
A
t
Z
t
CAL
t
W(CAL)L
t
W(WR)L
t
ACC
t0H,t
t
PD(INT)
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.
Note 2: All voltages are measured with respect to AGND and DGND, unless otherwise specified.
Note 3: When the input voltage (V
5 mA. The 20 mA maximum package input current rating allows the voltage at any four pins, with an input current limit of 5 mA, to simultaneously exceed the power
supply voltages.
Conversion Time 27(1/f
e
f
2.0 MHz 13.5 ms
CLK
Acquisition Time R
(Note 15)
f
CLK
SOURCE
e
e
50X 7(1/f
2.0 MHz
Auto Zero Time 26(1/f
e
f
2.0 MHz 13 ms
CLK
Calibration Time 1396(1/f
e
f
2.0 MHz 698 706 ms (max)
CLK
) 27(1/f
CLK
) 7(1/f
CLK
)a300 ns (max)
CLK
)a300 ns (max)
CLK
3.5 ms
) 26(1/f
CLK
) max
CLK
) (max)
CLK
Calibration Pulse Width (Note 16) 60 200 ns (min)
Minimum WR Pulse Width 60 200 ns (min)
Maximum Access Time C
(Delay from Falling Edge of 50 85 ns (max)
RD
to Output Data Valid)
TRI-STATE Control R
1H
(Delay from Rising Edge of C
RD
to Hi-Z State)
Maximum Delay from Falling Edge of
RD
or WR to Reset of INT
) at any pin exceeds the power supply rails (V
IN
e
100 pF
L
e
1kX,
L
e
100 pF 30 90 ns (max)
L
100 175 ns (max)
k
IN
Vbor V
l
(AVCCor DVCC), the current at that pin should be limited to
IN
4
AC Electrical Characteristics (Continued)
Note 4: The power dissipation of this device under normal operation should never exceed 169 mW (Quiescent Power DissipationaTTL Loads on the digital
outputs). Caution should be taken not to exceed absolute maximum power rating when the device is operating in a severe fault condition (ex. when any inputs or
outputs exceed the power supply). The maximum power dissipation must be derated at elevated temperatures and is dictated by T
temperature), i
is P
Dmax
resistance (i
Note 5: Human body model, 100 pF discharged through a 1.5 kX resistor.
Note 6: Two on-chip diodes are tied to the analog input as shown below. Errors in the A/D conversion can occur if these diodes are forward biased more than
50 mV.
(package junction to ambient thermal resistance), and TA(ambient temperature). The maximum allowable power dissipation at any temperature
JA
e
b
(T
TA)/iJAor the number given in the Absolute Maximum Ratings, whichever is lower. For this device, T
Jmax
) of the ADC12441 with CMJ and CIJ suffixes when board mounted is 47§C/W.
JA
Jmax
e
(maximum junction
Jmax
125§C, and the typical thermal
This means that if AVCCand DVCCare minimum (4.75 VDC) and Vbis maximum (b4.75 VDC), full-scale must bes4.8 VDC.
Note 7: A diode exists between AV
To guarantee accuracy, it is required that the AVCCand DVCCbe connected together to a power supply with separate bypass filters at each VCCpin.
Note 8: Accuracy is guaranteed at f
Characteristics section.
Note 9: Typicals are at T
Note 10: Limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 11: Positive linearity error is defined as the deviation of the analog value, expressed in LSBs, from the straight line that passes through positive full scale and
zero. For negative linearity error the straight line passes through negative full scale and zero. (See
Note 12: The ADC12441’s self-calibration technique ensures linearity, full scale, and offset errors as specified, but noise inherent in the self-calibration process will
result in a repeatability uncertainty of
Note 13: If T
Note 14: After an Auto-Zero or Auto-Cal cycle at the specified power supply extremes.
Note 15: If the clock is asynchronous to the falling edge of WR
t
periods.
Note 16: The CAL
Note 17: The specifications for these parameters are valid after an Auto-Cal cycle has been completed.
Note 18: The ADC12441 reference ladder is composed solely of capacitors.
Note 19: A Military RETS Electrical Test Specification is available on request. At time of printing the ADC12441CMJ/883 RETS complies fully with the boldface
limits in this column.
A
e
6 clock periods and the maximum t
A
J
changes then an Auto-Zero or Auto-Cal cycle will have to be re-started (see the Typical Performance Characteristic curves).
line must be high before a conversion is started.
and DVCCas shown below.
CC
e
2.0 MHz. At higher and lower clock frequencies accuracy may degrade. See curves in the Typical Performance
CLK
e
25§C and represent most likely parametric norm.
g
0.20 LSB.
e
7 clock periods. If the falling edge of the clock is synchronous to the rising edge of WR then tAwill be exactly 6.5 clock
A
an uncertainty of one clock period will exist in the interval of tA, therefore making the minimum
TL/H/11017– 3
TL/H/11017– 4
Figures 1b
and1c.)
FIGURE 1a. Transfer Characteristic
5
TL/H/11017– 5
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