NSC ADC12281CIVT Datasheet

ADC12281 12-Bit, 20 MSPS Single-Ended Input, Pipelined A/D Converter

March 2000

General Description

The ADC12281 is a monolithic CMOS analog-to-digital converter capable of converting analog input signals into 12-bit digital words at 20 megasamples per second (MSPS). It utilizes a pipeline architecture to minimize die size and power dissipation. Self-calibration and error correction maintain accuracy and performance over temperature.

TheADC12281operateson a 5V power supply and can digitize single-ended analog input signals in the range of 0V to 2V. A single convert clock controls the conversion operation and all digital I/O is TTL compatible.

The ADC12881 is designed to minimize external components necessary for the analog input interface. An internal sample-and-hold circuit samples the single-ended analog input and an internal amplifier buffers the reference voltage input.

The Power Down feature reduces power consumption to 20 mW, typical.

The ADC12281 is available in the 32-lead TQFP package and is designed to operate over the industrial temperature range of −40˚C to +85˚C.

Features

n Single 5V power supply n Single-ended analog input n Internal sample-and-hold n Internal reference buffer amplifier n Low offset and gain errors

Key Specifications

n Resolution 12 bits n Conversion rate up to 20 MSPS n DNL 0.35 LSB (typ) n SNR 65.5 dB (typ) n ENOB 10.5 bits (typ) n Analog input range 2 V n Supply voltage +5V n Power consumption, 20 MHz 443 mW (typ)

(min)

Applications

n Digital signal processing front end n Digital television n Radar n High speed data links n Waveform digitizers n Quadrature demodulation

Connection Diagram

DS101027-1

32-Lead TQFP Package

Order Number ADC12281CIVT

See NS Package Number VBE32A

TRI-STATE®is a registered trademark of National Semiconductor Corporation.

Ordering Information

ADC12281

Simplified Block Diagram

Industrial (−40˚C ≤ TA≤ +85˚C) Package

ADC12281CIVT 32-Pin TQFP

Pin Descriptions and Equivalent Circuits

Pin Symbol Equivalent Circuit Description

Single-ended analog signal input. With a 2.0V

REF

reference voltage, input signal voltages in the range of 0V to 2.0V will be converted. See Section

1.2. Reference voltage input. This pin should be driven

from an accurate, stable reference source in the range of 1.8V to 2.2V and bypassed to a low-noise ground with a monolithic ceramic capacitor, nominally 0.01 µF. See Section 1.1.

DS101027-2

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Pin Descriptions and Equivalent Circuits (Continued)

Pin Symbol Equivalent Circuit Description

Positive reference bypass pin. Bypass with a

32 V

31 V

30 V

0.1 µF capacitor. Do not connect anything else to this pin. See Section 3.1.

Reference midpoint bypass pin. Bypass with a

0.1 µF capacitor. Do not connect anything else to this pin. See Section 3.1.

Negative reference bypass pin. Bypass with a

0.1 µF capacitor. Do not connect anything else to this pin. See Section 3.1.

ADC12281

10 CLOCK

8 CAL

7PD

11 OE

28 OR

29 READY

Sample clock input, TTL compatible. Amplitude should not exceed 3 V

P-P

Calibration request, active High. Calibration cycle starts when CAL returns to logic low. CAL is ignored during power-down mode. See Section

2.2. Power-down, active High, ignored during

calibration cycle. See paragraph 2.4. Output enable control, active low. When this pin is

high the data outputs are in TRI-STATE

(high-impedance) mode.

Over-range indicator. This pin is at a logic High, for V

0 or for V

REF

Device ready indicator, active High. This pin will be at a logic Low during a calibration cycle and while the device is in the power down mode.

14–19,

22–27

D0–D11

Digital output word, CMOS compatible. D0 (pin 19) is LSB, D11 (pin 36) is MSB. Load with no more than 25 pF.

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Pin Descriptions and Equivalent Circuits (Continued)

ADC12281

Pin Symbol Equivalent Circuit Description

4, 6 AGND

13 V

9, 12 DGND

21 V

20 DGND I/O

IN COM

I/O

Analog input common. Connect to a quiet point in analog ground near the driving device. See Section 1.2.

Positive analog supply pin. Connect to a clean, quiet voltage source of +5V. V

and VDshould

have a common supply and be separately bypassed witha5µFto10µFcapacitor and a

0.1 µF chip capacitor. The ground return for the analog supply, AGND

and DGND should be connected together close to the ADC12281 package. See Section 5.0.

Positive digital supply pin. Connect to a clean, quiet voltage source of +5V. V

and VDshould

have a common supply and be separately bypassed witha5µFto10µFcapacitor and a

0.1 µF chip capacitor. The ground return for the digital supply. AGND

and DGND should be connected together close to the ADC12281 package. See Section 5.0.

The digital output driver supply pins. This pin can be operated from a supply voltage of 3V to 5V, but the voltage on this pin should never exceed the

supply pin voltage. See Section 3.4.

The ground return for the digital output drivers. This pin should be returned to a point in the digital ground that is removed from the other ground pins of the ADC12281.

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ADC12281

Absolute Maximum Ratings (Notes 1, 2)

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.

Supply Voltages (V

| ≤100 mV

A–VD

I/O–VA,VDI/O–V

A,VD,VD

Voltage on Any Input or Output Pin −0.3V to V Input Current at Any Pin (Note 3) Package Input Current (Note 3) Power Dissipation at T

I/O) 6.5V

= 25˚C See (Note 4)

≤300 mV

+0.3V

25 mA

50 mA

ESD Susceptibility

Human Body Model (Note 5) 2500V Machine Model (Note 5) 250V

Soldering Temperature, Infrared,

(10 sec.) (Note 6) 300˚C

Storage Temperature −65˚C to +150˚C

Operating Ratings (Notes 1, 2)

Operating Temperature Range −40˚C ≤ T Supply Voltage (V Output Driver Supply Voltage (V V

Input 1.8V to 2.2V

REF

CLOCK, CAL, PD, OE

) +4.75V to +5.25V

A,VD

I/O) +2.7V to V

−0.05V to VD+0.05V

≤ +85˚C

Ground Difference |AGND–DGND| ≤100 mV

Converter Electrical Characteristics

The following specifications apply for AGND = DGND = DGND I/O = 0V, VA=VD=VDI/O = +5V, PD = +5V, V f

=20MHz,3V

CLK

all other limits TA=TJ= 25˚C (Notes 7, 8, 9).

Symbol Parameter Conditions

at 50% duty cycle, CL= 25 pF/pin. After Auto-Cal. Boldface limits apply for TA=TJ=T

P-P

Typical

(Note 10)

Limits

(Note 11)

STATIC CONVERTER CHARACTERISTICS

Resolution with No Missing Codes 12 Bits (min) INL Integral Non-Linearity DNL Differential Non-Linearity

Full-Scale Error +3

Zero Error +7

1.0

0.35

2.5 LSB (max)

0.9 LSB (max)

10 LSB (max)

17 LSB (max)

DYNAMIC CONVERTER CHARACTERISTICS

BW Full Power Bandwidth 100 MHz SNR Signal-to-Noise Ratio f SINAD Signal-to-Noise and Distortion f ENOB Effective Number of Bits f THD Total Harmonic Distortion f SFDR Spurious Free Dynamic Range f

= 4.43 MHz, VIN= 2.0 V

P-P P-P P-P P-P P-P

65.5 62.5 dB (min) 65 62 dB (min)

10.5 10 Bits (min)

−76 dB 75 dB

REFERENCE AND ANALOG INPUT CHARACTERISTICS

REF

Input Voltage Range V VINInput Capacitance

(CLK LOW) 10 pF (CLK HIGH) 15 pF

Reference Voltage (Note 14) 2.00

REF

1.8 V (min)

2.2 V (max)

Reference Input Leakage Current 10 µA Reference Input Resistance 1 MΩ

REF

MIN

= +2.0V,

to T

MAX

Units

(Limits)

V (max)

;

DC and Logic Electrical Characteristics

The following specifications apply for AGND = DGND = DGND I/O = 0V, VA=VD=VDI/O = +5V, PD = +5V, V f

=20MHz,3V

CLK

all other limits T

Symbol Parameter Conditions

CLOCK, CAL, PD, OE DIGITAL INPUT CHARACTERISTICS

Logical “1” Input Voltage VD= 5.25V 2.0 V (min) Logical “0” Input Voltage VD= 4.75V 0.8 V (max) Logical “1” Input Current VIN= 5.0V 10 µA Logical “0” Input Current VIN= 0V −10 µA Logic Input Capacitance 8 pF

at 50% duty cycle, CL= 25 pF/pin. After Auto-Cal. Boldface limits apply for TA=TJ=T

P-P

= 25˚C (Notes 7, 8, 9).

A=TJ

Typical

(Note 10)

Limits

(Note 11)

REF

MIN

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= +2.0V,

to T

MAX

Units

(Limits)

;

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