NSC ADC12138CIWM, ADC12138CIMSA, ADC12132CIMSA, ADC12130CIWM Datasheet
ADC12130/ADC12132/ADC12138
Self-Calibrating 12-Bit Plus Sign Serial I/O A/D
Converters with MUX and Sample/Hold
March 2000
ADC12130/ADC12132/ADC12138 Self-Calibrating 12-Bit Plus Sign Serial I/O A/D Converters with
MUX and Sample/Hold
General Description
The ADC12130, ADC12132 and ADC12138 are 12-bit plus
sign successiveapproximationA/D converters with serial I/O
and configurable input multiplexer. The ADC12132 and
ADC12138 have a 2 and an 8 channel multiplexer, respectively.The differential multiplexer outputs andA/D inputs are
available on the MUXOUT1, MUXOUT2,A/DIN1 and A/DIN2
pins. TheADC12130 has a two channel multiplexer with the
multiplexer outputs and A/D inputs internally connected. The
ADC12130 family is tested with a 5 MHz clock. On request,
these A/Ds go through a self calibration process that adjusts
linearity, zero and full-scale errors to typically less than
LSB each.
The analog inputs can be configured to operate in various
combinations of single-ended, differential, or
pseudo-differential modes. A fully differential unipolar analog
input range (0V to +5V) can be accommodated with a single
+5V supply. In the differential modes, valid outputs are obtained even when the negative inputs are greater than the
positive because of the 12-bit plus sign output data format.
The serial I/O is configured to comply with the NSC MICROWIRE
LM4041.
™
. For voltage references, see the LM4040 or
±
Features
n Serial I/O (MICROWIRE, SPI and QSPI Compatible)
n 2 or 8 channel differential or single-ended multiplexer
n Analog input sample/hold function
n Power down mode
n Programmable acquisition time
n Variable digital output word length and format
n No zero or full scale adjustment required
n 0V to 5V analog input range with single 5V power
supply
1
Key Specifications
n Resolution: 12-bit plus sign
n 12-bit plus sign conversion time: 8.8 µs (max)
n 12-bit plus sign throughput time: 14 µs (max)
n Integral linearity error:
n Single supply: 3.3V or 5V
n Power consumption
— 3.3V 15 mW (max)
— 3.3V power down 40 µW (typ)
— 5V 33 mW (max)
— 5V power down 100 µW (typ)
±
2 LSB (max)
±
10%
Applications
n Pen-based computers
n Digitizers
n Global positioning systems
ADC12138 Simplified Block Diagram
DS012079-1
TRI-STATE®is a registered trademark of National Semiconductor Corporation.
™
COPS
microcontrollers, HPC™and MICROWIRE™are trademarks of National Semiconductor Corporation.
© 2000 National Semiconductor Corporation DS012079 www.national.com
Ordering Information
Industrial Temperature Range
ADC12130CIN N16E, Dual-In-Line
ADC12130CIWM M16B, Wide Body SO
ADC12132CIMSA MSA20, SSOP
ADC12138CIN N28B, Dual-In-Line
ADC12138CIWM M28B
ADC12138CIMSA MSA28, SSOP
Connection Diagrams
ADC12130/ADC12132/ADC12138
16-Pin Dual-In-Line and
Wide Body SO Packages
Top View
−40˚C ≤ T
DS012079-2
≤ +85˚C
A
NS Package Number
20-Pin SSOP Package
DS012079-47
Top View
28-Pin Dual-In-Line, SSOP and
Wide Body SO Packages
DS012079-3
Top View
www.national.com 2
Pin Descriptions
CCLK The clock applied to this input controls the su-
cessive approximation conversion time interval
and the acquisition time. The rise and falltimes
of the clock edges should not exceed 1 µs.
SCLK This is the serial data clock input. The clock
applied to this input controls the rate at which
the serial data exchange occurs. The rising
edge loads the information on the DI pin into
the multiplexer address and mode select shift
register. This address controls which channel
of the analog input multiplexer (MUX) is selected and the mode of operation for the A/D.
With CS low, the falling edge of SCLK shifts
the data resulting from the previous ADC conversion out on DO, with the exception of the
first bit of data. When CS is low continuously,
the first bit of the data is clocked out on the rising edge of EOC (end of conversion). When
CS is toggled, the falling edge of CS always
clocks out the first bit of data. CS should be
brought low when SCLK is low. The rise and
fall times of the clock edges should not exceed
1 µs.
DI This is the serial data input pin. The data ap-
plied to this pin is shifted by the rising edge of
SCLK into the multiplexer address and mode
select register.
the assignment of the multiplexer address and
the mode select data.
DO The data output pin. This pin is an active push/
pull output when CS is low. When CS is high,
this output is TRI-STATE. The A/D conversion
result (DB0–DB12) and converter status data
are clocked out by the falling edge of SCLK on
this pin. The word length and format of this result can vary (see
and format are controlled by the data shifted
into the multiplexer address and mode select
register (see
EOC This pin is an active push/pull output and indi-
cates the status of the ADC12130/2/8. When
low, it signals that the A/D is busy with a conversion, auto-calibration, auto-zero or power
down cycle. The rising edge of EOC signals
the end of one of these cycles.
CS
This is the chip select pin. When a logic low is
applied to this pin, the rising edge of SCLK
shifts the data on DI into the address register.
This low also brings DO out of TRI-STATE.
With CS low, the falling edge of SCLK shifts
the data resulting from the previous ADC conversion out on DO, with the exception of the
first bit of data. When CS is low continuously,
the first bit of the data is clocked out on the rising edge of EOC (end of conversion). When
CS is toggled, the falling edge of CS always
clocks out the first bit of data. CS should be
brought low when SCLK is low. The falling
edge of CS resets a conversion in progress
and starts the sequence for a new conversion.
When CS is brought back low during a conversion, that conversion is prematurely terminated. The data in the output latches may be
corrupted. Therefore, whenCS is brought back
Table 2
Table 4
through
Table 1
). The word length
).
Table 4
show
low during a conversion in progress the data
output at that time should be ignored. CS may
also be left continuously low. In this case it is
imperative that the correct number of SCLK
pulses be applied to the ADC in order to remain synchronous. After the ADC supply
power is applied it expects to see 13 clock
pulses for each I/O sequence. The number of
clock pulses the ADC expects is the same as
the digital output word length. This word length
can be modified by the data shifted in on the
DOR
DO pin.
This is the data output ready pin. This pin is an
Table 4
details the data required.
active push/pull output. It is low when the conversion result is being shifted out and goes
high to signal that all the data has been shifted
out.
CONV
A logic low is required on this pin to program
any mode or change the ADC’s configuration
as listed in the Mode Programming Table
(
Table 4
) such as 12-bit conversion, Auto Cal,
Auto Zero etc. When this pin is high theADC is
placed in the read dataonly mode. While in the
read data only mode, bringing CS low and
pulsing SCLK will only clock out on DO any
data stored in the ADCs output shift register.
The data on DI will be neglected. A new conversion will not be started and the ADC will remain in the mode and/or configuration previously programmed. Read data only cannot be
performed while a conversion, Auto-Cal or
Auto-Zero are in progress.
PD This is the power down pin. When PD is high
the A/D is powered down; when PD is low the
A/D is powered up. The A/D takes a maximum
of 700 µs to power up after the command is
given.
CH0–CH7 These are the analog inputs of the MUX. A
channel input is selected by the address information at the DI pin, which is loaded on the rising edge of SCLK into the address register
(see
Table 2
and
Table 3
).
The voltage applied to these inputs should not
exceed V
+ or go below GND. Exceeding this
A
range on an unselected channel will corrupt
the reading of a selected channel.
COM This pin is another analog input pin. It is used
as a pseudo ground when the analog multiplexer is single-ended.
MUXOUT1,
MUXOUT2
A/DIN1,
A/DIN2
These are the multiplexer output
pins.
These are the converter input pins. MUXOUT1
is usually tied to A/DIN1. MUXOUT2 is usually
tied to A/DIN2. If external circuitry is placedbetween MUXOUT1 and A/DIN1, or MUXOUT2
and A/DIN2 it may be necessary to protect
these pins. The voltage at these pins should
not exceed V
5
).
V
+ This is the positive analog voltage reference
REF
+
or go belowAGND (see
A
Figure
input. In order to maintain accuracy, the voltage range of V
REF(VREF=VREF
+−V
REF
−) is
ADC12130/ADC12132/ADC12138
www.national.com3
Pin Descriptions (Continued)
1V
to 5.0 VDCand the voltage at V
DC
cannot exceed V
mended bypassing.
V
− The negative voltage reference input. In order
REF
to maintain accuracy, the voltage at this pin
must not go below GND or exceed V
Figure 6
).
ADC12130/ADC12132/ADC12138
+. See
A
Figure 6
REF
for recom-
+. (See
A
+, VD+ These are the analog and digital power supply
V
A
pins. V
+
on the chip. These pins should be tied to the
A
+
and V
+
are not connected together
D
same power supply and bypassed separately
(see
Figure 6
V
+ and VD+ is 3.0 VDCto 5.5 VDC.
A
DGND This is the digital ground pin (see
AGND This is the analog ground pin (see
). The operating voltage range of
Figure 6
Figure 6
).
).
www.national.com 4
ADC12130/ADC12132/ADC12138
Absolute Maximum Ratings (Notes 1, 2)
Storage Temperature −65˚C to +150˚C
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Positive Supply Voltage
+
(V
=VA+=VD+) 6.5V
Voltage at Inputs and Outputs
+
except CH0–CH7 and COM −0.3V to V
+0.3V
Voltage at Analog Inputs
+
±
30 mA
±
120 mA
+5V
CH0–CH7 and COM GND −5V to V
+−VD+| 300 mV
|V
A
Input Current at Any Pin (Note 3)
Package Input Current (Note 3)
Package Dissipation at
= 25˚C (Note 4) 500 mW
T
A
ESD Susceptability (Note 5)
Human Body Model 1500V
Soldering Information
N Packages (10 seconds) 260˚C
Operating Ratings (Notes 1, 2)
Operating Temperature Range T
ADC12130CIN, ADC12130CIWM,
ADC12132CIMSA,
ADC12138CIMSA,
ADC12138CIN, ADC12138CIWM −40˚C ≤ T
+
Supply Voltage (V
+−VD+| ≤ 100 mV
|V
A
+ 0VtoVA+
V
REF
− 0VtoV
V
REF
V
REF(VREF
V
REF
+−V
Common Mode Voltage Range
=VA+=VD+) +3.0V to +5.5V
−) 1V to VA+
REF
A/DIN1, A/DIN2, MUXOUT1
and MUXOUT2 Voltage Range 0V to V
A/D IN Common Mode Voltage
Range
≤ TA≤ T
MIN
A
0.1 VA+ to 0.6 VA+
SO Package (Note 6):
Vapor Phase (60 seconds) 215˚C
Infrared (15 seconds) 220˚C
0V to VA+
Converter Electrical Characteristics
The following specifications apply for (V+=VA+=VD+ = +5V, V
common-mode voltage) or (V+=VA+=VD+ = 3.3V, V
common-mode voltage), V
25Ω,fCK=fSK= 5 MHz, and 10 (tCK) acquisition time unless otherwise specified. Boldface limits apply for TA=TJ=T
to T
; all other limits TA=TJ= 25˚C. (Notes 7, 8, 9)
MAX
− = 0V, 12-bit + sign conversion mode, source impedance for analog inputs, V
REF
+ = 2.5V and fully-differential input with fixed 1.250V
REF
Symbol Parameter Conditions Typical
STATIC CONVERTER CHARACTERISTICS
Resolution 12 + sign Bits (min)
+ILE Positive Integral Linearity Error After Auto-Cal (Notes 12, 18)
−ILE Negative Integral Linearity Error After Auto-Cal (Notes 12, 18)
DNL Differential Non-Linearity After Auto-Cal
Positive Full-Scale Error After Auto-Cal (Notes 12, 18)
Negative Full-Scale Error After Auto-Cal (Notes 12, 18)
Offset Error After Auto-Cal (Notes 5, 18)
V
(+)=VIN(−) = 2.048V
IN
DC Common Mode Error After Auto-Cal (Note 15)
TUE Total Unadjusted Error After Auto-Cal
(Notes 12, 13, 14)
+ = +4.096V, and fully differential input with fixed 2.048V
REF
−
and V
REF
Limits Units
(Note 10)
±
1/2
±
1/2
±
1/2
±
1/2
±
1/2
±
2 LSB (max)
±
1 LSB
(Note 11)
±
2 LSB (max)
±
2 LSB (max)
±
1.5 LSB (max)
±
3.0 LSB (max)
±
3.0 LSB (max)
±
2 LSB (max)
MAX
≤ +85˚C
REF
+
REF
MIN
(Limits)
+
+
A
≤
www.national.com5
Converter Electrical Characteristics
The following specifications apply for (V+=VA+=VD+ = +5V, V
common-mode voltage) or (V+=VA+=VD+ = 3.3V, V
common-mode voltage), V
≤ 25Ω,fCK=fSK= 5 MHz, and 10 (tCK) acquisition time unless otherwise specified. Boldface limits apply for TA=TJ=
T
MIN
to T
; all other limits TA=TJ= 25˚C. (Notes 7, 8, 9) (Continued)
MAX
− = 0V, 12-bit + sign conversion mode, source impedance for analog inputs, V
REF
+ = +2.5V and fully-differential input with fixed 1.250V
REF
Symbol Parameter Conditions Typical
STATIC CONVERTER CHARACTERISTICS (Continued)
Multiplexer Channel to Channel
Matching
Power Supply Sensitivity V
ADC12130/ADC12132/ADC12138
+
= +5V±10%
V
= +4.096V
REF
Offset Error
+ Full-Scale Error
− Full-Scale Error
+ Integral Linearity Error
− Integral Linearity Error
UNIPOLAR DYNAMIC CONVERTER CHARACTERISTICS
S/(N+D) Signal-to-Noise Plus f
Distortion Ratio f
−3 dB Full Power Bandwidth V
= 1 kHz, VIN=5VPP,V
IN
= 20 kHz, VIN=5VPP,V
IN
f
= 40 kHz, VIN=5VPP,V
IN
=5VPP, where S/(N+D) drops 3 dB 31 kHz
IN
DIFFERENTIAL DYNAMIC CONVERTER CHARACTERISTICS
S/(N+D) Signal-to-Noise Plus f
Distortion Ratio f
−3 dB Full Power Bandwidth V
= 1 kHz, VIN=±5V, V
IN
= 20 kHz, VIN=±5V, V
IN
f
= 40 kHz, VIN=±5V, V
IN
=±5V, where S/(N+D) drops 3 dB 40 kHz
IN
+ = +4.096V, and fully differential input with fixed 2.048V
REF
Limits Units
(Note 10)
±
0.05 LSB
±
0.5 LSB
±
0.5 LSB
±
0.5 LSB
±
0.5 LSB
±
0.5 LSB
+
= 5.0V 69.4 dB
REF
+
= 5.0V 68.3 dB
REF
+ = 5.0V 65.7 dB
REF
+
= 5.0V 77.0 dB
REF
+
= 5.0V 73.9 dB
REF
+
= 5.0V 67.0 dB
REF
(Note 11)
REF
− and V
+
REF
(Limits)
Electrical Characteristics
The following specifications apply for (V+=VA+=VD+ = +5V, V
common-mode voltage) or (V+=VA+=VD+ = +3.3V, V
common-mode voltage), V
≤ 25Ω,fCK=fSK= 5 MHz, and 10 (tCK) acquisition time unless otherwise specified. Boldface limits apply for TA=TJ=
T
MIN
to T
; all other limits TA=TJ= 25˚C. (Notes 7, 8, 9)
MAX
− = 0V, 12-bit + sign conversion mode, source impedance for analog inputs, V
REF
+ = 2.5V and fully-differential input with fixed 1.250V
REF
Symbol Parameter Conditions Typical Limits Units
REFERENCE INPUT, ANALOG INPUTS AND MULTIPLEXER CHARACTERISTICS
C
REF
C
A/D
Reference Input Capacitance 85 pF
A/DIN1 and A/DIN2 Analog Input 75 pF
Capacitance
A/DIN1 and A/DIN2 Analog Input V
Leakage Current V
= +5.0V or
IN
=0V
IN
CH0–CH7 and COM Input Voltage GND − 0.05 V
C
CH
CH0–CH7 and COM Input
Capacitance
C
MUXOUT
MUX Output Capacitance 20 pF
Off Channel Leakage (Note 16) On Channel = 5V and −0.01 µA
CH0–CH7 and COM Pins Off Channel = 0V
On Channel = 0V and 0.01 µA
Off Channel = 5V
+ = +4.096V, and fully differential input with fixed 2.048V
REF
− and V
REF
(Note 10) (Note 11) (Limits)
±
0.1 µA
V
+ + 0.05
A
10 pF
REF
+
www.national.com 6
Electrical Characteristics (Continued)
The following specifications apply for (V+=VA+=VD+ = +5V, V
common-mode voltage) or (V+=VA+=VD+ = +3.3V, V
common-mode voltage), V
≤ 25Ω,fCK=fSK= 5 MHz, and 10 (tCK) acquisition time unless otherwise specified. Boldface limits apply for TA=TJ=
T
MIN
to T
; all other limits TA=TJ= 25˚C. (Notes 7, 8, 9)
MAX
− = 0V, 12-bit + sign conversion mode, source impedance for analog inputs, V
REF
+ = 2.5V and fully-differential input with fixed 1.250V
REF
Symbol Parameter Conditions Typical Limits Units
REFERENCE INPUT, ANALOG INPUTS AND MULTIPLEXER CHARACTERISTICS
On Channel Leakage (Note 16) On Channel = 5V and 0.01 µA
CH0–CH7 and COM Pins Off Channel = 0V
On Channel = 0V and −0.01 µA
Off Channel = 5V
R
ON
MUXOUT1 and MUXOUT2 V
Leakage Current V
MUX On Resistance VIN= 2.5V and 850 1900 Ω (max)
R
Matching Channel to Channel VIN= 2.5V and 5 %
ON
Channel to Channel Crosstalk V
MUXOUT
MUXOUT
V
MUXOUT
V
MUXOUT
=5VPP,fIN= 40 kHz −72 dB
IN
MUX Bandwidth 90 kHz
+ = +4.096V, and fully differential input with fixed 2.048V
REF
− and V
REF
REF
(Note 10) (Note 11) (Limits)
= 5.0V or 0.01 µA
=0V
= 2.4V
= 2.4V
ADC12130/ADC12132/ADC12138
+
DC and Logic Electrical Characteristics
The following specifications apply for (V+=VA+=VD+ = +5V, V
common-mode voltage) or (V
common-mode voltage), V
≤ 25Ω,f
T
to T
MIN
CK=fSK
= 5 MHz, and 10 (tCK) acquisition time unless otherwise specified. Boldface limits apply for TA=TJ=
; all other limits TA=TJ= 25˚C. (Notes 7, 8, 9)
MAX
+
=VA+=VD+ = +3.3V, V
− = 0V, 12-bit + sign conversion mode, source impedance for analog inputs, V
REF
+ = +2.5V and fully-differential input with fixed 1.250V
REF
Symbol Parameter Conditions Typical
CCLK, CS, CONV, DI, PD AND SCLK INPUT CHARACTERISTICS
V
IN(1)
Logical “1” Input
VA+=VD+=V++10% 2.0 2.0 V (min)
Voltage
V
IN(0)
Logical “0” Input
VA+=VD+=V+−10% 0.8 0.8 V (max)
Voltage
I
IN(1)
Logical “1” Input
VIN=V
+
Current
I
IN(0)
Logical “0” Input
VIN= 0V −0.005 −1.0 −1.0 µA (min)
Current
DO, EOC AND DOR DIGITAL OUTPUT CHARACTERISTICS
V
V
I
+I
OUT
OUT(1)
OUT(0)
SC
Logical “1” VA+=VD+=V+− 10%,
Output Voltage I
= −360 µA 2.4 2.4 V (min)
OUT
V
+=VD+=V+− 10%, 2.9 4.25 V (min)
A
I
= −10 µA
OUT
Logical “0” VA+=VD+=V+− 10%
Output Voltage I
TRI-STATE V
Output Current V
Output Short
= 1.6 mA 0.4 0.4 V (max)
OUT
= 0V −0.1 −3.0 −3.0 µA (max)
OUT
OUT
V
OUT
+
=V
= 0V −14 mA
Circuit Source
Current
+ = +4.096V, and fully-differential input with fixed 2.048V
REF
(Note
10)
0.005 1.0 1.0 µA (max)
−0.1 3.0 3.0
− and V
REF
+
=VA+= V+=VA+ = Units
V
+ = 3.3V VD+=5V
V
D
Limits Limits
(Note 11) (Note 11)
+
REF
(Limits)
www.national.com7
DC and Logic Electrical Characteristics (Continued)
The following specifications apply for (V+=VA+=VD+ = +5V, V
common-mode voltage) or (V+=VA+=VD+ = +3.3V, V
common-mode voltage), V
≤ 25Ω,fCK=fSK= 5 MHz, and 10 (tCK) acquisition time unless otherwise specified. Boldface limits apply for TA=TJ=
T
MIN
to T
; all other limits TA=TJ= 25˚C. (Notes 7, 8, 9)
MAX
− = 0V, 12-bit + sign conversion mode, source impedance for analog inputs, V
REF
+ = +2.5V and fully-differential input with fixed 1.250V
REF
Symbol Parameter Conditions Typical
DO, EOC AND DOR DIGITAL OUTPUT CHARACTERISTICS
−I
SC
ADC12130/ADC12132/ADC12138
Output Short
Circuit Sink
V
OUT=VD
+16 mA
Current
POWER SUPPLY CHARACTERISTICS
I
+ Digital Supply 1.5 2.5 mA (max)
D
Current CS = HIGH, Powered Down, CCLK on
CS = HIGH, Powered Down, CCLK off
I
+ Positive Analog 3.0 4.0 mA (max)
A
Supply Current CS = HIGH, Powered Down, CCLK on
CS = HIGH, Powered Down, CCLK off
I
REF
Reference Input
Current CS = HIGH, Powered Down, CCLK on
CS = HIGH, Powered Down, CCLK off
+ = +4.096V, and fully-differential input with fixed 2.048V
REF
− and V
REF
+
=VA+= V+=VA+ = Units
(Note
10)
V
+ = 3.3V VD+=5V
V
D
Limits Limits
(Note 11) (Note 11)
600 µA
20 µA
10 µA
0.1 µA
70 µA
0.1 µA
+
REF
(Limits)
AC Electrical Characteristics
The following specifications apply for (V+=VA+=VD+ = +5V, V
common-mode voltage) or (V
common-mode voltage), V
≤ 25Ω,f
T
to T
MIN
CK=fSK
= 5 MHz, and 10 (tCK) acquisition time unless otherwise specified. Boldface limits apply for TA=TJ=
; all other limits TA=TJ= 25˚C. (Note 17)
MAX
+
=VA+=VD+ = +3.3V, V
− = 0V, 12-bit + sign conversion mode, source impedance for analog inputs, V
REF
+ = +2.5V and fully-differential input with fixed 1.250V
REF
Symbol Parameter Conditions Typical Limits Units
f
CK
Conversion Clock 10 5 MHz (max)
(CCLK) Frequency 1 MHz (min)
f
SK
Serial Data Clock 10 5 MHz (max)
SCLK Frequency 0 Hz (min)
Conversion Clock 40 % (min)
Duty Cycle 60 % (max)
Serial Data Clock 40 % (min)
Duty Cycle 60 % (max)
t
C
Conversion Time 12-Bit + Sign or 12-Bit 44(tCK) 44(tCK) (max)
+ = +4.096V, and fully-differential input with fixed 2.048V
REF
− and V
REF
(Note
10)
(Note
11)
8.8 µs (max)
REF
(Limits)
+
www.national.com 8
AC Electrical Characteristics (Continued)
The following specifications apply for (V+=VA+=VD+ = +5V, V
common-mode voltage) or (V+=VA+=VD+ = +3.3V, V
common-mode voltage), V
≤ 25Ω,fCK=fSK= 5 MHz, and 10 (tCK) acquisition time unless otherwise specified. Boldface limits apply for TA=TJ=
T
MIN
to T
; all other limits TA=TJ= 25˚C. (Note 17)
MAX
− = 0V, 12-bit + sign conversion mode, source impedance for analog inputs, V
REF
+ = +2.5V and fully-differential input with fixed 1.250V
REF
Symbol Parameter Conditions Typical Limits Units
t
A
Acquisition Time 6 Cycles Programmed 6(tCK) 6(tCK) (min)
(Note 19) 7(t
t
CAL
t
AZ
t
SYNC
Self-Calibration Time 4944(tCK) 4944(tCK) (max)
Auto-Zero Time 76(tCK) 76(tCK) (max)
Self-Calibration or 2(tCK) 2(tCK) (min)
Auto-Zero Synchronization 3(t
Time from DOR 0.40 µs (min)
t
DOR
DOR High Time when CS is Low 9(tSK) 9(tSK) (max)
Continuously for Read Data and Software
Power Up/Down
t
CONV
CONV Valid Data Time 8(tSK) 8(tSK) (max)
+ = +4.096V, and fully-differential input with fixed 2.048V
REF
(Note
10)
(Note
11)
CK
1.2 µs (min)
1.4 µs (max)
10 Cycles Programmed 10(t
) 10(tCK) (min)
CK
11(t
CK
2.0 µs (min)
2.2 µs (max)
18 Cycles Programmed 18(t
) 18(tCK) (min)
CK
19(t
CK
3.6 µs (min)
3.8 µs (max)
34 Cycles Programmed 34(t
) 34(tCK) (min)
CK
35(t
CK
6.8 µs (min)
7.0 µs (max)
988.8 µs (max)
15.2 µs (max)
CK
0.60 µs (max)
1.8 µs (max)
1.6 µs (max)
− and V
REF
REF
(Limits)
) (max)
) (max)
) (max)
) (max)
) (max)
ADC12130/ADC12132/ADC12138
+
AC Electrical Characteristics
The following specifications apply for (V+=VA+=VD+ = +5V, V
common-mode voltage) or (V
common-mode voltage), V
≤ 25Ω,f
T
to T
MIN
CK=fSK
= 5 MHz, and 10 (tCK) acquisition time unless otherwise specified. Boldface limits apply for TA=TJ=
; all other limits TA=TJ= 25˚C. (Note 17) (Continued)
MAX
+
=VA+=VD+ = +3.3V, V
− = 0V, 12-bit + sign conversion mode, source impedance for analog inputs, V
REF
+ = +2.5V and fully-differential input with fixed 1.250V
REF
Symbol Parameter Conditions Typical Limits Units
t
HPU
Hardware Power-Up Time, Time from 500 700 µs (max)
PD Falling Edge to EOC Rising Edge
t
SPU
Software Power-Up Time, Time from
Serial Data Clock Falling Edge to 500 700 µs (max)
EOC Rising Edge
t
ACC
Access Time Delay from 25 60 ns (max)
CS Falling Edge to DO Data Valid
+ = +4.096V, and fully-differential input with fixed 2.048V
REF
− and V
REF
(Note 10) (Note 11) (Limits)
www.national.com9
REF
+
AC Electrical Characteristics (Continued)
The following specifications apply for (V+=VA+=VD+ = +5V, V
common-mode voltage) or (V+=VA+=VD+ = +3.3V, V
common-mode voltage), V
≤ 25Ω,fCK=fSK= 5 MHz, and 10 (tCK) acquisition time unless otherwise specified. Boldface limits apply for TA=TJ=
T
MIN
to T
; all other limits TA=TJ= 25˚C. (Note 17) (Continued)
MAX
− = 0V, 12-bit + sign conversion mode, source impedance for analog inputs, V
REF
+ = +2.5V and fully-differential input with fixed 1.250V
REF
Symbol Parameter Conditions Typical Limits Units
t
SET-UP
Set-Up Time of CS Falling Edge to 50 ns (min)
Serial Data Clock Rising Edge
t
DELAY
ADC12130/ADC12132/ADC12138
t1H,t
0H
t
HDI
Delay from SCLK Falling 0 5 ns (min)
Edge to CS Falling Edge
Delay from CS Rising Edge to RL= 3k, CL= 100 pF 70 100 ns (max)
DO TRI-STATE
®
DI Hold Time from Serial Data 5 15 ns (min)
Clock Rising Edge
t
SDI
DI Set-Up Time from Serial Data 5 10 ns (min)
Clock Rising Edge
t
HDO
DO Hold Time from Serial Data RL= 3k, CL= 100 pF 35 65 ns (max)
Clock Falling Edge 5 ns (min)
t
DDO
Delay from Serial Data Clock 50 90 ns (max)
Falling Edge to DO Data Valid
t
RDO
DO Rise Time, TRI-STATE to High RL= 3k, CL= 100 pF 10 40 ns (max)
DO Rise Time, Low to High 10 40 ns (max)
t
FDO
DO Fall Time, TRI-STATE to Low RL= 3k, CL= 100 pF 15 40 ns (max)
DO Fall Time, High to Low 15 40 ns (max)
t
CD
Delay from CS Falling Edge 45 80 ns (max)
to DOR Falling Edge
t
SD
Delay from Serial Data Clock Falling 45 80 ns (max)
Edge to DOR Rising Edge
C
IN
C
OUT
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions.
Note 2: All voltages are measured with respect to GND, unless otherwise specified.
Note 3: When the input voltage (V
The 120 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 30 mA to four.
Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by T
allowable power dissipation at any temperature is P
max = 150˚C. The typical thermal resistance (θJA) of these parts when board mounted follow:
T
J
Capacitance of Logic Inputs 10 pF
Capacitance of Logic Outputs 20 pF
) at any pin exceeds the power supplies (V
IN
=(TJmax − TA)/θJAor the number given in theAbsolute Maximum Ratings, whichever is lower. For this device,
D
+ = +4.096V, and fully-differential input with fixed 2.048V
REF
REF
(Note 10) (Note 11) (Limits)
IN
<
GND or V
>
VA+orVD+), the current at that pin should be limited to 30 mA.
IN
max, θJAand the ambient temperature, TA. The maximum
J
− and V
REF
+
Thermal
Part Number Resistance
θ
JA
ADC12130CIN 53˚C/W
ADC12130CIWM 70˚C/W
ADC12132CIMSA 134˚C/W
ADC12138CIN 40˚C/W
ADC12138CIWM 50˚C/W
ADC12138CIMSA 125˚C/W
Note 5: The human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin.
Note 6: See AN450 “Surface Mounting Methods and Their Effect on Product Reliability” or the section titled “Surface Mount” found in any post 1986 National Semi-
conductor Linear Data Book for other methods of soldering surface mount devices.
www.national.com 10
AC Electrical Characteristics (Continued)
Note 7: Two on-chip diodes are tied to each analog input through a series resistor as shown below. Input voltage magnitude up to 5V above VA+ or 5V below GND
will not damage this device. However,errors in the A/D conversion can occur (if these diodes are forward biased by more than 50 mV) if the input voltage magnitude
of selected or unselected analog input go above V
to ensure accurate conversions.
V
DC
Note 8: To guarantee accuracy, it is required that the V
pin.
Note 9: With the test condition for V
Note 10: Typicals are at T
REF(VREF
= 25˚C and represent most likely parametric norm.
J=TA
Note 11: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 12: Positive integral linearity error is defined as the deviation of the analog value, expressed in LSBs, from the straight line that passes through positive
full-scale and zero. For negative integral linearity error, the straight line passes through negative full-scale and zero (see
Note 13: Zero error is a measure of the deviation from the mid-scale voltage (a code of zero), expressed in LSB. It is the average value of the code transitions be-
tween −1 to 0 and 0 to +1 (see
Figure 4
).
Note 14: Total unadjusted error includes offset, full-scale, linearity and multiplexer errors.
Note 15: The DC common-mode error is measured in the differential multiplexer mode with the assigned positive and negative input channels shorted together.
Note 16: Channel leakage current is measured after the channel selection.
Note 17: Timing specifications are tested at the TTL logic levels, V
to 1.4V.
Note 18: The ADC12130 family’s self-calibration technique ensures linearity and offset errors as specified, but noise inherent in the self-calibration process will re-
sult in a maximum repeatability uncertainty of 0.2 LSB.
Note 19: If SCLK and CCLK are driven from the same clock source, then t
Note 20: The “12-Bit Conversion of Offset” and “12-Bit Conversion of Full-Scale” modes are intended to test the functionality of the device. Therefore, the output
data from these modes are not an indication of the accuracy of a conversion result.
+ or below GND by more than 50 mV. As an example, if VA+ is 4.5 VDC, full-scale input voltage must be ≤4.55
A
DS012079-4
+ and VD+ be connected together to the same power supply with separate bypass capacitors at each V
A
+−V
−) given as +4.096V, the 12-bit LSB is 1.0 mV. For V
REF
= 0.4V for a falling edgeand VOL= 2.4V for a rising edge.TRI-STATEoutput voltage isforced
OL
is 6, 10, 18 or 34 clock periods minimum and maximum.
A
= 2.5V, the 12-bit LSB is 610 µV.
REF
Figure 2
and
Figure 3
).
ADC12130/ADC12132/ADC12138
+
FIGURE 1. Transfer Characteristic
DS012079-5
www.national.com11
AC Electrical Characteristics (Continued)
ADC12130/ADC12132/ADC12138
FIGURE 2. Simplified Error Curve vs Output Code without Auto-Calibration or Auto-Zero Cycles
DS012079-6
FIGURE 3. Simplified Error Curve vs Output Code after Auto-Calibration Cycle
FIGURE 4. Offset or Zero Error Voltage
www.national.com 12
DS012079-7
DS012079-8
Typical Performance Characteristics The following curves apply for 12-bit + sign mode after
auto-calibration unless otherwise specified.
ADC12130/ADC12132/ADC12138
Linearity Error Change
vs Clock Frequency
Linearity Error Change
vs Supply Voltage
DS012079-53
Linearity Error Change
vs Temperature
Full-Scale Error Change
vs Clock Frequency
DS012079-54
Linearity Error Change
vs Reference Voltage
DS012079-55
Full-Scale Error Change
vs Temperature
Full-Scale Error Change
vs Reference Voltage
DS012079-56
DS012079-59
Full-Scale Error Change
vs Supply Voltage
DS012079-57
DS012079-60
DS012079-58
Zero Error Change
vs Clock Frequency
DS012079-61
www.national.com13
Loading...