NSC ADC12041CIV Datasheet

ADC12041
12-Bit Plus Sign 216 kHz Sampling Analog-to-Digital
Converter

ADC12041 12-Bit Plus Sign 216 kHz Sampling Analog-to-Digital Converter

April 2000

General Description

Operating from a single 5V power supply,theADC12041 is a
12 bit + sign, parallel I/O, self-calibrating, sampling
analog-to-digital converter (ADC). The maximum sampling
rate is 216 kHz. On request, the ADC goes through a
self-calibration process that adjusts linearity, zero and
full-scale errors.

TheADC12041 can be configured to work with many popular
microprocessors/microcontrollers and DSPs including Na­tional’s HPC family, Intel386 and 8051, TMS320C25, Mo­torola MC68HC11/16, Hitachi 64180 and Analog Devices
ADSP21xx.

For complementary voltage references see the LM4040,
LM4041 or LM9140.

Features

n Fully differential analog input
n Programmable acquisition times and user-controllable

throughput rates

n Programmable data bus width (8/13 bits)
n Built-in Sample-and-Hold
n Programmable auto-calibration and auto-zero cycles

Block Diagram

n Low power standby mode
n No missing codes

Key Specifications

(f

= 12 MHz)

CLK

n Resolution 12-bits + sign
n 13-bit conversion time 3.6 µs, max
n 13-bit throughput rate 216 ksamples/s, min
n Integral Linearity Error (ILE)
n Single supply +5V
n V

range GND to VA+

IN

n Power consumption

— Normal operation 33 mW, max
— Stand-by mode 75 µw, max

±

1 LSB, max

±

10%

Applications

n Medical instrumentation
n Process control systems
n Test equipment
n Data logging
n Inertial guidance

DS012441-1

TRI-STATE®is a registered trademark of National Semiconductor Corporation.

© 2000 National Semiconductor Corporation DS012441 www.national.com

Connection Diagrams

ADC12041

28-Pin SSOP

DS012441-2

Order Number ADC12041CIMSA

See NS Package Number MSA28

28-Pin PLCC

DS012441-3

Order Number ADC12041CIV

See NS Package Number V28A

Ordering Information

Industrial Temperature Range

−40˚C ≤ T

ADC12041CIV PLCC
ADC12041CIMSA SSOP

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≤ +85˚C

A

NS

Package

Number

Pin Descriptions

PLCC and Pin

SSOP Pkg. Name Description

Pin Number

5
6

10 V

9V

4 WMODE The logic state of this pin at power-up determines which edge of the write signal (WR ) will latch in

27 SYNC The SYNC pin can be programmed as an input or an output. The Configuration register’s bit b4

12–20
23–26

28 CLK The clock input pin used to drive the ADC12041. The operating range is 0.05 MHz to 12 MHz.
1WR

2RD

3CS

11 RDY

7V

8 AGND Analog ground pin. This is the device’s analog supply ground connection. It should be connected

21 V

22 DGND Digital ground pin. This is the device’s digital supply ground connection. It should be connected

V

+

IN

−

V

IN
REF

The analog ADC inputs. V

+ is the non-inverting (positive) input and VIN− is the inverting (negative)

IN

input into the ADC.

+ Positive reference input. The operating voltage range for this input is 1V ≤ V

and

Figure 4

3

). This pin should be bypassed to AGND at least with a parallel combination of a 10

+ ≤ VA+ (see

REF

µF and a 0.1 µF (ceramic) capacitor. The capacitors should be placed as close to the part as
possible.

− Negative reference input. The operating voltage range for this input is 0V ≤ V

REF

Figure 3

and

Figure 4

). This pin should be bypassed to AGND at least with a parallel combination of

REF

− ≤ V

REF

a 10 µF and a 0.1 µF (ceramic) capacitor. The capacitors should be placed as close to the part as
possible.

data from the data bus. If tied low, the ADC12041 will latch in data on the rising edge of the WR
signal. If tied to a logic high, data will be latched in on the falling edge of the WR signal. The state of
this pin should not be changed after power-up.

controls the function of this pin. When programmed as an input pin (b4 = 1), a rising edge on this
pin causes the ADC’s sample-and-hold to hold the analog input signal and begin conversion. When
programmed as an output pin (b4 = 0), the SYNC pin goes high when a conversion begins and
returns low when completed.

D0–D8
D9–D12

13-bit Data bus of the ADC12041. D12 is the most significant bit and D0 is the least significant. The
BW(bus width) bit of the Configuration register (b3) selects between an 8-bit or 13-bit data bus width.
When the BW bit is cleared (BW = 0), D7–D0 are active and D12–D8 are always in TRI-STATE
When the BW bit is set (BW = 1), D12–D0 are active.

WR is the active low WRITE control input pin. A logic low on this pin and the CS will enable the
input buffers of the data pins D12–D0. The signal at this pin is used by the ADC12041 to latch in
data on D12–D0. The sense of the WMODE pin at power-up will determine which edge of the WR
signal the ADC12041 will latch in data. See WMODE pin description.

RD is the active low read control input pin. A logic low on this pin and CS will enable the active
output buffers to drive the data bus.

CS is the active low Chip Select input pin. Used in conjunction with the WR and RD signals to
control the active data bus input/output buffers of the data bus.

RDY is an active low output pin. The signal at this pin indicates when a requested function has
begun or ended. Refer to section Functional Description and the digital timing diagrams for more
detail.

+ Analog supply input pin. The device operating supply voltage range is +5V±10%. Accuracy is

A

guaranteed only if the V

+ and VD+ are connected to the same potential. This pin should be

A

bypassed to AGND with a parallel combination of a 10 µF and a 0.1 µF (ceramic) capacitor. The
capacitors should be placed as close to the supply pins of the part as possible.

through a low resistance and low inductance ground return to the system power supply.

+ Digital supply input pins. The device operating supply voltage range is +5V±10%. Accuracy is

D

guaranteed only if the V

+ and VD+ are connected to the same potential. This pin should be

A

bypassed to DGND with a parallel combination of a 10 µF and a 0.1 µF (ceramic) capacitor. The
capacitors should be placed as close to the supply pins of the part as possible.

through a low resistance and low inductance ground return to the system power supply.

Figure

+ −1 (see

ADC12041

®

.

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Absolute Maximum Ratings (Notes 1, 2)

Operating Ratings (Notes 1, 2, 6, 7, 8, 9)

Supply Voltage (V
Voltage at all Inputs −0.3V to V

ADC12041

+−VD+| 300 mV

|V

A

+ and VD+) 6.0V

A

|AGND − DGND| 300 mV
Input Current at Any Pin (Note 3)
Package Input Current (Note 3)
Power Dissipation (Note 4)

= 25˚C 500 mW

at T

A

Storage Temperature −65˚C to +150˚C
Lead Temperature

SSOP Package

Vapor Phase (60 sec.) 210˚C
Infared (15 sec.) 220˚C

+

+ 0.3V

±

30 mA

±

120 mA

Temperature Range

(T

min

≤ TA≤ T

) −40˚C ≤ TA≤ 85˚C

max

Supply Voltage

+, VD+ 4.5V to 5.5V

V

A

+−VD+| ≤100 mV

|V

A

|AGND − DGND| ≤100 mV

Voltage

V

IN

Range at all Inputs GND ≤ V

+ Input Voltage 1V ≤ V

V

REF

− Input Voltage 0 ≤ V

V

REF

+−V

V

REF

Common Mode

V

REF

(Note 16) 0.1 V

−1V≤V

REF

+ ≤ V

A

REF

REF

− ≤ V

REFCM

V Package, Infared (15 sec.) 300˚C

ESD Susceptibility (Note 5) 3.0 kV

Converter DC Characteristics

The following specifications apply to the ADC12041 for VA+=VD+ = 5V, V
version mode, f

2.048V common-mode voltage (V

T

A=TJ=TMIN

= 12.0 MHz, RS=25Ω, source impedance for V

CLK

to T

; all other limits TA=TJ= 25˚C

MAX

), and minimum acquisition time, unless otherwise specified. Boldface limits apply for

INCM

REF

Symbol Parameter Conditions Typical Limits Units

Resolution with No Missing Codes After Auto-Cal 13 Bits (max)

ILE Positive and Negative Integral After Auto-Cal

Linearity Error (Notes 12, 17)

DNL Differential Non-Linearity After Auto-Cal

Zero Error After Auto-Cal (Notes 13, 17)

V

= 5.0V

INCM

V

= 2.048V

INCM

V

=0V

INCM

Positive Full-Scale Error After Auto-Cal (Notes 12, 17)
Negative Full-Scale Error After Auto-Cal (Notes 12, 17)
DC Common Mode Error After Auto-Cal (Note 14)

TUE Total Unadjusted Error After Auto-Cal (Note 18)

REF

+ and V

+ = 4.096V, V

− ≤ 1Ω, fully differential input with fixed

REF

− = 0.0V, 12-bit + sign con-

REF

(Note 10) (Note 11) (Limit)

±

0.6

±

1.0

±

1.0

±

2

±

1 LSB

±

1

±

1 LSB (max)

±

5.5 LSB (max)

±

2.0 LSB (max)

±

5.5 LSB (max)

±

2.5 LSB (max)

±

2.5 LSB (max)

±

5.5 LSB (max)

+ ≤ VA+

IN

+ ≤ VA+

+−1V

REF

≤ VA+

REF

≤ 0.6 VA+

LSB (max)

Power Supply Characteristics

The following specifications apply to the ADC12041 for VA+=VD+ = 5V, V
sion mode, f
common-mode voltage, and minimum acquisition time, unless otherwise specified. Boldface limits apply for T

to T

; all other limits TA=TJ= 25˚C

MAX

= 12.0 MHz, RS=25Ω, source impedance for V

CLK

REF

+ and V

Symbol Parameter Conditions Typical Limits Unit

PSS Power Supply Sensitivity V

Zero Error V
Full-Scale Error V

+=VA+ = 5.0V±10% (Note 15)

D

+ = 4.096V

REF

−=0V

REF

Linearity Error

I

+V

D

+ Digital Supply Current Start Command (Performing a conversion)

D

with SYNC configured as an input and driven
with a 214 kHz signal. Bus width set to 13.

f

= 12.0 MHz, Reset Mode 850 µA

CLK

f

= 12.0 MHz, Conversion 2.45 2.6 mA (max)

CLK

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+ = 4.096V, V

REF

−1Ω, fully differential input with fixed 2.048V

REF

− = 0.0V, 12-bit + sign conver-

REF

A=TJ=TMIN

(Note 10) (Note 11) (Limit)

±

0.1 LSB

±

0.5 LSB

±

0.1 LSB

Power Supply Characteristics (Continued)

The following specifications apply to the ADC12041 for VA+=VD+ = 5V, V
sion mode, f
common-mode voltage, and minimum acquisition time, unless otherwise specified. Boldface limits apply for T

to T

; all other limits TA=TJ= 25˚C

MAX

= 12.0 MHz, RS=25Ω, source impedance for V

CLK

REF

+ and V

Symbol Parameter Conditions Typical Limits Unit

I

+V

A

+ Analog Supply Current Start Command (Performing a conversion)

A

with SYNC configured as an input and driven
with a 214 kHz signal. Bus width set to 13.

f

= 12.0 MHz, Reset Mode 2.3 mA

CLK

f

= 12.0 MHz, Conversion 2.3 4.0 mA (max)

CLK

I

ST

Standby Supply Current Standby Mode
(I

++IA+) f

D

= Stopped 5 15 µA (max)

CLK

f

= 12.0 MHz 100 120 µA (max)

CLK

+ = 4.096V, V

REF

−1Ω, fully differential input with fixed 2.048V

REF

− = 0.0V, 12-bit + sign conver-

REF

A=TJ=TMIN

(Note 10) (Note 11) (Limit)

Analog Input Characteristics

The following specifications apply to the ADC12041 for VA+=VD+ = 5V, V
sion mode, f
common-mode voltage, and minimum acquisition time, unless otherwise specified. Boldface limits apply for TA=TJ=T

to T

; all other limits TA=TJ= 25˚C

MAX

= 12.0 MHz, RS=25Ω, source impedance for V

CLK

REF

+ and V

Symbol Parameter Conditions Typical Limits Unit

I

R

IN

VIN+ and VIN− Input Leakage Current VIN+=5V

V

−=0V

IN

ADC Input On Resistance VIN= 2.5V 1000 Ω

ON

Refer to section titled INPUT CURRENT.

CV

ADC Input Capacitance 10 pF

IN

+ = 4.096V, V

REF

+ ≤ 1Ω, fully differential input with fixed 2.048V

REF

− = 0.0V, 12-Bit + sign conver-

REF

(Note 10) (Note 11) (Limit)

±

0.05 2.0 µA (max)

MIN

ADC12041

Reference Inputs

The following specifications apply to the ADC12041 for VA+=VD+ = 5V, V
version mode, f

2.048V common-mode voltage, and minimum acquisition time, unless otherwise specified. Boldface limits apply for T

=T

to T

MIN

MAX

= 12.0 MHz, RS=25Ω, source impedance for V

CLK

; all other limits TA=TJ= 25˚C

REF

Symbol Parameter Conditions Typical Limits Unit

I

REF

Reference Input Current V

+ 4.096V, V

REF

REF

−=0V
Analog Input Signal: 1 kHz 145 µA
(Note 20) 80 kHz 136 µA

C

REF

Reference Input Capacitance 85 pF

REF

+ and V

+ = 4.096V, V

− ≤ 1Ω, fully differential input with fixed

REF

− = 0.0V, 12-bit + sign con-

REF

(Note 10) (Note 11) (Limit)

A=TJ

Digital Logic Input/Output Characteristics

The following specifications apply to the ADC12041 for VA+=VD+ = 5V, V
version mode, f

2.048V common-mode voltage, and minimum acquisition time, unless otherwise specified. Boldface limits apply for TA=T

=T

to T

MIN

= 12.0 MHz, RS=25Ω, source impedance for V

CLK

; all other limits TA=TJ= 25˚C

MAX

REF

Symbol Parameter Conditions Typical Limits Unit

V

IH

V

IL

I

IH

I

IL

V

OH

Logic High Input Voltage VA+=VD+ = 5.5V 2.2 V (min)
Logic Low Input Voltage VA+=VD+ = 4.5V 0.8 V (max)
Logic High Input Current VIN= 5V 0.035 2.0 µA (max)
Logic Low Input Current VIN= 0V −0.035 −2.0 µA (max)
Logic High Output Voltage VA+=VD+ = 4.5V

= −1.6 mA

I

OUT

REF

+ and V

+ = 4.096V, V

− ≤ 1Ω, fully differential input with fixed

REF

− = 0.0V, 12-bit + sign con-

REF

(Note 10) (Note 11) (Limit)

2.4 2.4 V (min)

J

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Digital Logic Input/Output Characteristics (Continued)

The following specifications apply to the ADC12041 for VA+=VD+ = 5V, V
version mode, f

ADC12041

2.048V common-mode voltage, and minimum acquisition time, unless otherwise specified. Boldface limits apply for T

=T

to T

MIN

MAX

= 12.0 MHz, RS=25Ω, source impedance for V

CLK

; all other limits TA=TJ= 25˚C

REF

Symbol Parameter Conditions Typical Limits Unit

V

OL

I

OFF

C

IN

Logic Low Output Voltage VA+=VD+ = 4.5V

= 1.6 mA

I

OUT

TRI-STATE Output Leakage Current V

=0V

OUT

=5V

V

OUT

D12–D0 Input Capacitance 10 pF

REF

+ and V

+ = 4.096V, V

− ≤ 1Ω, fully differential input with fixed

REF

− = 0.0V, 12-bit + sign con-

REF

(Note 10) (Note 11) (Limit)

0.4 0.4 V (max)

±

2.0 µA (max)

Converter AC Characteristics

The following specifications apply to the ADC12041 for VS+=VD+ = 5V, V
version mode, f

2.048V common-mode voltage, and minimum acquisition time, unless otherwise specified. Boldface limits apply for T

=T

to T

MIN

MAX

= 12.0 MHz, RS=25Ω, source impedance for V

CLK

; all other limits TA=TJ= 25˚C

REF

Symbol Parameter Conditions Typical Limits Unit

t
t

Z
CAL

Auto Zero Time 78 78 clks + 120 ns clks (max)
Full Calibration Time 4946 4946 clks + 120 ns clks (max)
CLK Duty Cycle 50 %

t

CONV

t

AcqSYNCOUT

Conversion Time Sync-Out Mode 44 44 clks (max)
Acquisition Time Minimum for 13 Bits 9 9 clks + 120 ns clks (max)
(Programmable) Maximum for 13 Bits 79 79 clks + 120 ns clks (max)

REF

+ and V

+ = 4.096V, V

− ≤ 1Ω, fully differential input with fixed

REF

− = 0.0V, 12-bit + sign con-

REF

(Note 10) (Note 11) (Limit)

40 % (min)
60 % (max)

A=TJ

A=TJ

Digital Timing Characteristics

The following specifications apply to the ADC12041, 13-bit data bus width, VA+=VD+ = 5V, f

= 50 pF on data I/O lines

Symbol Parameter Conditions Typical Limits Unit

t

TPR

Throughput Rate Sync-Out Mode (SYNC Bit = “0”)

9 Clock Cycles of Acquisition Time

t

CSWR

Falling Edge of CS 0ns
to Falling Edge of WR

t

WRCS

Active Edge of WR 0ns
to Rising Edge of CS

t

WR

t

WRSETFalling

t

WRHOLDFalling

t

WRSETRising

t

WRHOLDRising

t

CSRD

WR Pulse Width 20 30 ns (min)
Write Setup Time WMODE = “1” 20 ns (min)
Write Hold Time WMODE = “1” 5 ns (min)
Write Setup Time WMODE = “0” 20 ns (min)
Write Hold Time WMODE = “0” 5 ns (min)
Falling Edge of CS to Falling

Edge of RD

t

RDCS

Rising Edge of RD 0ns
to Rising Edge of CS

t

RDDATA

t

RDDATA

t

RDHOLD

Falling Edge of RD to Valid Data 8-Bit Mode (BW Bit = “0”) 40 58 ns (max)
Falling Edge of RD to Valid Data 13-Bit Mode (BW Bit = “1”) 26 44 ns (max)
Read Hold Time 23 32 ns (max)

= 12 MHz, tf= 3 ns and C

CLK

(Note 10) (Note 11) (Limit)

222 kHz

0ns

L

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Digital Timing Characteristics (Continued)

The following specifications apply to the ADC12041, 13-bit data bus width, VA+=VD+ = 5V, f
= 50 pF on data I/O lines

Symbol Parameter Conditions Typical Limits Unit

t

RDRDY

Rising Edge of RD
to Rising Edge of RDY

t

WRRDY

Active Edge of WR

WMODE = “1”

to Rising Edge of RDY

t

STDRDY

Active Edge of WR WMODE = “0”. Writing the

RESET Command into the
Configuration Register

t

SYNC

Minimum SYNC Pulse Width 5 10 ns (min)

= 12 MHz, tf= 3 ns and C

CLK

(Note 10) (Note 11) (Limit)

24 38 ns (max)

37 60 ns (max)

1.4 2.5 ms (max)to Falling Edge of RDY

Notes on Specifications

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is

functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test condi­tions.

Note 2: All voltages are measured with respect to GND, unless otherwise specified.
Note 3: When the input voltage (V

mA. The 120 mA maximum package input current limits the number of pins that can safely exceed the power supplies with an input current of 30 mA to four.
Note 4: The maximum power dissipation must he derated at elevated temperatures and is dictated by T

tion to ambient thermal resistance), and T
the number given in theAbsolute Maximum Ratings, whichever is lower. For this device, T
in the V package, when board mounted, is 55˚C/W, and in the SSOP package, when board mounted, is 130˚C/W.

Note 5: Human body model, 100 pF discharged through 1.5 Ωk resistor.
Note 6: Each input is protected by a nominal 6.5V breakdown voltage zener diode to GND, as shown below, input voltage magnitude up to 5V above V

below GND will not damage the ADC12041. There are parasitic diodes that exist between the inputs and the power supply rails and errors in the A/D conversion
can occur if these diodes are forward biased by more than 50 mV.As an example, if V
conversions.

) at any pin exceeds the power supply rails (V

IN

(ambient temperature). The maximum allowable power dissipation at any temperature is P

A

<

GND or V

IN

+ is 4.50 VDC, full-scale input voltage must be 4.55 VDCto ensure accurate

A

>

(VA+orVD+)), the current at that pin should be limited to 30

IN

, (maximum junction temperature), θJA(package junc-

Jmax

= 150˚C, and the typical thermal resistance (θJA) of the ADC12041

Jmax

Dmax

=(T

Jmax−TA

A

ADC12041

L

)/θJAor

+or5V

DS012441-4

Note 7: V
comparison accuracy. Refer to the Power Supply Considerations section for a detailed discussion.

Note 8: Accuracy is guaranteed when operating at f
Note 9: With the test condition for V
Note 10: Typicals are at T
Note 11: Limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 12: Positive integral linearity error is defined as the deviation of the analog value, expressed in LSBs, from the straight line that passes through positive

full-scale and zero. For negative integral linearity error, the straight line passes through negative full-scale and zero.
Note 13: Zero error is a measure of the deviation from the mid-scale voltage (a code of zero), expressed in LSB. It is the average value of the code transitions be-

tween −1 to 0 and 0 to + 1 (see
Note 14: The DC common-mode error is measured with both inputs shorted together and driven from 0V to 5V. The measured value is referred to the resulting out-

put value when the inputs are driven with a 2.5V input.

Note 15: Power Supply Sensitivity is measured after an Auto-Zero and Auto Calibration cycle has been completed with V
Note 16: V

+ and VD+ must be connected together to the same power supply voltage and bypassed with separate capacitors at each V+pin to assure conversion/

A

= 12 MHz.

CLK

+−V

REF(VREF

= 25˚C and represent most likely parametric norm.

A

Figure 8

).

(Reference Voltage Common Mode Range) is defined as

REFCM

−) given as + 4.096V, the 12-bit LSB is 1.000 mV.

REF

+ and VD+ at the specified extremes.

A

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Notes on Specifications (Continued)

Note 17: The ADC12041’s self-calibration technique ensures linearity and offset errors as specified, but noise inherent in the self-calibration process will result in

a repeatability uncertainty of

ADC12041

Note 18: Total Unadjusted Error (TUE) includes offset, full scale linearity and MUX errors.
Note 19: The ADC12041 parts used to gather the information for these curves were auto-calibrated prior to taking the measurements at each test condition. The

auto-calibration cycle cancels any first order drifts due to test conditions. However, each measurement has a repeatability uncertainty error of 0.2 LSB. See Note

17.
Note 20: The reference input current is a DC average current drawn by the reference input with a full-scale sinewave input. The ADC12041 is continuously con-

verting with a throughput rate of 206 kHz.
Note 21: These typical curves were measured during continuous conversions with a positive half-scale DC input. A 240 ns RD pulse was applied 25 ns after the

RDY signal went low. The data bus lines were loaded with 2 HC family CMOS inputs (CL∼ 20 pF).
Note 22: Any other values placed in the command field are meaningless. However, if a code of 101 or 110 is placed in the command field and the CS , RD and WR

go low at the same time, theADC12041 will enter a test mode. These test modes are only to be used by the manufacturer of this device. A hardware power-off and
power-on reset must be done to get out of these test modes.

±

0.20 LSB.

Electrical Characteristics

FIGURE 1. Output Digital Code vs the Operating Input Voltage Range (General Case)

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DS012441-5

Electrical Characteristics (Continued)

ADC12041

FIGURE 2. Output Digital Code vs the Operating Input Voltage Range for V

REF

DS012441-6

= 4.096V

FIGURE 3. V

Operating Range (General Case)

REF

DS012441-7

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