ADC12041
12-Bit Plus Sign 216 kHz Sampling Analog-to-Digital
Converter
ADC12041 12-Bit Plus Sign 216 kHz Sampling Analog-to-Digital Converter
April 2000
General Description
Operating from a single 5V power supply,theADC12041 is a
12 bit + sign, parallel I/O, self-calibrating, sampling
analog-to-digital converter (ADC). The maximum sampling
rate is 216 kHz. On request, the ADC goes through a
self-calibration process that adjusts linearity, zero and
full-scale errors.
TheADC12041 can be configured to work with many popular
microprocessors/microcontrollers and DSPs including National’s HPC family, Intel386 and 8051, TMS320C25, Motorola MC68HC11/16, Hitachi 64180 and Analog Devices
ADSP21xx.
For complementary voltage references see the LM4040,
LM4041 or LM9140.
Features
n Fully differential analog input
n Programmable acquisition times and user-controllable
throughput rates
n Programmable data bus width (8/13 bits)
n Built-in Sample-and-Hold
n Programmable auto-calibration and auto-zero cycles
Block Diagram
n Low power standby mode
n No missing codes
Key Specifications
(f
= 12 MHz)
CLK
n Resolution 12-bits + sign
n 13-bit conversion time 3.6 µs, max
n 13-bit throughput rate 216 ksamples/s, min
n Integral Linearity Error (ILE)
n Single supply +5V
n V
range GND to VA+
IN
n Power consumption
— Normal operation 33 mW, max
— Stand-by mode 75 µw, max
±
1 LSB, max
±
10%
Applications
n Medical instrumentation
n Process control systems
n Test equipment
n Data logging
n Inertial guidance
DS012441-1
TRI-STATE®is a registered trademark of National Semiconductor Corporation.
© 2000 National Semiconductor Corporation DS012441 www.national.com
Connection Diagrams
ADC12041
28-Pin SSOP
DS012441-2
Order Number ADC12041CIMSA
See NS Package Number MSA28
28-Pin PLCC
DS012441-3
Order Number ADC12041CIV
See NS Package Number V28A
Ordering Information
Industrial Temperature Range
−40˚C ≤ T
ADC12041CIV PLCC
ADC12041CIMSA SSOP
www.national.com 2
≤ +85˚C
A
NS
Package
Number
Pin Descriptions
PLCC and Pin
SSOP Pkg. Name Description
Pin Number
5
6
10 V
9V
4 WMODE The logic state of this pin at power-up determines which edge of the write signal (WR ) will latch in
27 SYNC The SYNC pin can be programmed as an input or an output. The Configuration register’s bit b4
12–20
23–26
28 CLK The clock input pin used to drive the ADC12041. The operating range is 0.05 MHz to 12 MHz.
1WR
2RD
3CS
11 RDY
7V
8 AGND Analog ground pin. This is the device’s analog supply ground connection. It should be connected
21 V
22 DGND Digital ground pin. This is the device’s digital supply ground connection. It should be connected
V
+
IN
−
V
IN
REF
The analog ADC inputs. V
+ is the non-inverting (positive) input and VIN− is the inverting (negative)
IN
input into the ADC.
+ Positive reference input. The operating voltage range for this input is 1V ≤ V
and
Figure 4
3
). This pin should be bypassed to AGND at least with a parallel combination of a 10
+ ≤ VA+ (see
REF
µF and a 0.1 µF (ceramic) capacitor. The capacitors should be placed as close to the part as
possible.
− Negative reference input. The operating voltage range for this input is 0V ≤ V
REF
Figure 3
and
Figure 4
). This pin should be bypassed to AGND at least with a parallel combination of
REF
− ≤ V
REF
a 10 µF and a 0.1 µF (ceramic) capacitor. The capacitors should be placed as close to the part as
possible.
data from the data bus. If tied low, the ADC12041 will latch in data on the rising edge of the WR
signal. If tied to a logic high, data will be latched in on the falling edge of the WR signal. The state of
this pin should not be changed after power-up.
controls the function of this pin. When programmed as an input pin (b4 = 1), a rising edge on this
pin causes the ADC’s sample-and-hold to hold the analog input signal and begin conversion. When
programmed as an output pin (b4 = 0), the SYNC pin goes high when a conversion begins and
returns low when completed.
D0–D8
D9–D12
13-bit Data bus of the ADC12041. D12 is the most significant bit and D0 is the least significant. The
BW(bus width) bit of the Configuration register (b3) selects between an 8-bit or 13-bit data bus width.
When the BW bit is cleared (BW = 0), D7–D0 are active and D12–D8 are always in TRI-STATE
When the BW bit is set (BW = 1), D12–D0 are active.
WR is the active low WRITE control input pin. A logic low on this pin and the CS will enable the
input buffers of the data pins D12–D0. The signal at this pin is used by the ADC12041 to latch in
data on D12–D0. The sense of the WMODE pin at power-up will determine which edge of the WR
signal the ADC12041 will latch in data. See WMODE pin description.
RD is the active low read control input pin. A logic low on this pin and CS will enable the active
output buffers to drive the data bus.
CS is the active low Chip Select input pin. Used in conjunction with the WR and RD signals to
control the active data bus input/output buffers of the data bus.
RDY is an active low output pin. The signal at this pin indicates when a requested function has
begun or ended. Refer to section Functional Description and the digital timing diagrams for more
detail.
+ Analog supply input pin. The device operating supply voltage range is +5V±10%. Accuracy is
A
guaranteed only if the V
+ and VD+ are connected to the same potential. This pin should be
A
bypassed to AGND with a parallel combination of a 10 µF and a 0.1 µF (ceramic) capacitor. The
capacitors should be placed as close to the supply pins of the part as possible.
through a low resistance and low inductance ground return to the system power supply.
+ Digital supply input pins. The device operating supply voltage range is +5V±10%. Accuracy is
D
guaranteed only if the V
+ and VD+ are connected to the same potential. This pin should be
A
bypassed to DGND with a parallel combination of a 10 µF and a 0.1 µF (ceramic) capacitor. The
capacitors should be placed as close to the supply pins of the part as possible.
through a low resistance and low inductance ground return to the system power supply.
Figure
+ −1 (see
ADC12041
®
.
www.national.com3
Absolute Maximum Ratings (Notes 1, 2)
Operating Ratings (Notes 1, 2, 6, 7, 8, 9)
Supply Voltage (V
Voltage at all Inputs −0.3V to V
ADC12041
+−VD+| 300 mV
|V
A
+ and VD+) 6.0V
A
|AGND − DGND| 300 mV
Input Current at Any Pin (Note 3)
Package Input Current (Note 3)
Power Dissipation (Note 4)
= 25˚C 500 mW
at T
A
Storage Temperature −65˚C to +150˚C
Lead Temperature
SSOP Package
Vapor Phase (60 sec.) 210˚C
Infared (15 sec.) 220˚C
+
+ 0.3V
±
30 mA
±
120 mA
Temperature Range
(T
min
≤ TA≤ T
) −40˚C ≤ TA≤ 85˚C
max
Supply Voltage
+, VD+ 4.5V to 5.5V
V
A
+−VD+| ≤100 mV
|V
A
|AGND − DGND| ≤100 mV
Voltage
V
IN
Range at all Inputs GND ≤ V
+ Input Voltage 1V ≤ V
V
REF
− Input Voltage 0 ≤ V
V
REF
+−V
V
REF
Common Mode
V
REF
(Note 16) 0.1 V
−1V≤V
REF
+ ≤ V
A
REF
REF
− ≤ V
REFCM
V Package, Infared (15 sec.) 300˚C
ESD Susceptibility (Note 5) 3.0 kV
Converter DC Characteristics
The following specifications apply to the ADC12041 for VA+=VD+ = 5V, V
version mode, f
2.048V common-mode voltage (V
T
A=TJ=TMIN
= 12.0 MHz, RS=25Ω, source impedance for V
CLK
to T
; all other limits TA=TJ= 25˚C
MAX
), and minimum acquisition time, unless otherwise specified. Boldface limits apply for
INCM
REF
Symbol Parameter Conditions Typical Limits Units
Resolution with No Missing Codes After Auto-Cal 13 Bits (max)
ILE Positive and Negative Integral After Auto-Cal
Linearity Error (Notes 12, 17)
DNL Differential Non-Linearity After Auto-Cal
Zero Error After Auto-Cal (Notes 13, 17)
V
= 5.0V
INCM
V
= 2.048V
INCM
V
=0V
INCM
Positive Full-Scale Error After Auto-Cal (Notes 12, 17)
Negative Full-Scale Error After Auto-Cal (Notes 12, 17)
DC Common Mode Error After Auto-Cal (Note 14)
TUE Total Unadjusted Error After Auto-Cal (Note 18)
REF
+ and V
+ = 4.096V, V
− ≤ 1Ω, fully differential input with fixed
REF
− = 0.0V, 12-bit + sign con-
REF
(Note 10) (Note 11) (Limit)
±
0.6
±
1.0
±
1.0
±
2
±
1 LSB
±
1
±
1 LSB (max)
±
5.5 LSB (max)
±
2.0 LSB (max)
±
5.5 LSB (max)
±
2.5 LSB (max)
±
2.5 LSB (max)
±
5.5 LSB (max)
+ ≤ VA+
IN
+ ≤ VA+
+−1V
REF
≤ VA+
REF
≤ 0.6 VA+
LSB (max)
Power Supply Characteristics
The following specifications apply to the ADC12041 for VA+=VD+ = 5V, V
sion mode, f
common-mode voltage, and minimum acquisition time, unless otherwise specified. Boldface limits apply for T
to T
; all other limits TA=TJ= 25˚C
MAX
= 12.0 MHz, RS=25Ω, source impedance for V
CLK
REF
+ and V
Symbol Parameter Conditions Typical Limits Unit
PSS Power Supply Sensitivity V
Zero Error V
Full-Scale Error V
+=VA+ = 5.0V±10% (Note 15)
D
+ = 4.096V
REF
−=0V
REF
Linearity Error
I
+V
D
+ Digital Supply Current Start Command (Performing a conversion)
D
with SYNC configured as an input and driven
with a 214 kHz signal. Bus width set to 13.
f
= 12.0 MHz, Reset Mode 850 µA
CLK
f
= 12.0 MHz, Conversion 2.45 2.6 mA (max)
CLK
www.national.com 4
+ = 4.096V, V
REF
−1Ω, fully differential input with fixed 2.048V
REF
− = 0.0V, 12-bit + sign conver-
REF
A=TJ=TMIN
(Note 10) (Note 11) (Limit)
±
0.1 LSB
±
0.5 LSB
±
0.1 LSB
Power Supply Characteristics (Continued)
The following specifications apply to the ADC12041 for VA+=VD+ = 5V, V
sion mode, f
common-mode voltage, and minimum acquisition time, unless otherwise specified. Boldface limits apply for T
to T
; all other limits TA=TJ= 25˚C
MAX
= 12.0 MHz, RS=25Ω, source impedance for V
CLK
REF
+ and V
Symbol Parameter Conditions Typical Limits Unit
I
+V
A
+ Analog Supply Current Start Command (Performing a conversion)
A
with SYNC configured as an input and driven
with a 214 kHz signal. Bus width set to 13.
f
= 12.0 MHz, Reset Mode 2.3 mA
CLK
f
= 12.0 MHz, Conversion 2.3 4.0 mA (max)
CLK
I
ST
Standby Supply Current Standby Mode
(I
++IA+) f
D
= Stopped 5 15 µA (max)
CLK
f
= 12.0 MHz 100 120 µA (max)
CLK
+ = 4.096V, V
REF
−1Ω, fully differential input with fixed 2.048V
REF
− = 0.0V, 12-bit + sign conver-
REF
A=TJ=TMIN
(Note 10) (Note 11) (Limit)
Analog Input Characteristics
The following specifications apply to the ADC12041 for VA+=VD+ = 5V, V
sion mode, f
common-mode voltage, and minimum acquisition time, unless otherwise specified. Boldface limits apply for TA=TJ=T
to T
; all other limits TA=TJ= 25˚C
MAX
= 12.0 MHz, RS=25Ω, source impedance for V
CLK
REF
+ and V
Symbol Parameter Conditions Typical Limits Unit
I
R
IN
VIN+ and VIN− Input Leakage Current VIN+=5V
V
−=0V
IN
ADC Input On Resistance VIN= 2.5V 1000 Ω
ON
Refer to section titled INPUT CURRENT.
CV
ADC Input Capacitance 10 pF
IN
+ = 4.096V, V
REF
+ ≤ 1Ω, fully differential input with fixed 2.048V
REF
− = 0.0V, 12-Bit + sign conver-
REF
(Note 10) (Note 11) (Limit)
±
0.05 2.0 µA (max)
MIN
ADC12041
Reference Inputs
The following specifications apply to the ADC12041 for VA+=VD+ = 5V, V
version mode, f
2.048V common-mode voltage, and minimum acquisition time, unless otherwise specified. Boldface limits apply for T
=T
to T
MIN
MAX
= 12.0 MHz, RS=25Ω, source impedance for V
CLK
; all other limits TA=TJ= 25˚C
REF
Symbol Parameter Conditions Typical Limits Unit
I
REF
Reference Input Current V
+ 4.096V, V
REF
REF
−=0V
Analog Input Signal: 1 kHz 145 µA
(Note 20) 80 kHz 136 µA
C
REF
Reference Input Capacitance 85 pF
REF
+ and V
+ = 4.096V, V
− ≤ 1Ω, fully differential input with fixed
REF
− = 0.0V, 12-bit + sign con-
REF
(Note 10) (Note 11) (Limit)
A=TJ
Digital Logic Input/Output Characteristics
The following specifications apply to the ADC12041 for VA+=VD+ = 5V, V
version mode, f
2.048V common-mode voltage, and minimum acquisition time, unless otherwise specified. Boldface limits apply for TA=T
=T
to T
MIN
= 12.0 MHz, RS=25Ω, source impedance for V
CLK
; all other limits TA=TJ= 25˚C
MAX
REF
Symbol Parameter Conditions Typical Limits Unit
V
IH
V
IL
I
IH
I
IL
V
OH
Logic High Input Voltage VA+=VD+ = 5.5V 2.2 V (min)
Logic Low Input Voltage VA+=VD+ = 4.5V 0.8 V (max)
Logic High Input Current VIN= 5V 0.035 2.0 µA (max)
Logic Low Input Current VIN= 0V −0.035 −2.0 µA (max)
Logic High Output Voltage VA+=VD+ = 4.5V
= −1.6 mA
I
OUT
REF
+ and V
+ = 4.096V, V
− ≤ 1Ω, fully differential input with fixed
REF
− = 0.0V, 12-bit + sign con-
REF
(Note 10) (Note 11) (Limit)
2.4 2.4 V (min)
J
www.national.com5
Digital Logic Input/Output Characteristics (Continued)
The following specifications apply to the ADC12041 for VA+=VD+ = 5V, V
version mode, f
ADC12041
2.048V common-mode voltage, and minimum acquisition time, unless otherwise specified. Boldface limits apply for T
=T
to T
MIN
MAX
= 12.0 MHz, RS=25Ω, source impedance for V
CLK
; all other limits TA=TJ= 25˚C
REF
Symbol Parameter Conditions Typical Limits Unit
V
OL
I
OFF
C
IN
Logic Low Output Voltage VA+=VD+ = 4.5V
= 1.6 mA
I
OUT
TRI-STATE Output Leakage Current V
=0V
OUT
=5V
V
OUT
D12–D0 Input Capacitance 10 pF
REF
+ and V
+ = 4.096V, V
− ≤ 1Ω, fully differential input with fixed
REF
− = 0.0V, 12-bit + sign con-
REF
(Note 10) (Note 11) (Limit)
0.4 0.4 V (max)
±
2.0 µA (max)
Converter AC Characteristics
The following specifications apply to the ADC12041 for VS+=VD+ = 5V, V
version mode, f
2.048V common-mode voltage, and minimum acquisition time, unless otherwise specified. Boldface limits apply for T
=T
to T
MIN
MAX
= 12.0 MHz, RS=25Ω, source impedance for V
CLK
; all other limits TA=TJ= 25˚C
REF
Symbol Parameter Conditions Typical Limits Unit
t
t
Z
CAL
Auto Zero Time 78 78 clks + 120 ns clks (max)
Full Calibration Time 4946 4946 clks + 120 ns clks (max)
CLK Duty Cycle 50 %
t
CONV
t
AcqSYNCOUT
Conversion Time Sync-Out Mode 44 44 clks (max)
Acquisition Time Minimum for 13 Bits 9 9 clks + 120 ns clks (max)
(Programmable) Maximum for 13 Bits 79 79 clks + 120 ns clks (max)
REF
+ and V
+ = 4.096V, V
− ≤ 1Ω, fully differential input with fixed
REF
− = 0.0V, 12-bit + sign con-
REF
(Note 10) (Note 11) (Limit)
40 % (min)
60 % (max)
A=TJ
A=TJ
Digital Timing Characteristics
The following specifications apply to the ADC12041, 13-bit data bus width, VA+=VD+ = 5V, f
= 50 pF on data I/O lines
Symbol Parameter Conditions Typical Limits Unit
t
TPR
Throughput Rate Sync-Out Mode (SYNC Bit = “0”)
9 Clock Cycles of Acquisition Time
t
CSWR
Falling Edge of CS 0ns
to Falling Edge of WR
t
WRCS
Active Edge of WR 0ns
to Rising Edge of CS
t
WR
t
WRSETFalling
t
WRHOLDFalling
t
WRSETRising
t
WRHOLDRising
t
CSRD
WR Pulse Width 20 30 ns (min)
Write Setup Time WMODE = “1” 20 ns (min)
Write Hold Time WMODE = “1” 5 ns (min)
Write Setup Time WMODE = “0” 20 ns (min)
Write Hold Time WMODE = “0” 5 ns (min)
Falling Edge of CS to Falling
Edge of RD
t
RDCS
Rising Edge of RD 0ns
to Rising Edge of CS
t
RDDATA
t
RDDATA
t
RDHOLD
Falling Edge of RD to Valid Data 8-Bit Mode (BW Bit = “0”) 40 58 ns (max)
Falling Edge of RD to Valid Data 13-Bit Mode (BW Bit = “1”) 26 44 ns (max)
Read Hold Time 23 32 ns (max)
= 12 MHz, tf= 3 ns and C
CLK
(Note 10) (Note 11) (Limit)
222 kHz
0ns
L
www.national.com 6
Digital Timing Characteristics (Continued)
The following specifications apply to the ADC12041, 13-bit data bus width, VA+=VD+ = 5V, f
= 50 pF on data I/O lines
Symbol Parameter Conditions Typical Limits Unit
t
RDRDY
Rising Edge of RD
to Rising Edge of RDY
t
WRRDY
Active Edge of WR
WMODE = “1”
to Rising Edge of RDY
t
STDRDY
Active Edge of WR WMODE = “0”. Writing the
RESET Command into the
Configuration Register
t
SYNC
Minimum SYNC Pulse Width 5 10 ns (min)
= 12 MHz, tf= 3 ns and C
CLK
(Note 10) (Note 11) (Limit)
24 38 ns (max)
37 60 ns (max)
1.4 2.5 ms (max)to Falling Edge of RDY
Notes on Specifications
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions.
Note 2: All voltages are measured with respect to GND, unless otherwise specified.
Note 3: When the input voltage (V
mA. The 120 mA maximum package input current limits the number of pins that can safely exceed the power supplies with an input current of 30 mA to four.
Note 4: The maximum power dissipation must he derated at elevated temperatures and is dictated by T
tion to ambient thermal resistance), and T
the number given in theAbsolute Maximum Ratings, whichever is lower. For this device, T
in the V package, when board mounted, is 55˚C/W, and in the SSOP package, when board mounted, is 130˚C/W.
Note 5: Human body model, 100 pF discharged through 1.5 Ωk resistor.
Note 6: Each input is protected by a nominal 6.5V breakdown voltage zener diode to GND, as shown below, input voltage magnitude up to 5V above V
below GND will not damage the ADC12041. There are parasitic diodes that exist between the inputs and the power supply rails and errors in the A/D conversion
can occur if these diodes are forward biased by more than 50 mV.As an example, if V
conversions.
) at any pin exceeds the power supply rails (V
IN
(ambient temperature). The maximum allowable power dissipation at any temperature is P
A
<
GND or V
IN
+ is 4.50 VDC, full-scale input voltage must be 4.55 VDCto ensure accurate
A
>
(VA+orVD+)), the current at that pin should be limited to 30
IN
, (maximum junction temperature), θJA(package junc-
Jmax
= 150˚C, and the typical thermal resistance (θJA) of the ADC12041
Jmax
Dmax
=(T
Jmax−TA
A
ADC12041
L
)/θJAor
+or5V
DS012441-4
Note 7: V
comparison accuracy. Refer to the Power Supply Considerations section for a detailed discussion.
Note 8: Accuracy is guaranteed when operating at f
Note 9: With the test condition for V
Note 10: Typicals are at T
Note 11: Limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 12: Positive integral linearity error is defined as the deviation of the analog value, expressed in LSBs, from the straight line that passes through positive
full-scale and zero. For negative integral linearity error, the straight line passes through negative full-scale and zero.
Note 13: Zero error is a measure of the deviation from the mid-scale voltage (a code of zero), expressed in LSB. It is the average value of the code transitions be-
tween −1 to 0 and 0 to + 1 (see
Note 14: The DC common-mode error is measured with both inputs shorted together and driven from 0V to 5V. The measured value is referred to the resulting out-
put value when the inputs are driven with a 2.5V input.
Note 15: Power Supply Sensitivity is measured after an Auto-Zero and Auto Calibration cycle has been completed with V
Note 16: V
+ and VD+ must be connected together to the same power supply voltage and bypassed with separate capacitors at each V+pin to assure conversion/
A
= 12 MHz.
CLK
+−V
REF(VREF
= 25˚C and represent most likely parametric norm.
A
Figure 8
).
(Reference Voltage Common Mode Range) is defined as
REFCM
−) given as + 4.096V, the 12-bit LSB is 1.000 mV.
REF
+ and VD+ at the specified extremes.
A
www.national.com7
Notes on Specifications (Continued)
Note 17: The ADC12041’s self-calibration technique ensures linearity and offset errors as specified, but noise inherent in the self-calibration process will result in
a repeatability uncertainty of
ADC12041
Note 18: Total Unadjusted Error (TUE) includes offset, full scale linearity and MUX errors.
Note 19: The ADC12041 parts used to gather the information for these curves were auto-calibrated prior to taking the measurements at each test condition. The
auto-calibration cycle cancels any first order drifts due to test conditions. However, each measurement has a repeatability uncertainty error of 0.2 LSB. See Note
17.
Note 20: The reference input current is a DC average current drawn by the reference input with a full-scale sinewave input. The ADC12041 is continuously con-
verting with a throughput rate of 206 kHz.
Note 21: These typical curves were measured during continuous conversions with a positive half-scale DC input. A 240 ns RD pulse was applied 25 ns after the
RDY signal went low. The data bus lines were loaded with 2 HC family CMOS inputs (CL∼ 20 pF).
Note 22: Any other values placed in the command field are meaningless. However, if a code of 101 or 110 is placed in the command field and the CS , RD and WR
go low at the same time, theADC12041 will enter a test mode. These test modes are only to be used by the manufacturer of this device. A hardware power-off and
power-on reset must be done to get out of these test modes.
±
0.20 LSB.
Electrical Characteristics
FIGURE 1. Output Digital Code vs the Operating Input Voltage Range (General Case)
www.national.com 8
DS012441-5
Electrical Characteristics (Continued)
ADC12041
FIGURE 2. Output Digital Code vs the Operating Input Voltage Range for V
REF
DS012441-6
= 4.096V
FIGURE 3. V
Operating Range (General Case)
REF
DS012441-7
www.national.com9
Electrical Characteristics (Continued)
ADC12041
FIGURE 4. V
Operating Range for VA=5V
REF
FIGURE 5. Transfer Characteristic
DS012441-8
DS012441-9
www.national.com 10
Electrical Characteristics (Continued)
FIGURE 6. Simplified Error vs Output Code without Auto-Calibration or Auto-Zero Cycles
ADC12041
DS012441-10
FIGURE 7. Simplified Error vs Output Code after Auto-Calibration Cycle
DS012441-12
FIGURE 8. Offset or Zero Error Voltage (Note 13)
DS012441-11
www.national.com11
Timing Diagrams
ADC12041
DS012441-13
FIGURE 9. Sync-Out Write (WMODE = 1, BW = 1), Read and Convert Cycles
FIGURE 10. Sync-In Write (WMODE = 1, BW = 1), Read and Convert Cycles
www.national.com 12
DS012441-14
Timing Diagrams (Continued)
ADC12041
FIGURE 11. Sync-Out Write (WMODE = 0, BW = 1), Read and Convert Cycles
DS012441-46
FIGURE 12. Sync-In Write (WMODE = 0, BW = 1), Read and Convert Cycles
DS012441-47
www.national.com13
Timing Diagrams (Continued)
ADC12041
FIGURE 13. Sync-Out Read and Convert Cycles
DS012441-48
FIGURE 14. Sync-In Read and Convert Cycles
www.national.com 14
DS012441-49
Timing Diagrams (Continued)
ADC12041
FIGURE 15. 8-bit Bus Read Cycle (Sync-Out)
DS012441-50
FIGURE 16. 8-bit Bus Read Cycle (Sync-In)
DS012441-51
www.national.com15
Timing Diagrams (Continued)
ADC12041
FIGURE 17. Write Signal Negates RDY (Writing the Standby, Auto-Cal or Auto-Zero Command)
DS012441-15
FIGURE 18. Standby and Reset Timing (13-Bit Data Bus Width)
Typical Performance Characteristics (See (Note 19), Electrical Characteristic Section)
Integral Linearity Error (INL)
Change vs Clock Frequency
DS012441-17
Full-Scale Error Change vs Clock
Frequency
DS012441-18
Zero Error Change vs Clock
Frequency
DS012441-16
DS012441-19
www.national.com 16
Typical Performance Characteristics (See (Note 19), Electrical Characteristic Section) (Continued)
ADC12041
Integral Linearity Error (INL)
Change vs Temperature
DS012441-20
Integral Linearity Error (INL)
Change vs Reference Voltage
Full-Scale Error Change vs
Temperature
Full-Scale Error Change vs
Reference Voltage
DS012441-21
Zero Error Change vs Temperature
DS012441-22
Zero Error Change vs Reference
Voltage
DS012441-23
Integral Linearity Error (INL)
Change vs Supply Voltage
DS012441-26
DS012441-24
Full-Scale Error Change vs Supply
Voltage
DS012441-27
DS012441-25
Zero Error Change vs Supply
Voltage
DS012441-28
www.national.com17
Typical Performance Characteristics (See (Note 21), Electrical Characteristic Section) (Continued)
Supply Current vs Clock Frequency
ADC12041
Analog Supply Current vs Temperature
DS012441-29
Reference Current vs Clock Frequency
DS012441-30
Digital Supply Current vs Temperature
DS012441-31
DS012441-32
Typical Performance Characteristics (Continued) The curves were obtained under the following
conditions. R
less otherwise stated.
Full Scale Differential 1,099 Hz Sine Wave Input
=50Ω,TA= 25˚C, VA+=VD+=5V,V
S
DS012441-33
= 4.096V, f
REF
= 12 MHz, and the sampling rate fS= 215 kHz un-
CLK
Full Scale Differential 18,677 Hz Sine Wave Input
DS012441-34
www.national.com 18
Typical Performance Characteristics (Continued) The curves were obtained under the following
conditions. R
unless otherwise stated. (Continued)
=50Ω,TA= 25˚C, VA+=VD+ = 5V, V
S
= 4.096V, f
REF
= 12 MHz, and the sampling rate fS= 215 kHz
CLK
ADC12041
Full Scale Differential 38,452 Hz Sine Wave Input
DS012441-35
Half Scale Differential 1 kHz Sine Wave Input, fS=
153.6 kHz
Full Scale Differential 79,468 Hz Sine Wave Input
DS012441-36
Half Scale Differential 20 kHz Sine Wave Input, fS=
153.6 kHz
DS012441-37
Half Scale Differential 40 kHz Sine Wave Input, fS=
153.6 kHz
DS012441-39
Half Scale Differential 75 kHz Sine Wave Input, fS=
153.6 kHz
DS012441-38
DS012441-40
Register Bit Description
CONFIGURATION REGISTER (Write Only)
This is an 8-bit write-only register that is used to program the functionality of the ADC12041. All data written to the ADC12041 will
always go to this register only. The contents of this register cannot be read.
MSB LSB
b
Power on State: 10 Hex
b
7
b
6
b
5
b
b
4
3
b
2
1
COMMAND SYNC BW SE ACQ TIME
FIELD
b
0
www.national.com19
Register Bit Description (Continued)
b
: The ACQ TIME bits select one of four possible acquistion times in the SYNC-OUT mode (b4= 0). (Refer to Selectable
1–b0
Acquisition Time section, page 22).
ADC12041
b
1
00 9
01 15
10 47
11 79
b
:When the Single-Ended bit (SE bit) is a ’1’, conversion results will be limited to positive values only and any negative conver-
2
sion results will appear as a code of zero in the Data register. The SE bit is cleared at power-up.
b
: This is the Bus Width (BW) bit. When this bit is a ’0’ the ADC12041 is configured to interface with an 8-bit data bus; data pins
3
D
are active and pins D12–D9are in TRI-STATE. When the BW bit is a ’1’, the ADC12041 is configured to interface with a
7–D0
16-bit data bus and data pins D
b
: The SYNC bit. When the SYNC bit is a ’1’, the SYNC pin is programmed as an input and the converter is in synchronous
4
mode. In this mode a rising edge on the SYNC pin causes the ADC to hold the input signal and begin a conversion. When b
a ’0’, the SYNC pin is programmed as an output and the converter is in an asynchronous mode. In this mode the signal at the
SYNC pin indicates the status of the converter. The SYNC pin is high when a conversion is taking place. The SYNC bit is set at
power-up .
b
: The command field. These bits select the mode of operation of the ADC12041. Power-up value is 000. (See Note 22)
7–b5
b
0
Clocks
are all active. The BW bit is cleared at power-up.
12–D0
is
8
b7b6b
5
Command
0 0 0 Standby command. This puts the ADC in a low power consumption mode.
0 0 1 Ful-Cal command. This will cause the ADC to perform a self-calibrating cycle that will correct linearity and zero
errors.
0 1 0 Auto-zero command. This will cause the ADC to perform an auto-zero cycle that corrects offset errors.
0 1 1 Reset command. This puts the ADC in an idle mode.
1 0 0 Start command. This will put the converter in a start mode, preparing it to perform a conversion. If in
asynchronous mode (b
ended. In synchronous mode (b
= “0”), conversions will immediately begin after the programmed acquisition time has
4
= “1”), conversions will begin after a rising edge appears on the SYNC pin.
4
DATA REGISTER (Read Only)
This is a 13-bitreadonly register that holds the 12-bit + sign conversion result intwo’scomplement form. All reads performedfrom
the ADC12041 will place the contents of this register on the data bus. When reading the data register in 8-bit mode, the sign bit
is extended.
MSB LSB
b
12
b
b
11
b
b
b
b
b
b
10
9
8
7
6
5
b
4
b
3
b
2
b
1
0
sign Conversion Data
Power on State: 0000Hex
b11–b0: b11is the most significant bit and b0is the least significant bit of the conversion result.
b
: This bit contains the sign of the conversion result. 0 for positive results and 1 for negative.
12
Functional Description
The ADC12041 is programmed through a digital interface
that supports an 8-bit or 16-bit data bus. The digital interface
consists of a 13-bit data input/output bus (D
control signals and two internal registers: a write only 8-bit
Configuration register and a read only 13-bit Data register.
The Configuration register programs the functionality of the
ADC12041. The 8 bits of the Configuration register are divided into 5 fields. Each field controls a specific function of
the ADC12041: the acquisition time, synchronous or asynchronous conversions, mode of operation and the data bus
size.
12–D0
), digital
Features and Operating Modes
SELECTABLE BUS WIDTH
TheADC12041 can be programmed to interface with an 8-bit
or 16-bit data bus. The BW bit (b
ister controls the bus size. The bus width is set to 8 bits
(D
are active and D12–D8are in TRI-STATE) if the BW
7–D0
bit is cleared or 13 bits (D
set. At power-up the default bus width is 8 bits (BW = 0).
In 8-bit mode the Configuration register is accessed with a
single write. When reading the ADC in 8-bit mode, the first
read cycle places the lower byte of the Data register on the
) in the Configuration reg-
3
are active) if the BW bit is
12–D0
data bus followed by the upper byte during the next read
cycle.
In 13-bit mode all bits of the Data register and Configuration
register are accessible with a single read or write cycle.
www.national.com 20
Features and Operating Modes
(Continued)
Since the bus width of the ADC12041 defaults to 8 bits after
power-up, the first action when 13-bit mode is desired must
be to set the bus width to 13 bits.
WMODE
The WMODE pin is used to determine the active edge of the
write pulse. The state of this pin determines which edge of
the WR signal willcausethe ADC to latch in data.This is processor dependent. If the processor has valid data on the bus
during the falling edge of the WR signal, the WMODE pin
must be tied to VD+. This willcausethe ADC to latch the data
on the fallingedgeof the WR signal. If data is valid ontherising edge of the WR signal, the WMODE pin must be tied to
DGND causing the ADC to latch in the data on the rising
edge of the WR signal.
ANALOG INPUTS
The ADCIN+ and ADCIN− are the fully differential noninverting (positive) and inverting (negative) inputs into the
analog-to-digital converter (ADC) of the ADC12041.
STANDBY MODE
The ADC12041 has a low power consumption mode (75 µW
@
5V). This mode is entered when a Standby command is
written in the command field of the Configuration register.
The RDY ouput pin is high when the ADC12041 is in the
Standby mode. Any command other than the Standby command written to the Configuration register will get the
ADC12041 out of the Standby mode. The RDY pin will immediately switch to a logic “0” when the ADC12041 is out of
the standby mode. The ADC12041 defaults to the Standby
mode following a hardware power-up.
SYNC/ASYNC MODE
The ADC12041 may be programmed to operate in synchronous (SYNC-IN) or asynchronous (SYNC-OUT) mode. To
enter synchronous mode, the SYNC bit in the Configuration
register must be set.The ADC12041 is in synchronous mode
after a hardware power-up. In this mode, the SYNC pin is
programmed as an input and conversions are synchronized
to the rising edges of the signal applied at the SYNC pin. Acquisition time can also be controlled by the SYNC signal
when in synchronous mode. Refer to the sync-in timing diagrams. When the SYNC bit is cleared, the ADC is in asynchronous mode and the SYNC pin is programmed as an output. In asynchronous mode, the signal at the SYNC pin
indicates the status of the converter. This pin is high when
the converter is performing a conversion. Refer to the
sync-out timing diagrams.
SELECTABLE ACQUISITION TIME
The ADC12041’s internal sample/hold circuitry samples an
input voltage by connecting the input to an internal sampling
capacitor (approximately 70 pF) through an effective resistance equal to the “On” resistance of the analog switchatthe
input to the sample/hold circuit(2500Ωtypical) and the effective output resistance of the source. For conversion results
to be accurate, the period during which the sampling capacitor is connected to the source (the “acquisition time”) must
be long enough to chargethecapacitor to within a small fraction of an LSB of the input voltage.An acquisition time of 750
ns is sufficient when the external source resistance is less
than 1 kΩ and any active or reactive source circuitry settles
to 12 bits in less than 500 ns. When source resistance or
source settling time increase beyond these limits, the acquisition time must also be increased to preserve precision.
In asynchronous (SYNC-OUT) mode, the acquisition time is
controlled by an internal counter. The minimum acquisition
period is 9 clock cycles, which corresponds to the nominal
value of 750 ns when the clock frequency is 12 MHz. Bits b
and b1of the Configuration Register are used to select the
acquisition time from among four possible values (9, 15, 47,
or 79 clock cycles). Since acquisition time in the asynchronous mode is based on counting clock cycles, it is also inversely proportional to clock frequency:
Note that the actual acquisition time will be longer than T
ACQ
because acquisition begins either when the multiplexer
channel is changed or when RDY goes low, if the multiplexer
channel is not changed.After a read is performed, RDY goes
high, which starts the T
In synchronous (SYNC-IN) mode, bits b
counter (see
ACQ
Figure 9
and b1are ignored,
0
).
and the acquisition time depends on the sync signal applied
to the SYNC pin. The acquisition period begins on the falling
edge of RDY , which occurs at the end of the previous conversion (or at the end of an autozero or autocalibration procedure. The acquisition period ends when SYNC goes high.
To estimate the acquisition time necessary for accurate conversions when the source resistance is greater than 1 kΩ,
use the following expression:
where RSis the source resistance, and R
is the sample/
S/H
hold “On” resistance.
If the settling time of the source is greater than 500 ns, the
acquisition time should be about 300 ns longer than the settling time for a “well-behaved”, smoothsettlingcharacteristic.
FULL CALIBRATION CYCLE
A full calibration cycle compensates for the ADC’s linearity
and offset errors. The converter’s DC specifications are
guaranteed only after a full calibration has been performed.
A full calibration cycle is initated by writing a Ful-Cal command to the ADC12041. During a full calibration, the offset
error is measured eight times, averaged and a correction coefficient is created. The offset correction coefficient is stored
in an internal offset correction register.
The overall linearity correction is achieved by correcting the
internal DAC’s capacitor mismatches. Each capacitor is
compared eight times against all remaining smaller value capacitors. The errors are averaged out and correction coefficients are created.
Once the converter has been calibrated, an arithmetic logic
unit (ALU) uses the offsetandlinearitycorrection coefficients
to reduce the conversion offset and linearity errors to within
guaranteed limits.
AUTO-ZERO CYCLE
During an auto-zero cycle, the offset is measured only once
and a correction coefficient is created and stored in an internal offsetregister.An auto-zero cycle is initiated by writing an
Auto-Zero command to the ADC12041.
ADC12041
0
www.national.com21
Features and Operating Modes
(Continued)
DIGITAL INTERFACE
ADC12041
The digital control signals are CS, RD, WR and RDY. Specific timing relationships are associated with the interaction
of these signals. Refer to the Digital Timing Diagrams section for detailed timing specifications. The active low RDY
signal indicates when a certain event begins and ends. It is
recommended that the ADC12041 should only be accessed
when the RDY signal is low. It is in this state that the
ADC12041 is ready to accept a new command. This will
minimize the effect of noise generated by a switching data
bus on the ADC. The only exception to this is when the
ADC12041 is in the standby mode at which time the RDY is
high. The ADC12041 is in the standby mode at power up or
when a STANDBYcommand is issued. AFul-Cal, Auto-Zero,
Reset or Start command will get the ADC12041 out of the
standby mode. This may be observed by monitoring the status of the RDY signal. The RDY signal will go low when the
ADC12041 leaves the standby mode.
The following describes the state of the digitalcontrolsignals
for each programmed event in both 8-bit and 13-bit mode.
RDY should be low before each command is issued except
for the case when the device is in standby mode.
FUL-CAL OR AUTO-ZERO COMMAND
8-bit mode:
and the BW bit (b
pulse on the WR pin will force the RDY signal high. At this
time the converter begins executing a full calibration or
auto-zero cycle. The RDY signal will automatically go low
when the full calibration or auto-zero cycle is done.
13-bit mode:
sued and the BW bit (b
pulse on the WR pin will force the RDY signal high. At this
time the converter begins executing a full calibration or
auto-zero cycle. The RDY signal will automatically go low
when the full calibration or auto-zero cycle is done.
STARTING A CONVERSION: START COMMAND
In order to completely describe the events associated with
the Start command, both the SYNC-OUT and SYNC-IN
modes must be considered.
SYNC-OUT/Asynchronous
8-bit mode:
tion time, clear the BW and SYNC bit and select the START
command in the Configuration register. In order to initiate a
conversion, two reads must be performed from the
ADC12041. The rising edge of the second read pulse will
force the RDY pin high and begin the programmed acquisition time selected by bits b1and b0of the Configuration register. The SYNC pin will go high indicating that a conversion
sequence has begun following the end of the acquisition period. The RDY and SYNC signal will fall low when the conversion is done. At this time new information, such as a new
acquisition time and operational command can be written
into the Configuration register or it can remain unchanged.
Assuming that the START command is in the Configuration
register, the previous conversion can be read. The first read
places the lower byte of the conversion result contained in
the Data register on the data bus.Thesecondreadwillplace
the upper byte of the conversion result stored in the Data
register on the data bus. The rising edge on the second read
pulse will begin another conversion sequence and raise the
RDY and SYNC signals appropriately.
AFul-Cal or Auto-Zero command must be issued
) cleared. The active edge of the write
3
A Ful-Cal or Auto-Zero command must be is-
) set. The active edge of the write
3
A write to the ADC12041 should set the acquisi-
13-bit mode:
The acquisition time should be set, the BW bit
set, the SYNC bit cleared and the START command issued
with a write to the ADC12041. In order to initiate a conversion, a single read must be performed from the ADC12041.
The rising edge of the read signal will force the RDY signal
high and begin the programmed acquisition time selected by
bits b
and b0of the configuration register.The SYNC pin will
1
go high indicating that a conversion sequence hasbegunfollowing the end of the acquisition period.The RDY and SYNC
signal will fall low when the conversion is done. At this time
new information, such as a new acquisition time and operational command can be written into the Configuration register or it can remain unchanged.WiththeSTARTcommandin
the Configuration register, a read from the ADC12041 will
place the entire 13-bit conversion result stored in the data
register on the data bus. The rising edge of the read pulse
will immediately force the RDY output high and begin the
programmed acquisition time selected by bits b1and b0of
the configuration register. The SYNC will then go high at the
end of the programmed acquisition time.
SYNC-IN/Synchronous
For the SYNC-IN case, it is assumed that a series of SYNC
pulses at the desired sampling rate are applied at the SYNC
pin of the ADC12041.
8-bit mode: A write to the ADC12041 should set the SYNC
bit, write the START command and clear the BW bit. The
programmed acquisition time in bits b
and b0is a don’t care
1
condition in the SYNC-IN mode.
A rising edge on the SYNC pin or the second rising edge of
two consecutive reads from the ADC12041 will force the
RDY signal high. It is recommended that the action of reading from theADC12041 (not the rising edge of the SYNC signal) be used to raisetheRDY signal. This will ensure that the
conversion result is read during the acquisition period of the
next conversion cycle, eliminating a read from the
ADC12041 while it is performing a conversion. Noise generated by accessing the ADC12041 while it is converting may
degrade the conversion result. In the SYNC-IN mode, only
the rising edge of the SYNC signal will begin a conversion
cycle. The rising edge of the SYNC also ends the acquisition
period. The acquisition period begins after the falling edge of
the RDY signal. The input is sampled until the rising edge of
the SYNC pulse, at which time the signal will be held and
conversion begins.TheRDY signal will go low when the conversion is done and a new operational command may be
written into the Configuration register at this time, if needed.
Two consecutive read cycles are required to retrieve the entire 13-bit conversion result from the ADC12041’s Data register.The first read will place the lower byte of the conversion
result contained in the Data register on the data bus. The
second read will place the upper byte of the conversion result stored in the Data register on the data bus. With the
START command in the configuration register, the rising
edge of the second read pulse will raise the RDY signal high
and begin a conversion cycle following a rising edge on the
SYNC pin.
13-bit mode:
The SYNC bit and the BW bit should be set and
the START command issued with a write to the ADC12041.
Arisingedge on the SYNC pin or on the RD pin will force the
RDY signal high. It is recommended that the action of reading from theADC12041 (not the rising edge of the SYNC signal) be used to raisetheRDY signal. This will ensure that the
conversion result is read during the acquisition period of the
next conversion cycle, eliminating a read from the
ADC12041 while it is performing a conversion. Noise generated by accessing the ADC12041 while it is converting may
www.national.com 22
Features and Operating Modes
(Continued)
degrade the conversion result. In the SYNC-IN mode, only
the rising edge of the SYNC signal will begin a conversion
cycle. The RDY signal will go low when the conversion cycle
is done. The acquisition time is controlled by the SYNC signal. Theacquisitionperiod begins after the falling edge of the
RDY signal. The input is sampled until the rising edge of the
SYNC pulse, at which time the signal will be held and conversion begins. The RDY signal will go low when the conversion is done and a new operational command may be written
into the Configuration register at this time, if needed. With
the START command in the Configuration register, a read
from the ADC12041 will place the entire conversion result
stored in the Data register on the data bus and the rising
edge of the read pulse will force the RDY signal high.
STANDBY COMMAND
8-bit mode:
and issue the Standby command.
13-bit mode:
and issue the Standby command.
RESET
The RESET command places the ADC12041 into a ready
state and forces the RDY signal low. The RESET command
can be used to interrupt the ADC12041 while it is performing
a conversion, full-calibration or auto-zero cycle. It can also
be used to get the ADC12041 out of the standby mode.
Awrite to theADC12041 should clear the BW bit
A write to the ADC12041 should set the BW bit
put voltage is proportional to the voltage used for the ADC’s
reference voltage. This technique relaxes the system reference requirements because the analog input voltage moves
with the ADC’s reference. The system power supply can be
used as the reference voltage by connecting the V
to V
+ and the V
A
− pin to AGND. For absolute accuracy,
REF
REF
+ pin
where the analog input voltage varies between very specific
voltage limits, a time and temperature stable voltage source
can be connected to the reference inputs. Typically, the reference voltage’s magnitude will require an initial adjustment
to null reference voltage induced full-scale errors.
The reference voltage inputs are not fully differential. The
ADC12041 will not generate correct conversions if
(V
+) – (V
REF
able relationship between V
−) is below 1V.
REF
REF
Figure 19
+ and V
shows the allow-
−.
REF
ADC12041
Analog Application Information
REFERENCE VOLTAGE
TheADC12041 has two reference inputs, V
They define the zero to full-scale range of the analog input
signals over which 4095 positive and 4096 negative codes
exist. The reference inputs can be connected to span the entire supply voltage range (V
− = AGND, V
REF
they can be connected to different voltages when other input
spans are required. The reference inputs of the ADC12041
have transient capacitive switching currents. The voltage
sources driving V
REF
+ and V
− must have very low output
REF
impedence and noise and must be adequately bypassed.
The circuit in
Figure 20
is an example of a very stable refer-
ence source.
The ADC12041 can be used in either ratiometric or absolute
reference applications. In ratiometric systems, the analog in-
REF
REF
+ and V
REF
+=VA+) or
DS012441-43
FIGURE 19. V
Operating Range
REF
−.
OUTPUT DIGITAL CODE VERSUS ANALOG INPUT
VOLTAGE
The ADC12041’s fully differential 12-bit + sign ADC generates a two’s complement output that is found by using the
equation shown below:
Round off the result to the nearest integer value between
-4096 and 4095.
www.national.com23
Analog Application Information (Continued)
ADC12041
*Tantalum
*
*Ceramic
FIGURE 20. Low Drift Extremely Stable Reference Circuit
Part Number Output Voltage Temperature
LM4041CI-Adj
LM4040AI-4.1
LM4050
LM4120
LM9140BYZ-4.1
Circuit of
Figure 20
Tolerance Coefficient
±
0.5%
±
0.1%
±
0.2%
±
0.1%
±
0.5%
Adjustable
±
100ppm/˚C
±
100ppm/˚C
±
50ppm/˚C
±
50ppm/˚C
±
25ppm/˚C
±
2ppm/˚C
DS012441-44
INPUT CURRENT
At the start of the acquisition window (t
AcqSYNOUT
) a charging current (due to capacitive switching) flows through the
analog input pins (ADCIN+ and ADCIN−). The peak value of
this input current willdependon the amplitude and frequency
of the input voltage applied, the source impedance and the
ADCIN+ and ADCIN− input switch ON resistance of 2500Ω.
For low impedance voltage sources (
<
1000 Ω for 12 MHz
operation), the input charging current will decay to a value
that will not introduce any conversion errors before the end
of the default sample-and-hold (S/H) acquisition time
(9 clock cycles). For higher source impedances (
>
1000 Ω
for 12 MHz operation), the S/H acquisition time should be increased to allow the charging current to settle within specified limits. In asynchronous mode, the acquisition time may
be increased to 15, 47 or 79 clock cycles. If different acquisition times are needed, the synchronous mode can be used
to fully control the acquisition time.
INPUT BYPASS CAPACITANCE
External capacitors (0.01 µF–0.1 µF) can be connected between the ADCIN+ and ADCIN− analog input pins and the
analog ground to filter any noise caused by inductive pickup
associated with long leads.
POWER SUPPLY CONSIDERATIONS
Decoupling and bypassing the power supply on a high resolution ADC is an important design task. Noise spikes on the
V
+ (analog supply) or VD+ (digital supply) can cause con-
A
version errors. The analog comparator used in the ADC will
respond to power supply noise and will makeerroneouscon-
version decisions. The ADC is especially sensitive to power
supply spikes that occur during the auto-zero orlinearitycalibration cycles.
The ADC12041 is designed to operate from a single +5V
power supply. The separate supply and ground pins for the
analog and digital portions of the circuit allowseparateexternal bypassing. To minimize power supply noise and ripple,
adequate bypass capacitors should be placed directly between power supply pins and their associated grounds. Both
supply pins should be connected to the same supply source.
In systems with separate analog and digital supplies, the
ADC should be powered from the analog supply. At least a
10 µF tantalum electrolytic capacitor in parallel with a 0.1 µF
monolithic ceramic capacitor is recommended for bypassing
each power supply. The key consideration for these capacitors is to have low series resistance and inductance. The capacitors should be placed as close as physically possible to
the supply and ground pins with the smaller capacitor closer
to the device. The capacitors also should have the shortest
possible leads in order to minimize series lead inductance.
Surface mount chip capacitors are optimal in this respect
and should be used when possible.
When the power supply regulator is not local on the board,
adequate bypassing (a high value electrolytic capacitor)
should be placed at the power entry point. The value of the
capacitor depends on the total supply current of the circuits
on the PC board. All supply currents should be supplied by
the capacitor instead of being drawn from the external supply lines, while the external supply charges the capacitor at a
steady rate.
TheADC has two V
use a 0.1 µF plus a 10 µF capacitor between pin 21(V
+ and DGNDpins.It is recommended to
D
+)
D
www.national.com 24
Analog Application Information
(Continued)
and 22 (DGND) the SSOP and PLCC package. The layout
diagram in
for the supply bypass capacitors.
PC BOARD LAYOUT AND GROUNDING
CONSIDERATlONS
To get the best possible performance from the ADC12041,
the printed circuit boards should have separate analog and
digital ground planes. The reason for using two ground
planes is to prevent digital and analog ground currents from
sharing the same path until they reach a very low impedance
power supply point. This will prevent noisy digital switching
currents from being injected into the analog ground.
Figure 21
power supply and reference input bypass capacitors. It
shows a layout using a 28-pin PLCC socket and
through-hole assembly. A similar approach should be used
for the SSOP package.
The analog ground plane should encompass the area under
the analog pins and any other analog components such as
the reference circuit, input amplifiers, signal conditioning circuits, and analog signal traces.
The digital ground plane should encompass the area under
the digital circuits and the digital input/output pins of the
Figure 21
illustrates a favorable layout for ground planes,
shows the recommended placement
ADC12041. Having a continuous digital ground plane under
the data and clock traces is very important. This reduces the
overshoot/undershoot and high frequency ringing on these
lines that can be capacitively coupled to analog circuitry sections through stray capacitances.
The AGND and DGND in the ADC12041 are not internally
connected together. They should be connected together on
the PC board right at the chip. This will provide the shortest
return path for the signals being exchanged between the internal analog and digital sections of the ADC.
It is also a good design practice to have power plane layers
in the PC board. This will improve the supply bypassing (an
effective distributed capacitance between power and ground
plane layers) and voltage drops on the supply lines. However,power planes are not as essential as groundplanesare
for satisfactory performance. If power planes are used, they
should be separated into two planes and the area and connections should follow the same guidelines as mentioned for
the ground planes. Each power plane should be laid out over
its associated ground planes, avoiding any overlap between
power and ground planes of different types. When the power
planes are not used, it is recommended to use separate supply traces for the V
supply point (the regulator output or the power entry point to
the PC board). This will help ensure that the noisy digital
supply does not corrupt the analog supply.
+ and VD+ pins from a low impedance
A
ADC12041
www.national.com25
Analog Application Information (Continued)
ADC12041
FIGURE 21. Top View of Printed Circuit Board for a 28-Pin PLCC ADC12041
When measuring AC input signals, any crosstalk between
analog input lines and the reference lines (ADCIN
±
,V
REF
±
)
should be minimized. Crosstalk is minimized by reducing
any stray capacitance between the lines. This can be done
by increasing the clearance between traces, keeping the
traces as short as possible, shielding traces from each other
by placing them on differentsides of the AGND plane, or running AGND traces between them.
Figure 21
also shows the reference input bypass capacitors.
Here the reference inputs are considered to be differential.
The performance improves by having a 0.1 µF capacitor be-
www.national.com 26
DS012441-45
tween the V
REF
+ and V
−, and by bypassing in a manner
REF
similar to that described for the supply pins. When a single
ended reference is used, V
only two capacitors are used between V
− is connected to AGND and
REF
REF
+ and V
REF
− (0.1
µF + 10 µF). It is recommended to directly connect the
AGND side of these capacitors to the V
necting V
− and the ground sides of the capacitors sepa-
REF
− instead of con-
REF
rately to the ground planes. This provides a significantly
lower-impedance connection when using surface mount
technology.
Physical Dimensions inches (millimeters) unless otherwise noted
ADC12041
28-Lead Molded Plastic Leaded Chip Carrier
Order Number ADC12041CIV
NS Package Number V28A
www.national.com27
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
28-Lead SSOP
Order Number ADC12041CIMSA
NS Package Number MSA28
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
ADC12041 12-Bit Plus Sign 216 kHz Sampling Analog-to-Digital Converter
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL
COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and
whose failure to perform when properly used in
accordance with instructions for use provided in the
2. A critical component is any component of a life
support device or system whose failure to perform
can be reasonably expected to cause the failure of
the life support device or system, or to affect its
safety or effectiveness.
labeling, can be reasonably expected to result in a
significant injury to the user.
National Semiconductor
Corporation
Americas
Tel: 1-800-272-9959
Fax: 1-800-737-7018
Email: support@nsc.com
www.national.com
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
National Semiconductor
Europe
Fax: +49 (0) 180-530 85 86
Email: europe.support@nsc.com
Deutsch Tel: +49 (0) 69 9508 6208
English Tel: +44 (0) 870 24 0 2171
Français Tel: +33 (0) 1 41 91 8790
National Semiconductor
Asia Pacific Customer
Response Group
Tel: 65-2544466
Fax: 65-2504466
Email: ap.support@nsc.com
National Semiconductor
Japan Ltd.
Tel: 81-3-5639-7560
Fax: 81-3-5639-7507
Loading...