NSC ADC1173CIMTC, ADC1173CIJM Datasheet
ADC1173
8-Bit, 3-Volt, 15MSPS, 33mW A/D Converter
ADC1173 8-Bit, 3-Volt, 15MSPS, 33mW A/D Converter
February 1999
General Description
The ADC1173 is a low power, 15 MSPS analog-to-digital
converter that digitizes signals to 8 bits while consuming just
33 mW ofpower(typ). The ADC1173 uses a unique architecture that achieves 7.6 Effective Bits. Output formatting is
straight binary coding.
The excellent DC and AC characteristics of this device, together with its low power consumption and +3V single supply
operation, make it ideally suited for many video, imaging and
communications applications, including use in portable
equipment. Furthermore, the ADC1173 is resistant to latchup
and the outputs are short-circuit proof. The top and bottom of
theADC1173’s reference ladder is available for connections,
enabling a wide range of input possibilities.
TheADC1173 is offered in SOIC (EIAJ) and TSSOP. It is designed to operate over the commercial temperature range of
-20˚C to +75˚C.
Features
n Internal Sample-and-Hold Function
n Single +3V Operation
n Internal Reference Bias Resistors
n Industry Standard Pinout
n TRI-STATE
®
Outputs
Ordering Information
ADC1173CIJM SOIC (EIAJ)
ADC1173CIJMX SOIC (EIAJ) (tape & reel)
ADC1173CIMTC TSSOP
ADC1173CIMTCX TSSOP (tape & reel)
Key Specifications
n Resolution 8 Bits
n Maximum Sampling Frequency 15 MSPS (min)
n THD −56 dB (typ)
n DNL
n ENOB at 3.58 MHz Input 7.6 Bits (typ)
n Guaranteed No Missing Codes
n Differential Phase 0.5 Degree (max)
n Differential Gain 1.5%(typ)
n Power Consumption 33mW (typ)
(excluding reference current)
±
0.8 LSB (max)
Applications
n Video Digitization
n Digital Still Cameras
n Set Top Boxes
n Camcorders
n Personal Computer Video
n Digital Television
n CCD Imaging
n Electro-Optics
Pin Configuration
DS100890-1
TRI-STATE®is a registered trademark of National Semiconductor Corporation.
© 1999 National Semiconductor Corporation DS100890 www.national.com
Block Diagram
Pin Descriptions and Equivalent Circuits
DS100890-2
Pin
Symbol Equivalent Circuit
No.
19 V
16 V
17 V
23 V
RTS
Description
IN
Analog signal input. Conversion range is VRBto
.
V
RT
Reference Top Bias with internal pull-up resistor.
Short this pin to V
ladder.
to self bias the reference
RT
Analog Input that is the high (top) side of the
reference ladder of the ADC. Nominal range is 1.0V
. Voltage on VRTand VRBinputs define the
RT
to AV
DD
conversion range. Bypass well. See Section 2.0
V
IN
for more information.
Analog Input that is the low (bottom) side of the
reference ladder of the ADC. Nominal range is 0V
RB
to 2.0V. Voltage on V
conversion range. Bypass well. See Section 2.0
V
IN
for more information.
and VRBinputs define the
RT
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Pin Descriptions and Equivalent Circuits (Continued)
Pin
Symbol Equivalent Circuit
No.
22 V
RBS
1OE
12 CLK
Description
Reference Bottom Bias with internal pull down
resistor. Short to V
ladder.
to self bias the reference
RB
CMOS/TTL compatible Digital input that, when low,
enables the digital outputs of the ADC1173. When
high, the outputs are in a high impedance state.
CMOS/TTL compatible digital clock Input. VINis
sampled on the falling edge of CLK input.
3 thru
10
D0-D7
11, 13 DV
2, 24 DV
14,
15, 18
AV
20, 21 AV
Conversion data digital Output pins. D0 is the LSB,
D7 is the MSB. Valid data is output just after the
rising edge of the CLK input. These pins are
enabled by bringing the OE pin low.
Positive digital supply pin. Connect to a clean, quiet
voltage source of +3V. AV
DD
a common source and be separately bypassed with
a 10µF capacitor and a 0.1µF ceramic chip
and DVDDshould have
DD
capacitor. See Section 3.0 for more information.
The ground return for the digital supply. AVSSand
should be connected together close to the
SS
DV
SS
ADC1173.
Positive analog supply pin. Connected to a clean,
quiet voltage source of +3V. AV
DD
have a common source and be separately bypassed
with a 10 µF capacitor and a 0.1 µF ceramic chip
and DVDDshould
DD
capacitor. See Section 3.0 for more information.
The ground return for the analog supply. AVSSand
should be connected together close to the
SS
DV
SS
ADC1173 package.
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Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
AV
,DV
DD
DD
Voltage on Any Pin −0.3V to 6.5V
V
RT,VRB
CLK, OE Voltage −0.05 to (AVDD+ 0.05V)
Digital Output Voltage DV
Input Current (Note 3)
Package Input Current
(Note 3)
Package Dissipation at 25˚C (Note 4)
AVDDto V
to DV
SS
±
25mA
±
50mA
6.5V
SS
DD
ESD Susceptibility (Note 5)
Human Body Model 2000V
Machine Model 200V
Soldering Temp., Infared, 10
sec. (Note 6) 300˚C
Storage Temperature −65˚C to +150˚C
Operating Ratings(Notes 1, 2)
Temperature Range −20˚C ≤ T
AV
,DV
DD
|AV
V
V
V
DD
-DVSS| 0V to 100 mV
SS
RT
RB
Voltage Range VRBto V
IN
≤ +75˚C
A
+2.7V to +3.6V
1.0V to AV
0V to 2.0V
Converter Electrical Characteristics
The following specifications apply for AVDD=DV
at 50%duty cycle. Boldface limits apply for T
=
DD
=
T
A
MIN
+3.0V
to T
,OE=0V, V
DC
; all other limits T
MAX
Symbol Parameter Conditions
DC Accuracy
INL Integral Non Linearity
DNL Differential Non Linearity
Missing Codes 0 (max)
E
OT
E
OB
Top Offset −12 mV
Bottom Offset +1.0 mV
Video Accuracy
DP Differential Phase Error f
DG Differential Gain Error f
=
3.58 MHz sine wave 0.5 Degree
in
=
3.58 MHz sine wave 1.5
in
Analog Input and Reference Characteristics
V
IN
C
IN
R
IN
Input Range 2.0
VINInput Capacitance V
=
1.5V + 0.7Vrms
IN
Input Resistance
BW Analog Input Bandwidth 120 MHz
R
RT
R
REF
R
RB
I
REF
V
RT
V
RB
V
RTS
V
RBS
Top Reference Resistor 360 Ω
Reference Ladder
Resistance
to V
V
RT
RB
Bottom Reference Resistor 90 Ω
=
V
V
RT
RTS,VRB
=
V
RBS
Reference Ladder Current
Reference Top Self Bias
Voltage
Reference Bottom Self Bias
Voltage
Self Bias Voltage Delta
=
V
V
RT
VRTconnected to V
VRBconnected to V
connected to V
V
RT
V
connected to V
RB
connected to V
V
RT
connected to V
V
RB
connected to V
V
RT
connected to V
V
RB
RTS,VRB
=
AV
SS
RTS
RBS
RTS
RBS
,
RTS
RBS
,
RTS
SS
RT
=
+2.0V, V
A
(CLK
LOW)
(CLK
HIGH)
=
=
=
0V, C
RB
25˚C (Notes 7, 8)
Typical
(Note 9)
±
±
L
0.5
0.4
20 pF, f
Limits Units
4
11
>
1MΩ
300 200 Ω(min)
4.2
4.8 mA
1.56
0.36
1.2
1.38 V
=
15MHz
CLK
±
1.3 LSB( max)
±
0.85 LSB( max)
%
V
RB
V
RT
V(min)
V(max)
pF
400 Ω(max)
mA
1.45
1.65
V(min)
V(max)
0.32 V(min)
0.40 V(max)
1.1
1.3
µAmin
µAmax
DD
RT
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Converter Electrical Characteristics (Continued)
The following specifications apply for AVDD=DV
at 50%duty cycle. Boldface limits apply for T
=
DD
=
T
A
MIN
+3.0V
to T
,OE=0V, V
DC
; all other limits T
MAX
Symbol Parameter Conditions
Analog Input and Reference Characteristics
-
V
RT
V
RB
Reference Voltage Delta 2
Power Supply Characteristics
=
IA
ID
IAV
IDV
DD
DD
Analog Supply Current DV
Digital Supply Curretn DV
+
DD
Total Operating Current
DD
Power Consumption DV
DD
DD
DV
DDAVDD
DV
DD
(Note 10)
DD
=
AV
3.6V 6.8 mA
DD
=
=
AV
3.6V 2.3 mA
DD
=
3.6V, 9.1 11 mA
=
=
AV
3.6V, CLK Low
DD
=
=
AV
3.6V 33 40 mW
DD
CLK, OE Digital Input Characteristics
=
V
IH
V
IL
I
IH
I
IL
C
IN
Logical High Input Voltage DV
Logical Low Input Voltage DV
Logical High Input Current V
Logic Low Input Current V
DD
DD
=
IH
=
IL
Logic Input Capacitance 5 pF
AV
=
AV
DV
DD
0V, DV
=
3.6V 2.2 V (min)
DD
=
3.6V 0.8 V (max)
DD
=
=
AV
3.6V 5 µA
DD
=
=
AV
DD
DD
Digital Output Characteristics
V
V
I
I
OZH
OZL
=
DV
2.7V, I
OH
OL
High Level Output Voltage
Low Level Output Voltage DV
,
Tri-State®Leakage Current
DV
DV
V
DD
DD
DD
DD
OL
=
2.7V, I
=
2.7V, I
=
3.6V, OE=DV
=
0V or V
=
−360µA 2.4 V(min)
OH
=
−1.1mA 2.1 1.9 V(min)
OH
=
1.6mA 0.32 0.6 V(max)
OL
DD
=
DV
OH
DD
AC Electrical Characteristics
f
C1
f
C2
t
OD
t
OD
Maximum Conversion Rate 20 15 MHz(min)
Minimum Conversion Rate 1 MHz
−0 Output Delay CLK high to low data valid 28 ns(max)
−1 Output Delay CLK low to high data valid 24 ns(max)
Pipline Delay (Latency) 2.5
t
DS
t
AJ
t
OH
t
EN
t
DIS
ENOB Effective Number of Bits
SINAD Signal-to- Noise & Distortion
SNR Signal-to-Noise Ratio
SFDR
THD Total Harmonic Distortion
Sampling (Aperture) Delay CLK low to acquissition of data 3 ns
Aperture Jitter 30 ps rms
Output Hold Time CLK high to data invalid 15 ns
OE Low to Data Valid Loaded as in
OE High to High Z State Loaded as in
=
f
IN
=
f
IN
=
f
IN
=
f
IN
=
f
IN
=
f
IN
=
f
IN
=
f
IN
=
f
IN
=
f
Spurious Free Dynamic
Range
IN
=
f
IN
=
f
IN
=
f
IN
=
f
IN
=
f
IN
Figure 2
Figure 2
1.31 MHz
3.58 MHz
7.5 MHz
1.31 MHz
3.58 MHz
7.5 MHz
1.31 MHz
3.58 MHz
7.5 MHz
1.31 MHz
3.58 MHz
7.5 MHz
1.31 MHz
3.58 MHz
7.5 MHz
RT
=
+2.0V, V
A
=
0V, C
RB
=
25˚C (Notes 7, 8)
Typical
(Note 9)
=
20 pF, f
L
CLK
Limits Units
=
1.0 V(min)
V
A
5.8 mA
3.6V −5 µA
,
±
20 µA
22 ns
12 ns
7.7
7.6
7.0 Bits (min)
7.4
49
47.7
43 dB(min)
46.5
49
48.7
44 dB(min)
48.0
65
55
51
−62
−54
−51
15MHz
V(max)
Clock
Cycles
dB
dB
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Converter Electrical Characteristics (Continued)
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is func-
tional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions.
Note 2: All voltages are measured with respect to GND=AV
Note 3: When the input voltage at any pin exceeds the power supplies (that is, less than AV
be limited to 25 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of
25 mA to two.
Note 4: The absolute maximum junction temperatures (T
junction-to-ambient thermal resistance θ
TSSOP, θ
this part is 98˚C/W for the EIAJ SOIC). Note that the power dissipation of this device under normal operation will typically be about 49 mW (33 mW quiescent power
+ 13 mW reference ladder power+3mWdueto1TTLloan on each digital output. The values for maximum power dissipation listed above will be reached only when
the ADC1173 is operated in a severe fault condition (e.g. when input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed). Obviously, such conditions should always be avoided.
is 92˚C/W, so PDMAX=1,358 mW at 25˚C and 815 mW at the maximum operating ambient temperature of 75˚C. (Typical thermal resistance, θJA,of
JA
, and the ambient temperature, TA, and can be calculated using the formula PDMAX=(TJmax - TA)/θJA. In the 24-pin
JA
Note 5: Human body model is 100 pF capacitor discharged through a 1.5kΩ resistor. Machine model is 220 pf discharged through ZERO Ω.
Note 6: See AN450, ″Surface Mounting Methods and Their Effect on Product Reliability″, or the section entitled ″Surface Mount″ found in any post 1986 National
Semiconductor Linear Data Book, for other methods of soldering surface mount devices.
Note 7: The analog inputs are protected as shown below. Input voltage magnitudes up to 6.5V or to 500 mV below GND will not damage this device. However, errors
in the A/D conversion can occur if the input goes above V
be ≤2.75V
to ensure accurate conversions.
DC
Note 8: To guarantee accuracy, it is required that AV
Note 9: Typical figures are at T
Level).
= 25˚C, and represent most likely parametric norms. Test limits are guaranteed to National’s AOQL (Average Outgoing Quality
J
Note 10: At least two clock cycles must be presented to the ADC1173 after power up. See Section 4.0 for details.
=
=
DV
SS
max) for this device is 150˚C. The maximum allowable power dissipation is dictated by TJmax, the
J
or below GND by more than 50 mV. As an example, if AVDDis 2.7VDC, the full-scale input voltage must
DD
and DVDDbe well bypassed. Each supply pin must be decoupled with separate bypass capacitors.
DD
0V, unless otherwise specified.
SS
SS
DS100890-10
or DVSS, or greater than AVDDor DVDD), the current at that pin should
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