NSC ADC10731CIN Datasheet
ADC10731/ADC10732/ADC10734/ADC10738
10-Bit Plus Sign Serial I/O A/D Converters with Mux,
Sample/Hold and Reference
General Description
This series of CMOS 10-bit plus sign successive approximation A/D converters features versatile analog input multiplexers, sample/hold and a 2.5V band-gap reference. The 1-, 2-,
4-, or 8-channel multiplexers can be software configured for
single-ended or differential mode of operation.
An input sample/hold is implemented by a capacitive reference ladder and sampled-data comparator. This allows the
analog input to vary during the A/D conversion cycle.
In the differential mode, valid outputs are obtained even
when the negative inputs are greater than the positive because of the 10-bit plus sign output data format.
The serial I/O is configured to comply with the NSC MICROWIRE
™
serial data exchange standard for easy inter-
face to the COPS
™
and HPC™families of controllers, and
can easily interface with standard shift registers and microprocessors.
Features
n 0V to 5V analog input range with single 5V power
supply
n Serial I/O (MICROWIRE compatible)
n 1-, 2-, 4-, or 8-channel differential or single-ended
multiplexer
n Software or hardware power down
n Analog input sample/hold function
n Ratiometric or absolute voltage referencing
n No zero or full scale adjustment required
n No missing codes over temperature
n TTL/CMOS input/output compatible
n Standard DIP and SO packages
Key Specifications
n Resolution 10 bits plus sign
n Single supply 5V
n Power dissipation 37 mW (Max)
n In powerdown mode 18 µW
n Conversion time 5µs (Max)
n Sampling rate 74 kHz (Max)
n Band-gap reference 2.5V
±
2% (Max)
Applications
n Medical instruments
n Portable and remote instrumentation
n Test equipment
ADC10738 Simplified Block Diagram
COPS™, HPC™and MICROWIRE™are trademarks of National Semiconductor Corporation.
DS011390-1
May 1999
ADC10731/ADC10732/ADC10734/ADC10738 10-Bit Plus Sign Serial I/O A/D Converters with Mux,
Sample/Hold and Reference
© 2001 National Semiconductor Corporation DS011390 www.national.com
Connection Diagrams
DS011390-2
Top View
See NS Package Number M16B
DS011390-4
Top View
See NS Package Number M20B
DS011390-3
Top View
See NS Package Number M20B
DS011390-5
Top View
See NS Package Number M24B
SSOP Package
DS011390-34
See NS Package Number MSA20
ADC10731/ADC10732/ADC10734/ADC10738
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Ordering Information
Industrial Temperature Range Package
−40˚C ≤ T
A
≤ +85˚C
ADC10731CIWM M16B
ADC10732CIWM M20B
ADC10734CIMSA MSA20
ADC10734CIWM M20B
ADC10738CIWM M24B
Pin Descriptions
CLK The clock applied to this input controls the suc-
cessive approximation conversion time interval,
the acquisition time and the rate at which the
serial data exchange occurs. The rising edge
loads the information on the DI pin into the multiplexer address shift register. This address controls which channel of the analog input multiplexer (MUX) is selected. The falling edge shifts
the data resulting from the A/D conversion out
on DO. CS enables or disables the above functions. The clock frequency applied to this input
can be between 5 kHz and 3 MHz.
DI This is the serial data input pin. The data applied
to this pln is shifted by CLK into the multiplexer
address register.
Tables 1, 2, 3
show the multi-
plexer address assignment.
DO The data output pin. The A/D conversion result
(DB0-SIGN) are clocked out by the failing edge
of CLK on this pin.
CS
This is the chip select input pin. When a logic low
is applied to this pin, the rising edge of CLK
shifts the data on DI into the address register.
This low also brings DO out of TRI-STATE after
a conversion has been completed.
PD This is the power down input pin. When a logic
high is applied to this pin the A/D is powered
down. When a low is applied the A/D is powered
up.
SARS This is the successive approximation register
status output pin. When CS is high this pin is in
TRI-STATE. With CS low this pin is active high
when a conversion is in progress and active low
at all other times.
CH0–CH7 These are the analog inputs of the MUX. A chan-
nel input is selected by the address information
at the DI pin, which is loaded on the rising edge
of CLK into the address register (see
Tables 1, 2,
3
).
The voltage applied to these inputs should not
exceed AV
+
or go below GND by more than
50 mV. Exceeding this range on an unselected
channel will corrupt the reading of a selected
channel.
COM This pin is another analog input pln. It can be
used as a “pseudo ground” when the analog
multiplexer is single-ended.
V
REF
+ This is the positive analog voltage reference
input. In order to malntaln accuracy, the voltage
range V
REF(VREF=VREF
+–V
REF
−) is 0.5 VDCto
5.0 V
DC
and the voltage at V
REF
+ cannot exceed
AV
+
+50 mV.
V
REF
− The negative voltage reference input. In order to
maintain accuracy, the voltage at this pin must
not go below GND − 50 mV or exceed AV
+
+50mV.
AV
+
,DV+These are the analog and digital power supply
pins. These pins should be tied to the same
power supply and bypassed separately. The operating voltage range of AV
+
and DV+is 4.5 V
DC
to 5.5 VDC.
DGND This is the digital ground pin.
AGND This is the analog ground pin.
ADC10731/ADC10732/ADC10734/ADC10738
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Absolute Maximum Ratings (Notes 1, 3)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
+
=AV+=DV+) 6.5V
Total Reference Voltage
(V
REF
+–V
REF
−) 6.5V
Voltage at Inputs and Outputs V
+
+ 0.3V to −0.3V
Input Current at Any Pin (Note 4) 30 mA
Package Input Current (Note 4) 120 mA
Package Dissipation at T
A
= 25˚C
(Note 5) 500 mW
ESD Susceptability (Note 6)
Human Body Model 2500V
Machine Model 150V
Soldering Information
N packages (10 seconds) 260˚C
SO Package (Note 7)
Vapor Phase (60 seconds) 215˚C
Infrared (15 seconds) 220˚C
Storage Temperature −40˚C to +150˚C
Operating Ratings (Notes 2, 3)
Operating Temperature Range T
MIN
≤ TA≤ T
MAX
ADC10731CIWM,
ADC10732CIWM,
ADC10734CIWM,
ADC10734CIMSA,
ADC10738CIWM −40˚C ≤ T
A
≤ +85˚C
Supply Voltage
(V
+
=AV+=DV+) +4.5V to +5.5V
V
REF
+AV
+
+50 mV to −50 mV
V
REF
−AV
+
+50 mV to −50 mV
V
REF(VREF
+–V
REF
−) +0.5V to V
+
Electrical Characteristics
The following specifications apply for V+=AV+=DV+= +5.0 VDC,V
REF
+ = 2.5 VDC,V
REF
− = GND, VIN− = 2.5V for Signed
Characteristics, V
IN
− = GND for Unsigned Characteristics and f
CLK
= 2.5 MHz unless otherwise specified. Boldface limits ap-
ply for T
A=TJ=TMIN
to T
MAX
; all other limits TA=TJ= +25˚C. (Notes 8, 9, 10)
Symbol Parameter Conditions Typical Limits Units
(Note 11) (Note 12) (Limits)
SIGNED STATIC CONVERTER CHARACTERISTICS
Resolution with No Missing Codes 10 + Sign Bits
TUE Total Unadjusted Error (Note 13)
±
2.0 LSB(max)
INL Positive and Negative Integral
±
1.25 LSB(max)
Linearity Error
Positive and Negative
±
1.5 LSB(max)
Full-Scale Error
Offset Error
±
1.5 LSB(max)
Power Supply Sensitivity
Offset Error V
+
= +5.0V±10%
±
0.2
±
1.0 LSB(max)
+ Full-Scale Error
±
0.2
±
1.0 LSB(max)
− Full-Scale Error
±
0.1
±
0.75 LSB(max)
DC Common Mode Error (Note 14) V
IN
+=VIN−=VINwhere
±
0.1
±
0.33 LSB(max)
5.0V ≥ V
IN
≥ 0V
Multiplexer Channel to
±
0.1 LSB
Channel Matching
UNSIGNED STATIC CONVERTER CHARACTERISTICS
Resolution with No Missing Codes 10 Bits
TUE Total Unadjusted Error (Note 13) V
REF
+ = 4.096V
±
0.75 LSB
INL Integral Linearity Error V
REF
+ = 4.096V
±
0.50 LSB
Full-Scale Error V
REF
+ = 4.096V
±
1.25 LSB(max)
Offset Error V
REF
+ = 4.096V
±
1.25 LSB(max)
Power Supply Sensitivity
Offset Error V
+
= +5.0V±10%
±
0.1 LSB
Full-Scale Error V
REF
+ = 4.096V
±
0.1 LSB
DC Common Mode Error (Note 14) V
IN
+=VIN−=VINwhere
+5.0V ≥ V
IN
≥ 0V
±
0.1 LSB
ADC10731/ADC10732/ADC10734/ADC10738
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Electrical Characteristics (Continued)
The following specifications apply for V+=AV+=DV+= +5.0 VDC,V
REF
+ = 2.5 VDC,V
REF
− = GND, VIN− = 2.5V for Signed
Characteristics, V
IN
− = GND for Unsigned Characteristics and f
CLK
= 2.5 MHz unless otherwise specified. Boldface limits ap-
ply for T
A=TJ=TMIN
to T
MAX
; all other limits TA=TJ= +25˚C. (Notes 8, 9, 10)
Symbol Parameter Conditions Typical Limits Units
(Note 11) (Note 12) (Limits)
UNSIGNED STATIC CONVERTER CHARACTERISTICS
Multiplexer Channel to Channel
Matching
V
REF
+ = 4.096V
±
0.1 LSB
DYNAMIC SIGNED CONVERTER CHARACTERISTICS
S/(N+D) Signal-to-Noise Plus Distortion Ratio V
IN
= 4.85 VPP,67 dB
and f
IN
= 1 kHz to 15 kHz
ENOB Effective Number of Bits V
IN
= 4.85 VPP, 10.8 Bits
and f
IN
= 1 kHz to 15 kHz
THD Total Harmonic Distortion V
IN
= 4.85 VPP, −78 dB
and f
IN
= 1 kHz to 15 kHz
IMD Intermodulation Distortion V
IN
= 4.85 VPP, −85 dB
and f
IN
= 1 kHz to 15 kHz
Full-Power Bandwidth V
IN
= 4.85 VPP, where 380 kHz
S/(N + D) Decreases
3dB
Multiplexer Channel to Channel
Crosstalk
f
IN
= 15 kHz −80 dB
DYNAMIC UNSIGNED CONVERTER CHARACTERISTIC
S/(N+D) Signal-to-Noise Plus Distortion Ratio V
REF
+ = 4.096V,
V
IN
= 4.0 VPP, and 60 dB
f
IN
=1 kHz to 15 kHz
Effective Bits V
REF
+ = 4.096V,
V
IN
= 4.0 VPP, and 9.8 Bits
f
IN
= 1 kHz to 15 kHz
THD Total Harmonic Distortion V
REF
+ = 4.096V,
V
IN
= 4.0 VPP, and −70 dB
f
IN
= 1 kHz to 15 kHz
IMD Intermodulation Distortion V
REF
+ = 4.096V,
V
IN
= 4.0 VPP, and −73 dB
f
IN
= 1 kHz to 15 kHz
Full-Power Bandwidth V
IN
= 4.0 VPP,
V
REF
+ = 4.096V, 380 kHz
where S/(N+D) decreases
3dB
Multiplexer Channel to Channel f
IN
= 15 kHz,
−80 dB
Crosstalk V
REF
+ = 4.096V
REFERENCE INPUT AND MULTIPLEXER CHARACTERISTICS
Reference Input Resistance 7 kΩ
5.0 kΩ(min)
9.5 kΩ(max)
C
REF
Reference Input Capacitance 70 pF
MUX Input Voltage −50 mV(min)
AV
+
+50 mV (max)
C
IM
MUX Input Capacitance 47 pF
ADC10731/ADC10732/ADC10734/ADC10738
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Electrical Characteristics (Continued)
The following specifications apply for V+=AV+=DV+= +5.0 VDC,V
REF
+ = 2.5 VDC,V
REF
− = GND, VIN− = 2.5V for Signed
Characteristics, V
IN
− = GND for Unsigned Characteristics and f
CLK
= 2.5 MHz unless otherwise specified. Boldface limits ap-
ply for T
A=TJ=TMIN
to T
MAX
; all other limits TA=TJ= +25˚C. (Notes 8, 9, 10)
Symbol Parameter Conditions Typical Limits Units
(Note 11) (Note 12) (Limits)
REFERENCE INPUT AND MULTIPLEXER CHARACTERISTICS
Off Channel Leakage Current
(Note 15)
On Channel = 5V and −0.4 −3.0 µA(max)
Off Channel = 0V
On Channel = 0V and 0.4 3.0 µA(max)
Off Channel = 5V
On Channel Leakage Current On Channel = 5V and 0.4 3.0 µA(max)
(Note 15) Off Channel = 0V
On Channel = 0V and −0.4 −3.0 µA(max)
Off Channel = 5V
REFERENCE CHARACTERISTICS
V
REF
Out Reference Output Voltage 2.5V±0.5% 2.5V±2% V(max)
∆V
REF
/∆TV
REF
Out Temperature Coefficient
±
40 ppm/˚C
∆V
REF
/∆ILLoad Regulation, Sourcing 0 mA ≤ IL≤ +4 mA
±
0.003
±
0.05 %/mA(max)
∆V
REF
/∆ILLoad Regulation, Sinking 0 mA ≤ IL≤ −1 mA
±
0.2
±
0.6 %/mA(max)
Line Regulation 5V
±
10%
±
0.3
±
2.5 mV(max)
I
SC
Short Circuit Current V
REF
Out=0V 13 22 mA(max)
Noise Voltage
10 Hz to 10 kHz,
C
L
= 100 µF
5µV
∆V
REF
/∆t Long-term Stability
±
120 ppm/kHr
t
SU
Start-Up Time CL= 100 µF 100 ms
DIGITAL AND DC CHARACTERISTICS
V
IN(1)
Logical “1” Input Voltage V+= 5.5V 2.0 V(min)
V
IN(0)
Logical “0” Input Voltage V+= 4.5V 0.8 V(max)
I
IN(1)
Logical “1” Input Current VIN= 5.0V 0.005 +2.5 µA(max)
I
IN(0)
Logical “0” Input Current VIN= 0V −0.005 −2.5 µA(max)
V
OUT(1)
Logical “1” Output Voltage V+= 4.5V, I
OUT
= −360 µA 2.4 V(min)
V
+
= 4.5V, I
OUT
= −10 µA 4.5 V(min)
V
OUT(0)
Logical “0” Output Voltage V+= 4.5V, I
OUT
= 1.6 mA 0.4 V(min)
I
OUT
TRI-STATE Output Current V
OUT
= 0V −0.1 −3.0 µA(max)
V
OUT
= 5V +0.1 +3.0 µA(max)
+I
SC
Output Short Circuit Source Current V
OUT
= 0V, V+= 4.5V −30 −15 mA(min)
−I
SC
Output Short Circuit Sink Current V
OUT
=V+= 4.5V 30 15 mA(min)
I
D
+ Digital Supply Current CS = HIGH, Power Up 0.9 1.3 mA(max)
(Note 17) CS = HIGH, Power Down
0.2 0.4 mA(max)
CS = HIGH, Power Down,
and CLK Off
0.5 50 µA(max)
I
A
+ Analog Supply Current CS = HIGH, Power Up 2.7 6.0 mA(max)
(Note 17) CS = HIGH, Power Down
3 15 µA(max)
I
REF
Reference Input Current V
REF
+ = +2.5V and 0.6 mA(max)
CS = HIGH, Power Up
AC CHARACTERISTICS
f
CLK
Clock Frequency 3.0 2.5 MHz(max)
5 kHz(min)
Clock Duty Cycle 40 %(min)
60 %(max)
t
C
Conversion Time 12 12 Clock
ADC10731/ADC10732/ADC10734/ADC10738
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Electrical Characteristics (Continued)
The following specifications apply for V+=AV+=DV+= +5.0 VDC,V
REF
+ = 2.5 VDC,V
REF
− = GND, VIN− = 2.5V for Signed
Characteristics, V
IN
− = GND for Unsigned Characteristics and f
CLK
= 2.5 MHz unless otherwise specified. Boldface limits ap-
ply for T
A=TJ=TMIN
to T
MAX
; all other limits TA=TJ= +25˚C. (Notes 8, 9, 10)
Symbol Parameter Conditions Typical Limits Units
(Note 11) (Note 12) (Limits)
AC CHARACTERISTICS
Cycles
5 5 µs(max)
t
A
Acquisition Time 4.5 4.5 Clock
Cycles
2 2 µs(max)
t
SCS
CS Set-Up Time, Set-Up Time from
Falling Edge of CS to Rising Edge of
Clock
14 30 ns(min)
(1 t
CLK
(1 t
CLK
(max)
−14ns) −30 ns)
t
SDI
DI Set-Up Time, Set-Up Time from
Data Valid on DI to Rising Edge of
Clock
16 25 ns(min)
t
HDI
DI Hold Time, Hold Time of DI Data
from Rising Edge of Clock to Data
not Valid on DI
2 25 ns(min)
t
AT
DO Access Time from Rising Edge of
CLK When CS is “Low” during a
Conversion
30 50 ns(min)
t
AC
DO or SARS Access Time from CS ,
Delay from Falling Edge of CS to
Data Valid on DO or SARS
30 70 ns(max)
t
DSARS
Delay from Rising Edge of Clock to
Falling Edge of SARS when CS is
“Low”
100 200 ns(max)
t
HDO
DO Hold Time, Hold Time of Data on
DO after Falling Edge of Clock
20 35 ns(max)
t
AD
DO Access Time from Clock, Delay
from Falling Edge of Clock to Valid
Data of DO
40 80 ns(max)
t
1H,t0H
Delay from Rising Edge of CS to DO
or SARS TRI-STATE
40 50 ns(max)
t
DCS
Delay from Falling Edge of Clock to
Falling Edge of CS
20 30 ns(min)
t
CS(H)
CS “HIGH” Time for A/D Reset after
Reading of Conversion Result
1 CLK 1 CLK cycle(min)
t
CS(L)
ADC10731 Minimum CS “Low” Time
to Start a Conversion
1 CLK 1 CLK cycle(min)
t
SC
Time from End of Conversion to CS
Going “Low”
5 CLK 5 CLK
cycle(min)
t
PD
Delay from Power-Down command to
10% of Operating Current
1µs
t
PC
Delay from Power-Up Command to
Ready to Start a New Conversion
10
µs
C
IN
Capacitance of Logic Inputs 7 pF
C
OUT
Capacitance of Logic Outputs 12 pF
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.
Note 2: Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifcations and
test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may
degrade when the device is not operated under the listed test conditions.
Note 3: All voltages are measured with respect to GND, unless otherwise specified.
ADC10731/ADC10732/ADC10734/ADC10738
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Electrical Characteristics (Continued)
Note 4: When the input voltage (VIN) at any pin exceeds the power supplies (V
IN
<
GND or V
IN
>
AV+or DV+), the current at that pln should be limited to 30 mA.
The 120 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 30 mA to four.
Note 5: The maximum power dissipation must be derated at elevated temperatures and is dictated by T
Jmax
, θJAand the ambient temperature, TA. The maximum
allowable power dissipation at any temperature is P
D
=(T
Jmax−TA
)/θJAor the number given In the Absolute Maximum Ratings, whichever is lower.For this device,
T
Jmax
= 150˚C. The typical thermal resistance (θJA) of these Paris when board mounted can be found in the following table:
Part Number Thermal Resistance Package
Type
ADC10731CIWM 90˚C/W M16B
ADC10732CIWM 80˚C/W M20B
ADC10734CIMSA 134˚C/W MSA20
ADC10734CIWM 80˚C/W M20B
ADC10738CIWM 75˚C/W M24B
Note 6: The human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. The machine model is a 200 pF capacitor discharged
directly into each pin.
Note 7: See AN-450 “Surface Mounting Methods and Their Effect on Product Reliability” or the section titied “Surtace Mount” found in any post 1986 National
Semiconductor Linear Data Book for other methods of soldering surtace mount devices.
Note 8: Two on-ohip diodes are tied to each analog input as shown below. They will forward-conduct for analog input voltages one diode drop below ground or one
diode drop greater than V
+
supply. Be careful during testing at low V+levels (+4.5V), as high level analog inputs (+5V) can cause an input diode to conduct,
especially at elevated temperatures, which will cause errors In the conversion result. The specification allows 50 mV forward bias of either diode; this means that
as long as the analog V
IN
does not exceed the supply voltage by more than 50 mV, the output code will be oorrect. Exceeding this range on an unselected channel
will corrupt the reading of a selected channel. If AV
+
and DV+are minimum (4.5 VDC) and full scale must be ≤+4.55 VDC.
Note 9: No connection exists between AV
+
and DV+on the chip.
To guarantee accuracy, it is required that the AV
+
and DV+be connected together to a power supply with separate bypass filter at eacn V+pin.
Note 10: One LSB is referenced to 10 bits of resolution.
Note 11: Typicals are at T
J=TA
= 25˚C and represent most likely pararmetric norm.
Note 12: Tested limits are guaranteed to National’s AOQL (Average Outgolng Quality Level).
Note 13: Total unadjusted error includes offset, full-scale, linearity, multiplexer, and hold step errors.
Note 14: The DC common-mode error is measured in the differential multiplexer mode with the assigned positive and negative input channels shorted together.
Note 15: Channel leakage current is measured after the channel selection.
Note 16: All the timing specifications are tested at the TTL logic levels, V
IL
= 0.8V for a falling edge and VIH= 2.0V for a rising. TRl-STATE voltage level is forced
to 1.4V.
Note 17: The voltage applied to the digital inputs will affect the current drain during power down. These devices are tested with CMOS logic levels (logic Low = 0V
and logic High = 5V). TTL levels increase the current, during power down, to about 300 µA.
DS011390-6
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Electrical Characteristics (Continued)
DS011390-8
FIGURE 1. Transter Characteristic
DS011390-26
FIGURE 2. Simplified Error Curve vs Output Code
ADC10731/ADC10732/ADC10734/ADC10738
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