NSC ADC10664CIWM, ADC10662CIWM Datasheet
June 1999
ADC10662/ADC10664
10-Bit 360 ns A/D Converter with Input Multiplexer and
Sample/Hold
ADC10662/ADC10664 10-Bit 360 ns A/D Converter with Input Multiplexer and Sample/Hold
General Description
Using an innovative, patented multistep*conversion technique, the 10-bit ADC10662 and ADC10664 are 2- and
4-input CMOS analog-to-digital converters offering
sub-microsecond conversion times yet dissipating a maximum of only 235 mW. The ADC10662 and ADC10664 perform a 10-bit conversion in two lower-resolution “flashes”,
thus yielding a fast A/D without the cost, power dissipation,
and other problems associated with true flash approaches.
In addition to standard static performance specifications
(Linearity,Full-Scale Error, etc.) dynamic performance (THD,
S/N) is guaranteed.
The analog input voltage to the ADC10662 andADC10664 is
sampled and held by an internal sampling circuit. Input signals at frequencies from dc to over 250 kHz can therefore be
digitized accurately without the need for an external
sample-and-hold circuit.
The ADC10662 and ADC10664 include a “speed-up” pin.
Connecting an external resistor between this pin and ground
reduces the typical conversion time to as little as 360 ns.
For ease of interface to microprocessors, the ADC10662 and
ADC10664 have been designed to appear as a memory location or I/O port without the need for external interface
logic.
Ordering Information
ADC10662
Industrial
(−40˚C ≤ T
ADC10662CIWM M24B Small Outline
≤ +85˚C)
A
Package
Features
n Built-in sample-and-hold
n Single +5V supply
n 2- or 4-input multiplexer options
n No external clock required
Key Specifications
n Conversion time to 10 bits: 360 ns typical, 466 ns
max over temperature
n Sampling Rate: 1.5 MHz (min)
n Low power dissipation: 235 mW (max)
n Total harmonic distortion (50 kHz): −60 dB (max)
n No missing codes over temperature
Applications
n Digital signal processor front ends
n Instrumentation
n Disk drives
n Mobile telecommunications
ADC10664
Industrial
(−40˚C ≤ T
ADC10664CIWM M28B Small Outline
≤ +85˚C)
A
Package
*
U.S. Patent Number 4918449
®
TRI-STATE
is a registered trademark of National Semiconductor Corporation.
© 1999 National Semiconductor Corporation DS011192 www.national.com
Simplified Block Diagram
*ADC10664 Only
Connection Diagrams
Top View
DS011192-9
DS011192-10
DS011192-11
Top View
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Pin Descriptions
DVCC,
AV
CC
INT
S/H This is the Sample/Hold control input. When
RD
CS
S0, S1 These pins select the analog input that will be
V
REF−
V
REF+
These are the digital and analog positive supply voltage inputs. They should always be connected to the same voltage source, but are
brought out separately to allow for separate
bypass capacitors. Each supply pin should be
bypassed with a 0.1 µF ceramic capacitor in
parallel with a 10 µF tantalum capacitor to
ground.
This is the active low interrupt output. INT
goes low at the end of each conversion, and
returns to a high state following the rising edge
of RD .
this pin is forced low (and CS is low), it causes
the analog input signal to be sampled and initiates a new conversion.
This is the active low Read control input.
When this RD and CS are low, any data
present in the output registers will be placed
on the data bus.
This is the active low Chip Select control input.
When low, this pin enables the RD and S /H
pins.
connected to the A/D during the conversion.
The input is selected based on the state of S0
and S1 when S /H makes its High-to-Low transition (See the Timing Diagrams). The
ADC10664 includes both S0 and S1. The
ADC10662 includes just S0.
,
These are the reference voltage inputs. They
may be placed at any voltage between GND
and V
, but V
CC
V
. An input voltage equal to V
REF−
duces an output code of 0, and an input voltage equal to (V
put code of 1023.
must be greater than
REF+
− 1 LSB) produces an out-
REF+
REF−
pro-
V
V
IN0,VIN1
IN2,VIN3
,
These are the analog input pins. The
ADC10662 has two inputs (V
the ADC10664 has four inputs (V
V
and V
IN2
should be less than 500Ω for best accuracy
). The impedance of the source
IN3
and V
IN0
and conversion speed. For accurate conversions, no input pin (even one that is not selected) should be driven more than 50 mV
GND, AGND,
DGND
above V
These are the power supply ground pins. The
ADC10662 and ADC10664 have separate
or 50 mV below ground.
CC
analog and digital ground pins (AGND and
DGND) for separate bypassing of the analog
and digital supplies. The ground pins should
be connected to a stable, noise-free system
ground. Both pins should be returned to the
same potential.
DB0–DB9 These are the TRI-STATE output pins.
SPEED
ADJ
By connecting a resistor between this pin and
ground, the conversion time can be reduced.
The specifications listed in the table of Electri-
cal Characteristics apply for a speed adjust re-
sistor (R
kΩ (Mode 2). See the Typical Performance
) equal to 14.0 kΩ (Mode 1) or 8.26
SA
Curves and the table of Electrical Characteris-
tics.
) and
IN1
IN0,VIN1
,
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Absolute Maximum Ratings (Notes 1, 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
+
=
Supply Voltage (V
Voltage at Any Input or Output −0.3V to V
Input Current at Any Pin (Note 3) 5 mA
Package Input Current (Note 3) 20 mA
Power Dissipation (Note 4) 875 mW
ESD Susceptability (Note 5) 2000V
Soldering Information (Note 6)
N Package (10 Sec) 260˚C
Converter Characteristics
The following specifications apply for V
through a 14.0 kΩ resistor (Mode 1) or an 8.26 kΩ resistor (Mode 2) unless otherwise specified. Boldface limits apply for T
=
=
T
to T
T
J
Min
Max
=
AV
DV
CC
CC
; all other limits T
) −0.3V to +6V
+
=
=
T
A
+5V, V
=
+25˚C.
J
REF(+)
+
+ 0.3V
=
+5V, V
SO Package:
Vapor Phase (60 Sec) 215˚C
Infrared (15 Sec) 220˚C
Storage Temperature Range −65˚C to +150˚C
Junction Temperature 150˚C
Operating Ratings (Notes 1, 2)
Temperature Range T
ADC10662CIN, ADC10662CIWM,
ADC10664CIN,
ADC10664CIWM −40˚C ≤ T
Supply Voltage Range 4.5V to 5.5V
=
GND, and Speed Adjust pin connected to ground
REF(−)
MIN
≤ TA≤ T
≤ +85˚C
A
Symbol Parameter Conditions Typical Limit Units
(Note 7) (Note 8) (Limit)
Resolution 10 Bits
Integral Linearity Error
Offset Error
Full-Scale Error
Total Unadjusted Error
±
0.5
±
0.5
±
1.0/±1.5 LSB
±
1 LSB (max)
±
1 LSB (max)
±
1.5/±2.0 LSB
Missing Codes 0 (max)
Power Supply Sensitivity V
THD Total Harmonic Distortion (Note 10) f
SNR Signal-to-Noise Ratio (Note 10) f
ENOB Effective Number of Bits (Note 10) f
R
REF
Reference Resistance 650 400 Ω (min)
=
5V
+
=
V
5V
=
1 kHz, 4.85 V
IN
=
f
50 kHz, 4.85 V
IN
=
f
100 kHz, 4.85 V
IN
=
f
240 kHz, 4.85 V
IN
=
1 kHz, 4.85 V
IN
=
f
50 kHz, 4.85 V
IN
=
f
100 kHz, 4.85 V
IN
=
1 kHz, 4.85 V
IN
=
f
50 kHz, 4.85 V
IN
±
5%,V
±
10%,V
REF
REF
=
4.5V
=
4.5V
P-P
P-P
P-P
P-P
P-P
P-P
P-P
P-P
P-P
±
1/16 LSB
1
±
⁄
8
LSB
−68 dB
−66 −60 dB (max)
−62 dB
−58 dB
61 dB
60 58 dB (min)
60 dB
9.6 Bits
9.5 9 Bits (min)
+
900 Ω (max)
V
V
V
V
V
V
REF(+)
REF(−)
REF(+)
REF(−)
IN
IN
V
Input Voltage V++ 0.05 V (max)
REF(+)
V
Input Voltage GND −
REF(−)
V
Input Voltage V
REF(+)
V
Input Voltage V
REF(−)
0.05
REF(−)
REF(+)
V (min)
V (min)
V (max)
Input Voltage V++ 0.05 V (max)
Input Voltage GND −
V (min)
0.05
OFF Channel Input Leakage Current CS=V
ON Channel Input Leakage Current CS=V
+
+
,V
,V
+
=
V
IN
+
=
V
IN
0.01 3 µA (max)
±
1 −3 µA (max)
MAX
A
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DC Electrical Characteristics
The following specifications apply for V
through a 14.0 kΩ resistor (Mode 1) or an 8.26 kΩ resistor (Mode 2) unless otherwise specified. Boldface limits apply for
=
=
to T
T
T
A
T
J
MIN
Symbol Parameter Conditions
V
V
I
I
V
V
I
DI
AI
IN(1)
IN(0)
OUT
IN(1)
IN(0)
OUT(1)
OUT(0)
CC
CC
Logical “1” Input Voltage V
Logical “0” Input Voltage V
Logical “1” Input Current V
Logical “0” Input Current V
Logical “1” Output Voltage V
Logical “0” Output Voltage V
TRI-STATE®Output Current V
DVCCSupply Current CS=S/H=RD=0 1.0 2 mA (max)
AVCCSupply Current CS=S/H=RD=0 30 45 mA (max)
; all other limits T
MAX
+
=
+5V, V
A
=
5V V
REF(+)
=
=
T
+25˚C.
J
+
=
5.5V 2.0 V (min)
+
=
4.5V 0.8 V (max)
=
5V 0.005 3.0 µA (max)
IN(1)
0V −0.005 −3.0 µA (max)
IN(0)
+
=
4.5V, I
+
=
V
4.5V, I
+
=
4.5V, I
=
5V 0.1 50 µA (max)
OUT
=
V
0V −0.1 −50 µA (max)
OUT
=
GND, and Speed Adjust pin connected to ground
REF(−)
Typical
(Note 7)
=
−360 µA 2.4 V (min)
OUT
=
−10 µA 4.25 V (min)
OUT
=
1.6 mA 0.4 V (max)
OUT
Limit
(Note 8)
(Limits)
Units
AC Electrical Characteristics
The following specifications apply for V
nected to ground through a 14.0 kΩ resistor (Mode 1) or an 8.26 kΩ resistor (Mode 2) unless otherwise specified. Boldface
limits apply for T
Symbol Parameter Conditions
=
=
T
A
T
J
MIN
to T
+
MAX
=
+5V, t
=
=
t
r
f
; all other limits T
20 ns, V
=
A
=
5V, V
REF(+)
=
T
+25˚C.
J
=
GND, and Speed Adjust pin con-
REF(−)
Typical
(Note 7)
Limit
(Note 8)
Units
(Limits)
Mode 1 Conversion Time
t
CONV
t
CRD
t
ACC1
t
ACC2
t
SH
t
1H,t0H
t
INTH
t
P
t
MS
t
MH
C
VIN
C
OUT
C
IN
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.OperatingRatings indicate conditions for which the device is functional. These ratings do not guarantee specific performance limits, however.For guaranteed specifications and test conditions, see the Electrical Characteristics. The
guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed
test conditons.
Note 2: All voltages are measured with respect to GND, unless otherwise specified.
Note 3: When the input voltage (V
to 5 mA or less. The 20 mA package input current limits the number of pins that can safely exceed the power supplies with an input current of 5 mA to four.
Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by T
allowable power dissipation at any temperature is P
the maximum derated power dissipation will be reached only during fault conditions. For these devices, T
tables below:
from Rising Edge of S /H
to Falling Edge of INT
Mode 2 Conversion Time 470 610 ns (max)
=
1k, C
=
100 pF
L
=
100 pF
L
(Figure 1 )
=
10 pF
L
; (Note 9) 150 ns (max)
Access Time (Delay from Falling
Mode 1; C
Edge of RD to Output Valid)
Access Time (Delay from Falling
Mode 2; C
Edge of RD to Output Valid)
Minimum Sample Time Mode 1
TRI-STATE Control (Delay
from Rising Edge of RD
R
L
to High-Z State)
Delay from Rising Edge of RD
to Rising Edge of INT
=
C
100 pF
L
Delay from End of Conversion
to Next Conversion
Multiplexer Control Setup Time 10 75 ns (max)
Multiplexer Hold Time 10 40 ns (max)
Analog Input Capacitance 35 pF (max)
Logic Output Capacitance 5 pF (max)
Logic Input Capacitance 5 pF (max)
) at any pin exceeds the power supply rails (V
IN
=
(T
D
)/θJAor the number given in the Absolute Maximum Ratings, whichever is lower. In most cases,
JMAX−TA
IN
<
GND or V
>
V+) the absolute value of current at that pin should be limited
IN
JMAX
JMAX
360 466 ns (max)
30 50 ns (max)
475 616 ns (max)
30 60 ns (max)
25 50 ns (max)
50 ns (max)
, θJAand the ambient temperature, TA. The maximum
for a board-mounted device can be found from the
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