January 2000
ADC10030
10-Bit, 30 MSPS, 125 mW A/D Converter with Internal
Sample and Hold
ADC10030 10-Bit, 30 MSPS, 125 mW A/D Converter with Internal Sample and Hold
General Description
The ADC10030 is a low power, high performance CMOS
analog-to-digital converter that digitizes signals to 10 bits
resolution at sampling rates up to 30 Msps while consuming
a typical 125 mW from a single 5V supply. Reference force
and sense pins allow the user to connect an external reference buffer amplifierto ensure optimal accuracy.No missing
codes is guaranteed over the full operating temperature
range. The unique two-stage architecture achieves 9.1 Effective Bits with a 15 MHz input signal and a 30 MHz clock
frequency. Output formatting is straight binary coding.
To ease interfacing to 3V systems, the digital I/O power pins
of the ADC10030 can be tied to a 3V power source, making
the outputs 3V compatible. When not converting, power consumption can be reduced by pulling the PD (Power Down)
pin high, placing the converter into a low power standby
state, where it typically consumes less than 4 mW. The
ADC10030’s speed, resolution and single supply operation
makes it well suited for a variety of applications in video, imaging, communications, multimedia and high speed data acquisition. Low power, single supply operation ideally suit the
ADC10030 for high speed portable applications, and its
speed and resolution are ideal for charge coupled device
(CCD) input systems.
The ADC10030 comes in a space saving 32-pin TQFP and
operates over the industrial (−40˚C ≤ T
ture range.
≤ +85˚C) tempera-
A
Features
n Internal Sample-and-Hold
n Single +5V Operation
n Low Power Standby Mode
n Guaranteed No Missing Codes
n TRI-STATE
n TTL/CMOS or 3V Logic Input/Output Compatible
®
Outputs
Key Specifications
n Resolution 10 Bits
n Conversion Rate 30 Msps
n ENOB
n DNL 0.40 LSB (typ)
n Conversion Latency 2 Clock Cycles
n PSRR 56 dB
n Power Consumption 125 mW (typ)
n Low Power Standby Mode
@
15 MHz Input 9.1 Bits (typ)
<
3.5 mW (typ)
Applications
n Digital Video
n Communications
n Document Scanners
n Medical Imaging
n Electro-Optics
n Plain Paper Copiers
n CCD Imaging
Connection Diagram
DS101064-1
TRI-STATE®is a registered trademark of National Semiconductor Corporation.
© 2000 National Semiconductor Corporation DS101064 www.national.com
Ordering Information
Commercial Temperature Range
ADC10030
Block Diagram
(−40˚C ≤ T
ADC10030CIVT TQFP
≤ +85˚C)
A
NS Package
DS101064-2
www.national.com 2
Pin Descriptions and Equivalent Circuits
ADC10030
Pin
No.
30 V
31 V
32 V
2V
1V
Symbol Equivalent Circuit Description
IN
REF
REF
REF
REF−
9 CLK
Analog Input signal to be converted. Conversion
range is V
REF
+
StoV
REF
−
S.
Analog input that goes to the high side of the
+
F
+
S
reference ladder of the ADC. This voltage should
+
force V
S to be in the range of 2.6V to 3.8V.
REF
Analog output used to sense the voltage at the top
of the ADC reference ladder.
Analog input that goes to the low side of the
−
F
S
reference ladder of the ADC. This voltage should
force V
S to be in the range of 1.7V to 2.8V.
REF−
Analog output used to sense the voltage at the
bottom of the ADC reference ladder.
Converter digital clock input. VINis sampled on the
falling edge of CLK input.
8PD
26 OE
14
thru
19
and
D0–D9
22
thru
25
3, 7,
28
5, 10 V
V
A
D
Power Down input. When this pin is high, the
converter is in the Power Down mode and the data
output pins are in a high impedance state.
Output Enable pin. When this pin and the PD pin
are low, the output data pins are active. When this
pin or the PD pin is high, the data output pins are in
a high impedance state.
Digital Output pins providing the 10-bit conversion
results. D0 is the LSB, D9 is the MSB. Data is
acquired on the falling edge of the CLK input and
valid data is present 2.0 clock cycles plus t
OD
later.
Positive analog supply pins. These pins should be
connected to a clean, quiet voltage source of +5V.
and VDshould have a common supply and be
V
A
separately bypassed with 10 µF to 50 µF capacitors
in parallel with 0.1 µF capacitors.
Positive digital supply pins. These pins should be
connected to a clean, quiet voltage source of +5V.
and VDshould have a common supply and be
V
A
separately bypassed with 10 µF to 50 µF capacitors
in parallel with 0.1 µF capacitors.
www.national.com3
Pin Descriptions and Equivalent Circuits (Continued)
Pin
ADC10030
No.
12, 21 V
4, 27,
29
6, 11 DGND
13, 20 DGND I/O The ground return of the digital output drivers.
Symbol Equivalent Circuit Description
Positive supply pins for the digital output drivers.
I/O
D
AGND
These pins should be connected to a clean, quiet
voltage source of +3V to +5V and be separately
bypassed with 10 µF to 50 µF capacitors.
The ground return for the analog supply. AGND and
DGND should be connected together close to the
ADC10030 package.
The ground return for the digital supply. AGND and
DGND should be connected together close to the
ADC10030 package.
www.national.com 4
ADC10030
Absolute Maximum Ratings (Notes 1, 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Positive Supply Voltage (V=V
Voltage on Any Pin −0.3V to (V
Input Current at Any Pin (Note 3)
Package Input Current (Note 3)
Package Dissipation at T
A
=
) 6.5V
V
A
D
or VD+0.3V)
A
±
25 mA
±
50 mA
=
25˚C See (Note 4)
ESD Susceptibility (Note 5)
Human Body Model 1500V
Machine Model 200V
Converter Electrical Characteristics
The following specifications apply for V
C
=
L
20 pF, f
CLK
=
27 MHz, R
=
S
=
+5.0V
A
50Ω. Boldface limits apply for T
Symbol Parameter Conditions
Static Converter Characteristics
INL Integral Non-Linearity
DNL Differential-Non-Linearity
Resolution with No Missing
Codes
Zero Scale Offset Error −4 mV
Full-Scale Offset Error +3 mV
Dynamic Converter Characteristics
=
f
IN
=
f
IN
ENOB Effective Number of Bits
S/(N+D)
Signal-to-Noise Plus
Distortion Ratio
SNR Signal-to-Noise Ratio
THD Total Harmonic Distortion
SFDR
Spurious Free Dynamic
Range
Overrange Output Code V
=
f
IN
=
f
IN
=
f
IN
=
f
IN
=
f
IN
=
f
IN
=
f
IN
=
f
IN
=
f
IN
=
f
IN
=
f
IN
=
f
IN
=
f
IN
=
f
IN
=
f
IN
=
f
IN
=
f
IN
=
f
IN
=
f
IN
=
f
IN
=
f
IN
=
f
IN
=
f
IN
>
IN
=
DC,VD
5.0V
DC,VD
1.0 MHz 9.6
4.43 MHz 9.4 Bits
13.5 MHz 9.4 Bits
4.43 MHz, f
15.0 MHz, f
= 30 MHz 9.3 Bits
CLK
= 30 MHz 9.1 Bits
CLK
1.0 MHz 60
4.43 MHz 59 dB
13.5 MHz 58 dB
4.43 MHz, f
15.0 MHz, f
= 30 MHz 58 dB
CLK
= 30 MHz 57 dB
CLK
1.0 MHz 60
4.43 MHz 59 dB
13.5 MHz 59 dB
4.43 MHz, f
15.0 MHz, f
= 30 MHz 59 dB
CLK
= 30 MHz 58 dB
CLK
1.0 MHz −72
4.43 MHz −69 dB
13.5 MHz −66 dB
4.43 MHz, f
15.0 MHz, f
= 30 MHz −64 dB
CLK
= 30 MHz −61 dB
CLK
1.0 MHz 73 dB
4.43 MHz 71 dB
13.5 MHz 68 dB
4.43 MHz, f
15.0 MHz, f
V
+ 1023
REF
= 30 MHz 66 dB
CLK
= 30 MHz 62 dB
CLK
Soldering Temp., Infrared, 10 sec. (Note 6) 300˚C
Storage Temperature −65˚C to +150˚C
Operating Ratings (Notes 1, 2)
Operating Temperature Range −40˚C ≤ T
V
Supply Voltage +4.75V to +5.5V
A,VD
V
I/O Supply Voltage +2.7V to 5.5V
D
V
Voltage Range 1.7V to (VA−1.2V)
IN
V
+ Voltage Range 2.6V to (VA−1.2V)
REF
V
− Voltage Range 1.7V to 2.8V
REF
PD, CLK, OE Voltage Range
I/O=+5.0VDC,V
=
to T
T
A
MIN
MAX
+=+3.5VDC,V
REF
: all other limits T
Typical
(Note 8)
±
0.45
±
0.40
REF
=
25˚C (Note 7)
A
Limits
(Note 9)
±
1.0 LSB(max)
±
0.95 LSB(max)
10 Bits
8.6
53.5
54
−61
≤ +85˚C
A
−0.3V to +5.5V
−=+1.75VDC,
Units
Bits
dB
dB
dB
www.national.com5
Converter Electrical Characteristics (Continued)
The following specifications apply for V
=
C
20 pF, f
L
ADC10030
CLK
=
27 MHz, R
=
S
=
+5.0V
A
50Ω. Boldface limits apply for T
Symbol Parameter Conditions
Dynamic Converter Characteristics
Underrange Output Code V
<
IN
BW Full Power Bandwidth 150 MHz
PSRR
Power Supply Rejection
Ratio
Change in Full Scale with 4.5V to
5.5V Supply Change
DC,VD
V
REF
=
5.0V
I/O=+5.0VDC,V
DC,VD
=
A
+=+3.5VDC,V
to T
T
MIN
REF
: all other limits T
MAX
Typical
(Note 8)
REF
=
25˚C (Note 7)
A
Limits
(Note 9)
−=+1.75VDC,
−
56 dB
Reference, DC, and Logic Electrical Characteristics
The following specifications apply for V
+1.75VDC,C
(Note 7)
L
=
20 pF, f
CLK
=
27 MHz, R
=
+5.0V
A
=
50Ω. Boldface limits apply for T
S
Symbol Parameter Conditions
Reference and Analog Input Characteristics
V
IN
C
IN
I
IN
R
REF
V
+ Positive Reference Voltage 3.5 3.8 V(max)
REF
−
V
REF
(V
REF
(V
REF
Analog Input Range
Analog VINInput
Capacitance
Input Leakage Current 10 µA
Reference Ladder
Resistance
Negative Reference
Voltage
+) −
Total Reference Voltage 1.75
−)
CLK, OE, PD, Digital Input Characteristics
V
IH
V
IL
I
IH
I
IL
Logical “1” Input Voltage V
Logical “0” Input Voltage V
Logical “1” Input Current V
Logical “0” Input Current V
=
D
=
D
=
IH
=
IL
DB0–DB9 Digital Output Characteristics
I/O=+4.5V, I
V
V
OH
V
OL
I
OZ
I
OS
Logical “1” Output Voltage
Logical “0” Output Voltage
TRI-STATE Output Current
Output Short Circuit
Current
D
I/O=+2.7V, I
V
D
I/O=+4.5V, I
V
D
I/O=+2.7V, I
V
D
V
OUT
V
OUT
VDI/O=3V
V
I/O=5V
D
Power Supply Characteristics
PD=LOW, Ladder Current not
I
A
Analog Supply Current
included
PD=HIGH, Ladder Current not
included
PD=LOW, Ladder Current not
+
I
D
I/O
I
D
Digital Supply Current
included
PD=HIGH, Ladder Current not
included
DC,VD
=
+5.0V
I/O=+5.0VDC,V
DC,VD
+=+3.5VDC,V
REF
=
to T
T
A
MIN
Typical
(Note 8)
: all other limits T
MAX
Limits
(Note 9)
1.75
3.5
1.6
3.8
REF
−
5pF
1000
850
1150
1.75 1.6 V(min)
1.0
2.2
5.5V 2.0 V(min)
4.5V 1.0 V(max)
V
D
10 µA
DGND −10 µA
=
=
DGND
V
D
OUT
OUT
OUT
OUT
=
−0.5 mA
=
−0.5 mA
=
−1.6 mA
=
−1.6 mA
−10
10
±
12 mA
±
25 mA
4.0
2.4
0.4
0.4
17.6
0.5
6.6
0.2
=
=
A
mA(max)
mA(max)
Units
25˚C
Units
V(min)
V(max)
Ω(min)
Ω(max)
V(min)
V(max)
V(min)
V(min)
V(max)
V(max)
µA
µA
mA
mA
www.national.com 6
Reference, DC, and Logic Electrical Characteristics (Continued)
The following specifications apply for V
+1.75VDC,C
(Note 7)
L
=
20 pF, f
CLK
=
27 MHz, R
=
+5.0V
A
=
50Ω. Boldface limits apply for T
S
DC,VD
=
+5.0V
DC,VD
Symbol Parameter Conditions
Power Supply Characteristics
PD = LOW 121 130 mW(max)
P
D
Power Consumption
PD = HIGH 3.5
PD = LOW, f
= 30 MHz 125 mW
CLK
I/O=+5.0VDC,V
=
T
A
MIN
+=+3.5VDC,V
REF
to T
MAX
Typical
(Note 8)
: all other limits T
Limits
(Note 9)
REF
=
−
=
25˚C
A
Units
AC Electrical Characteristics
The following specifications apply for V
+1.75V
(Note 7)
DC,CL
=
20 pF, f
CLK
=
27 MHz, R
=
+5.0V
A
=
50Ω. Boldface limits apply for T
S
Symbol Parameter Conditions
f
f
t
t
CLK1
CLK2
CH
CL
Maximum Clock Frequency 27 30 MHz
Minimum Clock Frequency 1 MHz
Clock High Time 16.5 ns(min)
Clock Low Time 16.5 ns(min)
Duty Cycle 50
DC,VD
=
+5.0V
DC,VD
I/O=5.0VDC,V
=
T
A
MIN
Typical
(Note 8)
+=+3.5VDC,V
REF
to T
: all other limits T
MAX
(Note 9)
Limits
45
55
Pipeliine Delay (Latency) 2.0 Clock Cycles
t
rc,tfc
t
r,tf
t
OD
t
OH
t
DIS
t
EN
t
VALID
t
AJ
t
WU
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions.
Note 2: All voltages are measured with respect to GND=AGND=DGND=0V, unless otherwise specified.
Note 3: When the input voltage at any pin exceeds the power supplies (V
maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 25 mA to two.
Note 4: The absolute maximum junction temperature (T
junction-to-ambient thermal resistance (θ
TQFP, θ
device under normal operation will typically be about 137 mW (125 mW quiescent power+2mWreference ladder power +10 mW due to 1 TTL load on each digital
output). The values for maximum power dissipation listed above will be reached only when the ADC10030 is operated in a severe fault condition (e.g. when input or
output pins are driven beyond the power supply voltages, or the power supply polarity is reversed). Obviously, such conditions should always be avoided.
Note 5: Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through ZERO Ω.
Note 6: See AN450, “Surface Mounting Methods and Their Effect on Product Reliability”, or the section entitled “Surface Mount” found in any post 1986 National
Semiconductor Linear Data Book, for other methods of soldering surface mount devices.
Note 7: The inputs are protected as shown below. Input voltage magnitudes up to 300 mV beyond the supply rails will not damage this device. However, errors in
the A/D conversion can occur if the input goes above V
is 69˚C/W, so PDMAX = 1,811 mW at 25˚C and 942 mW at the maximum operating ambient temperature of 85˚C. Note that the power dissipation of this
JA
Clock Input Rise and Fall Time 4 ns(max)
Output Rise and Fall Times 10 ns
Fall of CLK to Data Valid 20 25 ns(max)
Output Data Hold Time 12 ns
Rising Edge of OE to
TRI-STATE
Falling Edge of OE to Valid
Data
From Output High,
2kΩto Ground
From Output Low, 2
kΩ to V
1kΩto V
I/O
D
CC
25 ns
18 ns
25 ns
Data Valid Time 27 ns
Aperture Jitter
Full Scale Step Response t
Overrange Recovery Time
PD Low to1⁄2LSB Accurate
Conversion (Wake-Up Time)
max) for this device is 150˚C. The maximum allowable power dissipation is dictated by TJmax, the
), and the ambient temperature (TA), and can be calculated using the formula PDMAX=(TJmax − TA)/θJA. In the 32-pin
JA
J
or below AGND by more than 300 mV.
A
=
10 ns 1 conversion
r
V
Step from
IN
+ +100 mV) to
(V
REF
−)
(V
REF
IN
<
GND or V
>
VAor VD), the current at that pin should be limited to 25 mA. The 50 mA
IN
<
30 ps
1 conversion
700 ns
REF
−
=
A
(Limits)
%
=
Units
%
(min)
(max)
25˚C
ADC10030
www.national.com7
AC Electrical Characteristics (Continued)
ADC10030
DS101064-12
DS101064-11
Note 8: Typical figures are at T
Note 9: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 10: When the input signal is between V
the output code will be 000h, or all 0s.
Typical Performance Characteristics V
=
25˚C, and represent most likely parametric norms.
J
+ and (VA+ 300 mV), the output code will be 3FFh, or all 1s. When the input signal is between −300 mV and V
REF
=
V
A
D
MHz, unless otherwise specified.
Typical INL
DS101064-41
INL vs Clock Duty Cycle
INL vs f
CLK
Typical DNL
=
V
D
DS101064-42
I/O=5V, T
=
25˚C, f
A
INL vs V
DNL vs f
A
CLK
=
IN
4.4 MHz, f
DS101064-24
CLK
DS101064-43
−,
REF
=
27
DS101064-44
www.national.com 8
DS101064-45
DS101064-46
Typical Performance Characteristics V
MHz, unless otherwise specified.. (Continued)
ADC10030
=
=
D
I/O=5V, T
V
D
V
A
A
=
25˚C, f
=
IN
4.4 MHz, f
CLK
=
27
DNL vs V
A
SINAD & ENOB vs V
A
DS101064-47
DNL vs Clock Duty Cycle
IA+IDvs Temparature
DS101064-48
SINAD & ENOB vs
Temperature and f
IN
DS101064-49
Spectral Response at 27 MSPS
DS101064-50
Spectral Response at 30 MSPS
DS101064-54
Dynamics at 27 MSPS
Specification Definitions
APERTURE JITTER is the variation in aperture delay from
sample to sample. Aperture jitter shows up as input noise.
APERTURE DELAY See Sampling Delay.
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of
the maximum deviation from the ideal step size of 1 LSB.
EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE
BITS) is another method of specifying Signal-to-Noise plus
Distortion Ratio (S/N+D or SINAD). ENOB is defined as (SINAD −1.76) / 6.02.
FULL POWER BANDWIDTH is a measure of the frequency
at which the reconstructed output fundamental drops 3 dB
below its 1 MHz value for a full scale input. The test is performed with f
equal to 100 kHz plus integral multiples of
IN
DS101064-52
DS101064-53
Dynamics at 30 MSPS
DS101064-55
. The input frequency at which the output is −3 dB rela-
f
CLK
DS101064-56
tive to the 1 MHz input signal is the full power bandwidth.
FULL SCALE (FS) INPUT RANGE of the ADC is the input
range of voltages over which the ADC will digitize that input.
For V
(V
FULL SCALE OFFSET ERROR is a measure of how far the
last code transition is from the ideal 1
and is defined as V
+=3.5V and V
REF
−)=2.0V.
REF
+1.5 LSB − V
1023
−=1.5V, FS=(V
REF
1
⁄2LSB below V
+, where V
REF
REF
+) −
REF
1023
the voltage at which the transition from code 1022 to 1023
occurs.
INTEGRAL NON-LINEARITY (INL) is a measure of the deviation of each individual code from a line drawn from negative full scale (
1
⁄2LSB below the first code transition) through
+
is
www.national.com9
Specification Definitions (Continued)
positive full scale (1
The deviation of any given code from this straight line is
ADC10030
measured from the center of that code value.
OUTPUT DELAY is the time delay after the fall of the input
clock before the data update is present at the output pins.
OUTPUT HOLD TIME is the length of time that the output
data is valid after the fall of the input clock.
PIPELINE DELAY (LATENCY) is the number of clock cycles
between initiation of conversion and when that data is presented to the output driver stage. Data for any given sample
is available by the Pipeline Delay plus the Output Delay after
that sample is taken. New data is available at every clock
cycle, but the data lags the conversion by the Pipeline Delay
plus the Output Delay.
PSRR (POWER SUPPLY REJECTION RATIO) is the ratio
of the change in dc power supply voltage to the resulting
change in Full Scale Error, expressed in dB.
SAMPLING (APERTURE) DELAY or APERTURE TIME is
that time required after the fall of the clock input for the sampling switch to open. The sample is effectively taken this
amount of time after the fall of the clock input.
1
⁄2LSB above the last code transition).
Timing Diagram
SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in
dB, of the RMS value of the input signal to the RMS value of
other spectral components below half the clock frequency,
not including harmonics or dc.
SIGNAL TO NOISE PLUS DISTORTION (S/(N+D) or
SINAD) is the ratio, expressed in dB, of the RMS value of the
input signal to the RMS value of all of the other spectral components below half the clock frequency, including harmonics
but excluding dc.
SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB or dBc, between the RMS value of the
input signal and the peak spurious signal, where a spurious
signal is any signal present in the output spectrum that is not
present at the input.
TOTAL HARMONIC DISTORTION (THD) is the ratio, expressed in dB, of the RMS total of the first six harmonic components, to the RMS value of the input signal.
ZERO SCALE OFFSET ERROR is the difference between
the ideal input voltage (
that just causes a transition from an output code of zero to
an output code of one.
1
⁄2LSB) and the actual input voltage
FIGURE 1. ADC10030 Timing Diagram
www.national.com 10
DS101064-15
Timing Diagram (Continued)
DS101064-17
FIGURE 2. AC Test Circuit
Functional Description
The ADC10030 maintains excellent dynamic performance
for input signals up to and exceeding half the clock frequency. The use of an internal sample-and-hold amplifier
(SHA) enables sustained dynamic performance for signals of
input frequency beyond the clock rate, lowers the converter’s
input capacitance and reduces the number of external components required.
The analog signal at V
by V
+ S and V
REF
30 MSPS. Input voltages below V
that is within the voltage range set
IN
− S are digitized to ten bits at up to
REF
− S will cause the out-
REF
put word to consist of all zeroes. Input voltages above
V
+ S will cause the output word to consist of all ones.
REF
V
+ S has a range of 2.6V to 3.8V, while V
REF
range of 1.7V to 2.8V. V
1.0V more positive than V
+ S should always be at least
REF
−S.
REF
− S has a
REF
Data is acquired at the falling edge of the clock and the digital equivalent of that data is available at the digital outputs
2.0 clock cycles plus t
later.TheADC10030 will convert as
OD
long as the clock signal is present at pin 9 and the PD pin is
low.The Output Enable pin (OE), when low,enables the output pins. The digital outputs are in the high impedance state
when the OE pin or the PD pin is high.
Applications Information
1.0 THE ANALOG INPUT
The analog input of the ADC10030 is a switch (transmission
gate) followed by a switched capacitor amplifier. The capacitance seen at the input changes with the clock level, appearing as about 3 pF when the clock is low, and about 5 pF
when the clock is high. This small change in capacitance can
be reasonably assumed to be a fixed capacitance. Care
should be taken to avoid driving the input beyond the supply
rails, even momentarily, as during power-up.
The CLC409 has been found to be a good device to drive the
ADC10030 because of its wide bandwidth, low distortion and
DS101064-16
FIGURE 3. tEN,t
Test Circuit
DIS
minimal Differential Gain and Differential Phase. The
CLC409 performs best with a feedback resistor of about
100Ω.
Care should be taken to keep digital noise out of the analog
input circuitry to maintain highest noise performance.
2.0 REFERENCE INPUTS
Note: Throughout this data sheet reference is made to V
These refer to the internal voltage across the reference ladder and are,
nominally, V
Figure 4
+ S and V
REF
− S, respectively.
REF
shows a simple reference biasing scheme with
+ and to V
REF
REF
minimal components. While this circuit might suffice for
some applications, it does suffer from thermal drift because
the external will have a different temperature coefficient than
the on-chip resistors. Also, the on-chip resistors, while well
matched to each other, will have a large tolerance compared
with any external resistors, causing the value of V
V
− to be somewhat variable.
REF
The V
+ F and V
REF
− F pins should each be bypassed to
REF
REF
+ and
AGND with 10 µF tantalum or electrolytic capacitors and
0.1 µF ceramic capacitors.
The circuit of
Figure 4
Figure 5
is an improvement over the circuit of
in that the positive end of the reference ladder is defined with a reference voltage. This reduces problems of
high reference variability and thermal drift.
In addition to the usual V
+F and V
REF
−F reference in-
REF
puts, the ADC10030 has two sense outputs for precision
control of the ladder voltages. These sense outputs (V
S and V
− S) compensate for errors due to IR drops be-
REF
REF
tween the source of the reference voltages and the ends of
the reference ladder itself.
With the addition of two op-amps, the voltages at the top and
bottom of the reference ladder can be forced to the exact
value desired, as shown in
Figure 6
.
ADC10030
−.
+
www.national.com11
Applications Information (Continued)
ADC10030
DS101064-18
FIGURE 4. Simple, Low Component Count Reference Biasing
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Applications Information (Continued)
ADC10030
FIGURE 5. Improved Low Component Count Reference Biasing
The circuit of
Figure 6
may be used if it is desired to obtain
precise reference voltages. The LMC6082 in this circuit was
chosen for its low offset voltage, low voltage rail-to-rail capability and low cost.
Since the current flowing through the sense lines (those lines
associated with V
+ S and V
REF
− S) is essentially zero,
REF
there is negligible voltage drop across any resistance in series with these sense pins and the voltage at the inverting input of the op-amp accurately represents the voltage at the
top (or bottom) of the ladder. The op-amp drives the force input, forcing the voltage at the ends of the ladder to equal the
voltage at the op-amp’s non-inverting input, plus any offset
voltage. For this reason, op-amps with low V
, such as the
OS
LMC6081 and LMC6082, should be used for this application.
Voltagesat the reference sense pins (V
+ S and V
REF
REF
−S)
should be within the range specified in the Operating Ratings
DS101064-19
table (2.6V to 3.8V for V
V
−). Any device used to drive the reference pins should
REF
be able to source sufficient current into the V
sink sufficient current from the V
+ and 1.7V to VA- 1.2V for
REF
+ F pin and
− F pin when the ladder
REF
REF
is at its minimum value of 850Ω.
The reference voltage at the top of the ladder (V
REF
+) may
take on values as low as 1.0V above the voltage at the bottom of the ladder (V
voltage at the bottom of the ladder (V
−) and as high as (VA− 1.2V). The
REF
−) may take on val-
REF
ues as low as 1.7V and as high as 2.8V. However, to minimize noise effects and ensure accurate conversions, the total reference voltage range (V
REF
+−V
−) should be a
REF
minimum of 1.0V and a maximum of 2.2V.
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Applications Information (Continued)
ADC10030
FIGURE 6. Setting Precision Reference Voltages
3.0 POWER SUPPLY CONSIDERATIONS
A/D converters draw sufficient transient current to corrupt
their own power supplies if not adequately bypassed. A
10 µF to 50 µF tantalum or aluminum electrolytic capacitor
should be placed within an inch (2.5 centimeters) of the A/D
power pins, with a 0.1 µF ceramic chip capacitor placed as
close as possible to each of the converter’s power supply
pins. Leadless chip capacitors are preferred because they
have low lead inductance.
While a single voltage source should be used for the analog
and digital supplies of the ADC10030, these supply pins
should be well isolated from each other to prevent any digital
noise from being coupled to the analog power pins. A choke
or ferrite bead is recommended between the analog and
digital supply lines, with a ceramic capacitor close to the
analog supply pin.
The converter digital supply should not be the supply that is
used for other digital circuitry on the board. It should be the
same supply used for the ADC10030 analog supply.
As is the case with all high-speed converters, theADC10030
should be assumed to have little high frequency power supply rejection. A clean analog power source should be used.
No pin should ever have a voltage on it that is more than
300 mV in excess of the supply voltages or below ground,
not even on a transient basis. This can be a problem upon
application of power to a circuit. Be sure that the supplies to
DS101064-20
circuits driving the CLK, PD, OE, analog input and reference
pins do not come up any faster than does the voltage at the
ADC10030 power pins.
4.0 THE ADC10030 CLOCK
Although the ADC10030 is tested and its performance is
guaranteed with a 27 MHz clock, it typically will function with
clock frequencies from 1 MHz to 30 MHz. Performance is
best if the clock rise and fall times are 4 ns or less and if the
clock line is terminated with a series RC of about 100Ω and
47 pF near the clock input pin, as shown in
5.0 LAYOUT AND GROUNDING
Proper routing of all signals and proper ground techniques
are essential to ensure accurate conversion. Separate analog and digital ground planes are required to meet data sheet
limits. The analog ground plane should be low impedance
and free of noise from other parts of the system.
Each bypass capacitor should be located as close to the appropriate converter pin as possible and connected to the pin
and the appropriate ground plane with short traces. The analog input should be isolated from noisy signal traces to avoid
coupling of spurious signals into the input. Any external component (e.g., a filter capacitor) connected between the converter’s input and ground should be connected to a very
clean point in the analog ground return.
Figure 6
.
www.national.com 14
Applications Information (Continued)
Figure 7
separation, and bypass capacitor placement. All analog circuitry (input amplifiers, filters, reference components, etc.)
should be placed on or over the analog ground plane. All
digital circuitry and I/O lines should be over the digital ground
plane.
gives an example of a suitable layout, ground plane
ADC10030
Digital and analog signal lines should never run parallel to
each other in close proximity with each other. They should
only cross each other when absolutely necessary, and then
only at 90˚ angles. Violating this rule can result in digital
noise getting into the input, which degrades accuracy and
dynamic performance (THD, SNR, SINAD).
FIGURE 7. An Acceptable Layout Pattern for the ADC10030
DS101064-21
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Applications Information (Continued)
6.0 DYNAMIC PERFORMANCE
The ADC10030 is ac tested and its dynamic performance is
ADC10030
guaranteed. To meet the published specifications, the clock
source driving the CLK input must be free of jitter. For best
ac performance, isolating the ADC clock from any digital circuitry should be done with adequate buffers, as with a clock
tree. See
Meeting dynamic specifications is also dependent upon
keeping digital noise out of the input, as mentioned in Sections 1.0 and 5.0.
7.0 COMMON APPLICATION PITFALLS
Driving the inputs (analog or digital) beyond the power
supply rails. For proper operation, all inputs should not go
more than 300 mV beyond the supply pins. Exceeding these
limits on even a transient basis can cause faulty or erratic
operation. It is not uncommon for high speed digital circuits
Figure 8
.
FIGURE 8. Isolating the ADC Clock
from Digital Circuitry
DS101064-22
(e.g., 74F and 74AC devices) to exhibit undershoot that goes
more than a volt below ground. A resistor of 50Ω to 100Ω in
series with the offending digital input will usually eliminate
the problem.
Care should be taken not to overdrive the inputs of the
ADC10030 (or any device) with a device that is powered
from supplies outside the range of the ADC10030 supply.
Such practice may lead to conversion inaccuracies and even
to device damage.
Attempting to drive a high capacitance digital data bus.
The more capacitance the output drivers has to charge for
each conversion, the more instantaneous digital current is
required from V
I/O and DGND I/O. These large charging
D
current spikes can couple into the analog section, degrading
dynamic performance. Adequate bypassing and maintaining
separate analog and digital ground planes will reduce this
problem on the board. Buffering the digital data outputs (with
an 74F541, for example) may be necessary if the data bus to
be driven is heavily loaded. Dynamic performance can also
be improved by adding series resistors of 47Ω at each digital
output.
Driving the V
+ F pin or the V
REF
− F pin with devices
REF
that can not source or sink the current required by the
ladder. As mentioned in section 2.0, be careful to see that
any driving devices can source sufficient current into the
V
+ F pin and sink sufficient current from the V
REF
REF
− F pin.
If these pins are not driven with devices than can handle the
required current, they will not be held stable and the converter output will exhibit excessive noise.
Using a clock source with excessive jitter. This will cause
the sampling interval to vary, causing excessive output noise
and a reduction in SNR performance. The use of simple
gates with RC timing is generally inadequate.
Using the same voltage source for V
As mentioned in section 3.0, V
source used by V
, but should be decoupled from VA.
A
should use the same power
D
and digital logic.
D
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Physical Dimensions inches (millimeters) unless otherwise noted
ADC10030 10-Bit, 30 MSPS, 125 mW A/D Converter with Internal Sample and Hold
32-Lead TQFP Package
Ordering Number ADC10030CIVT
NS Package Number VBE32A
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