NSC ADC10030CIVT Datasheet
January 2000
ADC10030
10-Bit, 30 MSPS, 125 mW A/D Converter with Internal
Sample and Hold
ADC10030 10-Bit, 30 MSPS, 125 mW A/D Converter with Internal Sample and Hold
General Description
The ADC10030 is a low power, high performance CMOS
analog-to-digital converter that digitizes signals to 10 bits
resolution at sampling rates up to 30 Msps while consuming
a typical 125 mW from a single 5V supply. Reference force
and sense pins allow the user to connect an external reference buffer amplifierto ensure optimal accuracy.No missing
codes is guaranteed over the full operating temperature
range. The unique two-stage architecture achieves 9.1 Effective Bits with a 15 MHz input signal and a 30 MHz clock
frequency. Output formatting is straight binary coding.
To ease interfacing to 3V systems, the digital I/O power pins
of the ADC10030 can be tied to a 3V power source, making
the outputs 3V compatible. When not converting, power consumption can be reduced by pulling the PD (Power Down)
pin high, placing the converter into a low power standby
state, where it typically consumes less than 4 mW. The
ADC10030’s speed, resolution and single supply operation
makes it well suited for a variety of applications in video, imaging, communications, multimedia and high speed data acquisition. Low power, single supply operation ideally suit the
ADC10030 for high speed portable applications, and its
speed and resolution are ideal for charge coupled device
(CCD) input systems.
The ADC10030 comes in a space saving 32-pin TQFP and
operates over the industrial (−40˚C ≤ T
ture range.
≤ +85˚C) tempera-
A
Features
n Internal Sample-and-Hold
n Single +5V Operation
n Low Power Standby Mode
n Guaranteed No Missing Codes
n TRI-STATE
n TTL/CMOS or 3V Logic Input/Output Compatible
®
Outputs
Key Specifications
n Resolution 10 Bits
n Conversion Rate 30 Msps
n ENOB
n DNL 0.40 LSB (typ)
n Conversion Latency 2 Clock Cycles
n PSRR 56 dB
n Power Consumption 125 mW (typ)
n Low Power Standby Mode
@
15 MHz Input 9.1 Bits (typ)
<
3.5 mW (typ)
Applications
n Digital Video
n Communications
n Document Scanners
n Medical Imaging
n Electro-Optics
n Plain Paper Copiers
n CCD Imaging
Connection Diagram
DS101064-1
TRI-STATE®is a registered trademark of National Semiconductor Corporation.
© 2000 National Semiconductor Corporation DS101064 www.national.com
Ordering Information
Commercial Temperature Range
ADC10030
Block Diagram
(−40˚C ≤ T
ADC10030CIVT TQFP
≤ +85˚C)
A
NS Package
DS101064-2
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Pin Descriptions and Equivalent Circuits
ADC10030
Pin
No.
30 V
31 V
32 V
2V
1V
Symbol Equivalent Circuit Description
IN
REF
REF
REF
REF−
9 CLK
Analog Input signal to be converted. Conversion
range is V
REF
+
StoV
REF
−
S.
Analog input that goes to the high side of the
+
F
+
S
reference ladder of the ADC. This voltage should
+
force V
S to be in the range of 2.6V to 3.8V.
REF
Analog output used to sense the voltage at the top
of the ADC reference ladder.
Analog input that goes to the low side of the
−
F
S
reference ladder of the ADC. This voltage should
force V
S to be in the range of 1.7V to 2.8V.
REF−
Analog output used to sense the voltage at the
bottom of the ADC reference ladder.
Converter digital clock input. VINis sampled on the
falling edge of CLK input.
8PD
26 OE
14
thru
19
and
D0–D9
22
thru
25
3, 7,
28
5, 10 V
V
A
D
Power Down input. When this pin is high, the
converter is in the Power Down mode and the data
output pins are in a high impedance state.
Output Enable pin. When this pin and the PD pin
are low, the output data pins are active. When this
pin or the PD pin is high, the data output pins are in
a high impedance state.
Digital Output pins providing the 10-bit conversion
results. D0 is the LSB, D9 is the MSB. Data is
acquired on the falling edge of the CLK input and
valid data is present 2.0 clock cycles plus t
OD
later.
Positive analog supply pins. These pins should be
connected to a clean, quiet voltage source of +5V.
and VDshould have a common supply and be
V
A
separately bypassed with 10 µF to 50 µF capacitors
in parallel with 0.1 µF capacitors.
Positive digital supply pins. These pins should be
connected to a clean, quiet voltage source of +5V.
and VDshould have a common supply and be
V
A
separately bypassed with 10 µF to 50 µF capacitors
in parallel with 0.1 µF capacitors.
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Pin Descriptions and Equivalent Circuits (Continued)
Pin
ADC10030
No.
12, 21 V
4, 27,
29
6, 11 DGND
13, 20 DGND I/O The ground return of the digital output drivers.
Symbol Equivalent Circuit Description
Positive supply pins for the digital output drivers.
I/O
D
AGND
These pins should be connected to a clean, quiet
voltage source of +3V to +5V and be separately
bypassed with 10 µF to 50 µF capacitors.
The ground return for the analog supply. AGND and
DGND should be connected together close to the
ADC10030 package.
The ground return for the digital supply. AGND and
DGND should be connected together close to the
ADC10030 package.
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ADC10030
Absolute Maximum Ratings (Notes 1, 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Positive Supply Voltage (V=V
Voltage on Any Pin −0.3V to (V
Input Current at Any Pin (Note 3)
Package Input Current (Note 3)
Package Dissipation at T
A
=
) 6.5V
V
A
D
or VD+0.3V)
A
±
25 mA
±
50 mA
=
25˚C See (Note 4)
ESD Susceptibility (Note 5)
Human Body Model 1500V
Machine Model 200V
Converter Electrical Characteristics
The following specifications apply for V
C
=
L
20 pF, f
CLK
=
27 MHz, R
=
S
=
+5.0V
A
50Ω. Boldface limits apply for T
Symbol Parameter Conditions
Static Converter Characteristics
INL Integral Non-Linearity
DNL Differential-Non-Linearity
Resolution with No Missing
Codes
Zero Scale Offset Error −4 mV
Full-Scale Offset Error +3 mV
Dynamic Converter Characteristics
=
f
IN
=
f
IN
ENOB Effective Number of Bits
S/(N+D)
Signal-to-Noise Plus
Distortion Ratio
SNR Signal-to-Noise Ratio
THD Total Harmonic Distortion
SFDR
Spurious Free Dynamic
Range
Overrange Output Code V
=
f
IN
=
f
IN
=
f
IN
=
f
IN
=
f
IN
=
f
IN
=
f
IN
=
f
IN
=
f
IN
=
f
IN
=
f
IN
=
f
IN
=
f
IN
=
f
IN
=
f
IN
=
f
IN
=
f
IN
=
f
IN
=
f
IN
=
f
IN
=
f
IN
=
f
IN
=
f
IN
>
IN
=
DC,VD
5.0V
DC,VD
1.0 MHz 9.6
4.43 MHz 9.4 Bits
13.5 MHz 9.4 Bits
4.43 MHz, f
15.0 MHz, f
= 30 MHz 9.3 Bits
CLK
= 30 MHz 9.1 Bits
CLK
1.0 MHz 60
4.43 MHz 59 dB
13.5 MHz 58 dB
4.43 MHz, f
15.0 MHz, f
= 30 MHz 58 dB
CLK
= 30 MHz 57 dB
CLK
1.0 MHz 60
4.43 MHz 59 dB
13.5 MHz 59 dB
4.43 MHz, f
15.0 MHz, f
= 30 MHz 59 dB
CLK
= 30 MHz 58 dB
CLK
1.0 MHz −72
4.43 MHz −69 dB
13.5 MHz −66 dB
4.43 MHz, f
15.0 MHz, f
= 30 MHz −64 dB
CLK
= 30 MHz −61 dB
CLK
1.0 MHz 73 dB
4.43 MHz 71 dB
13.5 MHz 68 dB
4.43 MHz, f
15.0 MHz, f
V
+ 1023
REF
= 30 MHz 66 dB
CLK
= 30 MHz 62 dB
CLK
Soldering Temp., Infrared, 10 sec. (Note 6) 300˚C
Storage Temperature −65˚C to +150˚C
Operating Ratings (Notes 1, 2)
Operating Temperature Range −40˚C ≤ T
V
Supply Voltage +4.75V to +5.5V
A,VD
V
I/O Supply Voltage +2.7V to 5.5V
D
V
Voltage Range 1.7V to (VA−1.2V)
IN
V
+ Voltage Range 2.6V to (VA−1.2V)
REF
V
− Voltage Range 1.7V to 2.8V
REF
PD, CLK, OE Voltage Range
I/O=+5.0VDC,V
=
to T
T
A
MIN
MAX
+=+3.5VDC,V
REF
: all other limits T
Typical
(Note 8)
±
0.45
±
0.40
REF
=
25˚C (Note 7)
A
Limits
(Note 9)
±
1.0 LSB(max)
±
0.95 LSB(max)
10 Bits
8.6
53.5
54
−61
≤ +85˚C
A
−0.3V to +5.5V
−=+1.75VDC,
Units
Bits
dB
dB
dB
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Converter Electrical Characteristics (Continued)
The following specifications apply for V
=
C
20 pF, f
L
ADC10030
CLK
=
27 MHz, R
=
S
=
+5.0V
A
50Ω. Boldface limits apply for T
Symbol Parameter Conditions
Dynamic Converter Characteristics
Underrange Output Code V
<
IN
BW Full Power Bandwidth 150 MHz
PSRR
Power Supply Rejection
Ratio
Change in Full Scale with 4.5V to
5.5V Supply Change
DC,VD
V
REF
=
5.0V
I/O=+5.0VDC,V
DC,VD
=
A
+=+3.5VDC,V
to T
T
MIN
REF
: all other limits T
MAX
Typical
(Note 8)
REF
=
25˚C (Note 7)
A
Limits
(Note 9)
−=+1.75VDC,
−
56 dB
Reference, DC, and Logic Electrical Characteristics
The following specifications apply for V
+1.75VDC,C
(Note 7)
L
=
20 pF, f
CLK
=
27 MHz, R
=
+5.0V
A
=
50Ω. Boldface limits apply for T
S
Symbol Parameter Conditions
Reference and Analog Input Characteristics
V
IN
C
IN
I
IN
R
REF
V
+ Positive Reference Voltage 3.5 3.8 V(max)
REF
−
V
REF
(V
REF
(V
REF
Analog Input Range
Analog VINInput
Capacitance
Input Leakage Current 10 µA
Reference Ladder
Resistance
Negative Reference
Voltage
+) −
Total Reference Voltage 1.75
−)
CLK, OE, PD, Digital Input Characteristics
V
IH
V
IL
I
IH
I
IL
Logical “1” Input Voltage V
Logical “0” Input Voltage V
Logical “1” Input Current V
Logical “0” Input Current V
=
D
=
D
=
IH
=
IL
DB0–DB9 Digital Output Characteristics
I/O=+4.5V, I
V
V
OH
V
OL
I
OZ
I
OS
Logical “1” Output Voltage
Logical “0” Output Voltage
TRI-STATE Output Current
Output Short Circuit
Current
D
I/O=+2.7V, I
V
D
I/O=+4.5V, I
V
D
I/O=+2.7V, I
V
D
V
OUT
V
OUT
VDI/O=3V
V
I/O=5V
D
Power Supply Characteristics
PD=LOW, Ladder Current not
I
A
Analog Supply Current
included
PD=HIGH, Ladder Current not
included
PD=LOW, Ladder Current not
+
I
D
I/O
I
D
Digital Supply Current
included
PD=HIGH, Ladder Current not
included
DC,VD
=
+5.0V
I/O=+5.0VDC,V
DC,VD
+=+3.5VDC,V
REF
=
to T
T
A
MIN
Typical
(Note 8)
: all other limits T
MAX
Limits
(Note 9)
1.75
3.5
1.6
3.8
REF
−
5pF
1000
850
1150
1.75 1.6 V(min)
1.0
2.2
5.5V 2.0 V(min)
4.5V 1.0 V(max)
V
D
10 µA
DGND −10 µA
=
=
DGND
V
D
OUT
OUT
OUT
OUT
=
−0.5 mA
=
−0.5 mA
=
−1.6 mA
=
−1.6 mA
−10
10
±
12 mA
±
25 mA
4.0
2.4
0.4
0.4
17.6
0.5
6.6
0.2
=
=
A
mA(max)
mA(max)
Units
25˚C
Units
V(min)
V(max)
Ω(min)
Ω(max)
V(min)
V(max)
V(min)
V(min)
V(max)
V(max)
µA
µA
mA
mA
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