ADC08061/ADC08062
500 ns A/D Converter with S/H Function and Input
Multiplexer
General Description
Using a patented multi-step A/D conversion technique, the
8-bit ADC08061 and ADC08062 CMOS ADCs offer 500 ns
(typ) conversion time, internal sample-and-hold (S/H), and
dissipate only 125 mW of power. The ADC08062 has a
two-channel multiplexer. The ADC08061/2 family performs
an 8-bit conversion using a 2-bit voltage estimator that generates the 2 MSBs andtwo low-resolution (3-bit) flashes that
generate the 6 LSBs.
Input track-and-hold circuitry eliminates the need for an external sample-and-hold. The ADC08061/2 family performs
accurate conversions of full-scale input signals that have a
frequency range of DC to 300 kHz (full-power bandwidth)
without need of an external S/H.
The digital interface has been designed to ease connection
to microprocessors and allows theparts to be I/O or memory
mapped.
Key Specifications
n Resolution 8 bits
n Conversion Time 560 ns max (WR-RD Mode)
n Full Power Bandwidth 300 kHz
n Throughput rate 1.5 MHz
n Power Dissipation 100 mW max
n Total Unadjusted Error
±
1
⁄2LSB and±1 LSB
Features
n 1 or 2 input channels
n No external clock required
n Analog input voltage range from GND to V
+
n Overflow output available for cascading (ADC08061)
n ADC08061 pin-compatible with the industry standard
ADC0820
Applications
n Mobile telecommunications
n Hard disk drives
n Instrumentation
n High-speed data acquisition systems
Block Diagram
TRI-STATE®is a registered trademark of NationalSemiconductor Corporation.
DS011086-1
* ADC08061
*
*
ADC08062
June 1999
ADC08061/ADC08062 500 ns A/D Converter with S/H Function and Input Multiplexer
© 1999 National Semiconductor Corporation DS011086 www.national.com
Connection Diagrams
Ordering Information
Industrial (−40˚C ≤ TA≤ 85˚C) Package
ADC08061BIN, ADC08062BIN N20A
ADC08061CIWM, ADC08062CIWM M20B
Pin Description
VIN,
V
IN1–8
These are analog inputs. The input range is
GND–50 mV ≤ V
INPUT
≤ V++50mV.The
ADC08061 has a single input (V
IN
) and the
ADC08062 has a two-channel multiplexer
(V
IN1–2
).
DB0–DB7 TRI-STATE data outputs — bit 0 (LSB) through
bit 7 (MSB).
WR /RDY
WR-RD Mode (Logic high appliedto MODEpin)
WR: With CS low, the conversion is started on
the falling edge of WR. The digital result will be
strobed into the output latch at the end of conversion (see
Figures 2, 3, 4
).
: RD Mode (Logic low applied to MODE pin)
RDY: This is an open drain output (no internal
pull-up device). RDY will go low after the falling
edge of CS and return highat the endof conversion.
MODE Mode: Mode (RD or WR-RD) selection
input— This pin is pulled to a logic low through
an internal 50 µA current sink when left unconnected.
RD Mode is selected if the MODE pin is left unconnected or externally forced low. A complete
conversion is accomplished by pulling RD low
until output data appears.
WR-RD Mode is selected when a high is applied
to the MODE pin. A conversion starts with the
WR signal’s rising edge and then using RD to
access the data.
RD
WR-RD Mode (logic high on the MODE pin)
This is the active low Read input. With a logic
low applied to the CS pin, the TRI-STATE data
outputs (DB0–DB7) will be activated when RD
goes low (
Figures 2, 3, 4
).
RD Mode (logic low on the MODE pin)
With CS low, a conversion starts on the falling
edge of RD. Output data appears on DB0–DB7
at the end of conversion(see
Figures 1, 5
).
INT
This is an active low output that indicates that a
conversion is complete and the data is in the
output latch. INT is reset by the rising edge of
RD.
GND This is the power supply groundpin. The ground
pin should be connectedto a “clean” ground reference point.
V
REF−
,
V
REF+
These are the reference voltage inputs. They
may be placed at any voltage between GND −
50 mV and V
+
+50mV,butV
REF+
must be
greater than V
REF−
. Ideally, an input voltage
equal to V
REF−
produces an output code of 0,
and an input voltage greater than V
REF+
− 1.5
LSB produces an output code of 255.
For the ADC08062, an input voltage on any un-
selected input that exceeds V
+
by more than
100 mV or is below GND by more than 100 mV
will create errors in a selected channel that is
operating within proper operating conditions.
CS
This is the active low Chip Select input. A logic
low signal applied to this input pin enables the
RD and WR inputs. Internally, the CS signal is
ORed with RD and WR signals.
OFL Overflow Output. If the analog input is higher
than V
REF+
−1⁄2LSB, OFL will be low at the end
of conversion. It can be used when cascading
two ADC08061s to achieve higher resolution (9
bits). This output is always active and does not
go into TRI-STATEas DB0–DB7 do. When OFL
is set, all data outputs remain high when the
ADC08061’s output data is read.
NC No connection.
DS011086-14
Dual-In-Line and Wide-Body
Small-Outline
Packages N20A or M20B
DS011086-15
Dual-In-Line and Wide-Body
Small-Outline
Packages N20A or M20B
www.national.com 2
Pin Description (Continued)
A0 This logic input is used to select one of the
ADC08062’s input multiplexer channels. A channel is selected as shown in the table below.
ADC08062 Channel
A0
0V
IN1
1V
IN2
V+Positive power supply voltage input. Nominal operating
supply voltage is +5V. The supply pin should be bypassed with a 10 µFbead tantalumin parallelwith a0.1
ceramic capacitor. Lead length should be as short as
possible.
www.national.com3
Absolute Maximum Ratings (Notes 1, 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
+
)6V
Logic Control Inputs −0.3V to V
+
+ 0.3V
Voltage at Other lInputs and Outputs −0.3V to V
+
+ 0.3V
Input Current at Any Pin (Note 3) 5 mA
Package Input Current (Note 3) 20 mA
Power Dissipation (Note 4)
J Package 875 mW
N Package 875 mW
WM Package 875 mW
Storage Temperature −65˚C to +150˚C
Lead Temperature (Note 5)
J Package (Soldering, 10 sec.) +300˚C
N Package (Soldering, 10 sec.) +260˚C
WM Package
(Vapor Phase, 60 sec.) +215˚C
WM Package (Infrared, 15 sec.) +220˚C
ESD Susceptibility (Note 6) 2 kV
Operating Ratings (Notes 1, 2)
Temperature Range T
MIN
≤ TA≤ T
MAX
ADC08061/2BIN,
ADC08061/2CIWM −40˚C ≤ T
A
≤ 85˚C
Supply Voltage, (V
+
) 4.5V to 5.5V
Converter Characteristics
The following specifications apply for RD Mode, V
+
=
5V, V
REF+
=
5V, and V
REF−
=
GND unless otherwise specified. Bold-
face limits apply for T
A
=
T
J
=
T
MIN
to T
MAX
; all other limits T
A
=
T
J
=
25˚C.
Symbol Parameter Conditions Typical Limits Units
(Limit)
(Note 7) (Note 8)
INL Integral Non Linearity ADC08061/2BIN
±
1
⁄
2
LSB (max)
ADC08061/2CIWM
±
1 LSB (max)
TUE Total Unadjusted Error ADC08061/2BIN
±
1
⁄
2
LSB (max)
ADC08061/2CIWM
±
1 LSB (max)
Missing Codes 0 Bits (max)
Reference Input Resistance 700 500 Ω(min)
700 1250 Ω (max)
V
REF+
Positive Reference V
REF−
V (min)
Input Voltage V
+
V (max)
V
REF−
Negative Reference GND V (min)
Input Voltage V
REF+
V (max)
V
IN
Analog (Note 10) GND − 0.1 V (min)
Input Voltage V
+
+ 0.1 V (max)
On Channel Input On Channel Input=5V, −0.4 −20 µA (max)
Current Off Channel Input=0V (Note 11)
On Channel Input=0V, −0.4 −20 µA (max)
Off Channel Input=5V (Note 11)
PSS Power Supply Sensitivity V
+
=
5V
±
5%,V
REF
=
4.75V
±
1/16
±
1
⁄
2
LSB (max)
All Codes Tested
Effective Bits 7.8 Bits
Full-Power Bandwidth 300 kHz
THD Total Harmonic Distortion 0.5
%
S/N Signal-to-Noise Ratio 50 dB
IMD Intermodulation Distortion 50 dB
AC Electrical Characteristics
The following specifications apply for V
+
=
5V, t
r
=
t
f
=
10 ns, V
REF+
=
5V, V
REF−
=
0V unless otherwise specified. Bold-
face limits apply for T
A
=
T
J
=
T
MIN
to T
MAX
; all other limits T
A
=
T
J
=
25˚C.
Symbol Parameter Condition
Typical
(Note 7)
Limits
(Note 8)
Units
(Limit)
t
WR
Write Time Mode Pin to V+; 100 100 ns (min)
(
Figures 2, 3, 4
)
t
RD
Read Time (Time from Falling Edge Mode Pin to V+;(
Figure 2
) 350 350 ns (min)
of WR to Falling Edge of RD )
www.national.com 4
AC Electrical Characteristics (Continued)
The following specifications apply for V
+
=
5V, t
r
=
t
f
=
10 ns, V
REF+
=
5V, V
REF−
=
0V unless otherwise specified. Bold-
face limits apply for T
A
=
T
J
=
T
MIN
to T
MAX
; all other limits T
A
=
T
J
=
25˚C.
Symbol Parameter Condition
Typical
(Note 7)
Limits
(Note 8)
Units
(Limit)
t
RDW
RD Width Mode Pin to GND; (
Figure 5
) 200 250 ns (min)
400 400 ns (max)
t
CONV
WR -RD Mode Conversion Time Mode Pin to V+;(
Figure 2
) 500 560 ns (max)
(t
WR+tRD+tACC1
)
t
CRD
RD Mode Conversion Time Mode Pin to GND; (
Figure 1
) 655 900 ns (max)
t
ACCO
Access Time (Delay from Falling CL≤ 100 pF 640 900 ns (max)
Edge of RD to Output Valid)
Mode Pin to GND; (
Figure 1
)
t
ACC1
Access Time (Delay from CL≤ 10 pF 45 110 ns (max)
Falling Edge C
L
=
100 pF 50
of RD to Output Valid)
Mode Pin to V+,tRD≤ t
INTL
(
Figure 2
)
t
ACC2
Access Time (Delay from CL≤ 10 pF 25 55 ns (max)
Falling Edge C
L
=
100 pF 30
of RD to Output Valid)
t
RD
>
t
INTL
;(
Figures 3, 4
)
t
0H
TRI-STATE®Control (Delay from R
L
=
3kΩ,C
L
=
10 pF 30 60 ns (max)
Rising Edge of RD to HI-Z State)
t
1H
TRI-STATE Control (Delay from R
L
=
3kΩ,C
L
=
10 pF 30 60 ns (max)
Rising Edge of RD to HI-Z State)
t
INTL
Delay from Rising Edge of (
Figures 3, 4
) 520 690 ns (max)
WR to Falling Edge of INT
Mode Pin=V+,C
L
=
50 pF
t
INTH
Delay from Rising Edge of C
L
=
50 pF; (
Figures 1, 2, 3, 4
)50 95 ns (max)
RD to Rising Edge of INT
2b, and 4
)
t
INTH
Delay from Rising Edge of C
L
=
50 pF; (
Figure 4
)4595 ns (max)
WR to Rising Edge of INT
t
RDY
Delay from CS to RDY Mode Pin=0V, C
L
=
50 pF, 25 45 ns (max)
R
L
=
3kΩ(
Figure 1
)
t
ID
Delay from INT to Output Valid R
L
=
3kΩ,C
L
=
100 pF; 0 15 ns (max)
(
Figure 4
)
t
RI
Delay from RD to INT Mode Pin=V+,tRD≤ t
INTL
; 60 115 ns (max)
(
Figure 3
)
t
N
Time between End of RD (
Figures 1, 2, 3, 4, 5
)5050 ns (min)
and Start of New Conversion
t
AH
Channel Address Hold Time (
Figures 1, 2, 3, 4, 5
)1060 ns (min)
t
AS
Channel Address Setup Time (
Figures 1, 2, 3, 4, 5
)00ns (max)
t
CSS
CS Setup Time (
Figures 1, 2, 3, 4, 5
)00ns (max)
t
CSH
CS Hold Time (
Figures 1, 2, 3, 4, 5
)00ns (min)
C
VIN
Analog Input Capacitance 25 pF
C
OUT
Logic Output Capacitance 5 pF
C
IN
Logic Input Capacitance 5 pF
DC Electrical Characteristics
The following specifications apply for V
+
=
5V unless otherwise specified. Boldface limits apply for T
A
=
T
J
=
T
MIN
to T
MAX
;
all other limits T
A
=
T
J
=
25˚C.
Symbol Parameter Conditions Typical Limits Units
(Limit)
(Note 7) (Note 8)
V
IH
Logic “1” Input Voltage V
+
=
5.5V
Mode Pin 3.5 V (min)
ADC08062
CS, WR, RD, A0 Pins
2.2 V (min)
ADC08061
CS, WR, RD Pins
2.0 V (min)
www.national.com5
DC Electrical Characteristics (Continued)
The following specifications apply for V
+
=
5V unless otherwise specified. Boldface limits apply for T
A
=
T
J
=
T
MIN
to T
MAX
;
all other limits T
A
=
T
J
=
25˚C.
Symbol Parameter Conditions Typical Limits Units
(Limit)
(Note 7) (Note 8)
V
IL
Logic “0” Input Voltage V
+
=
4.5V
Mode Pin 1.5 V (max)
ADC08062
CS, WR, RD, A0 Pins
0.7 V (max)
ADC08061
CS, WR, RD Pins
0.8 V (max)
I
IH
Logic “1” Input Current V
IH
=
5V
CS, RD, A0 Pins
0.005 1 µA (max)
WR Pin
0.1 3 µA (max)
Mode Pin 50 200 µA (max)
I
IL
Logic “0” Input Current V
IL
=
0V
CS, RD, WR, A0 Pins
−0.005 µA (max)
Mode Pin −2
V
OH
Logic “1” Output Voltage V
+
=
4.75V
I
OUT
=
−360 µA
DB0–DB7, OFL, INT
2.4 V (min)
I
OUT
=
−10 µA
DB0–DB7, OFL, INT
4.5 V (min)
V
OL
Logic “0” Output Voltage V
+
=
4.75V
I
OUT
=
1.6 mA 0.4 V (max)
DB0–DB7, OFL, INT, RDY
I
O
TRI-STATE Output Current V
OUT
=
5.0V 0.1 3 µA (max)
DB0–DB7, RDY
V
OUT
=
0V −0.1 −3 µA (max)
DB0–DB7, RDY
I
SOURCE
Output Source Current V
OUT
=
0V −26 −6 mA (min)
DB0–DB7, OFL, INT
I
SINK
Output Sink Current V
OUT
=
5V 24 7 mA (min)
DB0–DB7, OFL, INT, RDY
I
C
Supply Current CS=WR=RD=0 11.5 20 mA (max)
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified operating ratings. Operating Ratings indicate conditions for which the device is functional, but do not guarantee performance limits.
For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions.
Note 2: All voltages are measured with respect to the GND pin, unless otherwise specified.
Note 3: When the input voltage (V
IN
) at any pin exceeds the power supply voltage (V
IN
<
GND or V
IN
>
V+), the absolute value of the current at that pin should be
limited to 5 mA or less. The 20 mA package input current specification limits the number of pins that can exceed the power supply boundaries witha5mAcurrent
limit to four.
Note 4: The power dissipation of this device under normal operation should never exceed 875 mW (Quiescent Power Dissipation + the loads on the digital outputs).
Caution should be taken not to exceed absolute maximum power rating when the device is operating in a severe fault condition (e.g., when any input or output exceeds the power supply). The maximum power dissipation must be derated at elevated temperatures and is dictated by T
JMAX
(maximum junction temperature), θ
JA
(package junction to ambient thermal resistance), and TA(ambient temperature). The maximum allowable power dissipation at any temperature is PD
max
=
(T
JMAX
−TA)/θJAor the number given in the Absolute Maximum Ratings, whichever is lower. The table below details T
JMAX
and θJAfor the various packages and versions
of the ADC08061/2.
Part Number T
JMAX
θ
JA
ADC08061/2BIN 105 51
ADC08061/2CIWM 105 85
Note 5: See AN-450 “Surface Mounting Methods and Their Effect on Product Reliability” for other methods of soldering surface mount devices.
Note 6: Human body model, 100 pF discharged through a 1.5 kΩ resistor.
Note 7: Typicals are at 25˚C and represent most likely parametric norm.
www.national.com 6
DC Electrical Characteristics (Continued)
Note 8: Limits are guaranteed to National’s AOQL (Average Output Quality Level).
Note 9: Total unadjusted error includes offset, full-scale, and linearity errors.
Note 10: Two on-chip diodes are tied to each analog input and are reversed biased during normal operation. One is connected to V
+
and the other is connected to
GND. They will become forward biased and conduct when an analog input voltage is equal to or greater than one diode drop above V
+
or below GND. Therefore,
caution should be exercised when testing with V
+
=
4.5V.Analog inputs with magnitudes equal to 5V can cause an input diode to conduct, especially at elevated temperatures. This can create conversion errors for analog signals near full-scale. The specification allows 50 mV forward bias on either diode; e.g., the output code will
be correct as long as the analog input signal does not exceed the supply voltage by more than 50 mV. Exceeding this range on an unselected channel will corrupt
the reading of a selected channel. An absolute analog input signal voltage range of 0V ≤ V
IN
≤ 5V can be achieved by ensuring that the minimum supply voltage ap-
plied to V
+
is 4.950V over temperature variations, initial tolerance, and loading.
Note 11: Off-channel leakage current is measured after the on-channel selection.
TRI-STATE Test Circuits and Waveforms
t
1H
DS011086-2
t1H,C
L
=
10 pF
DS011086-4
t
r
=
10 ns
t
0H
DS011086-3
t0H,C
L
=
10 pF
DS011086-5
t
r
=
10 ns
www.national.com7
Timing Diagrams
DS011086-6
FIGURE 1. RD Mode (Mode Pin is Low)
DS011086-7
FIGURE 2. WR-RD Mode (Mode Pin is High and tRD≤ t
INTL
)
www.national.com 8
Timing Diagrams (Continued)
DS011086-8
FIGURE 3. WR-RD Mode (Mode Pin is High and t
RD
>
t
INTL
)
DS011086-9
FIGURE 4. WR-RD Mode (Mode Pin is High) Reduced Interface System Connection (CS=RD=0)
www.national.com9
Timing Diagrams (Continued)
Typical Performance Characteristics
Application Information
1.0 FUNCTIONAL DESCRIPTION
The ADC08061 and ADC08062 perform an 8-bit
analog-to-digital conversion using a multi-step flash technique. The first flash generates the five most significant bits
(MSBs) and the second flash generates the three least significant bits (LSBs).
Figure 6
shows the major functional
blocks of the ADC08061/2’s multi-step flash converter. It
consists of an over-encoded 2
1
⁄2-bit Voltage Estimator, an internal DAC with two differentvoltage spans, a 3-bit half-flash
converter and a comparator multiplexer.
The resistor string near the center of the block diagram in
Figure 6
forms the internal main DAC. Each of the eight resistors at the bottom of the string is equal to 1/256 of the total
string resistance. These resistors form the LSB Ladder and
DS011086-10
FIGURE 5. RD Mode (Pipeline Operation) (Mode Pin is Low and t
RDW
must be between 200 ns and 400 ns)
t
CRD
vs Temperature
DS011086-25
Linearity Error vs
Reference Voltage
DS011086-26
Offset Error vs
Reference Voltage
DS011086-27
Supply Current
vs Temperature
DS011086-28
Logic Threshold
vs Temperature
DS011086-29
Output Current
vs Temperature
DS011086-30
www.national.com 10
Application Information (Continued)
have a voltage drop of 1/256 of the total reference voltage
(V
REF+−VREF−
) across them. Theremaining resistors make
up the MSB Ladder. They are made up of eight groups of
four resistors connected in series. EachMSB Ladder section
has
1
⁄8of the total reference voltage across it. Within a given
MSB Ladder section, each of the MSB resistors has 8/256,
or 1/32 of the total reference voltageacross it. Tap points are
found between all of the resistors in both the MSB and LSB
Ladders. Through the Comparator Multiplexer these tap
points can be connected, in groups of eight, to the eight comparators shown at the right of
Figure 6
. This function provides the necessary reference voltages to the comparators
during each flash conversion.
The six comparators, seven-resistor string (estimator DAC),
and Estimator Decoder at the left of
Figure 6
form the Voltage Estimator. The estimator DAC connected between
V
REF+
and V
REF−
generates the reference voltages for the
six Voltage Estimator comparators. These comparators perform a very low resolution A/D conversion to obtain an “estimate” of the input voltage.This estimate is then used to control the Comparator Multiplexer, connecting the appropriate
MSB Ladder section to the eight flash comparators. Only 14
comparators, six in the Voltage Estimator and eight in the
flash converter, are needed to achieve the full eight-bit resolution, instead of 32 comparators that would be needed by
traditional half-flash methods.
A conversion begins with the Voltage Estimator comparing
the analog input signal against the six tap voltages on the estimator DAC. The estimator decoder then selects one of the
groups of tap points along the MSB Ladder.These eight tap
points are then connected to the eight flash comparators.
For example, if the analog input signal applied to V
IN
is be-
tween 0 and 3/16 of V
REF(VREF
=
V
REF+−VREF−
), the esti-
mator decoder instructs the comparator multiplexer to select
the eight tap pointsbetween 8/256 and 2/8 of V
REF
and connects them to the eight flash comparators. The first flash
conversion is now performed, producing the five MSBs of
data.
The remaining three LSBs are generated next using the
same eight comparators that were used for the first flash
conversion.As determinedby the results of the MSB flash, a
voltage from the MSBLadder equivalent to the magnitude of
DS011086-18
FIGURE 6. Block Diagram of the ADC08061/2 Multi-Step Flash Architecture
www.national.com11
Application Information (Continued)
the five MSBs is subtracted from the analog input voltage as
the upper switch is moved from position one to position two.
The resulting remainder voltage is applied to the eight flash
comparators and, with the lower switch in position two, compared with the eight tap points from the LSB Ladder.
By using the same eight comparators for both flash conversions, the number of comparators needed by the multi-step
converter is significantly reduced when compared to standard half-flash techniques.
Voltage Estimator errors as large as 1/16 of V
REF
(16 LSBs)
will be corrected since the flash comparators are connected
to ladder voltages that extendbeyond therange specifiedby
the Voltage Estimator. For example, if 7/16 V
REF
<
V
IN
<
9/16 V
REF
the Voltage Estimator’s comparators tied to the
tap points below 9/16 V
REF
will output “1”s (000111). This is
decoded by the estimator decoder to “10”. The eight flash
comparators will be placed atthe MSB Laddertap pointsbetween
3
⁄8V
REF
and5⁄8V
REF
. The overlap of 1/16 V
REF
on
each side of the Voltage Estimator’s span will automatically
correct an error of up to 16 LSBs (16 LSBs=312.5 mV for
V
REF
=
5V). If the first flash conversion determines that the
input voltage is between
3
⁄8V
REF
and 4/8 V
REF
− LSB/2, the
Voltage Estimator’s output code will be corrected by subtracting “1”. This results in a corrected value of “01”. If the
first flash conversion determines that the input voltage is between 8/16 V
REF
− LSB/2 and5⁄8V
REF
, the Voltage Estima-
tor’s output code remains unchanged.
After correction, the 2-bit data from both the Voltage Estima-
tor and the firstflash conversion are decoded to produce the
five MSBs. Decoding is similar to that of a 5-bit flash converter since there are 32 tap points on the MSB Ladder.
However, 31 comparators are not needed since the Voltage
Estimator places the eight comparators along the MSB Ladder where reference tap voltages are present that fall above
and below the magnitude of V
IN
. Comparators are not
needed outside this selected range. If a comparator’s output
is a “0”, all comparators above it will also have outputs of “0”
and if a comparator’s outputis a“1”, all comparators below it
will also have outputs of “1”.
2.0 DIGITAL INTERFACE
The ADC08061/2 has two basic interface modes which are
selected by connecting the MODE pin to a logic high or low.
2.1 RD Mode
With a logic low applied to the MODE pin, the converter is set
to Read mode. In this configuration (see
Figure 1
), a complete version is done by pulling RD low, and holding low, until
the conversion is complete and output data appears. This
typically takes 655 ns. The INT (interrupt) line goes low at
the end of conversion.A typical delay of 50 ns is needed between the rising edge of RD (after the end of a conversion)
and the start of the next conversion (by pulling RD low). The
RDY output goes low after the falling edge of CS and goes
high at the end-of-conversion. It can be used to signala processor that the converter is busy or serve as a system Transfer Acknowledge signal. For the ADC08062 the data generated by the first conversion cycle after power-up is from an
unknown channel.
2.2 RD Mode Pipelined Operation
Applications that require shorter RD pulse widths than those
used in the Read mode as described above canbe achieved
by setting RD’s width between 200 ns–400 ns (
Figure 5
). RD
pulse widths outside this range will create conversion linearity errors. These errors are caused by exercising internal interface logic circuitry using CS and/or RD during a conversion.
When RD goes low, a conversion is initiated and the data
from the previous conversion is available on the DB0–DB7
outputs. Reading D0–D7 for the first two times after
power-up produces random data. The data will be valid during the third RD pulse that occurs after the first conversion.
2.3 WR-RD (WR then RD) Mode
The ADC08061/2 is in the WR-RD mode with the MODE pin
tied high. A conversion starts on the falling edge of the WR
signal. There are two options for reading the output data
which relate to interface timing. Ifan interrupt-driven scheme
is desired, the user can wait for the INT output to go low before reading the conversion result (see
Figure 3
). Typically,
INT will go low 520 ns, maximum, after WR ’s rising edge.
However, if a shorter conversion time is desired, the processor need not wait for INT and can exercise a read after only
350 ns (see
Figure 2
). If RD is pulled low before INT goes
low, INT will immediately go low and data will appear at the
outputs. This is the fastest operating mode (tRD≤ t
INTL
) with
a conversion time, including data access time, of 560 ns. Allowing 100 ns for reading the conversion data and the delay
between conversions gives a total throughput time of 660 ns
(throughput rate of 1.5 MHz).
2.4 WR-RD Mode with Reduced Interface
System Connection
CS and RD can be tied low, using only WR to control the
start of conversion for applications that require reduced digital interface while operating in the WR-RD mode (
Figure 4
).
Data will be valid approximately 705 ns following WR ’s rising edge.
2.5 Multiplexer Addressing
The ADC08062 has 2 multiplexer inputs. These are selected
using the A0 multiplexer channel selection input.
Table 1
shows the input code needed to select a given channel.The
multiplexer address is latched when received but the multiplexer channel is updated after the completion of the current
conversion.
TABLE 1. Multiplexer Addressing
ADC08062 Channel
A0
0V
IN1
1V
IN2
The multiplexer address data must be valid at the time of
RD’s falling edge, remain valid during the conversion, and
can go high after RD goes high when operating in the Read
Mode.
The multiplexer address data should be valid at orbefore the
time of WR’s falling edge, remain valid while WR is low, and
go invalid after WR goes high when operating in the WR-RD
Mode.
3.0 REFERENCE INPUTS
The two V
REF
inputs of theADC08061/2 are fully differential
and define the zero to full-scale input range of the A to D converter. This allows the designer to vary the span of the analog input since this range will beequivalent to the voltagedifference between V
REF+
and V
REF−
. Transducers with
www.national.com 12
Application Information (Continued)
minimum output voltages above GND can also be compensated by connecting V
REF−
to a voltage that is equal to this
minimum voltage. By reducing V
REF(VREF
=
V
REF+−VREF−
)
to less than 5V, the sensitivity of the converter can be increased (i.e., if V
REF
=
2.5V, then 1 LSB=9.8 mV). The
ADC08061/2’s reference arrangement also facilitates ratiometric operation and in many cases the ADC08061/2’s
power supply can be used for transducer power as well as
the V
REF
source. Ratiometric operation is achieved by con-
necting V
REF−
to GND and connecting V
REF+
and a trans-
ducer’s power supply input to V
+
. The ADC08061/2’s linear-
ity degrades when V
REF+
−|V
REF−
| is less than 2.0V.
The voltage at V
REF−
sets the input level that produces a
digital output of all zeros. Though V
IN
is not itself differential,
the reference design affords nearly differential-input capability for some measurement applications.
Figure 7
shows one
possible differential configuration.
It should be noted that, while the two V
REF
inputs are fully
differential, the digital output will be zerofor anyanalog input
voltage if V
REF−
≥ V
REF+
.
4.0 ANALOG INPUT AND SOURCE IMPEDANCE
The ADC08061/2’s analog input circuitry includes an analog
switch with an “on” resistance of 70Ω and capacitance of
1.4 pF and 12 pF (see
Figure 7
). The switch isclosed during
theA/D’s inputsignal acquisition time (while WRis lowwhen
using the WR -RD Mode). A small transient current flows into
the input pin each time the switch closes. A transient voltage,
whose magnitude can increase as the source impedance increases, may be present at the input. So long as the source
impedance is less than 500Ω, the input voltage transient will
not cause errors and need not be filtered.
Large source impedances can slowthe chargingof thesampling capacitors and degrade conversion accuracy. There-
fore, only signal sources with output impedances less than
500Ω should be used if rated accuracy is to be achieved at
the minimum sample time (100 ns maximum). A signal
source with a high output impedance should have its output
buffered with an operational amplifier. Any ringing or voltage
shifts at the op amp’s output during the sampling period can
result in conversion errors.
Correct conversion results willbe obtained for input voltages
greater than GND − 100 mV and less than V
+
+ 100 mV. Do
not allow the signal source to drivethe analog input pinmore
than 300 mV higher than V
+
, or more than 300 mV lower
than GND. The current flowing through any analog input pin
should be limited to 5 mA or less to avoid permanent damage to the IC if an analog input pin is forced beyond these
voltages. The sum of all the overdrive currents into all pins
must be less than 20 mA. Some sort of protection scheme
should be used when the input signal is expected to extend
more than 300 mV beyond the power supply limits.A simple
protection network using resistors and diodes is shown in
Figure 9
.
6.0 INHERENT SAMPLE-AND-HOLD
An important benefit of the ADC08061/2’s input architecture
is the inherent sample-and-hold (S/H) and its ability to measure relatively high speed signals without the help of an external S/H. In a non-sampling converter, regardless of its
speed, the input must remain stable to at least
1
⁄2LSB
throughout the conversion process if full accuracy is to be
maintained. Consequently, for many high speed signals, this
signal must be externally sampled and held stationary during
the conversion.
The ADC08061 and ADC08062 are suitable for DSP-based
systems because of the direct control of the S/H through the
WR signal. The WR input signal allows the A/D to be synchronized to a DSP system’s sampling rate or to other
ADC08061 and ADC08062s.
DS011086-19
*
Represents a multiplexer channel in the ADC08062.
FIGURE 7. ADC08061 and ADC08062 Equivalent Input Circuit Model
www.national.com13
Application Information (Continued)
The ADC08061 can perform accurate conversions of
full-scale input signals at frequencies from dc to more than
300 kHz (full power bandwidth) without the need of anexternal sample-and-hold (S/H).
7.0 LAYOUT, GROUNDS, AND BYPASSING
In order to ensure fast, accurate conversions from the
ADC08061/2, it is necessaryto useappropriate circuit board
layout techniques. Ideally, the analog-to-digital converter’s
ground reference should be low impedance and free of noise
from other parts of the system. Digital circuits can produce a
great deal of noise on their ground returns and, therefore,
should have their own separate ground lines. Best performance is obtained using separate ground planesfor the digital and analog parts of the system.
The analog inputs should be isolated from noisy signal
traces to avoid having spurious signals couple to the input.
Any external component (e.g., an input filter capacitor) connected across the inputs should be returned to a very clean
ground point. Incorrectly grounding the ADC08061/2 will result in reduced conversion accuracy.
The V
+
supply pin, V
REF+
, and V
REF−
(if not grounded)
should be bypassed with a parallel combination of a 0.1 µF
ceramic capacitor and a 10 µF tantalum capacitor placed as
close as possible to the supply pin using short circuit board
traces. See
Figures 8, 9
.
External Reference 2.5V Full-Scale
(Standard Application)
DS011086-20
Note : Bypass capacitors consist of a 0.1 µF
ceramic in parallel with a 10 µF bead tantalum.
Power Supply as Reference
DS011086-21
Input Not Referred to GND
DS011086-22
* Signal source driving VIN(−) must be capable
of sinking 5 mA.
FIGURE 8. Analog Input Options
DS011086-23
Note the multiple bypass capacitors on the reference and power supply pins. V
REF−
should be bypass to analog ground using multiple capacitors if it is not
grounded (see Section 7.0 “Layout, Grounds, and Bypassing”). V
IN1
is shown with an optional input protection network.
FIGURE 9. Typical Connection
www.national.com 14
Physical Dimensions inches (millimeters) unless otherwise noted
Wide-Body Small-Outline Package (M)
Order Number ADC08061CIWM, or ADC08062CIWM
NS Package Number M20B
Dual-In-Line Package (N)
Order Number ADC08061BIN or ADC08062BIN
NS Package Number N20A
www.national.com15
Notes
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www.national.com
ADC08061/ADC08062 500 ns A/D Converter with S/H Function and Input Multiplexer
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
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