NSC ADC08062CIWM, ADC08062BIN Datasheet
ADC08061/ADC08062
500 ns A/D Converter with S/H Function and Input
Multiplexer
General Description
Using a patented multi-step A/D conversion technique, the
8-bit ADC08061 and ADC08062 CMOS ADCs offer 500 ns
(typ) conversion time, internal sample-and-hold (S/H), and
dissipate only 125 mW of power. The ADC08062 has a
two-channel multiplexer. The ADC08061/2 family performs
an 8-bit conversion using a 2-bit voltage estimator that generates the 2 MSBs andtwo low-resolution (3-bit) flashes that
generate the 6 LSBs.
Input track-and-hold circuitry eliminates the need for an external sample-and-hold. The ADC08061/2 family performs
accurate conversions of full-scale input signals that have a
frequency range of DC to 300 kHz (full-power bandwidth)
without need of an external S/H.
The digital interface has been designed to ease connection
to microprocessors and allows theparts to be I/O or memory
mapped.
Key Specifications
n Resolution 8 bits
n Conversion Time 560 ns max (WR-RD Mode)
n Full Power Bandwidth 300 kHz
n Throughput rate 1.5 MHz
n Power Dissipation 100 mW max
n Total Unadjusted Error
±
1
⁄2LSB and±1 LSB
Features
n 1 or 2 input channels
n No external clock required
n Analog input voltage range from GND to V
+
n Overflow output available for cascading (ADC08061)
n ADC08061 pin-compatible with the industry standard
ADC0820
Applications
n Mobile telecommunications
n Hard disk drives
n Instrumentation
n High-speed data acquisition systems
Block Diagram
TRI-STATE®is a registered trademark of NationalSemiconductor Corporation.
DS011086-1
* ADC08061
*
*
ADC08062
June 1999
ADC08061/ADC08062 500 ns A/D Converter with S/H Function and Input Multiplexer
© 1999 National Semiconductor Corporation DS011086 www.national.com
Connection Diagrams
Ordering Information
Industrial (−40˚C ≤ TA≤ 85˚C) Package
ADC08061BIN, ADC08062BIN N20A
ADC08061CIWM, ADC08062CIWM M20B
Pin Description
VIN,
V
IN1–8
These are analog inputs. The input range is
GND–50 mV ≤ V
INPUT
≤ V++50mV.The
ADC08061 has a single input (V
IN
) and the
ADC08062 has a two-channel multiplexer
(V
IN1–2
).
DB0–DB7 TRI-STATE data outputs — bit 0 (LSB) through
bit 7 (MSB).
WR /RDY
WR-RD Mode (Logic high appliedto MODEpin)
WR: With CS low, the conversion is started on
the falling edge of WR. The digital result will be
strobed into the output latch at the end of conversion (see
Figures 2, 3, 4
).
: RD Mode (Logic low applied to MODE pin)
RDY: This is an open drain output (no internal
pull-up device). RDY will go low after the falling
edge of CS and return highat the endof conversion.
MODE Mode: Mode (RD or WR-RD) selection
input— This pin is pulled to a logic low through
an internal 50 µA current sink when left unconnected.
RD Mode is selected if the MODE pin is left unconnected or externally forced low. A complete
conversion is accomplished by pulling RD low
until output data appears.
WR-RD Mode is selected when a high is applied
to the MODE pin. A conversion starts with the
WR signal’s rising edge and then using RD to
access the data.
RD
WR-RD Mode (logic high on the MODE pin)
This is the active low Read input. With a logic
low applied to the CS pin, the TRI-STATE data
outputs (DB0–DB7) will be activated when RD
goes low (
Figures 2, 3, 4
).
RD Mode (logic low on the MODE pin)
With CS low, a conversion starts on the falling
edge of RD. Output data appears on DB0–DB7
at the end of conversion(see
Figures 1, 5
).
INT
This is an active low output that indicates that a
conversion is complete and the data is in the
output latch. INT is reset by the rising edge of
RD.
GND This is the power supply groundpin. The ground
pin should be connectedto a “clean” ground reference point.
V
REF−
,
V
REF+
These are the reference voltage inputs. They
may be placed at any voltage between GND −
50 mV and V
+
+50mV,butV
REF+
must be
greater than V
REF−
. Ideally, an input voltage
equal to V
REF−
produces an output code of 0,
and an input voltage greater than V
REF+
− 1.5
LSB produces an output code of 255.
For the ADC08062, an input voltage on any un-
selected input that exceeds V
+
by more than
100 mV or is below GND by more than 100 mV
will create errors in a selected channel that is
operating within proper operating conditions.
CS
This is the active low Chip Select input. A logic
low signal applied to this input pin enables the
RD and WR inputs. Internally, the CS signal is
ORed with RD and WR signals.
OFL Overflow Output. If the analog input is higher
than V
REF+
−1⁄2LSB, OFL will be low at the end
of conversion. It can be used when cascading
two ADC08061s to achieve higher resolution (9
bits). This output is always active and does not
go into TRI-STATEas DB0–DB7 do. When OFL
is set, all data outputs remain high when the
ADC08061’s output data is read.
NC No connection.
DS011086-14
Dual-In-Line and Wide-Body
Small-Outline
Packages N20A or M20B
DS011086-15
Dual-In-Line and Wide-Body
Small-Outline
Packages N20A or M20B
www.national.com 2
Pin Description (Continued)
A0 This logic input is used to select one of the
ADC08062’s input multiplexer channels. A channel is selected as shown in the table below.
ADC08062 Channel
A0
0V
IN1
1V
IN2
V+Positive power supply voltage input. Nominal operating
supply voltage is +5V. The supply pin should be bypassed with a 10 µFbead tantalumin parallelwith a0.1
ceramic capacitor. Lead length should be as short as
possible.
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Absolute Maximum Ratings (Notes 1, 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
+
)6V
Logic Control Inputs −0.3V to V
+
+ 0.3V
Voltage at Other lInputs and Outputs −0.3V to V
+
+ 0.3V
Input Current at Any Pin (Note 3) 5 mA
Package Input Current (Note 3) 20 mA
Power Dissipation (Note 4)
J Package 875 mW
N Package 875 mW
WM Package 875 mW
Storage Temperature −65˚C to +150˚C
Lead Temperature (Note 5)
J Package (Soldering, 10 sec.) +300˚C
N Package (Soldering, 10 sec.) +260˚C
WM Package
(Vapor Phase, 60 sec.) +215˚C
WM Package (Infrared, 15 sec.) +220˚C
ESD Susceptibility (Note 6) 2 kV
Operating Ratings (Notes 1, 2)
Temperature Range T
MIN
≤ TA≤ T
MAX
ADC08061/2BIN,
ADC08061/2CIWM −40˚C ≤ T
A
≤ 85˚C
Supply Voltage, (V
+
) 4.5V to 5.5V
Converter Characteristics
The following specifications apply for RD Mode, V
+
=
5V, V
REF+
=
5V, and V
REF−
=
GND unless otherwise specified. Bold-
face limits apply for T
A
=
T
J
=
T
MIN
to T
MAX
; all other limits T
A
=
T
J
=
25˚C.
Symbol Parameter Conditions Typical Limits Units
(Limit)
(Note 7) (Note 8)
INL Integral Non Linearity ADC08061/2BIN
±
1
⁄
2
LSB (max)
ADC08061/2CIWM
±
1 LSB (max)
TUE Total Unadjusted Error ADC08061/2BIN
±
1
⁄
2
LSB (max)
ADC08061/2CIWM
±
1 LSB (max)
Missing Codes 0 Bits (max)
Reference Input Resistance 700 500 Ω(min)
700 1250 Ω (max)
V
REF+
Positive Reference V
REF−
V (min)
Input Voltage V
+
V (max)
V
REF−
Negative Reference GND V (min)
Input Voltage V
REF+
V (max)
V
IN
Analog (Note 10) GND − 0.1 V (min)
Input Voltage V
+
+ 0.1 V (max)
On Channel Input On Channel Input=5V, −0.4 −20 µA (max)
Current Off Channel Input=0V (Note 11)
On Channel Input=0V, −0.4 −20 µA (max)
Off Channel Input=5V (Note 11)
PSS Power Supply Sensitivity V
+
=
5V
±
5%,V
REF
=
4.75V
±
1/16
±
1
⁄
2
LSB (max)
All Codes Tested
Effective Bits 7.8 Bits
Full-Power Bandwidth 300 kHz
THD Total Harmonic Distortion 0.5
%
S/N Signal-to-Noise Ratio 50 dB
IMD Intermodulation Distortion 50 dB
AC Electrical Characteristics
The following specifications apply for V
+
=
5V, t
r
=
t
f
=
10 ns, V
REF+
=
5V, V
REF−
=
0V unless otherwise specified. Bold-
face limits apply for T
A
=
T
J
=
T
MIN
to T
MAX
; all other limits T
A
=
T
J
=
25˚C.
Symbol Parameter Condition
Typical
(Note 7)
Limits
(Note 8)
Units
(Limit)
t
WR
Write Time Mode Pin to V+; 100 100 ns (min)
(
Figures 2, 3, 4
)
t
RD
Read Time (Time from Falling Edge Mode Pin to V+;(
Figure 2
) 350 350 ns (min)
of WR to Falling Edge of RD )
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AC Electrical Characteristics (Continued)
The following specifications apply for V
+
=
5V, t
r
=
t
f
=
10 ns, V
REF+
=
5V, V
REF−
=
0V unless otherwise specified. Bold-
face limits apply for T
A
=
T
J
=
T
MIN
to T
MAX
; all other limits T
A
=
T
J
=
25˚C.
Symbol Parameter Condition
Typical
(Note 7)
Limits
(Note 8)
Units
(Limit)
t
RDW
RD Width Mode Pin to GND; (
Figure 5
) 200 250 ns (min)
400 400 ns (max)
t
CONV
WR -RD Mode Conversion Time Mode Pin to V+;(
Figure 2
) 500 560 ns (max)
(t
WR+tRD+tACC1
)
t
CRD
RD Mode Conversion Time Mode Pin to GND; (
Figure 1
) 655 900 ns (max)
t
ACCO
Access Time (Delay from Falling CL≤ 100 pF 640 900 ns (max)
Edge of RD to Output Valid)
Mode Pin to GND; (
Figure 1
)
t
ACC1
Access Time (Delay from CL≤ 10 pF 45 110 ns (max)
Falling Edge C
L
=
100 pF 50
of RD to Output Valid)
Mode Pin to V+,tRD≤ t
INTL
(
Figure 2
)
t
ACC2
Access Time (Delay from CL≤ 10 pF 25 55 ns (max)
Falling Edge C
L
=
100 pF 30
of RD to Output Valid)
t
RD
>
t
INTL
;(
Figures 3, 4
)
t
0H
TRI-STATE®Control (Delay from R
L
=
3kΩ,C
L
=
10 pF 30 60 ns (max)
Rising Edge of RD to HI-Z State)
t
1H
TRI-STATE Control (Delay from R
L
=
3kΩ,C
L
=
10 pF 30 60 ns (max)
Rising Edge of RD to HI-Z State)
t
INTL
Delay from Rising Edge of (
Figures 3, 4
) 520 690 ns (max)
WR to Falling Edge of INT
Mode Pin=V+,C
L
=
50 pF
t
INTH
Delay from Rising Edge of C
L
=
50 pF; (
Figures 1, 2, 3, 4
)50 95 ns (max)
RD to Rising Edge of INT
2b, and 4
)
t
INTH
Delay from Rising Edge of C
L
=
50 pF; (
Figure 4
)4595 ns (max)
WR to Rising Edge of INT
t
RDY
Delay from CS to RDY Mode Pin=0V, C
L
=
50 pF, 25 45 ns (max)
R
L
=
3kΩ(
Figure 1
)
t
ID
Delay from INT to Output Valid R
L
=
3kΩ,C
L
=
100 pF; 0 15 ns (max)
(
Figure 4
)
t
RI
Delay from RD to INT Mode Pin=V+,tRD≤ t
INTL
; 60 115 ns (max)
(
Figure 3
)
t
N
Time between End of RD (
Figures 1, 2, 3, 4, 5
)5050 ns (min)
and Start of New Conversion
t
AH
Channel Address Hold Time (
Figures 1, 2, 3, 4, 5
)1060 ns (min)
t
AS
Channel Address Setup Time (
Figures 1, 2, 3, 4, 5
)00ns (max)
t
CSS
CS Setup Time (
Figures 1, 2, 3, 4, 5
)00ns (max)
t
CSH
CS Hold Time (
Figures 1, 2, 3, 4, 5
)00ns (min)
C
VIN
Analog Input Capacitance 25 pF
C
OUT
Logic Output Capacitance 5 pF
C
IN
Logic Input Capacitance 5 pF
DC Electrical Characteristics
The following specifications apply for V
+
=
5V unless otherwise specified. Boldface limits apply for T
A
=
T
J
=
T
MIN
to T
MAX
;
all other limits T
A
=
T
J
=
25˚C.
Symbol Parameter Conditions Typical Limits Units
(Limit)
(Note 7) (Note 8)
V
IH
Logic “1” Input Voltage V
+
=
5.5V
Mode Pin 3.5 V (min)
ADC08062
CS, WR, RD, A0 Pins
2.2 V (min)
ADC08061
CS, WR, RD Pins
2.0 V (min)
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