NSC ADC0803LCWM, ADC0803LCV, ADC0803LCN, ADC0803LCJ, ADC0805LCN Datasheet

TL/H/5671

ADC0801/ADC0802/ADC0803/ADC0804/ADC0805

8-Bit mP Compatible A/D Converters

December 1994

ADC0801/ADC0802/ADC0803/ADC0804/ADC0805
8-Bit mP Compatible A/D Converters

General Description

The ADC0801, ADC0802, ADC0803, ADC0804 and
ADC0805 are CMOS 8-bit successive approximation A/D
converters that use a differential potentiometric ladderÐ
similar to the 256R products. These converters are de­signed to allow operation with the NSC800 and INS8080A
derivative control bus with TRI-STATE

É

output latches di­rectly driving the data bus. These A/Ds appear like memory
locations or I/O ports to the microprocessor and no inter­facing logic is needed.

Differential analog voltage inputs allow increasing the com­mon-mode rejection and offsetting the analog zero input
voltage value. In addition, the voltage reference input can
be adjusted to allow encoding any smaller analog voltage
span to the full 8 bits of resolution.

Features

Y

Compatible with 8080 mP derivativesÐno interfacing
logic needed - access time - 135 ns

Y

Easy interface to all microprocessors, or operates
‘‘stand alone’’

Y

Differential analog voltage inputs

Y

Logic inputs and outputs meet both MOS and TTL volt­age level specifications

Y

Works with 2.5V (LM336) voltage reference

Y

On-chip clock generator

Y

0V to 5V analog input voltage range with single 5V
supply

Y

No zero adjust required

Y

0.3×standard width 20-pin DIP package

Y

20-pin molded chip carrier or small outline package

Y

Operates ratiometrically or with 5 VDC, 2.5 VDC, or ana­log span adjusted voltage reference

Key Specifications

Y

Resolution 8 bits

Y

Total error

g

(/4 LSB,g(/2 LSB andg1 LSB

Y

Conversion time 100 ms

Typical Applications

TL/H/5671– 1

8080 Interface

TL/H/5671– 31

Error Specification (Includes Full-Scale,

Zero Error, and Non-Linearity)

Part

Full-

V

REF

/2e2.500 VDCV

REF

/2eNo Connection

Number

Scale

(No Adjustments) (No Adjustments)

Adjusted

ADC0801g(/4 LSB

ADC0802

g

(/2 LSB

ADC0803g(/2 LSB

ADC0804

g

1 LSB

ADC0805

g

1 LSB

TRI-STATEÉis a registered trademark of National Semiconductor Corp.
Z-80

É

is a registered trademark of Zilog Corp.

C

1995 National Semiconductor Corporation RRD-B30M115/Printed in U. S. A.

Absolute Maximum Ratings (Notes1&2)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.

Supply Voltage (V

CC

) (Note 3) 6.5V

Voltage

Logic Control Inputs

b

0.3V toa18V

At Other Input and Outputs

b

0.3V to (V

CC

a

0.3V)

Lead Temp. (Soldering, 10 seconds)

Dual-In-Line Package (plastic) 260

§

C

Dual-In-Line Package (ceramic) 300

§

C

Surface Mount Package

Vapor Phase (60 seconds) 215

§

C

Infrared (15 seconds) 220

§

C

Storage Temperature Range

b

65§Ctoa150§C

Package Dissipation at T

A

e

25§C 875 mW

ESD Susceptibility (Note 10) 800V

Operating Ratings (Notes1&2)

Temperature Range T

MIN

s

T

A

s

T

MAX

ADC0801/02LJ, ADC0802LJ/883b55§CsT

A

s

a

125§C

ADC0801/02/03/04LCJ

b

40§CsT

A

s

a

85§C

ADC0801/02/03/05LCN

b

40§CsT

A

s

a

85§C

ADC0804LCN 0

§

CsT

A

s

a

70§C

ADC0802/03/04LCV 0

§

CsT

A

s

a

70§C

ADC0802/03/04LCWM 0

§

CsT

A

s

a

70§C

Range of V

CC

4.5 VDCto 6.3 V

DC

Electrical Characteristics

The following specifications apply for V

CC

e

5VDC,T

MIN

s

T

A

s

T

MAX

and f

CLK

e

640 kHz unless otherwise specified.

Parameter Conditions Min Typ Max Units

ADC0801: Total Adjusted Error (Note 8) With Full-Scale Adj.

g

(/4 LSB

(See Section 2.5.2)

ADC0802: Total Unadjusted Error (Note 8) V

REF

/2e2.500 V

DC

g

(/2 LSB

ADC0803: Total Adjusted Error (Note 8) With Full-Scale Adj.

g

(/2 LSB

(See Section 2.5.2)

ADC0804: Total Unadjusted Error (Note 8) V

REF

/2e2.500 V

DC

g

1 LSB

ADC0805: Total Unadjusted Error (Note 8) V

REF

/2-No Connection

g

1 LSB

V

REF

/2 Input Resistance (Pin 9) ADC0801/02/03/05 2.5 8.0 kX

ADC0804 (Note 9) 0.75 1.1 kX

Analog Input Voltage Range (Note 4) V(a)orV(b) Gnd–0.05 V

CC

a

0.05 V

DC

DC Common-Mode Error Over Analog Input Voltage

g

(/16

g

(/8 LSB

Range

Power Supply Sensitivity V

CC

e

5V

DC

g

10% Over

g

(/16

g

(/8 LSB
Allowed VIN(a) and VIN(b)
Voltage Range (Note 4)

AC Electrical Characteristics

The following specifications apply for V

CC

e

5VDCand T

A

e

25§C unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Units

T

C

Conversion Time f

CLK

e

640 kHz (Note 6) 103 114 ms

T

C

Conversion Time (Note 5, 6) 66 73 1/f

CLK

f

CLK

Clock Frequency V

CC

e

5V, (Note 5) 100 640 1460 kHz

Clock Duty Cycle (Note 5) 40 60 %

CR Conversion Rate in Free-Running INTR tied to WR with 8770 9708 conv/s

Mode CS

e

0VDC,f

CLK

e

640 kHz

t

W(WR)L

Width of WR Input (Start Pulse Width) CSe0VDC(Note 7) 100 ns

t

ACC

Access Time (Delay from Falling C

L

e

100 pF 135 200 ns

Edge of RD

to Output Data Valid)

t1H,t

0H

TRI-STATE Control (Delay C

L

e

10 pF, R

L

e

10k 125 200 ns

from Rising Edge of RD

to (See TRI-STATE Test

Hi-Z State) Circuits)

tWI,t

RI

Delay from Falling Edge 300 450 ns
of WR or RD to Reset of INTR

C

IN

Input Capacitance of Logic 5 7.5 pF
Control Inputs

C

OUT

TRI-STATE Output 5 7.5 pF
Capacitance (Data Buffers)

CONTROL INPUTS[Note: CLK IN (Pin 4) is the input of a Schmitt trigger circuit and is therefore specified separately

]

VIN(1) Logical ‘‘1’’ Input Voltage V

CC

e

5.25 V

DC

2.0 15 V

DC

(Except Pin 4 CLK IN)

2

AC Electrical Characteristics (Continued)

The following specifications apply for V

CC

e

5VDCand T

MIN

s

T

A

s

T

MAX

, unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Units

CONTROL INPUTS[Note: CLK IN (Pin 4) is the input of a Schmitt trigger circuit and is therefore specified separately

]

VIN(0) Logical ‘‘0’’ Input Voltage V

CC

e

4.75 V

DC

0.8 V

DC

(Except Pin 4 CLK IN)

IIN(1) Logical ‘‘1’’ Input Current V

IN

e

5V

DC

0.005 1 mA

DC

(All Inputs)

IIN(0) Logical ‘‘0’’ Input Current V

IN

e

0V

DC

b

1

b

0.005 mA

DC

(All Inputs)

CLOCK IN AND CLOCK R

V

T

a

CLK IN (Pin 4) Positive Going 2.7 3.1 3.5 V

DC

Threshold Voltage

V

T

b

CLK IN (Pin 4) Negative 1.5 1.8 2.1 V

DC

Going Threshold Voltage

V

H

CLK IN (Pin 4) Hysteresis 0.6 1.3 2.0 V

DC

(V

T

a)b

(V

T

b

)

V

OUT

(0) Logical ‘‘0’’ CLK R Output I

O

e

360 mA 0.4 V

DC

Voltage V

CC

e

4.75 V

DC

V

OUT

(1) Logical ‘‘1’’ CLK R Output I

O

eb

360 mA 2.4 V

DC

Voltage V

CC

e

4.75 V

DC

DATA OUTPUTS AND INTR

V

OUT

(0) Logical ‘‘0’’ Output Voltage

Data Outputs I

OUT

e

1.6 mA, V

CC

e

4.75 V

DC

0.4 V

DC

INTR Output I

OUT

e

1.0 mA, V

CC

e

4.75 V

DC

0.4 V

DC

V

OUT

(1) Logical ‘‘1’’ Output Voltage I

O

eb

360 mA, V

CC

e

4.75 V

DC

2.4 V

DC

V

OUT

(1) Logical ‘‘1’’ Output Voltage I

O

eb

10 mA, V

CC

e

4.75 V

DC

4.5 V

DC

I

OUT

TRI-STATE Disabled Output V

OUT

e

0V

DC

b

3 mA

DC

Leakage (All Data Buffers) V

OUT

e

5V

DC

3 mA

DC

I

SOURCE

V

OUT

Short to Gnd, T

A

e

25§C 4.5 6 mA

DC

I

SINK

V

OUT

Short to VCC,T

A

e

25§C 9.0 16 mA

DC

POWER SUPPLY

I

CC

Supply Current (Includes f

CLK

e

640 kHz,

Ladder Current) V

REF

/2eNC, T

A

e

25§C

and CS

e

5V
ADC0801/02/03/04LCJ/05 1.1 1.8 mA
ADC0804LCN/LCV/LCWM 1.9 2.5 mA

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified operating conditions.

Note 2: All voltages are measured with respect to Gnd, unless otherwise specified. The separate A Gnd point should always be wired to the D Gnd.

Note 3: A zener diode exists, internally, from V

CC

to Gnd and has a typical breakdown voltage of 7 VDC.

Note 4: For V

IN

(b)tVIN(a) the digital output code will be 0000 0000. Two on-chip diodes are tied to each analog input (see block diagram) which will forward

conduct for analog input voltages one diode drop below ground or one diode drop greater than the V

CC

supply. Be careful, during testing at low VCClevels (4.5V),
as high level analog inputs (5V) can cause this input diode to conduct – especially at elevated temperatures, and cause errors for analog inputs near full-scale. The
spec allows 50 mV forward bias of either diode. This means that as long as the analog V

IN

does not exceed the supply voltage by more than 50 mV, the output

code will be correct. To achieve an absolute 0 V

DC

to5VDCinput voltage range will therefore require a minimum supply voltage of 4.950 VDCover temperature

variations, initial tolerance and loading.

Note 5: Accuracy is guaranteed at f

CLK

e

640 kHz. At higher clock frequencies accuracy can degrade. For lower clock frequencies, the duty cycle limits can be

extended so long as the minimum clock high time interval or minimum clock low time interval is no less than 275 ns.

Note 6: With an asynchronous start pulse, up to 8 clock periods may be required before the internal clock phases are proper to start the conversion process. The
start request is internally latched, see

Figure 2

and section 2.0.

Note 7: The CS

input is assumed to bracket the WR strobe input and therefore timing is dependent on the WR pulse width. An arbitrarily wide pulse width will hold

the converter in a reset mode and the start of conversion is initiated by the low to high transition of the WR

pulse (see timing diagrams).

Note 8: None of these A/Ds requires a zero adjust (see section 2.5.1). To obtain zero code at other analog input voltages see section 2.5 and

Figure 5

.

Note 9: The V

REF

/2 pin is the center point of a two-resistor divider connected from VCCto ground. In all versions of the ADC0801, ADC0802, ADC0803, and

ADC0805, and in the ADC0804LCJ, each resistor is typically 16 kX. In all versions of the ADC0804 except the ADC0804LCJ, each resistor is typically 2.2 kX.

Note 10: Human body model, 100 pF discharged through a 1.5 kX resistor.

3

Typical Performance Characteristics

Logic Input Threshold Voltage
vs. Supply Voltage

Delay From Falling Edge of
RD

to Output Data Valid

vs. Load Capacitance

CLK IN Schmitt Trip Levels

vs. Supply Voltage

f

CLK

vs. Clock Capacitor

Full-Scale Error vs
Conversion Time

Effect of Unadjusted Offset Error

vs. V

REF

/2 Voltage

Output Current vs
Temperature

Power Supply Current
vs Temperature (Note 9)

Linearity Error at Low

V

REF

/2 Voltages

TL/H/5671– 2

4

TRI-STATE Test Circuits and Waveforms

t

1H

t1H,C

L

e

10 pF

t

r

e

20 ns

t

0H

t0H,C

L

e

10 pF

t

r

e

20 ns

TL/H/5671– 3

Timing Diagrams (All timing is measured from the 50% voltage points)

Output Enable and Reset INTR

Note: Read strobe must occur 8 clock periods (8/f

CLK

) after assertion of interrupt to guarantee reset of INTR.

TL/H/5671– 4

5

Typical Applications (Continued)

6800 Interface Ratiometric with Full-Scale Adjust

Note: before using caps at VINor V

REF

/2,

see section 2.3.2 Input Bypass Capacitors.

Absolute with a 2.500V Reference

*For low power, see also LM385-2.5

Absolute with a 5V Reference

Zero-Shift and Span Adjust: 2V

s

V

IN

s

5V Span Adjust: 0VsV

IN

s

3V

TL/H/5671– 5

6

Typical Applications (Continued)

Directly Converting a Low-Level Signal

V

REF

/2e256 mV

A mP Interfaced Comparator

For: VIN(a)lVIN(b)

Output

e

FF

HEX

For: VIN(a)kVIN(b)

Output

e

00

HEX

1 mV Resolution with mP Controlled Range

V

REF

/2e128 mV

1 LSB

e

1mV

V

DAC

s

V

IN

s

(V

DAC

a

256 mV)

Digitizing a Current Flow

TL/H/5671– 6

7

Typical Applications (Continued)

Self-Clocking Multiple A/Ds

*Use a large R value

to reduce loading
at CLK R output.

External Clocking

100 kHzsf

CLK

s

1460 kHz

Self-Clocking in Free-Running Mode

*After power-up, a momentary grounding

of the WR

input is needed to guarantee operation.

mP Interface for Free-Running A/D

Operating with ‘‘Automotive’’ Ratiometric Transducers

*VIN(b)e0.15 V

CC

15% of V

CC

s

V

XDR

s

85% of V

CC

Ratiometric with V

REF

/2 Forced

TL/H/5671– 7

8

Typical Applications (Continued)

mP Compatible Differential-Input Comparator with Pre-Set V

OS

(with or without Hysteresis)

*See

Figure 5

to select R value

DB7

e

‘‘1’’ for VIN(a)lVIN(b)a(V

REF

/2)

Omit circuitry within the dotted area if

hysteresis is not needed

Handlingg10V Analog Inputs

*Beckman InstrumentsÝ694-3-R10K resistor array

Low-Cost, mP Interfaced, Temperature-to-Digital Converter

mP Interfaced Temperature-to-Digital Converter

*Circuit values shown are for 0§CsT

A

s

a

128§C

**Can calibrate each sensor to allow easy replacement, then

A/D can be calibrated with a pre-set input voltage.

TL/H/5671– 8

9

Typical Applications (Continued)

Handling

g

5V Analog Inputs

TL/H/5671– 33

*Beckman InstrumentsÝ694-3-R10K resistor array

Read-Only Interface

TL/H/5671– 34

mP Interfaced Comparator with Hysteresis

TL/H/5671– 35

Analog Self-Test for a System

TL/H/5671– 36

Protecting the Input

TL/H/5671– 9

A Low-Cost, 3-Decade Logarithmic Converter

TL/H/5671– 37

*LM389 transistors

A, B, C, D

e

LM324A quad op amp

Diodes are 1N914

10

Typical Applications (Continued)

3-Decade Logarithmic A/D Converter

Noise Filtering the Analog Input

f

C

e

20 Hz

Uses Chebyshev implementation for steeper roll-off
unity-gain, 2nd order, low-pass filter
Adding a separate filter for each channel increases
system response time if an analog multiplexer
is used

Multiplexing Differential Inputs

Output Buffers with A/D Data Enabled

*A/D output data is updated 1 CLK period
prior to assertion of INTR

Increasing Bus Drive and/or Reducing Time on Bus

*Allows output data to set-up at falling edge of CS

TL/H/5671– 10

11