NSC ADC08038CIWM, ADC08038CIN Datasheet
ADC08031/ADC08034/ADC08038
8-Bit High-Speed Serial I/O A/D Converters with
Multiplexer Options, Voltage Reference, and Track/Hold
Function
General Description
The ADC08031/ADC08032/ADC08034/ADC08038 are 8-bit
successive approximationA/D converters with serial I/O and
configurable input multiplexers with up to 8 channels. The
serial I/O is configured to comply with the NSC MICROWIRE
™
serial data exchangestandard for easy interface to the
COPS
™
family of controllers, and can easily interface with
standard shift registers or microprocessors.
TheADC08034 and ADC08038 provide a 2.6V band-gap de-
rived reference. For devices offering guaranteed voltage reference performance over temperature see ADC08131,
ADC08134 and ADC08138.
Atrack/hold function allows the analog voltage at the positive
input to vary during the actual A/D conversion.
The analog inputs can be configured to operate in various
combinations of single-ended, differential, or
pseudo-differential modes. In addition, input voltage spans
as small as 1V can be accommodated.
Applications
n Digitizing automotive sensors
n Process control monitoring
n Remote sensing in noisy environments
n Instrumentation
n Test systems
n Embedded diagnostics
Features
n Serial digital data link requires few I/O pins
n Analog input track/hold function
n 2-, 4-, or 8-channel input multiplexer options with
address logic
n 0V to 5V analog input range with single 5V power
supply
n No zero or full scale adjustment required
n TTL/CMOS input/output compatible
n On chip 2.6V band-gap reference
n 0.3" standard width 8-, 14-, or 20-pin DIP package
n 14-, 20-pin small-outline packages
Key Specifications
n Resolution 8 bits
n Conversion time (f
C
=
1 MHz) 8µs (max)
n Power dissipation 20mW (max)
n Single supply 5V
DC
(±5%)
n Total unadjusted error
±
1
⁄2LSB and±1LSB
n No missing codes over temperature
Ordering Information
Industrial (−40˚C ≤ TA≤ +85˚C) Package
ADC08031CIN N08E
ADC08031CIWM, ADC08034CIWM M14B
ADC08038CIWM M20B
TRI-STATE®is a registered trademark of National Semiconductor Corporation.
COPS
™
microcontrollers and MICROWIRE™are trademarks of National Semiconductor Corporation.
June 1999
ADC08031/ADC08034/ADC08038 8-Bit High-Speed Serial I/O A/D Converters with Multiplexer
Options, Voltage Reference, and Track/Hold Function
© 1999 National Semiconductor Corporation DS010555 www.national.com
Connection Diagrams
ADC08038
DS010555-2
ADC08034
DS010555-3
ADC08031
Dual-In-Line Package
DS010555-5
ADC08031
Small Outline Package
DS010555-31
www.national.com 2
Absolute Maximum Ratings (Notes 1, 3)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
CC
) 6.5V
Voltage at Inputs and Outputs −0.3V to V
CC
+ 0.3V
Input Current at Any Pin (Note 4)
±
5mA
Package Input Current (Note 4)
±
20 mA
Power Dissipation at T
A
=
25˚C
(Note 5) 800 mW
ESD Susceptibility (Note 6) 1500V
Soldering Information
N Package (10 sec.)
SO Package:
Vapor Phase (60 sec.)
Infrared (15 sec.) (Note 7)
260˚C
215˚C
220˚C
Storage Temperature −65˚C to +150˚C
Operating Ratings (Notes 2, 3)
Temperature Range T
MIN
≤ TA≤ T
MAX
ADC08031CIN, −40˚C ≤ TA≤ +85˚C
ADC08031CIWM,
ADC08034CIWM, ADC08038CIWM
Supply Voltage (V
CC
) 4.5 VDCto 6.3 V
DC
Electrical Characteristics
The following specifications apply for V
CC
=
V
REF
=
+5 V
DC
, and f
CLK
=
1 MHz unless otherwise specified. Boldface limits
apply for T
A
=
T
J
=
T
MIN
to T
MAX
; all other limits T
A
=
T
J
=
25˚C.
Symbol Parameter Conditions
ADC08031, ADC08034 and
ADC08038
Units (Limits)
Typical (Note8)Limits (Note 9)
CONVERTER AND MULTIPLEXER CHARACTERISTICS
Total Unadjusted Error (Note 10)
BIN, BIWM
±
1
⁄
2
LSB (max)
CIN, CIWM
±
1 LSB (max)
Differential 8 Bits (min)
Linearity
R
REF
Reference Input Resistance 3.5 kΩ
1.3 kΩ (min)
6.0 kΩ (max)
V
IN
Analog Input Voltage (Note 11) (VCC+ 0.05) V (max)
(GND − 0.05) V (min)
DC Common-Mode Error
±
1
⁄
4
LSB (max)
Power Supply Sensitivity V
CC
=
5V
±
5%,
±
1
⁄
4
LSB (max)
V
REF
=
4.75V
On Channel Leakage On Channel=5V, 0.2 µA (max)
Current (Note 12) Off Channel=0V 1
On Channel=0V, −0.2 µA (max)
Off Channel=5V −1
Off Channel Leakage On Channel=5V, −0.2 µA (max)
Current (Note 12) Off Channel=0V −1
On Channel=0V, 0.2 µA (max)
Off Channel=5V 1
DIGITAL AND DC CHARACTERISTICS
V
IN(1)
Logical “1” Input Voltage V
CC
=
5.25V 2.0 V (min)
V
IN(0)
Logical “0” Input Voltage V
CC
=
4.75V 0.8 V (max)
I
IN(1)
Logical “1” Input Current V
IN
=
5.0V 1 µA (max)
I
IN(0)
Logical “0” Input Current V
IN
=
0V −1 µA (max)
V
OUT(1)
Logical “1” Output Voltage V
CC
=
4.75V:
I
OUT
=
−360 µA 2.4 V (min)
I
OUT
=
−10 µA 4.5 V (min)
www.national.com3
Electrical Characteristics (Continued)
The following specifications apply for V
CC
=
V
REF
=
+5 V
DC
, and f
CLK
=
1 MHz unless otherwise specified. Boldface limits
apply for T
A
=
T
J
=
T
MIN
to T
MAX
; all other limits T
A
=
T
J
=
25˚C.
Symbol Parameter Conditions
ADC08031, ADC08034 and
ADC08038
Units (Limits)
Typical (Note8)Limits (Note 9)
DIGITAL AND DC CHARACTERISTICS
V
OUT(0)
Logical “0” Output Voltage V
CC
=
4.75V 0.4 V (max)
I
OUT
=
1.6 mA
I
OUT
TRI-STATE®Output Current V
OUT
=
0V −3.0 µA (max)
V
OUT
=
5V 3.0 µA (max)
I
SOURCE
Output Source Current V
OUT
=
0V −6.5 mA (min)
I
SINK
Output Sink Current V
OUT
=
V
CC
8.0 mA (min)
I
CC
Supply Current
ADC08031, ADC08034, and
ADC08038
CS=HIGH
3.0 mA (max)
REFERENCE CHARACTERISTICS
V
REF
OUT Nominal Reference Output V
REF
OUT Option
Available Only on 2.6 V
ADC08034 and
ADC08038
Electrical Characteristics
The following specifications apply for V
CC
=
V
REF
=
+5 V
DC
, and t
r
=
t
f
=
20 ns unless otherwise specified. Boldface limits
apply for T
A
=
T
J
=
T
MIN
to T
MAX
; all other limits T
A
=
T
J
=
25˚C.
Symbol Parameter Conditions Typical Limits Units
(Note 8) (Note 9) (Limits)
f
CLK
Clock Frequency 10 kHz (min)
1 MHz (max)
Clock Duty Cycle 40
%
(min)
(Note 13) 60
%
(max)
T
C
Conversion Time (Not Including f
CLK
=
1 MHz 8 1/f
CLK
(max)
MUX Addressing Time) 8 µs (max)
t
CA
Acquisition Time
1
⁄
2
1/f
CLK
(max)
t
SELECT
CLK High while CS is High 50 ns
t
SET-UP
CS Falling Edge or Data Input 25 ns (min)
Valid to CLK Rising Edge
t
HOLD
Data Input Valid after CLK 20 ns (min)
Rising Edge
t
pd1,tpd0
CLK Falling Edge to Output C
L
=
100 pF:
Data Valid (Note 14) Data MSB First 250 ns (max)
Data LSB First 200 ns (max)
t
1H,t0H
TRI-STATE Delay from Rising Edge C
L
=
10 pF, R
L
=
10 kΩ 50 ns
of CS to Data Output and SARS Hi-Z
(see TRI-STATE Test Circuits)
C
L
=
100 pF, R
L
=
2kΩ 180 ns (max)
C
IN
Capacitance of Logic Inputs 5 pF
C
OUT
Capacitance of Logic Outputs 5 pF
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.
Note 2: Operating Ratings indicate conditions for which the device is functional. These ratings do not guarantee specific performance limits. For guaranteed speci-
fications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions.
Note 3: All voltages are measured with respect to AGND=DGND=0V
DC
, unless otherwise specified.
www.national.com 4
Electrical Characteristics (Continued)
Note 4: When the input voltage VINat any pin exceeds the power supplies (V
IN
<
(AGND or DGND) or V
IN
>
VCC) the current at that pin should be limited to 5 mA.
The 20 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 5 mA to four pins.
Note 5: The maximum power dissipation must be derated at elevated temperatures and is dictated by T
JMAX
, θJAand the ambient temperature, TA. The maximum
allowable power dissipation at any temperature is P
D
=
(T
JMAX−TA
)/θJAor the number given in the Absolute Maximum Ratings, whichever is lower. For devices with
suffixes CIN and CIWM T
JMAX
=
125˚C. The typical thermal resistances (θ
JA
) of these parts when board mounted follow: ADC08031CIN 120˚C/W,ADC08031CIWM
140˚C/W, ADC08034 CIWM 140˚C/W, ADC08038CIWM suffixes 91˚C/W.
Note 6: Human body model, 100 pF capacitor discharged through a 1.5 kΩ resistor.
Note 7: See AN450 “Surface Mounting Methods and Their Effect on Product Reliability” or Linear Data Book section “Surface Mount” for other methods of soldering
surface mount devices.
Note 8: Typicals are at T
J
=
25˚C and represent the most likely parametric norm.
Note 9: Guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 10: Total unadjusted error includes offset, full-scale, linearity, multiplexer.
Note 11: For V
IN(−)
≥ V
IN(+)
the digital code will be 0000 0000. Two on-chip diodes are tied to each analog input (see Block Diagram) which will forward-conduct for
analog input voltages one diode drop below ground or one diode drop greater than V
CC
supply.During testing at low VCClevels (e.g., 4.5V), high level analog inputs
(e.g., 5V) can cause an input diode to conduct, especially at elevated temperatures, which will cause errors for analog inputs near full-scale. The spec allows 50 mV
forward bias of either diode; this means that as long as the analog V
IN
does not exceed the supply voltage by more than 50 mV, the output code will be correct. Ex-
ceeding this range on an unselected channel will corruptthe reading of a selected channel. Achievement of an absolute 0 V
DC
to5VDCinput voltage range will there-
fore require a minimum supply voltage of 4.950 V
DC
over temperature variations, initial tolerance and loading.
Note 12: Channel leakage current is measured after a single-ended channel is selected and the clock is turned off. For off channel leakage current the following two
cases are considered: one, with the selected channel tied high (5 V
DC
) and the remaining seven off channels tied low (0 VDC), total current flow through the off channels is measured; two, with the selected channel tied low and the off channels tied high, total current flow through the off channels is again measured. The two cases
considered for determining on channel leakage current are the same except total current flow through the selected channel is measured.
Note 13: A40%to 60%duty cycle range insures proper operation at all clock frequencies. In the case that an available clock has a duty cycle outside of these limits
the minimum time the clock is high or low must be at least 450 ns. The maximum time the clock can be high or low is 100 µs.
Note 14: Since data, MSB first, isthe output of the comparator used in the successive approximation loop, an additional delay is built in (see Block Diagram) to allow
for comparator response time.
Typical Performance Characteristics
Linearity Error vs
Reference Voltage
DS010555-32
Linearity Error vs
Temperature
DS010555-33
Linearity Error vs
Clock Frequency
DS010555-34
Power Supply Current vs
Temperature
DS010555-35
Output Current vs
Temperature
DS010555-36
Power Supply Current
vs Clock Frequency
DS010555-37
www.national.com5
Leakage Current Test Circuit
TRI-STATE Test Circuits and Waveforms
Timing Diagrams
DS010555-7
t
1H
DS010555-38
DS010555-39
t
0H
DS010555-40
DS010555-41
Data Input Timing
DS010555-10
*To reset these devices, CLK and CS must be simultaneously high for a period of t
SELECT
or greater. Otherwise these devices are compatible with industry
standards ADC0831/2/4/8.
www.national.com 6
Timing Diagrams (Continued)
Data Output Timing
DS010555-11
ADC08031 Start Conversion Timing
DS010555-12
ADC08031 Timing
DS010555-13
*LSB first output not available on ADC08031.
LSB information is maintained for remainder of clock periods until CS goes high.
www.national.com7
Timing Diagrams (Continued)
ADC08034 Timing
DS010555-15
www.national.com 8
Loading...