NSC ADC0800PD, ADC0800PCD Datasheet

TL/H/5670

ADC0800 8-Bit A/D Converter

February 1995

ADC0800 8-Bit A/D Converter

General Description

The ADC0800 is an 8-bit monolithic A/D converter using P­channel ion-implanted MOS technology. It contains a high
input impedance comparator, 256 series resistors and ana­log switches, control logic and output latches. Conversion is
performed using a successive approximation technique
where the unknown analog voltage is compared to the re­sistor tie points using analog switches. When the appropri­ate tie point voltage matches the unknown voltage, conver­sion is complete and the digital outputs contain an 8-bit
complementary binary word corresponding to the unknown.
The binary output is TRI-STATE

É

to permit bussing on com-

mon data lines.

The ADC0800PD is specified over

b

55§Ctoa125§C and

the ADC0800PCD is specified over 0

§

Cto70§C.

Features

Y

Low cost

Y

g

5V, 10V input ranges

Y

No missing codes

Y

Ratiometric conversion

Y

TRI-STATE outputs

Y

Fast T

C

e

50 ms

Y

Contains output latches

Y

TTL compatible

Y

Supply voltages 5 VDCandb12 V

DC

Y

Resolution 8 bits

Y

Linearity

g

1 LSB

Y

Conversion speed 40 clock periods

Y

Clock range 50 to 800 kHz

Block Diagram

TL/H/5670– 1

(00000000eafull-scale)

TRI-STATEÉis a registered trademark of National Semiconductor Corp.

C

1995 National Semiconductor Corporation RRD-B30M115/Printed in U. S. A.

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.

Supply Voltage (V

DD

)V

SS

b

22V

Supply Voltage (VGG)V

SS

b

22V

Voltage at Any Input V

SS

a

0.3V to V

SS

b

22V

Input Current at Any Pin (Note 2) 5 mA

Package Input Current (Note 2) 20 mA

Power Dissipation (Note 3) 875 mW

ESD Susceptibility (Note 4) 500V

Storage Temperature 150

§

C

Lead Temperature (Soldering, 10 sec.) 300§C

Operating Ratings (Note 1)

Temperature Range T

MIN

s

T

A

s

T

MAX

ADC0800PD

b

55§CsT

A

s

a

125§C

ADC0800PCD 0

§

CsT

A

s

a

70§C

Electrical Characteristics

These specifications apply for V

SS

e

5.0 VDC,V

GG

eb

12.0 VDC,V

DD

e

0VDC, a reference voltage of 10.000 VDCacross the

on-chip R-network (V

R-NETWORK TOP

e

5.000 VDCand V

R-NETWORK BOTTOM

eb

5.000 VDC), and a clock frequency of 800

kHz. For all tests, a 475X resistor is used from pin 5 to V

R-NETWORK BOTTOM

eb

5VDC. Unless otherwise noted, these

specifications apply over an ambient temperature range of

b

55§Ctoa125§C for the ADC0800PD and 0§Ctoa70§C for the

ADC0800PCD.

Parameter Conditions Min Typ Max Units

Non-Linearity T

A

e

25§C, (Note 8)

g

1 LSB

Over Temperature, (Note 8)

g

2 LSB

Differential Non-Linearity

g

(/2 LSB

Zero Error

g

2 LSB

Zero Error Temperature Coefficient (Note 9) 0.01 %/§C

Full-Scale Error

g

2 LSB

Full-Scale Error Temperature Coefficient (Note 9) 0.01 %/§C

Input Leakage 1 mA

Logical ‘‘1’’ Input Voltage All Inputs V

SS

b

1.0 V

SS

V

Logical ‘‘0’’ Input Voltage All Inputs V

GG

V

SS

b

4.2 V

Logical Input Leakage T

A

e

25§C, All Inputs, V

IL

e

1 mA

V

SS

b

10V

Logical ‘‘1’’ Output Voltage All Outputs, I

OH

e

100 mA 2.4 V

Logical ‘‘0’’ Output Voltage All Outputs, I

OL

e

1.6 mA 0.4 V

Disabled Output Leakage T

A

e

25§C, All Outputs, V

OL

e

2 mA

V

SS

@

10V

Clock Frequency 0§CsT

A

s

a

70§C 50 800 kHz

b

55§CsT

A

s

a

125§C 100 500 kHz

Clock Pulse Duty Cycle 40 60 %

TRI-STATE Enable/Disable Time 1 ms

Start Conversion Pulse (Note 10) 1 3(/2 Clock

Periods

Power Supply Current T

A

e

25§C20mA

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified operating conditions.

Note 2: When the input voltage (V

IN

) at any pin exceeds the power supply rails (V

IN

k

Vbor V

IN

l

Va) the absolute value of current at that pin should be limited

to 5 mA or less. The 20 mA package input current limits the number of pins that can exceed the power supply boundaries witha5mAcurrent limit to four.

Note 3: The maximum power dissipation must be derated at elevated temperatures and is dictated by T

JMAX

, iJA, and the ambient temperature, TA. The maximum

allowable power dissipation at any temperature is P

D

e

(T

JMAX

b

TA)/iJAor the number given in the Absolute Maximum Ratings, whichever is lower. For this

device, T

JMAX

e

125§C, and the typical junction-to-ambient thermal resistance of the ADC0800PD and ADC0800PCD when board mounted is 66§C/W.

Note 4: Human body model, 100 pF discharged through a 1.5 kX resistor.

Note 5: Typicals are at 25

§

C and represent most likely parametric norm.

Note 6: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).

Note 7: Design limits are guaranteed but not 100% tested. These limits are not used to calculate outgoing quality levels.

Note 8: Non-linearity specifications are based on best straight line.

Note 9: Guaranteed by design only.

Note 10: Start conversion pulse duration greater than 3(/2 clock periods will cause conversion errors.

2

Timing Diagram

TL/H/5670– 2

Data is complementary binary (full scale is all ‘‘0’s’’ output).

Application Hints

OPERATION

The ADC0800 contains a network with 256-300X resistors
in series. Analog switch taps are made at the junction of
each resistor and at each end of the network. In operation,
a reference (10.00V) is applied across this network of 256
resistors. An analog input (V

IN

) is first compared to the cen-

ter point of the ladder via the appropriate switch. If V

IN

is

larger than V

REF

/2, the internal logic changes the switch

points and now compares V

IN

and */4 V

REF

. This process,
known as successive approximation, continues until the
best match of V

IN

and V

REF

/N is made. N now defines a
specific tap on the resistor network. When the conversion is
complete, the logic loads a binary word corresponding to
this tap into the output latch and an end of conversion
(EOC) logic level appears. The output latches hold this data
valid until a new conversion is completed and new data is
loaded into the latches. The data transfer occurs in about
200 ns so that valid data is present virtually all the time in
the latches. The data outputs are activated when the Output
Enable is high, and in TRI-STATE when Output Enable is
low. The Enable Delay time is approximately 200 ns. Each
conversion requires 40 clock periods. The device may be
operated in the free running mode by connecting the Start
Conversion line to the End of Conversion line. However, to
ensure start-up under all possible conditions, an external
Start Conversion pulse is required during power up condi­tions.

REFERENCE

The reference applied across the 256 resistor network de­termines the analog input range. V

REF

e

10.00V with the top
of the R-network connected to 5V and the bottom connect­ed to

b

5V gives ag5V range. The reference can be level

shifted between V

SS

and VGG. However, the voltage, ap­plied to the top of the R-network (pin 15), must not exceed
V

SS

, to prevent forward biasing the on-chip parasitic silicon
diodes that exist between the P-diffused resistors (pin 15)
and the N-type body (pin 10, V

SS

). Use of a standard logic

power supply for V

SS

can cause problems, both due to initial
voltage tolerance and changes over temperature. A solution
is to power the V

SS

line (15 mA max drain) from the output

of the op amp that is used to bias the top of the

R-network (pin 15). The analog input voltage and the volt­age that is applied to the bottom of the R-network (pin 5)
must be at least 7V above the

b

VGGsupply voltage to

ensure adequate voltage drive to the analog switches.

Other reference voltages may be used (such as 10.24V). If a
5V reference is used, the analog range will be 5V and accu­racy will be reduced by a factor of 2. Thus, for maximum
accuracy, it is desirable to operate with at least a 10V refer­ence. For TTL logic levels, this requires 5V and

b

5V for the

R-network. CMOS can operate at the 10 V

DCVSS

level and

a single 10 V

DC

reference can be used. All digital voltage
levels for both inputs and outputs will be from ground to
V

SS

.

ANALOG INPUT AND SOURCE RESISTANCE
CONSIDERATIONS

The lead to the analog input (pin 12) should be kept as short
as possible. Both noise and digital clock coupling to this
input can cause conversion errors. To minimize any input
errors, the following source resistance considerations
should be noted:

For R

S

s

5k No analog input bypass capacitor re-

quired, although a 0.1 m F input bypass
capacitor will prevent pickup due to un­avoidable series lead inductance.

For 5k

k

R

S

s

20k A 0.1 mF capacitor from the input (pin

12) to ground should be used.

For R

S

l

20k Input buffering is necessary.

If the overall converter system requires lowpass filtering of
the analog input signal, use a 20 kX or less series resistor
for a passive RC section or add an op amp RC active low­pass filter (with its inherent low output resistance) to ensure
accurate conversions.

CLOCK COUPLING

The clock lead should be kept away from the analog input
line to reduce coupling.

LOGIC INPUTS

The logical ‘‘1’’ input voltage swing for the Clock, Start Con­version and Output Enable should be (V

SS

b

1.0V).

3