NSC 5962-8955601SA, 5962-89556012A, 5962-8955601RA Datasheet
54ACT563
Octal Latch with TRI-STATE
®
Outputs
General Description
The ’ACT563 is a high-speed octal latch with buffered common LatchEnable (LE) and buffered common Output Enable
(OE) inputs.
The ’ACT563 device is functionally identical to the ’ACT573,
but with inverted outputs.
Features
n ICCand IOZreduced by 50
%
n Inputs and outputs on opposite sides of package allow
easy interface with microprocessors
n Useful as input or output port for microprocessors
n Functionally identical to ’ACT573 but with inverted
outputs
n Outputs source/sink 24 mA
n ’ACT563 has TTL-compatible inputs
n Standard Military Drawing (SMD)
—’ACT563: 5962-89556
Logic Symbols
Pin Names Description
D
0–D7
Data Inputs
LE Latch Enable Input
OE
TRI-STATE Output Enable Input
O
0–O7
TRI-STATE Latch Outputs
TRI-STATE®is a registered trademark of National Semiconductor Corporation.
FACT
™
is a trademark of Fairchild Semiconductor Corporation.
DS100331-1
IEEE/IEC
DS100331-2
July 1998
54ACT563 Octal Latch with TRI-STATE Outputs
© 1998 National Semiconductor Corporation DS100331 www.national.com
Connection Diagrams
Functional Description
The ’ACT563 contains eight D-type latches with TRI-STATE
complementary outputs. When the Latch Enable (LE) input
is HIGH, data on the D
n
inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will
change state each time its D input changes. When LE is
LOW the latches store the information that was present on
the D inputs a setup time preceding the HIGH-to-LOW transition of LE. The TRI-STATE buffers are controlled by the
Output Enable (OE) input. When OE is LOW, the buffers are
in the bi-state mode. When OE is HIGH thebuffers arein the
high impedance mode but that does not interfere with entering new data into the latches.
Function Table
Inputs Internal Outputs Function
OE
LE D Q O
H X X X Z High-Z
H H L H Z High-Z
H H H L Z High-Z
H L X NC Z Latched
L H L H H Transparent
L H H L L Transparent
L L X NC NC Latched
H=HIGH Voltage Level
L=LOW Voltage Level
X=Immaterial
Z=High Impedance
NC=No Change
Logic Diagram
Pin Assignment
for DIP and Flatpak
DS100331-3
Pin Assignment
for LCC
DS100331-4
DS100331-5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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