NSC 54F823FMQB, 54F823SDMQB, 54F823LMQB Datasheet
TL/F/9596
54F/74F823 9-Bit D-Type Flip-Flop
December 1994
54F/74F823
9-Bit D-Type Flip-Flop
General Description
The ’F823 is a 9-bit buffered register. It features Clock Enable and Clear which are ideal for parity bus interfacing in
high performance microprogramming systems.
The ’F823 is functionally and pin compatible with AMD’s
Am29823.
Features
Y
TRI-STATEÉoutputs
Y
Clock Enable and Clear
Y
Direct replacement for AMD’s Am29823
Commercial Military
Package
Package Description
Number
74F823SPC N24C 24-Lead (0.300×Wide) Molded Dual-In-Line
54F823SDM (Note 2) J24F 24-Lead (0.300×Wide) Ceramic Dual-In-Line
74F823SC (Note 1) M24B 24-Lead (0.300×Wide) Molded Small Outline, JEDEC
54F823FM (Note 2) W24C 24-Lead Cerpack
54F823LM (Note 2) E28A 24-Lead Ceramic Chip Carrier, Type C
Note 1: Devices also available in 13×reel. Use suffixeSCX.
Note 2: Military grade device with environmental and burn-in processing. Use suffix
e
SDMQB, FMQB and LMQB.
Logic Symbols Connection Diagrams
TL/F/9596– 2
IEEE/IEC
TL/F/9596– 1
Pin Assignment for
DIP, SOIC and Flatpak
TL/F/9596– 3
Pin Assignment
for LCC
TL/F/9596– 4
TRI-STATEÉis a registered trademark of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation RRD-B30M75/Printed in U. S. A.
Unit Loading/Fan Out
Pin Names Description
54F/74F
U.L. Input IIH/I
IL
HIGH/LOW Output IOH/I
OL
D0–D
8
Data Inputs 1.0/1.0 20 mA/b0.6 mA
OE
Output Enable Input 1.0/1.0 20 mA/b0.6 mA
CLR
Clear 1.0/1.0 20 mA/b0.6 mA
CP Clock Input 1.0/2.0 20 mA/b1.2 mA
EN
Clock Enable 1.0/1.0 20 mA/b0.6 mA
O0–O
8
TRI-STATE Outputs 150/40 (33.3)
b
3 mA/24 mA (20 mA)
2
Functional Description
The ’F823 device consists of nine D-type edge-triggered
flip-flops. It has TRI-STATE true outputs and is organized in
broadside pinning. The buffered Clock (CP) and buffered
Output Enable (OE
) are common to all flip-flops. The flipflops will store the state of their individual D inputs that meet
the setup and hold times requirements on the LOW-to-HIGH
CP transition. With the OE
LOW the contents of the flip-
flops are available at the outputs. When the OE
is HIGH, the
outputs go to the high impedance state. Operation of the
OE
input does not affect the state of the flip-flops. In addi-
tion to the Clock and Output Enable pins, the ’F823 has
Clear (CLR
) and Clock Enable (EN) pins.
When the CLR is LOW and the OE is LOW, the outputs are
LOW. When CLR
is HIGH, data can be entered into the flip-
flops. When EN
is LOW, data on the inputs is transferred to
the outputs on the LOW to HIGH clock transition. When the
EN
is HIGH, the outputs do not change state regardless of
the data or clock inputs transitions. This device is ideal for
parity bus interfacing in high performance systems.
Function Table
Inputs Internal Output
Function
OE CLR EN CP D Q O
H H L H X NC Z Hold
H H L L X NC Z Hold
H H H X X NC Z Hold
L H H X X NC NC Hold
H L X X X H Z Clear
L L X X X H L Clear
HHLLH H Z Load
HHLLH L Z Load
LHLLL H L Data Available
LHLLH L H Data Available
L H L H X NC NC No Change in Data
L H L L X NC NC No Change in Data
LeLOW Voltage Level
H
e
HIGH Voltage Level
X
e
Immaterial
Z
e
High Impedance
L
e
LOW-to-HIGH Transition
NC
e
No Change
Logic Diagram
TL/F/9596– 5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
3
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