NSC 54F74MW8, 54F74LMQB, 54F74FMQB, 54F74DM, 54F74DC Datasheet

TL/F/9469

54F/74F74 Dual D-Type Positive Edge-Triggered Flip-Flop

December 1994

54F/74F74
Dual D-Type Positive Edge-Triggered Flip-Flop

General Description

The ’F74 is a dual D-type flip-flop with Direct Clear and Set
inputs and complementary (Q, Q

) outputs. Information at the
input is transferred to the outputs on the positive edge of
the clock pulse. Clock triggering occurs at a voltage level of
the clock pulse and is not directly related to the transition
time of the positive-going pulse. After the Clock Pulse input
threshold voltage has been passed, the Data input is locked
out and information present will not be transferred to the
outputs until the next rising edge of the Clock Pulse input.

Asynchronous Inputs:

LOW input to S

D

sets Q to HIGH level

LOW input to C

D

sets Q to LOW level
Clear and Set are independent of clock
Simultaneous LOW on C

D

and S

D

makes both Q and Q HIGH

Features

Y

Guaranteed 4000V minimum ESD protection

Commercial Military

Package

Package Description

Number

74F74PC N14A 14-Lead (0.300×Wide) Molded Dual-In-Line

54F74DM (Note 2) J14A 14-Lead Ceramic Dual-In-Line

74F74SC (Note 1) M14A 14-Lead (0.150×Wide) Molded Small Outline, JEDEC

74F74SJ (Note 1) M14D 14-Lead (0.300×Wide) Molded Small Outline, EIAJ

54F74FM (Note 2) W14B 14-Lead Cerpack

54F74LM (Note 2) E20A 20-Lead Ceramic Leadless Chip Carrier, Type C

Note 1: Devices also available in 13×reel. Use SuffixeSCX.

Note 2: Military grade device with environmental and burn-in processing. Use suffix

e

DMQB, FMQB and LMQB.

Logic Symbols

TL/F/9469– 3 TL/F/9469– 4

IEEE/IEC

TL/F/9469– 6

TRI-STATEÉis a registered trademark of National Semiconductor Corporation.

C

1995 National Semiconductor Corporation RRD-B30M75/Printed in U. S. A.

Connection Diagrams

Pin Assignment

for DIP, SOIC, and Flatpak

TL/F/9469– 1

Pin Assignment

for LCC

TL/F/9469– 2

Unit Loading/Fan Out

54F/74F

Pin Names Description

U.L. Input I

IH/IIL

HIGH/LOW Output IOH/I

OL

D1,D

2

Data Inputs 1.0/1.0 20 mA/b0.6 mA

CP

1

,CP

2

Clock Pulse Inputs (Active Rising Edge) 1.0/1.0 20 mA/b0.6 mA

C

D1,CD2

Direct Clear Inputs (Active LOW) 1.0/3.0 20 mA/b1.8 mA

SD1,S

D2

Direct Set Inputs (Active LOW) 1.0/3.0 20 mA/b1.8 mA

Q

1,Q1,Q2,Q2

Outputs 50/33.3

b

1 mA/20 mA

Truth Table

Inputs Outputs

S

D

C

D

CP D Q Q

LH XXHL
HL XXLH
LL XXHH
HHLhH L
HHLlLH
HH L XQ

0

Q

0

H (h)eHIGH Voltage Level

L (l)

e

LOW Voltage Level

X

e

Immaterial

Q

0

e

Previous Q (Q) before LOW-to-HIGH Clock Transition

Lower case letters indicate the state of the referenced input or output one
setup time prior to the LOW-to-HIGH clock transition.

Logic Diagram

TL/F/9469– 5

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

2

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.

Storage Temperature

b

65§Ctoa150§C

Ambient Temperature under Bias

b

55§Ctoa125§C

Junction Temperature under Bias

b

55§Ctoa175§C

Plastic

b

55§Ctoa150§C

V

CC

Pin Potential to

Ground Pin

b

0.5V toa7.0V

Input Voltage (Note 2)

b

0.5V toa7.0V

Input Current (Note 2)

b

30 mA toa5.0 mA

Voltage Applied to Output

in HIGH State (with V

CC

e

0V)

Standard Output

b

0.5V to V

CC

TRI-STATEÉOutput

b

0.5V toa5.5V

Current Applied to Output

in LOW State (Max) twice the rated I

OL

(mA)

ESD Last Passing Voltage (Min) 4000V

Note 1: Absolute maximum ratings are values beyond which the device may
be damaged or have its useful life impaired. Functional operation under
these conditions is not implied.

Note 2: Either voltage limit or current limit is sufficient to protect inputs.

Recommended Operating
Conditions

Free Air Ambient Temperature

Military

b

55§Ctoa125§C

Commercial 0

§

Ctoa70§C

Supply Voltage

Military

a

4.5V toa5.5V

Commercial

a

4.5V toa5.5V

DC Electrical Characteristics

Symbol Parameter

54F/74F

Units V

CC

Conditions

Min Typ Max

V

IH

Input HIGH Voltage 2.0 V Recognized as a HIGH Signal

V

IL

Input LOW Voltage 0.8 V Recognized as a LOW Signal

V

CD

Input Clamp Diode Voltage

b

1.2 V Min I

IN

eb

18 mA

V

OH

Output HIGH 54F 10% V

CC

2.5 I

OH

eb

1mA

Voltage 74F 10% V

CC

2.5 V Min I

OH

eb

1mA

74F 5% V

CC

2.7 I

OH

eb

1mA

V

OL

Output LOW 54F 10% V

CC

0.5
V Min

I

OL

e

20 mA

Voltage 74F 10% V

CC

0.5 I

OL

e

20 mA

I

IH

Input HIGH 54F 20.0

mA Max V

IN

e

2.7V

Current 74F 5.0

I

BVI

Input HIGH Current 54F 100

mA Max V

IN

e

7.0V

Breakdown Test 74F 7.0

I

CEX

Output HIGH 54F 250

mA Max V

OUT

e

V

CC

Leakage Current 74F 50

V

ID

Input Leakage

74F 4.75 V 0.0

I

ID

e

1.9 mA

Test All Other Pins Grounded

I

OD

Output Leakage

74F 3.75 mA 0.0

V

IOD

e

150 mV

Circuit Current All Other Pins Grounded

I

IL

Input LOW Current

b

0.6
mA Max

V

IN

e

0.5V (D, CP)

b

1.8 V

IN

e

0.5V (CD,SD)

I

OS

Output Short-Circuit Current

b

60

b

150 mA Max V

OUT

e

0V

I

CC

Power Supply Current 10.5 16.0 mA Max

3