NSC 54F194LMQB, 54F194FM-MIL, 54F194DMQB, 54F194DM, 54F194DC Datasheet

TL/F/9498

54F/74F194 4-Bit Bidirectional Universal Shift Register

November 1994

54F/74F194
4-Bit Bidirectional Universal Shift Register

General Description

The ’F194 is a high-speed 4-bit bidirectional universal shift
register. As a high-speed, multifunctional, sequential build­ing block, it is useful in a wide variety of applications. It may
be used in serial-serial, shift left, shift right, serial-parallel,
parallel-serial, and parallel-parallel data register transfers.
The ’F194 is similar in operation to the ’F195 universal shift
register, with added features of shift left without external
connections and hold (do nothing) modes of operation.

Features

Y

Typical shift frequency of 150 MHz

Y

Asynchronous master reset

Y

Hold (do nothing) mode

Y

Fully synchronous serial or parallel data transfers

Commercial Military

Package

Package Description

Number

74F194PC N16E 16-Lead (0.300×Wide) Molded Dual-In-Line

54F194DM (Note 2) J16A 16-Lead Ceramic Dual-In-Line

74F194SC (Note 1) M16A 16-Lead (0.150×Wide) Molded Small Outline, JEDEC

74F194SJ (Note 1) M16D 16-Lead (0.300×Wide) Molded Small Outline, EIAJ

54F194FM (Note 2) W16A 16-Lead Cerpack

54F194LM (Note 2) E20A 20-Lead Ceramic Leadless Chip Carrier, Type C

Note 1: Devices also available in 13×reel. Use suffixeSCX and SJX.

Note 2: Military grade device with environmental and burn-in processing. Use suffix

e

DMQB, FMQB and LMQB.

Logic Symbols Connection Diagrams

IEEE/IEC

TL/F/9498– 5

TL/F/9498– 3

Pin Assignment for

DIP, SOIC and Flatpak

TL/F/9498– 1

Pin Assignment

for LCC

TL/F/9498– 2

TRI-STATEÉis a registered trademark of National Semiconductor Corporation.

C

1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.

Unit Loading/Fan Out

Pin

54F/74F

Names

Description

U.L. Input I

IH/IIL

HIGH/LOW Output IOH/I

OL

S0,S1Mode Control Inputs 1.0/1.0 20 mA/b0.6 mA
P

0–P3

Parallel Data Inputs 1.0/1.0 20 mA/b0.6 mA

D

SR

Serial Data Input (Shift Right) 1.0/1.0 20 mA/b0.6 mA

D

SL

Serial Data Input (Shift Left) 1.0/1.0 20 mA/b0.6 mA
CP Clock Pulse Input (Active Rising Edge) 1.0/1.0 20 mA/b0.6 mA
MR Asynchronous Master Reset Input (Active LOW) 1.0/1.0 20 mA/b0.6 mA
Q

0–Q3

Parallel Outputs 50/33.3

b

1 mA/20 mA

Functional Description

The ’F194 contains four edge-triggered D flip-flops and the
necessary interstage logic to synchronously perform shift
right, shift left, parallel load and hold operations. Signals
applied to the Select (S

0,S1

) inputs determine the type of
operation, as shown in the Mode Select Table. Signals on
the Select, Parallel data (P

0–P3

) and Serial data (DSR,DSL)

inputs can change when the clock is in either state, provid­ed only that the recommended setup and hold times, with
respect to the clock rising edge, are observed. A LOW sig­nal on Master Reset (MR

) overrides all other inputs and

forces the outputs LOW.

Mode Select Table

Operating Inputs Outputs

Mode

MR S

1

S

0

D

SR

D

SL

P

n

Q

0

Q

1

Q

2

Q

3

Reset L X X X X X LLLL

Hold H l l X X X q

0

q

1

q

2

q

3

Shift Left H h l X l X q

1

q

2

q

3

L

Hhl X h Xq

1

q

2

q

3

H

Shift Right H l h l X X L q

0

q

1

q

2

Hlhh XXHq

0

q

1

q

2

Parallel Load H h h X X p

n

p

0

p

1

p

2

p

3

H (h)eHigh Voltage Level

L (l)

e

Low Voltage Level

p

n(qn

)eLower case letters indicate the state of the referenced input (or output) one setup time prior to the LOW-to-HIGH clock transition.

X

e

Immaterial

Logic Diagram

TL/F/9498– 4

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

2

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.

Storage Temperature

b

65§Ctoa150§C

Ambient Temperature under Bias

b

55§Ctoa125§C

Junction Temperature under Bias

b

55§Ctoa175§C

Plastic

b

55§Ctoa150§C

V

CC

Pin Potential to

Ground Pin

b

0.5V toa7.0V

Input Voltage (Note 2)

b

0.5V toa7.0V

Input Current (Note 2)

b

30 mA toa5.0 mA

Voltage Applied to Output

in HIGH State (with V

CC

e

0V)

Standard Output

b

0.5V to V

CC

TRI-STATEÉOutput

b

0.5V toa5.5V

Current Applied to Output

in LOW State (Max) twice the rated I

OL

(mA)

Note 1: Absolute maximum ratings are values beyond which the device may
be damaged or have its useful life impaired. Functional operation under
these conditions is not implied.

Note 2: Either voltage limit or current limit is sufficient to protect inputs.

Recommended Operating
Conditions

Free Air Ambient Temperature

Military

b

55§Ctoa125§C

Commercial 0

§

Ctoa70§C

Supply Voltage

Military

a

4.5V toa5.5V

Commercial

a

4.5V toa5.5V

DC Electrical Characteristics

Symbol Parameter

54F/74F

Units V

CC

Conditions

Min Typ Max

V

IH

Input HIGH Voltage 2.0 V Recognized as a HIGH Signal

V

IL

Input LOW Voltage 0.8 V Recognized as a LOW Signal

V

CD

Input Clamp Diode Voltage

b

1.2 V Min I

IN

eb

18 mA

V

OH

Output HIGH 54F 10% V

CC

2.5 I

OH

eb

1mA

Voltage 74F 10% V

CC

2.5 V Min I

OH

eb

1mA

74F 5% V

CC

2.7 I

OH

eb

1mA

V

OL

Output LOW 54F 10% V

CC

0.5
V Min

I

OL

e

20 mA

Voltage 74F 10% V

CC

0.5 I

OL

e

20 mA

I

IH

Input HIGH 54F 20.0

mA Max

V

IN

e

2.7V

Current 74F 5.0

I

BVI

Input HIGH Current 54F 100

mA Max

V

IN

e

7.0V

Breakdown Test 74F 7.0

I

CEX

Output HIGH 54F 250

mA Max

V

OUT

e

V

CC

Leakage Current 74F 50

V

ID

Input Leakage

74F 4.75 V 0.0

I

ID

e

1.9 mA

Test All Other Pins Grounded

I

OD

Output Leakage

74F 3.75 mA 0.0

V

IOD

e

150 mV

Circuit Current All Other Pins Grounded

I

IL

Input LOW Current

b

0.6 mA Max V

IN

e

0.5V

I

OS

Output Short-Circuit Current

b

60

b

150 mA Max V

OUT

e

0V

I

CC

Power Supply Current 33 46 mA Max

3