Limit
Parameter Symbol Condition MIN TYP MAX Unit
Output rise time tr Test circuit 6, load circuit 1, C
L= 15pF 3.5 7 ns
0.1V
DD to 0.9VDD
Output fall time tf Test circuit 6, load circuit 1, CL= 15pF 3.5 7 ns
0.9V
DD to 0.1VDD
Output duty cycle DUTY Test circuit 6, Ta= 25˚C, VDD=5.0V 45 55 %
load circuit 1, C
L= 15pF, f= 30MHz (*1)
Output disable delay time t
PLZ Test circuit 6, Ta= 25˚C, VDD= 5.0V 100 ns
Output enable delay time t
PZL load circuit 1, CL= 15pF 100 ns
Duty level CMOS (VDD= 4.5 to 5.5V, VSS = 0V, Ta= -20 to 80°C, unless otherwise noted)
Duty level TTL (V
DD= 4.5 to 5.5V, VSS = 0V, Ta= -20 to 80 C, unless otherwise noted)
Limit
Parameter Symbol Condition MIN TYP MAX Unit
Output rise time tr Test circuit 6, load circuit 2, C
L= 15pF 2.5 7 ns
0.4V
DD to 2.4VDD
Output fall time tf Test circuit 6, load circuit 2, CL= 15pF 2.5 7 ns
2.4V
DD to 0.4VDD
Output duty cycle DUTY Test circuit 6, Ta= 25˚C, VDD=5.0V 45 55 %
load circuit 2, C
L= 15pF, f= 30MHz (*1)
Output disable delay time t
PLZ Test circuit 6, Ta= 25˚C, VDD= 5.0V 100 ns
Output enable delay time t
PZL load circuit 2, CL= 15pF 100 ns
Note:
(*1) Determined by the lot monitor.