Novametrix 7000 User manual

Gals

Iban

Service

SaO2/ETCO2

Model

Part

This

manual

based

July

20,

Number

on

Version

Manual

Monitor

7000

1989

5007-90-P3

5.7

-

CPU

|

software.

Wallingford,

No

part

of

permission

Novametrix

Connecticut,

this

manual

of

Novametrix

Medical

may

Preliminary

Systems

U.S.A:

be

reproduced

Medical

Systems

Inc.,

06492.

Documentation

All

rights

without

Inc.

Printed

reserved.

the

written

in

U.S.A.

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Service

Manual:

Model

7000

Guarantee

Equipment is

fully

guaranteed,

from

year products right

tion,

Novametrix’ Novametrix’

except

occur

Claims portation both equipment.

Improper out release

with

to

perform

the

at

or

fuses,

during

for

company.

the

model

use,

following

Novametrix

manufactured

covering

of

date

the

stated

customer’s

obligations option,

batteries,

normal

damages

mishandling,

guarantees

guarantee

replacement

service.

during

All

correspondence

name

specific

and

from

and

Guarantee

or

distributed

materials

shipment,

service(s)

installation.

under

calibration

number,

tampering

operating

further

any

except

other

this

of

shipment

and

instructions

guarantee

by

Novametrix

and

workmanship,

certain

for

than

one

at

its

factory,

guarantee

defective

any

gasses,

must

be

concerning

the

serial

with,

or

operation

obligations.

year.

at

are

limited

parts

without

filed

promptly

the

number

will

void

Coz

Medical

disposable Novametrix

an

charge,

equipment

of

colt.

for

a

authorized

to

our

of

if

with

as

it

appears

the

equipment

this

guarantee

Systems

period

products

repairs,

of

reserves

repair

equipment,

said

defects

the

must

specify

on

Inc.,

one and

the

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or

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and

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For

Caution:

by

or

This

Novametrix retrieval means,

Systems

Federal

on

the

document

system,

without

Inc.

Novametrix’

In

Connecticut,

(U.S.A.)

order

of a physician.

contains

Medical

Systems

translated,

prior

Service

factory

1-800-243-3444

call

Telex

Facsimile

law

restricts

information

Inc.,

transcribed,

explicit

written

Department

repair

Collect

956-054

(203)

which

and

service,

(203)

284-0753

this

device

is

proprietary

may

not

be

or

transmitted,

permission

265-7701

to

from

call

toll

free

sale,

distribution,

and

the

reproduced,

in

any

form,

Novametrix

or

use

property

stored

or

by

in

any

Medical

of

a

Novametrix

5007-90-P3

20-Jul-89

Service

Manual:

Model

7000

Table

of

Contents:

10

2.0

3.0

4.0

5.0

6.0

7.0

80

Table

Theory

11

1.2

1.3

1.4

1.5

1.6

1.7

1.8

19 110

Maintenance

21

2.2

2.3

2.4

。

Operational

3.1

3.2

3.3

3.4

Calibration

4.1

4.2

4.3

44

Assembly

4.1

42

|

Specifications..

5.1

5.2

5.3

5.4 55

Connecting

6.1

6.2

Troubleshooting

7.1

Partslists...............

8.1

8.2

of

Operation

Introduction.............

Power

CPU

MainCPUBoard#2403....................

VideoController#2404............................

CO2 Saturation

Motherboard,

SaO2 CO2

Supply

Memory

Front

Sensors

Senmsor

..

#

2401.

#

2402................

End + 2418

End $ 2267, # 2268

CRT

nee

иьненииииолиизлинильзмишиниитоталили

Schedule..........

General....................

Battery Fuses Cleaning

OvervieW

Equipment Monitor

Safety

A

Calibration Adjustment

Software

Disassembly

Assembly

General........................

The Oxygen The

Optonst..........................

RS-232outputs..................

AnalogIn/Out........

20007

ASSY: ASSY:

Maintenance

and

Line

Cord

the

Model

TeSS

Required

Tests.......

Checks.....................

and

Adjustments

Procedure

Updates...

and

Disassembly

CapnostatTM

Saturation

Monitor...

External

Guide

746668865.0.000

5007-00 5007-01

инь

Procedure.

ue

Sensor

SaO2

Equipment.

06

MODEL

06

MAIN

of

Contents

..

eserse

(2409), # 2421

Assembly,

and

(2407)

..............

Front

Panel..

ити

000

rennes

7000...

оноюонеиньзиононоьовавонотвотиниивиоиоини

ee

лилии

ee

шииты,

ee

излить

scan

τος

cod

…

… …

„8

9

38 40

42 42

42 43

44

44 44

51

...52

52

dre.

Instructions.

AN

…

52

.

58

.

64

70

.

70

72

73

…

73

...........

Sensor...

iii

.............asesesesesemes

아

나

아

이

아

이

아

7000

-

SAO2

AND

ASSY,

METAL

BOX,

아

마

ETCO2

eric

라

여

라

MODEL

erezioni

ee

아

어

MONITOR

7000

마

아

마

아

.

...........................

마

이

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73

.

73

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75 76

78

이

78

81

..

81 81

5007-90-P3

Preliminary

Documentation

20-Jul-89

(Rev.P3)

Page

1

Table

of

Contents:

Service

Manual:

Model

7000

9.0

8.3 84

8.5

8.6

8.7

8.8

8.9

8.10

8.11

8.12

8.13

8.14

8.15

8.16

8.17

8.18

8.19

8.20

8.21

8.22

8.23

8.24

8.25

ASSY: ASSY:

ASSY:

ASSY: ASSY:

ASSY:

ASSY: ASSY:

ASSY:

ASSY: ASSY: ASSY: ASSY: ASSY: ASSY:

ASSY:

ASSY: ASSY: ASSY:

ASSY:

ASSY: ASSY:

ASSY:

Schematics

4977-13 2400-01 2402-01

2403-01 2404-01 2405-01

2407-01

2409-01 2418-01 2421-01

5006-01

5055-01

2267-01 2267-17 2268-01 2268-17

5088-01

5062-01

5007-06 4998-01

5013-01 4959-01 5218-01

and

Assembly

02

TOP

06

MOTHER

04

CPU

04

MAIN

04

VIDEO

05

RAM

03

FRONT

02

PIGGYBACK

04

PIGGYBACK

01

FRONT

03

POWER

04

REAR

03

Sa02

00

FNT

03

FRONT

00

FNT

06

BEZEL

00

SAO2

XX

OPTION

02

CO2

02

REGULATOR

03

SENSOR

02

SENSOR

COVER

MEMORY

SIMM

FRONT

END

INPUT

SCREENED,

BOARD

CPU

BOARD

CONTROLLER

BOARD

END

BD

BD BOARD

END

BOARD

HARNESS

PANEL

ASSY,

INPUT

DIGITAL

END

ANALOG

LIST,

HARNESS,

CAL CAL

ASSY,

END

ANALOG

MODEL,

HARNESS,

HARNESS RCPT

RECEPTACLE

ASSY,

BOARD

ASSY,

ASSEMBLY

ASSY

ASSEMBLY,

ASSY,

MODEL

BD

ASSY,

BD

MODEL

ASSY,

MODEL

ASSY,

MODEL

BD

ASSY,

(CTC),

MODEL

ASSY...........................

BD

ASSY,

ASSY

7000

MOD

7000

MODEL

ASSY,

7000..

7000...

MODEL

(CTC),

1260......

MODEL

7000

7000...

MODEL

......

7000.

........

7000 MODEL

1260... ASSY,

7000

7000...

7000..........

MODEL

MO!

7000

....

7000.

7

7000..

7000.

MODEL

7000..

Drawing6s...........cseccscssssecscecsssceeseceees

Page

2

Preliminary

Documentation

20-Jul-89

(Rev.P3)

5007-90-P3

Service

Manual:

Model

7000

Theory

of

Operation:Introduction

1.0

11

Theory

of

Introduction

The

Model

reliable rate,

infra-red A requirements, after

sent the five

along

panel

used

connections

ease

changing

backup

possible

continuous

expired

light

user

friendly

the

unit

is

There

monitor’s

The

are

Status

softkeys,

for

of

or

with

the

jacks

the

“SaO2

system,

are

disassembly.

unit

can

a

programming

will

supply

battery

Operation

7000

is a

non-invasive

measurement,

CO2,

and

respiratory

sources

once

turned

five

menu

operation.

power

Cal

damage.

and

menu

display

programmed

off.

“softkeys”

displayed,

The

switch

Cell

used

INPUT”

The

jacks

run

through

operate

from

key

approximately

monitoring,

rate.

computing

system

any

which

front

and

found

perform

this

panel

indicators,

in

calibrating

“CO2

are

different

the

system’s

any

voltage in

1

hour

portable

This

the

assists

changes

eliminates

is

Sa02/ETCO2

is

results

different

a

membrane

the

INPUT”

to

avoid

Motherboard

and

the

power

of

operation

and

display

performed

to

acquire

in

programming

are

permanently

commands

large

are

confusing

switch

ALERT

Capnostat™

for

the

connection

frequency

entry

module

with

monitor

of by the

overlay

RESET

(202

designed

oxygen

analyzing

correct

the

stored

depending

keypanels

and

sensor.

connection

of

the

via

removable

found

protection

on

in the

the

rear

to

saturation,

the

changes

parameter

unit

for

in

memory

upon

and

which

of

circuitry

contains

AUDIO

The

the

two

wrong

world

sensor.

connectors

panel.

produce

pulse

in

results.

individual

even

the

pre-

simplifies

the

buttons,

two

front

sensors

All

for

by

simply

A

battery

to

prevent

The

monitor

to

as

the

functions

nicates

lines The

tions, Manual.

with

are

CRT

Various

The

different

*

2401

*

2402

*

2403

*

2404

*

2421

*

2418

*

2267

+

2268

+

Motherboard

is

“host”.

through

external

run

through

displays

assemblies Power CPU Main Video Digital Analog Digital Analog

controlled

Consider

communication

equipment

the

by

the

Motherboard

waveforms

are

found

Supply

Memory

CPU

Board Board

Board

Controller

CO2

Front

CO2

Front

SaO2

Front

SaO2

Front

the

Motorola

host

as

the

with

each

through

where

as

selected

available,

in

the

Model

-

End

Board

End

Board

End

Board

End

Board

MC68000

“brains”

board,

the

each

runs

rear

panel

all

the

by

the

is

described

7000

are

(previously

Microprocessor

of

the

system,

the

system

connectors.

individual

user

along

thoroughly

listed

below:

2407)

2409)

it

controls

software,

All

circuit

boards

with

which

the

in

is

referred

all

internal

and

commu-

communication

are

housed.

softkey

the

Operating

func-

5007-90-P3

Preliminary

Documentation

20-Jul-89

(Rev.P3)

Page

3

¿Theory

of

Operation:Power

+ *

Supply

CRT

Front

#

2401

Assembly

Panel

Membrane

Switch

Overlay

Service

Manual:

Model

7000

1.2

Power

1.2.1

There supply. they

are

the

monitor.

or

even

it

is

used

to

within

1.22

AC

acceptable

AC/DC

The

power

AC

Plugged

*

Supply # 2401

Output

Three

charge

1260/7000

operation

level.

Both

voltages

are

four

used

to

Even

device

to

power

line

the

low

of

these

power

small

failure.

the

battery.

limits

operation

monitor

or

in

DC

mode

into

a

line

cord and

level

DC

voltages

critical

deviations

The

CRT

so

fourth

picture

While

that

the

digital

can

mode

occurs

properly

with

when

fuses

voltages (+5V,

and

from

voltage

tube

this

voltage

components

operate

wired

either

its

internal

the

monitor

AC

are

in

supplied

+15V,

analog

their

(V

BAT)

and

operate

in

battery.

line

good

condition,

as

-15V) components

nominal

need

the

fan,

may

be

properly.

AC

mode

is:

with

outputs

need

to

values

not

and

under

less

regulated

by

an

acceptable

and

from

be

closely

which

may

lead

be

as

tightly

AC

an

external

the

1260/7000

regulated

make

up

to

erroneous

regulated

operation

it

must

connection

operating

power

the

heart

mode

still

be

voltage

since

of

data

since

is

kept

to

an

+

the

rear

DC

operating

*

unit

is

operating

*

Power

*

AC

line

*

the

rear

While

operating

charged. ating operating introduced information

panel

1.2.3

The

battery

the

mode

As

level,

mode

into

occurs

indicates

DC

power

from

panel

mode

unplugged

level.

cord

and/or

power

panel

monitor

are

soon

as

or

the

is

the

monitor, when

that

AC

source

being

power

met,

the

unit

automatically

entry

occurs

from

fuse

is

lost,

or

entry

is

connected

the

AC

line

is

turned

AC

switch

when

the

are

bad.

switch

monitor

voltage

initiated.

operating

switching

power

for

ruined

is

present.

the

DC

by a deep

is

set

either:

AC

line

is

set

to

an

acceptable

operates

into

on

while

mode

between

mode

is

discharge

ON

or

the

to

OFF

in

the

not

When

is

AC

and

the

internal

(|).

AC

voltage

(0).

AC

source

AC

mode

monitor

falls

connected

an

acceptable

restored.

DC

modes.

lead

under

DC

is

below

and

the

and

the

below

to

an

AC

No

loss

of

The

AC

acid

battery.

operation,

an

acceptable

conditions

internal

the

acceptable

line

source,

line

is

once

monitor

LED

the

function

on

To

prevent

power

for

AC

battery

oper-

DC

again

the

front

the

supply

is

or

Page

4

Preliminary

Documentation

20-Jul-89

(Rev.P3)

5007-90-P3

Service

Manual:

turns

warning

provide

up

volts

Model

7000

the

power,

when

monitor

is

provided

battery

a

constant

it

is

fully

of

when

to

alert

with

voltage

charged

battery

a

quick

down

voltage

the

user

charge

charging

to

before

while

method

the

turn

falls

to

a

the

turn

off

maintaining

is

used.

off

threshold

Theory

preset

of

threshold.

threshold

stand-by

The

battery

of

10.5

Operation:Power

A

“Low

is

actually

float

current

delivers

VDC.

between

Supply

#

2401

Battery”

reached.

for

To

back-

13.8

1.24

how

users.

changing

also

normal erated

120

1.2.5

RAW from DC/BATTERY SWITCH MONITOR whether CONVERTER. the

front

SIGNAL

ER,

and

DC POWER

AC

power

well

the

The

the

required

power

by

the

-

10%

Block

The

AC

DC

is

the

+BAT

is

the

processor

The

POWER

membrane

is

turning

to

the

supplies.

ON/OFF

power

1260/7000

source

input

power

voltage

when

line

system.

=

108

VAC

diagram

INPUT/RAW fed

into

GENERATOR

SWITCH

sent

into

senses

RAW

The

as

well

ON/OFF

the

DC/BATTERY

RAW

keypanel

used

to

the

monitor

fan,.while

The

SIGNAL

depends

company

can

selector

going

conditions

For

and

operation

the

and

the

voltage

as

on

switch

from

example,

the

DC

block

+BAT

the

input

DC/BATTERY

controls

LATCH

and

control

+5V

on

the

DC-DC

output

for

the

and

not

only

can

regulate

its

primary

on

the

rear

100/120

in

excess

with

high-line

converts

GENERATOR

is

used

to

CRT/FAN

of

the

level

on

both

SWITCH

MONITOR.

the

AC

ON

is

activated

generates

outputs

off.

from

POWER

of

The

CONVERTER

the

ON

the

country

their

input

panel

VAC

to

of

10%

120

VAC

value

is

AC

and

charge

SWITCH.

DC-DC

the

should

LED

by

a

POWER

the

CRT/FAN

DC-DC

LED

on

in

which

power

given

between

power

200/240

of

the

nominal

120

+

10%

line

input

the

RAW

the

battery,

The

CONVERTER.

RAW

DC

send

RAW

also

sends

on

the

front

the

POWER

ON/OFF

CRT/FAN

SWITCH

provides

CONVERTER

the

front

the

monitor

the

varying

100,

entry

VAC.

DC/BATTERY

output

module.

Voltage

value

input,

=

132

VAC.

into

an

unregulated

and

is

of

The

and

BATTERY

DC

or

a

BATTERY

membrane

ON/OFF

RAW

SIGNAL.

and

provides

power

for

is

also

membrane

is

demands

120,

200,

A

fuse

fluctuations

are

expected

the

low

SWITCH.

also

sent

the

RAW

DC/BATTERY

lines

BATTERY

ON/OFF

keypanel.

SWITCH

The

POWER

the

DC-DC

power

the

to

+5V

used

to

keypanel.

used

but

of

240

VAC

change

due

and

line

voltage

DC

voltage.

The

output

to

the

DC/BATTERY

and

decides

to

the

DC-DC

signal

located

on

ON/OFF

CONVERT-

the

CRT

and

the

generate

also

their

by

is

to

tol-

is

RAW

LINE

to

the

tube

+15V

the

5007-90-P3

Preliminary

Documentation

20-Jul-89

(Rev.P3)

Page

5

>

Theory

of

Operation:Power

Supply

#

2401

Service

Manual:

Mode!

7000

INPUT/RAW

POWER

ON/OFF.

FRONT

1.2.6

former, integral provides

the ondary

D1

tors

following

DC

ACINPUT/RAW

The

AC

a

bridge

power

a

desired

during

to

produce

Cl,

C2,

equations,

varies

AC

D1,

ON

PANEL

INPUT/RAW

receptacle

voltage

and

according

DC

C1,

C2,

2400

C3

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6

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voltage

the

monitor

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during

voltage

Documentation

20-Jul-89

voltage

(Vrms) / .707

/.707

on

120

Hz)

the

battery

regulator

which

of

RAW

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during

it

DC

ripple

AC

integrated

uses

as a heatsink.

produces a regulated

battery

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charge

of

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(Rev.P3)

is

Hz

operation

circuit

14.5

is

VDC

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to

the

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for

a

bridge

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power

used.

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takes

at

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for a 0.7

volts per

5007-90-P3

This

as

out-

V

Service

Manual:

Modei

7000

Theory

of

Operation:Power

Supply

#

2401

battery

the

1.2.8

tion volt voltage mary

switches

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5007-90-P3

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upper

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and

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transistor

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=

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to

compensate

The

output

AC

battery

bringing

Documentation

У

+07 У

state

LED

on

and

DC-DC

is

gated

off

the

20-Jul-89

for

component

of

the

front

CONVERTER

to

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internal

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(Rev.P3)

tolerances

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input

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*1.3V

when

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CONVERTER

at

the

output

turning

to

pro-

it

Page

the

ON

of

on.

7

Theory

of

Operation:CPU

Memory # 2402

Service

Manual:

Model

7000

Transistor

switch

power

transistor VERTER. convert a 9 efficiency from nal

1.2.10

the

associated

line.

in

sideration

directly

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closure whose flip-flop

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tion

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monitor

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ofthe

width

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LATCH

power-up.

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transistor

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pulse

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CRT

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line.

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regulated

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tube

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converter

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on

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through

regulated

display

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diode

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power

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reset

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directly

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Converter

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The

positive

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OFF’

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important

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controlled

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the

edge

to

latch

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the

POWER

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battery

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an

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to

sig-

since

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its +BAT is

lost

con-

the

pulse,

first

D

of

onto

condi-

R13.

during

13

Page

8

CPU

1.3.1

age, information. per

(128K X 8)

up

low

1.3.2

inputs transition

Memory

Two

types

and

SRAM

The

byte

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and

in a similar

and

high).

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The

analog

at a time.

of the

#

2402

of

memory

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SRAM

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is

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to

Digital

to

When

LBWE

U2

Converter

digital

converter IC35

the

line.

Preliminary

devices

are

boards)

contained

is

enabled

by

the

which

CS11

Data

consists

line

lines

Documentation

used,

EPROM

for

temporary

on

two

2405-01

by

the

UBRE

LBRE

line.

of

two

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has a multiplexed

is

low

IC49

D@-D3

20-Jul-89

feed

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line,

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chips

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IC49

(Rev.P3)

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the lower are

broken

(two

chips,

one

of

data

to

5007-90-P3

stor-

up-

byte

four

going

the

Service

Manual:

Model

7000

Theory

of

Operation:Main

CPU

Board

#

2403

1.4

multiplexor

amplified

monitoring

IC35.

and

Main

1.4.1

The MHz program peripheral

the

rest

packets

bits

16

Mbytes

protocol.

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external

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by

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heart

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that

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data

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IC28C

Board # 2403

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if

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system

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system

are

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word)

of

continuous

(Read/Write)

to

and

by

in

length

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in

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via

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data

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data

transfer.

microprocessor.

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MHz

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with

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the

microprocessor

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on

the

address

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packet

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information, UDS:

ignore

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addressed

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the

lower

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bus

by

the

cycle.

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of

data

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lower

upper

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byte

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upper

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8-bits.

together:

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microprocessor

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IC30C,

UBWE

of

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data

should

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data

by

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device.

address

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contains

to

valid

information,

contains

the

that

the

data

been

the

the are gat- develop

valid

external

sent

5007-90-P3

Preliminary

Documentation

20-Jul-89

(Rev.P3)

Page

9

Theory

of

Operation:Main

CPU

Board # 2403

Service

Manual:

Model

7000

VPA an

address

CLK fer which

There These device processor reads modified

A gram

information

Read/Write it

requires

ing

that

asserts

are

to

data

Read

step

the

are

the

to

from a device,

data

Bus

from

from a peripheral.

signal

by

data

handshaking

(Valid

interrupt

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cycles.

is

three

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microprocessor,

the

device,

to

the

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ROM,

asserting

on

the

requested

CLOCK

Peripheral

address

bus.

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divided

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Bus

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occurs

needs

high

and

the

data

is

lines,

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signal

down

types

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address.

letting

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bus

cycles,

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data

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it

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device

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table

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of

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by

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the

processor rather

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|

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than

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MHz

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addressed

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of

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processor

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data

packet

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know

the

bus,

the

pro-

the

de-

DATA

S=60

nsec

1-Address

IN

Strobe

Delay = 60

nsec

Page

10

Preliminary

Documentation

20-Jul-89

(Rev.P3)

5007-90-P3

Sarvice

Manual: Model

7000

Theory

of

Operation:Main

CPU

Board

#

2403

2-Decoder 3-UBRE/LBRE 4-DTACK 5-Data

6-Memory

A

Write RAM Address on into

asserting address

or

the

Strobe

data

addressed

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Setup

Bus

wants

bus

DTACK

data

Prop

Delay = 3

Prop

Setup = 20

Time = 15

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to

send

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the

device.

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AS

A1-A23

DECODER OUTPUTS

decoder

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nsec

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when

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a

the

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|

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the

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the

bus

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and

by

the

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LBWE/UBWE

DATA

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nsec

1-Address 2-Decoder 3-UDS/LDS 4-R/W 5-LBRE/UBRE 6-LBRE/UBRE

Strobe

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from

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ΒΑΝ.

DTACK

OUT

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width = 115

ns

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5

7—>|

ei

nsec

ns

6

—

5007-90-P3

7-DTACK

setup = 130

Preliminary

ns

Documentation

20-Jul-89

(Rev.P3)

Page

11

Theory

of

Operation:Main

CPU

Board

#

2403

Service

Manual:

Model

7000

8-Data

9-CE

A

Read-Modify-Write

a

single

manner

the

sor’s the the

DTACK,

including

1.4.2

device accomplished

2

high,

C4) ously

cause

143

coordinated

similar

read

and

internal

Write

original

RESET

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the

Address

Reset

on

power

this

after

the

monitors

the

processor

Status

(system

will

Setup = 130

pulse

width = (S2 + S3.+3+5+6)-(1+2)=221

to

a

the

original

registers

The

address

processor

Strobe

up

by

IC39A

cause

power

the

processor

to

Lines

ns

Bus

cycle.

Read

In

Cycle,

address

and

logic

modified

with

the removes and

RESET)

or

if

something

,

when

4

and

system

get

lost.

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the

first

except

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unit,

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assertion

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clock

will

also

combines

part

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on

and

put

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have

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of

the

cycle,

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the

bus.

the

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the

bus

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then

the

device

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the

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The

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completed.

and

the

pro-

let

Page

12

Preliminary

Documentation

20-Jul-89

(Rev.P3)

5007-90-P3

Service

Manual:

Model

7000

Theory

of

Operation:Main

CPU

Board # 2403

1.4.5

Kilobytes

long-life keep providing

SRAM monitor this viously

1.4.6

mation volts. nels addressing

low

and

or

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5007-90-P3

Preliminary

Documentation

20-Jul-89

(Rev.P3)

Page

13

Theory

of

Operation:Main

CPU

Board

#

2403

Service

Manual:

Model

7000

brane

generated which events

1.4.9

tem configurations ding and switches

1.4.10

ties

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pin sound.

4.15

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to

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signal

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peripherals

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correct

can

be

varied

DTACK

line,

8

in

Page

14

Preliminary

Documentation

20-Jul-89

(Rev.P3)

5007-90-P3

Service

Manual:

then the

Model

that

data

7000

supersedes

as

soon

as

the

it

is

available.

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#

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parameters,

display

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is

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the

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Documentation

20-Jul-89

The

heart

detailed

modes

the

system

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long

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driv-

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and

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15

Theory

of

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to

is

68000. talk

which

Documentation

20-Jul-89

MC68000

with

appears

the

as

Host

one

of

(either

to

bus

and

specified

to

by

the

informs

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peripheral

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initiate

that

a

prepro-

as

possible.

5007-90-P3

runs

bus

2

by

and

or

write

is

the

Service

Manual:

Model

7000

Theory

of

Operation:Video

Controller

#

2404

After to

power the the DACK has

used ate the

ing

address

find

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MRD

between

cycles displayed

of

DRAW

cycles,

play

the

cycles.

character/graphic

MAD CUD

these dow

generation

into

2CLK

All

(Memory

the

ACRTC

and

indicates

in

the

pipeline

video

the

works

and

with

periods.

responsibility

In

addition

signal.

and

MA

lines

1 & 2

signals

in

the

of

the

timing

is

timing

are the

to

superimposed

the

ACRTC

control

the

basic

events

ReaD)

superimposed

HSYNC

of the to

the

line

and

the

whether

registers.

shift

MRD

to

Display

MAD

during

display

cursor

indicates

Frame

the

background

display

to

define

inhibit

Processor

and

MA

cycles.

generation

load

produce a blinking

mode.

timing

registers

ACRTC

can

be

signals

and

clock

traced

2CLK.

and

back

the

direction

Buffer

ACRTC

mode

pulse

to

lines

the

during

or

to

Frame

generation

manage

signals.

background

for

the

CRT

is

derived

to

this

clock

of

memory

window

enable

screens

load

Buffer

in

the

processor

The

area

also

system

under

depends

from

the

Dot

source.

data

flow

drawing

pulses

drawing

non-dis-

Frame

controls

uses

the

win-

on

the

Clock.

The

Dot

are

Buffer

the

values

during

cur-

pro-

5007-90-P3

Preliminary

Documentation

20-Jul-89

(Rev.P3)

-

Page

17

Theory

of

Operation:Video

Controller

#

2404

Service

Manual:

Model

7000

Clock

is

and

MCYC this

AS

has Buffer pulse

HSYNC display video DRAW 2CLK

CRT

VSYNC flicker

runs

at

used

to

latch

enable

is

(Address

been

load

is

manufactured

used

to

placed

address

generation.

is

the

line

beam

to

inhibit

to

latch

scan

line.

is

the

free

display.

20

pulses.

control

Strobe)

and

horizontal

and

to

the

vertical

DISP 1 & 2 are

video

signal

during

MHz

the

on

the

that

start

load

the

video

the

retrace

and

the

video

memory

provide

active

attributes,

by

signifies

MAD

sync

horizontal

of

the

pulses

attributes

sync

pulse.

video

periods.

2CLK

the

chip

lines.

qualification

pulse

during

runs

control

ACRTC

selects

that a valid

retrace

and

AS

is

to

indicate

should

line.

HSYNC

non-display

at

the

This

is

They

at 5 MHz.

memory

at

1/2

2CLK

enable

Frame

used

to

chip

the

occur

beginning

set

to

57

are

It

is

2CLK

chip

(2.5

load

pulses.

Buffer

latch

selects

end

of a current

to

is

also

periods

of

Hz

to

used

to

selects

MHz),

address

the

Frame

and

bring

used

and

each

present

blank

that

load

the with with

new

a

the

1.5.5

and

a then

proper

address used

is

1.5.6

MAD held

pulse

1.5.7

ADDRESS

To

make

data

Frame

puts

memory

is

to

control

placed

VIDEO

The

Video

lines

for

MEMORY

share

Buffer

out

on

the

latches

When a Frame

be

selected

one

chip

supplying

uses

higher

EPROM

IC11A

regions,

and

efficient

the

access,

the

location

valid,

the

hardware

the

lines.

ATTRIBUTE

Attributes

carry

entire

IC4

(chips

order

IC9B

LATCH

use

of

MAD

the

data.

The

for

ACRTC

Inverter

available

signal

lines

ACRTC

address

the

data

provides

latches

IC24C

and

puts

must transfer.

IC2

and

is

IC

a

used

LATCH

are

the

Attributes

raster

CHIP

and

line.

ICS

SELECT

Buffer

are

accessed

the

lower address with

each

saved

IC11C

which

access

lines

memory

in a similar

during

and

capture

is

requested,

in

pairs

8-bits

and

to

partition

chip

provide a validation

pins

are

put

out

the

be

To

signal

IC3

to

change

the

last

IC25D

the

Attributes

to

provide

the

other the pair

signal

the

video

on

address

held

signify

called

to

capture

way 2CLK combine

one

attributes,

these

for

and

saved

the

and

the

polarity

as

explained

period

HSYNC

when

memory

lines

16-bits

the

upper

available

given a unique

by

gating

MCYC,

at

different

the

first

at

this

point

Address

hold

of

HSYNC

and

they

become

chip

pair

of

data 8-bits).

memory

2CLK,

Frame

half

of

point

in

the

Strobe

the

address

AS

for

in

section

2CLK

out

for the

The

space

base

starting

Buffer

times.

the

to

cycle

(AS)

while

IC’s

2

1.4.5.

and

need

to

valid.

of

several

ACRTC,

decoder

into

RAM

and

AS

address,

During

cycle select

when

which

and

the the

is

data

and

3.

The

to

be

produce

must

with

IC8A

and

address.

(a

chip

a

Page

18

Preliminary

Documentation

20-Jul-89

(Rev.P3)

5007-90-P3

Service

Manual:

Mode!

7000

Theory

of

Operation:Video

Controller

#

2404

select

valid

IC14B

the

fers data

nals for

1.5.8

is removal).

EPROMS

tionally

fonts

64 K words

words

1.5.9

pulse

address

and

memory The

RAMs

data

from

into

the

circuitry

memory

MEMORY

The

Frame

volatile

The

are

removed

and

other

of

addressable

CLOCK

can

only

has

IC11D

at

the

proper

need

the

memory

RAM

creates

writes.

Buffer

(it

can

RAM

not

so

from

static

of

RAM

GENERATION

be

generated

been

placed

serve

to

time.

to

know

to

from

the

a

data

contains

be

read

space

volatile.

ACRTC

is

the information and

64 K words

on

clock

circuit

validated

if

the

ACRTC,

Drawing

direction

two

and

written used Data

which

memory.

if

the

MAD

ACRTC

Processor.

signal

types

of

to

as

video

placed

to

in

be

reprogrammed.

needs

of

EPROM

ACRTC

lines.

chip

select

is

executing

or

a

memory

By

which

memory:

repeatedly

memory

them

will

to

be

located

has

asserted

Gates

combining

to

used

IC24D,

pulses

a

memory

write

is

high

RAM

but

hold

not

be

The

over and in

from

and

looses

dynamic

the

AS),

the

read

cycle

the

MRD

for

memory

EPROM.

lost

unless

EPROMS

first

signifying

E,

F;

address

cycle

which

and

its

data

screen

the are

over

again.

half

of

that

IC13A,

decoder

which

will

place

DRAW

reads

RAM

and low

memory

with

displays. chip

is

used

to

There

the 2 Mega-

a

B,

C;

to

trans-

new

sig-

power

The

inten-

hold

are

The

entire

ing

pulse

by 4 through

1.5.10

Data

carefully latch of

information

ground with arrive IC9B controls 2CLK, every

To monitors nals superimpose es

or

derived

IC10

LOAD

retrieved

coordinated

the

data

and

window

the

MCYC

at

the

video

uses

AS

timing

MCYC

eighth

dot

inhibit

both

are

active.

window

IC14C superimposed video

mode

attribute

to

the

Video

ACRTC

directly

to

PULSE

from

the

is

sent

periods

shift

and

MCYC

pulses and clock

load

DRAW

The

for

load

mode.

to

channel

Pipeline.

circuitry

from

produce

the 5 MHz

GENERATOR

the

Frame

manner.

video

to

the

screens,

of

registers

to

(generated

another

into

pulses

and

timing

gates

during

HSYNC,

last

are

produced

pulses

Gates

IC25C,

regular

runs

synchronously

the

Dot

Buffer

The

load

memory

display.

two

the

signify

To

sets

ACRTC.

at

the

that

by

IC15C)

pulse

IC14 A and

cycles

turning

signal,

MRD

by

which

IC16B

loads

Clock

at

of

oscillator.

2CLK

pulse

signal.

for

display

circuitry

the

precise

set

the

load

These

proper

a

valid

display

pulses

time

address

through

generated

C.

reserved

gates

IC14A

determines

selectively

trail

the

turning

regular

and C and

for

interleaved

off

the

2CLK

The

needs

generates

moment

up

must

need

and

in

has

gate

by

IC10

for

non-display

and C off

if

on

loads

IC6C

or

which

20

MHz

to

be

sent

the

so

that

for

superimposing

be

generated

to

be

the

correct

been

placed

IC6B.

Then

to

produce

offset

IC14A

by 8 dot

work

offset

with

loads

is

the

Dot

Clock

out

to

the

control

a

signals

continuous

which

channelled

sequence.

on

IC15C

one

periods,

when

load

for

those

pulses

regular

clocks

MODE_SELECT

for

superimposed

master

is

divided

CRT

which

stream

the

back-

tim-

coincide

so

they

Flip-flop

the

bus

combines

load

pulse

gates

IC6D

two

for

load

puls-

in

a

and

sig-

the

5007-90-P3

Preliminary

Documentation

20-Jul-89

(Rev.P3)

Page

19

Theory

of

Operation:

Video

Controller

#

2404

Service

Manual:

Model

7000

1.5.11

convert

channels,

zontal (Video

offset

buffer lowing first) IC31

pair

1C27.are

HDS0-3 possible

multiplexers

shift position the the

putted

position.

address, a new ly

SCROLL

The

video

it

pixel

Pipeline)

load

The

scroll

data

dot

and

are

The

current

register

from HDS shift

to

across

into

one

scrolling

pulses

into

clock, shifts IC32.

full

and

filled

lines

16

will

IC33

display

lines

register

the

The

the

screen.

CHANNEL

shift

registers

a

serial

used

for

which

to

latch

channel

the

first

the down After

the

with

the

background

at

the

begin

and

video

above

video

9

and

indicated

output

mixers,

bits

below

starting

stream

the

(Scroll

does

the

uses

pair

frame

one

16

dot

first

of

that

IC34

fed

that

line

bit

&

PIPELINE

take

parallel

of

information

background

Channel)

not

support

video

data

regular

of

scroll

buffer

bit

at

a

clocks,

pair

are

Data

word.

screen’s

each

raster

current

to

will

into

for

and

bit

position

display

determine

be

taken

Video

the

display

that

on

10

are

frame

screens

and

off

load

pulses

channel

data

time

into

16

shifts

empty.

start

scan

from.

Mixer

bit

would

each

new

ignored

is

selected

CHANNEL

buffer

for

which

one

smooth

of

the

data

shift

leaves

the

have

A

new

dot

address

line

line.

which

New

IC17A

should

be

dot

and

display

the

CRT.

is

used

scrolling

bus.

which

registers

the

output

second

taken

load

to

determine

The

HDS

data

There

designated

for

but

it

uses

IC26

of

scroll

place,

pulse

is

placed

lines

corresponding

data

is

continually

via

the

multiplexers.

start

with

the

selected

clock

not

the

by

the

display

off

of

are

two

to

allow

the

superimposed

can

use

to

parallel

and

IC27.

IC26

(least

channel

the

second

generated

on

the

which control

output

10th

the

By

appears

one

line

shifted

bit

multiplexers

bit

would

updating

the

data

separate

smooth

either

shift

gates

of

regular

load

the

On

significant

register

shift

and

IC26

video

bit

out

IC25E,

of

the

into

For

example,

the

data

to

be

fed

the

to

move

bus

and

video

hori-

window

or

frame

each

fol-

bit

pair

register

and

attribute

of

the

and

second

this

bit

if

word,

be

out-

to

this

start

dot

smooth-

The

video

scrolling,

the

window

there

is

separate

or

window

1.5.12

active data

sent and

active

play

attribute.

VIDEO

The

video

streams

to

the

2

signals

video

format

pipeline

non-superimposed

during

control

or

both

can

its

cycle

in

screens.

CONTROL

video

output

period.

sending

CRT

depends

from

cycle.

or

inverse

sends

Video

the

ACRTC

Gates

IC16A

video

either

display

in

the

any

display

the

mixer

result

on

the

black

be

loaded

of

video

superimposed

mode

serialized

IC17A

into

gate

control

and

signal

inhibits

IC12C

on

white

with

data,

to

selectively

display

combines

IC7A.

from

the

video

select

is

regular

or

with

offset

display

the

mode.

information

video

Whether

IC12D

output

whether

chosen,

this

load

pulses load

For

enable

to

pipeline

the

mixed

which

if

the

a

regular

is

to

provide

pulses

each

or

disable

the

and

for

video

background

CRT

scroll

video

monitors

system

white

controlled

the

is

on

by a video

non-

latching

channel

during

channel

signal

DISP

not

in

black

the

gets

1

the

dis-

Paga

20

Preliminary

Documentation

20-Jul-89

(Rev.P3)

5007-90-P3

Service

Manual:

Model

7000

Theory

of

Operation:Video

Controller

#

2404

1.5.13

Test

Monitor

SIGNAL

2CLK

MCYC

HSYNC

VSYNC

DOTCLOCK

DISPI

DISP2

DISP1+2

AS

ASCINVERTED)

MRD

WE

DRAW

MAD

CS

LINES

LOAD SCROLL PIPELINE PIPELINE SCROLL VIDEO

Points

the

NAME

(INVERTED)

0-17

LOAD

LOAD VIDEO

VIDEO

OUTPUT

following

points

with

SIG.

DESCRIPTION

5

MHz

2.5

MHz

2.5

MHz

30.3

KHz

30.3

KHz

37Hz

20

MHz

BACKGROUND

WINDOW

DISPI

and

ADDRESS

2.5

MHz

2.5

MHz

VERIFY APPEAR

VERIFY

CHIP

SELECTS

2.5

MHz

1.25

MHz

1.25

MHz

VERIFY

an

oscilloscope

SCREEN

DISP2

STROBE

TRANSITIONS

to

verify

proper

TEST

POINTS

Ul1-1;

Ul-53;

U11-9;

U15-10

U11-2;

U1-56;

U15-9

U244

U25-8;

U11-10

U6-12

U25-12

U31-8;

U32-8; U26-7; U27-7; U29-7; U30-7;

U12-2 TIME

30.3

U12-13 TIME

303

U7-9

30.3

KHz

U13-1; U13-9; U13-3; U14-5; U9-10;

U9-9

U2-11;

U3-11

U16-12;

U14-1

27

OF

(018-023)

U16-13

AND

U14-9

U27-15

U30-15

U17-2

ALL

U3

AND

PIN PIN

RAMS

U6-13;

U2 INPUTS OUTPUTS

U18-U23

U38-U39

U14-13;

U26-15;

U29-15;

U17-13

U17-1;

U7-8

operation:

KHz

20 20

5007-90-P3

Preliminary

Documentation

20-Jul-89

(Rev.P3)

Page

21

Theory

of

Operation:CO2

Front

End # 2418, # 2421

Service

Manual:

Model

7000

1.6

CO:

Front

1.6.1

the

microcomputer. end ed boards

serial

red

1.6.2

as

by

1

state of bits

“Expanded

Introduction

The

interface

board

through

link

CO»

Mode 1 Operation

The

well

the

Hitachi

which

After

when

End # 2418

capnometer

between

and

connector

provide

as

well

sensor.

digital

as

the

functions

the

microcontroller

three

pins;

the

Non-multiplexed

interface

It

is

made

the

2418

P3

continuous

as

providing

DIGITAL

front

end control HD63701

reset

and

as

follows:

P20, P21,

goes

(2409), # 2421

system

the

infra-red

up

of

(previously 2409)

and

are

real

FRONT

board

timing

microcontroller.

is

reset,

and

high.

Mode”.

designed

COz

two

(2)

connected

time

CO2

all

the

necessary

END

provides

of

the

P22.

This

sets

(2407)

by

Cascadia

Sensor

boards;

analog

to

reading

BOARD

the

interface

analog

This

microcontroller

configuration

These

the

microcontroller

(Capnostat™

the

piggyback

external

to

control

#2421

interface

pins

are

Technologies

2421

(previously

board.

circuitry

the

host

signals

(previously

to

the

host

to

the

is

of

the

device

latched

to

Corporation

Sensor)

They

through

microcomputer

to

the

and

2407) are

interconnect-

P208.

Capnostat™

2407)

microprocessor

CO2

Sensor.

set

up

is

into

the

Mode 1 which

It

to

operate

determined

program

the

digital

front

These

through

infra-

system

is

operated in

Mode

by

control

is

called

is

host

two

a

the

In

Mode

P10-P17)

address Finally, port. which

opens. tions transmit

1.6.3

by 4 to by down

(Auto trol

1.6.4

ate

Motorola

lines

port 2 (P20-P24)

P22

monitors

to

the

data)

System

The

crystal

provide

512

to

further

Zero)

acquisition

Mode

In

order

in

mode 1 on

1,

port 3 (pins

functions

as

A8-A15.

is

configured

XDUCER

P20

is

configured

host

processor.

of

the

serial

clocks

frequency

the

system

establish

(on

and

the

piggyback

S/H

of

CO2

configuration

to

correctly

power

MC14053

analog

P30-P37)

address

SC1

is

configured

as a 4800

DISC, a signal

as

Pins

link.

input

clock

4800

(Sample

data.

support

write

up,

multiplexer/demultiplexer

lines

on

Hz

DTR

P23

to

the

output

Hz

clock

board

and

hardware

to

pins

and

functions

A0-A7,

port 3 is

unused

as a combination

clock

output,

which

is a handshaking

and

P24

are

HD63701

on

the

E pin

out

on

which

Hold)

P20-P22

then

will

signals

on

switch

as

the

data

and

port 4 (P40-P47)

and

I/O

P21

is

configured

is

generated

the

RXD

is

2.4576

MHz,

of the

P22.

This

4800

be

explained

which

the

pins

are

the

HD63701

P20-P22

(IC1)

bus

bits

DO-D7,

SC2

acts

and

serial

as a TTL

when

line of the

and

TXD

this

frequency

HD63701

Hz

is

later)

two

so

is

main

it

is

to

I/O

used.

to

port 1 (pins

is

configured

as a R/W

communications

level

the

CO2

serial

and

configured

On

communica-

(receive

ultimately

generate

pulses

is

data

is

also

that

divided divided divided

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to

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lines,

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signal.

input

sensor

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con-

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a

an

Page

22

Preliminary

Documentation

20-Jul-89

(Rev.P3)

5007-90-P3

Novametrix 7000 User manual

Specifications and Main Features

Frequently Asked Questions

User Manual