Nortel Networks MSC8101 User Manual
Freescale Semiconductor, Inc.
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MOTOROLA
Metrowerks
SW/HW Dept
cale Semiconductor,
Frees
MSC8101 ADS
User’s Manual
Revision B
(Revision Release 1.2)
Dragilev Lev
SW/HW Dept
Motorola Semiconductor Israel
1 Shenkar Street,
Herzlia 46120, Israel
TEL
: 972-9-522-579
email: Lev.Dragilev@motorola.com
FAX: 972-9-9562990
For More Information On This Product,
Go to: www.freescale.com
25/1/2004
Freescale Semiconductor, Inc.
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MSC8101ADS RevB User’s Manual
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CONTENTS
1•1 Introduction 11
1•2 Abbreviations’ List 11
1•3 Related Documentation 11
1•4 Specification 12
1•5 ADS Features 13
2•1 INTRODUCTION 16
2•2 UNPACKING INSTRUCTIONS 16
2•3 HARDWARE PREPARATION 16
2•3•1 Setting The Core Supply Voltage Level 18
2•3•2 Setting MODCK(1:3) For Initial PLLs’ Multiplication Factor - SW9 18
2•3•3 Setting HReset Configuration Source 18
3•1 OnCE Connection Scheme 19
3•2 Host I/F Operation 19
3•3 Stand Alone Operation 20
3•4 +5V Power Supply Connection 21
3•5 JTAG/OnCE Connector - P6 21
3•6 HOST I/F Connector - P4 22
3•7 Terminal to MSC8101ADS RS-232 Connection 23
3•8 10/100-Base-T Ethernet Port Connection 24
3•9 Flash Memory SIMM Installation 24
4•1 INTRODUCTION 26
4•2 SWITCHES 26
4•2•1 Host I/F Setting - SW1 26
4•2•2 Emulator Enable (EE) - SW2 26
4•2•3 ABORT Switch - SW3 27
4•2•4 SOFT RESET (SRESET) Switch - SW4 27
4•2•5 DATA Bus Width Setting - SW5 & SW6. 27
4•2•6 HARD RESET (HRESET) - Switch - SW7 28
4•2•7 Power-On RESET Switch (PRESET) - SW8 28
4•2•8 Configuration Switch - SW9 28
4•2•9 Boot Mode Select - SW10 29
4•2•10 Software Options Switch - SW11 30
4•3 Jumpers 30
4•3•1 JP1 - DLL Disable. 30
4•3•2 JP2 - Clock Buffer Set. 30
4•3•3 JP3 - 50 Ohm Enable. 31
4•3•4 JP4 - VPP Source Selector 31
4•3•5 JP5,JP8 - 600 Ohm Termination. 31
4•3•6 JP6,JP7 - MIC Enable. 31
4•3•7 JP9 - 5V power supply for CODEC 31
4•3•8 JS1-5 - Current Consumption Measurement 32
4•3•9 JG1-6 GND Bridges 32
4•3•10 Solder Bridges 32
4•4 LEDs 32
4•4•1 Fast Ethernet Indicator - LD1 32
4•4•2 Fast Ethernet RX Indicator - LD2 32
4•4•3 Ethernet TX Indicator - LD3 32
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4•4•4 Ethernet LINK Indicator - LD4 33
4•4•5 Fast Ethernet CLSN Indicator - LD5 33
4•4•6 ATM RX Indicator - LD6 33
4•4•7 ATM TX Indicator - LD7 33
4•4•8 TEXP Indicator - LD8 33
4•4•9 Signaling Indicator 1 - LD9 33
4•4•10 Signaling Indicator 0 - LD10 33
4•4•11 RS232 Port 2 ON - LD11 33
4•4•12 RS232 Port 1 ON - LD12 33
4•4•13 Fast Ethernet Port Initially Enabled - LD13 33
4•4•14 ATM ON - LD14 34
4•4•15 T1-1 TDM Port 1 Enable - LD15 34
4•4•16 T1-234 TDM Ports 2,3,4 Enable - LD16 34
4•4•17 CODEC Enable - LD17 34
4•4•18 RUN Indicator - LD18 34
4•4•19 Host I/F Enable - LD19 34
4•4•20 1.5V Indicator - LD20 34
4•4•21 3.3V Indicator - LD21 34
4•4•22 5V Indicator - LD22 34
4•5 The MSC8101’s Registers’ Programming 34
4•5•1 System Initialization 35
5•1 Reset & Reset - Configuration 39
5•1•1 Power- On Reset 39
5•1•2 Manual Hard Reset 39
5•1•3 Hard Reset Configuration 39
5•1•4 Manual Soft Reset 41
5•1•5 MSC8101 Internal Hard Reset Sources 42
5•2 Local Interrupter 42
5•2•1 ABORT Interrupt 42
5•2•2 ATM UNI Interrupt 42
5•2•3 QFALC Interrupt 42
5•3 Clock Generator 42
5•4 Bus Buffering 43
5•5 Chip - Select Generator 43
5•6 Synchronous DRAM Bank 44
5•6•1 SDRAM Programming 45
5•6•2 SDRAM Refresh 46
5•7 Flash Memory SIMM 46
5•7•1 Flash Programming Voltage 47
5•8 Communication Ports 48
5•8•1 ATM Port 50
5•8•2 100/10 Base - T Port 50
5•8•3 Audio CODEC 51
5•8•4 T1/E1 Ports 52
5•8•5 RS232 Ports 52
5•9 Host I/F 53
5•10 DMA off-board tool 54
5•11 Board Control & Status Register - BCSR 54
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5•11•1 BCSR0 - Board Control / Status Register 0 55
5•11•2 BCSR1 - Board Control / Status Register 1 56
5•11•3 BCSR2 - Board Control / Status Register 2 58
5•11•4 BCSR3 - Board Status Register 3 59
7•1 Power rails. 65
7•1•1 5V Bus 66
7•1•2 3.3V Bus 66
7•1•3 1.5V Bus 66
A•1 BOM 68
B•1 Interconnect Signals 76
B•1•1 MSC8101ADS’s P1- System Expansion Connector 76
B•1•2 MSC8101ADS’s P2 - CPM Expansion Connector 82
B•1•3 P3 - Altera’s In System Programming (ISP) 90
B•1•4 P4 - Host Interface Connector 90
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B•1•5 P5, P7, P8, P9, P10, P13, P14 - Logic Analyzer Connectors 92
B•1•6 P6 - JTAG/OnCE Port Connector 92
B•1•7 P12 - Ethernet Port Connector 93
B•1•8 P15,P16 - SMB Connectors 93
B•1•9 P17,P18 - Double RJ45 T1/E1 Line Connectors 93
B•1•10 P19,P21,P24 - Stereo Phone Jack Connectors 94
B•1•11 P20,P22,P23,P25 - RCA Jack Connectors 94
B•1•12 P26 - 5V Power Supply Connectors 95
B•1•13 P27A,B - RS232 Ports’ Connectors 95
C•1 Logic Equations 99
C•1•1 First Include File 99
C•1•2 Second Include file 100
C•1•3 Main File 101
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MOTOROLA MSC8101ADS RevB User’s Manual V
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VI MSC8101ADS RevB User’s Manual MOTOROLA
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LIST OF FIGURES
FIGURE 1-1 MSC8101ADS Block Diagram 15
FIGURE 2-1 MSC8101ADS Top Side Part Location diagram 17
FIGURE 3-1 Host System Debug Scheme A 19
FIGURE 3-2 Host System Debug Scheme B 20
FIGURE 3-3 Stand Alone Configuration 21
FIGURE 3-4 P26: +5V Power Connector 21
FIGURE 3-5 P6 - JTAG/OnCE Port Connector 22
FIGURE 3-6 P4 - Host I/F Connector 23
FIGURE 3-7 P27A - Upper RS-232 Serial Port Connector 24
FIGURE 3-8 P27B - Lower RS-232 Serial Port Connector 24
FIGURE 3-9 Flash Memory SIMM Insertion 25
FIGURE 4-1 Switch SW1 HOST - Description 26
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FIGURE 4-2 Switch SW2 - Description 27
FIGURE 4-3 DIP-Switch 64/32 Bit Setting 28
FIGURE 4-4 Switch SW9 MODCK - Description 29
FIGURE 4-5 Switch SW10 BOOT MODE - Description 30
FIGURE 4-6 Switch SW11 S/W Option - Description 30
FIGURE 4-7 JP4 - FLASH Programming Source Selection 31
FIGURE 4-8 JP9 - 5V CODEC Source Selection 32
FIGURE 5-1 Clock Distribution Scheme 43
FIGURE 5-2 SDRAM Connection Scheme 45
FIGURE 5-3 FLASH SIMM Connection Scheme 47
FIGURE 5-4 MSC8101 to CODEC connection. 51
FIGURE 5-5 RS232 Serial Ports’ Connector 52
FIGURE 5-6 Host Interface Diagram 53
FIGURE 7-1 ADS Power Scheme 65
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VIII MSC8101ADS RevB User’s Manual MOTOROLA
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LIST OF TABLES
TABLE 1-1. MSC8101ADS Specifications 12
TABLE 4-1. Available Clock Mode Setting 29
TABLE 4-2. JP1/JP2 Settings 31
TABLE 4-3. SIU Registers’ Programming 35
TABLE 4-4. Memory Controller Initialization for 100(50) MHz 36
TABLE 5-1 Summary Reset Configuration Schemes. 40
TABLE 5-2. Hard Reset Configuration Word 40
TABLE 5-3. MSC8101ADS Chip Select Assignments 44
TABLE 5-4. 100 MHz SDRAM Mode Register Programming 45
TABLE 5-5. Flash Memory Projected Performance Figures 46
TABLE 5-6. Ports Function Enable 49
TABLE 5-7. CS4221 Programming 51
TABLE 5-8. Host I/F Interconnect signals 54
TABLE 5-9. BCSR0 Description 55
TABLE 5-10. BCSR1 Description 56
TABLE 5-11. Peripheral’s Availability Decoding. 58
TABLE 5-12. BCSR2 Description 58
TABLE 5-13. Flash Presence Detect (7:5) Encoding 59
TABLE 5-14. Flash Presence Detect (4:1) Encoding 59
TABLE 5-15. BCSR3 Description 60
TABLE 5-16. EXTOOLI(0:3) Assignment 61
TABLE 5-17. External Tool Revision Encoding 61
TABLE 5-18. ADS Revision Encoding 61
TABLE 6-1. MSC8101ADS Memory Map 63
TABLE 7-1. Off-Board Application Maximum Current Consumption 66
TABLE A-1. MSC8101ADS Bill Of Material 68
TABLE B1-2. P1 - System Expansion - Interconnect Signals 77
TABLE B1-3. P2 - CPM Expansion - Interconnect Signals 82
TABLE B1-4. P3 - ISP Connector - Interconnect Signals 90
TABLE B1-5. P4 - Host Interface Connector - Interconnect Signals 90
TABLE B1-6. P6 - JTAG/ONCE Connector - Interconnect Signals 92
TABLE B1-7. P12 - Ethernet Port Interconnect Signals 93
TABLE B1-8. P17,P18 - T1/E1 Line Connectors Interconnect Signals 94
TABLE B1-9. P19,P21,P24 - Stereo Phone Connectors Interconnect Signals 94
TABLE B1-10. P27A Interconnect Signals 95
TABLE B1-11. P27B Interconnect Signals 95
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T-X MSC8101ADS RevB User’s Manual MOTOROLA
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General Information
1 - General Information
1•1 Introduction
This document describes the engineering specifications of the MSC8101ADS board based on the
MSC8101- first member of the family of programmable DSP based around the SC100 DSP cores.
It integrates a high-performance Star*Core SC140 DSP is four ALU DSP Core, large on-chip
memory (1/2 MByte), Communication Processor Module compatible with PowerQUICCII
(MPC8260) CPM, a very flexible system integration unit (SIU) and a 16-channel DMA engine.
This board is meant to serve as a platform for s/w and h/w development around the MSC8101 processor. Using its on-board resources and its associated debugger, a developer is able to download
code, run it, set breakpoints, display memory and registers and connect proprietary h/w via the expansion and host interface connectors, to be incorporated into a desired system with the MSC8101
processor.
This board could also be used as a demonstration tool, i.e., application s/w may be burned
its flash memory and ran in exhibitions etc.
A
into
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1•2 Abbreviations’ List
• Processor - The MSC8101
• ADS - The MSC8101ADS, the subject of this document
• SDRAM Machine - Synchronous Dynamic RAM Machine
• UPM - User Programmable Machine
• GPCM - General Purpose Chip-select Machine
• CPM - Communication Processor Module
• FCC - Fast communications controller
• SCC - Serial communications controller
• SMC - Serial management controller
• TDMA(B,C,D) - One of four A(B,C,D) time-division multiplexed interfaces
• HID16 - Host Parallel Interface 16 bit-wide
• GPL - General Purpose Line (associated with a UPM)
• EOnCE - Enhanced On-Chip Emulation (debug port)
• EE - EOnCE Event Signal
• BCSR - Board Control & Status Register
• ZIF - Zero Input Force
• BGA - Ball Grid Array
• SIMM - Single In-line Memory Module
• MII - Media Independent Interface
1•3 Related Documentation
[1] StarCore 140 Architecture Functional Specification
[2] SC140 DSP Core Reference Manual
[3] MSC8101 Reference Manual
[4] MSC8101 Hardware Specification
A. Either on or off-board.
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PMC-SIERRA 5350 Long Form Data Sheet
[5]
[6] PMC-SIERRA 5350 Errata Notice
[7] PMC-SIERA 5350 Reference Design
[8] LXT970A (by Level One) Data Sheet
[9] LXT970 Demo Board User’s Guide
General Information
1•4 Specification
The MSC8101ADS specifications are given in TABLE 1-1. "MSC8101ADS Specifications" below
TABLE 1-1. MSC8101ADS Specifications
CHARACTERISTICS SPECIFICATIONS
Power requirements (no other boards attached) +5V DC @ 2A (Typ.), 3A (Max.)
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MSC8101 Internal clock up to 300MHz @ 1.5V
PowerPC(60x) Bus Running up to 100 MHz Bus Clock Frequency.
PowerPC (60x) bus:
Total address range:
Data Bus width:
Flash memory mounted on SIMM
Synchronous DRAM 100MHz soldered (non-buffered)
Operating temperature 0
Storage temperature -25
Relative humidity 5% to 90% (non-condensing)
Dimensions:
Length
Width
PCB Thickness
4 Giga Bytes (32 address lines)
256 KBytes External (18 address lines)
64 bit without Host Interface(HID16)/32bit with HID16
8 MByte, 32 bits wide expandable to 32 MBytes.
16MBytes, organized as 2x8Megx32 bit. May be reconfiged
to 32bits wide with 8MByte (expansion to 16MByte is
optional)
O
C - 30OC (room temperature)
O
C to 85OC
9.549" (240 mm)
7.480" (190 mm)
0.063" (1.6 mm)
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General Information
1•5 ADS Features
o 64-bit MSC8101, running up to @ 100MHz external bus frequency.
o 8 MByte, 80 pin Flash SIMM reside after buffer. Support for up to 32 MByte, con-
trolled by GPCM, 5V Programmable, with Automatic Flash SIMM identification, via
BCSR.
o 16 MByte unbuffered SDRAM on PPC bus, controlled by SDRAM machine, sol-
dered directly on the board. Data bus width 64/32 bits is controlled by Jumper Array. The narrow data bus configuration is supported with 8MByte SDRAM memory
space.
o 256 KBit serial EEPROM on I2C bus.
o Board Control & Status Register - BCSR, controlling Board’s Operation on PPC
bus. Access via GPCM.
o Programmable Hard-Reset Configuration via Flash memory or Host Interface.
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Also may be forced from BCSR.
o High density (MICTOR) Logic Analyzer connectors, carrying all MSC8101 signals,
for fast logic analyzer connection.
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o 155 Mbps ATM UNI on FCC1 with Optical I/F, connected to the MSC8101 via
UTOPIA, using the PMC-SIERA 5350.
o 10/100-Base-T Port on FCC2 with T.P. I/F, MII controlled, using Level-One
LXT970.
o Four channels T1/E1 on TDMs using Infeneon Quad FALC PEB22554.
o 24-bit audio-CODEC CS4221 connected to the CPM’s TDMA1 channel with
gained stereo audio Input/Output.
o Dual RS232 port residing on SCC1 & SMC1.
o Module disable (i.e., low-power mode) option for all communication transceivers -
BCSR controlled, enabling use of communication ports, off-board via expansion
connectors.
o Dedicated MSC8101’s communication ports expansion connectors for convenient
tools’ connection, carrying also necessary bus signals, for transceivers’ M/P I/F
connection. Use is done with 2 X 128 pin DIN 41612 receptacle connectors.
o Host I/F, providing through expansion connectors or dedicated header.
o External Tools’ Identification & status read Capability, via BCSR.
o SMB-connectors for external pulse generator and clock output
o Configuration setting via DIP switches.
o Power-On Reset Push, Soft - Hard Reset Push, ABORT Push - Buttons.
o Ext. Single 5V DC Supply with Reverse / Over Voltage Protection for Power Input
and Power-On sequence.
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o On-board 1.2V - 2.2V adjustable for MSC8101 Internal Logic Operation and
3.3V±10% fixed Voltage Regulators for other circuits. May be bypassed in case of
external power supplying.
o Software Option Switch provides 8 S/W options via BCSR.
o LED’s for power supply, module enables, timer expired and SW indications.
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General Information
FIGURE 1-1 MSC8101ADS Block Diagram
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Ext CLK
14pin
To
Command
Converter
RJ45
Clock
16.4/25MHz
Reset,Config
Interrupts
MSC8101
332 pin
19x19 matrix
(3M Socket)
JTAG/OnCE
QFALC
4xT1/E1
0.8mm
3.3V
TDMA,B,C,D
ClkOut
HOST Buffers
D[32:59]
DATA Transceivers &
Address Buffers
D[0:31]
3.3V<->5V
3ns
Clock Buffer
1
7
DLLIN
SCC1,SMC1
FCC2
MIIctrl.
FCC1
EEPROM
I2C
PPC (non-buffered)
28
Control &
Status Register
3.3V<->5V
D[0:59]
Address Mux
for variable
Port Size 64/32
HOST I/F
PPC Bus (buffered)
Flash Detect
Altera
3.3V
LXT970
PM5350
SDRAM
2Megx32
Flash SIMM.
8 - 32MByte
32 - Bit
MC145583
3.3V
Magnetics
5V
Buffered Exp. System Bus
3.3V
*
2
1
36pin
Host PORT
5V
D-9RJ45-8
OPTICAL
2
3
2
S
R
T
e
s
a
B
0
0
1
/
0
1
ATM-155
16Mbyte @ 64bit
S
T
R
O
P
T
R
O
P
PORT
CPM
DIN 41612
TDMA1
SPI
cnt
CODEC
CS4221
From MIC/LINE STEREO
To STEREO AUDIO AMP
* - Additional memory part is optional
MOTOROLA MSC8101ADS RevB User’s Manual 15
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Hardware Preparation
2 - Hardware Preparation
2•1 INTRODUCTION
This chapter provides unpacking instructions, hardware preparation, and installation instructions
for the
2•2 UNPACKING INSTRUCTIONS
Unpack equipment from shipping carton. Refer to packing list and verify that all items are present.
Save packing material for storing and reshipping of equipment.
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MSC8101ADS.
NOTE
If the shipping carton is damaged upon
receipt, request carrier’s agent to be
present during unpacking and inspection of
equipment.
CAUTION
AVOID TOUCHING AREAS OF
INTEGRATED CIRCUITRY; STATIC
DISCHARGE CAN DAMAGE CIRCUITS.
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2•3 HARDWARE PREPARATION
To select the desired configuration and ensure proper operation of the MSC8101-ADS board,
changes of the DIP-Switch settings may be required before installation. The location of the
switches, indicators, DIP-Switches, and connectors is illustrated in FIGURE 2-1 "MSC8101-ADS
Top Side Part Location diagram" on page 17. The board has been factory tested and is shipped
with DIP-Switch settings as described in the following paragraphs. Parameters can be changed for
the following conditions:
• The Processor Internal Logic and PLLs Supply Level (1.6V) via potentiometer RP2.
• The Processor I/O Supply Voltage (3.3V) via potentiometer RP1 (be careful since this
power supply feeds another logic devices on the ADS and tool boards).
• The Processor Clocking:
o MODCK(1:3). Determining Core’s and CPM’s PLLs multiplication factor via the
DIP Switch SW9.
o MODCKH(4:6) for the Flash Memory Config. Word/Host Config Word (Power-On
Reset Source Dependent) or from the DIP Switch SW9 for FPGA Config. Setting
(Safe Mode).
o Clock mode update requires power up operation.
• Hard Reset Configuration Word source is selected by the DIP Switch SW9/7.
• Normal (64-bit wide) or Narrow (32-bit wide) Data bus width for Host I/F mode is
selected by the DIP Switches SW5,6.
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FIGURE 2-1 MSC8101ADS Top Side Part Location diagram
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Host SW
EE SW
64/32 Select
Boot Mode SW
Config SW
S/W Opt
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2•3•1 Setting The Core Supply Voltage Level
The internal Logic & PLL’s of the MSC8101 is powered separately through a supply bus named
1V5. The voltage level over this power bus may vary between 0.9V - 2.1V. In the lower voltage
level, the Processor will operate at lower frequency range, consuming a smaller amount of power
and vice-versa for the higher voltage level.
1V5 power level is factory set for 1.5V, but may be changed by RP2.
2•3•2 Setting MODCK(1:3) For Initial PLLs’ Multiplication Factor - SW9
During Power On reset sequence the Processor samples the three MODCK(1:3) lines which are
driven by Altera FPGA device in accordance with SW9/1-3 setting. MODCK_HI field (MODCK[4–
6]), taken from the reset configuration word, are read from the Flash memory (default value from
Altera FPGA for non-programmed Flash is read from SW9/4-6) or from Host Interface to establish
with the multiplication factors of the CPM’s and Core’s PLLs. SW9 is shown in FIGURE 4-4 "Switch
SW9 MODCK - Description" on page 29:
Some Clock Configuration can see in FIGURE 5-1 on page 43:
2•3•3 Setting HReset Configuration Source
The HReset Configuration WordA, read by the Processor while HRESET~ is asserted, may be
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taken from three sources:
1) Flash Memory SIMM.
2) Altera FPGA (Safe Mode).
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3) Host I/F.
When SW9/7 is OFF, the Hard Reset Configuration Word is taken from Altera FPGA, when it is
ON, the Hard Reset Configuration Word is taken from the Flash SIMM. If SW9/8 (Configuration)
set OFF the Processor will be configured from Host, independent of SW9/7 (Flash Configuration
Enable) position. For correct operation for Host Config. Mode Data bus width will be set to 32-bit
wide.
A. In fact 8 Hard-Reset configuration words are read by a configuration master, however only the first is rel-
evant for a single MSC8101.
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Installation Instructions
3 - Installation Instructions
The MSC8101ADS may be configured according to the required working environment as follows:
• Host Controlled Operation through OnCE Port
• Host Interface Operation through HDI16 Port
• Stand-Alone Mode
3•1 OnCE Connection Scheme
In this configuration the MSC8101ADS is controlled by a host computer via the OnCE Port, which
is a subset of the JTAG port. This configuration allows for extensive debugging using on-host debugger. The host is connected to the ADS by a Command Converter provided by a third party
(Macraigor Systems).
FIGURE 3-1 Host System Debug Scheme A
Host
Computer
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Media I/F
Command
Converter
14 Wire
Flat Cable
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5V Power Supply
3•2 Host I/F Operation
In this configuration the MSC8101ADS is using HDI16 I/F that provide 16-bit wide, full-duplex,
double-buffered, parallel port to connect directly to the data bus of a host processor. The HDI16
supports two classes of interfaces:
• Host processor/Microcontroller (MCU) connection interface
• DMA controller interface
A Host Device may be connected to the ADS via dedicated 36pin two rows header or via 128pin
DIN - connector P2.
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Installation Instructions
FIGURE 3-2 Host System Debug Scheme B
Host
Computer
Media I/F
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Command
Converter
14 Wire
Flat Cable
To JTAG/OnCE
36Wire
Flat Cable
Host
Device
5V Power Supply
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3•3 Stand Alone Operation
In this mode, the ADS is not controlled by the host via the OnCE port. It may connect to host via
one of its other ports, e.g., RS232 port, Fast Ethernet port, ATM155 port etc. Operating in this
mode requires an application program to be programmed into the board’s Flash memory.
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5V Power Supply
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Installation Instructions
FIGURE 3-3 Stand Alone Configuration
t
e
n
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T1/E1
four ch.
2
3
2
S
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Host
Computer
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cale Semiconductor,
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Audio
Stereo
3•4 +5V Power Supply Connection
The MSC8101 requires +5V DC @ 4A max, power supply for operation. Connect the +5V power
supply to connector P26 as shown below:
FIGURE 3-4 P26: +5V Power Connector
+5V
GND
GND
P26 is a 3 terminal block power connector with power plug. The plug is designed to accept 14 to
22 AWG wires. It is recommended to use 14 to 18 AWG wires. To provide solid ground, two GND
terminals are supplied. It is recommended to connect both GND wires to the common of the power
supply, while “Hot” line is connected with a single wire.
Since hardware applications may be connected
to the MSC8101ADS via the expansion connectors P1 and P2, the additional power consumption should be taken into consideration when a
power supply is connected to the MSC8101ADS.
1
2
3
NOTE
3•5 JTAG/OnCE Connector - P6
The MSC8101ADS JTAG/OnCE connector, P6, is a 14 pin, two rows, header connector with key.
The connection between the MSC8101ADS and the Command Converter is by a 14 line flat cable,
MOTOROLA MSC8101ADS RevB User’s Manual 21
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supplied with the Command Converter obtained from Macraigor Systems. FIGURE 3-5 "P6 -
JTAG/OnCE Port Connector" below shows the pin configuration of the connector.
Installation Instructions
FIGURE 3-5 P6 - JTAG/OnCE Port Connector
1
TDI
3
TDO
5
TCK
7
N.C.
RESET
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9
11
3.3V
13 14
N.C.
2
GND
4
GND
6
GND
8
KEY (NO PIN)
10
TMS
12
N.C.
TRST
3•6 HOST I/F Connector - P4
The MSC8101ADS HOST I/F connector, P4, is a 36 pin, two rows, header connector. The
connection between the MSC8101-ADS and the Host Board is by a 36 line flat cable, not shipped
with the ADS. FIGURE 3-6 "P4 - Host I/F Connector" below shows the pin configuration of the
connector.
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Installation Instructions
FIGURE 3-6 P4 - Host I/F Connector
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GND
HD0
HD2
HD4
HD6
HD8
HD10
HD12
HD14
GND
HA0
HA2
HCS1
HRRQACK
HRDRW
HRESET
3.3V
GND
1
3
5
7
9
11
13 14
15 16
17
19
21
23
25
27
29
31
35
26
28
30
32
3433
36
2
4
6
8
10
12
18
20
22
24
GND
HD1
HD3
HD5
HD7
HD9
HD11
HD13
HD15
GND
HA1
HA3
HCS2
HREQ
HDS
PORST
N.C.
GND
3•7 Terminal to MSC8101ADS RS-232 Connection
A serial (RS232) terminal or any other RS232 equipment, may be connected to both connectors
P27/A-B (Upper and Lower). This connectors are a 9 pin, female, D-type connectors, arranged in
a stacked configuration. P27A connected to SCC1 of the MSC8101 is the lower and P27B,
connected to SMC1 of the MSC8101, is the upper in the stack.
The connectors are arranged in a manner that allows for 1:1 connection with the serial port of an
IBM-AT
to DCE connection unlike it the P27B supports Null Modem connection (DTE to DTE). The
difference is shown in FIGURE 3-7 and FIGURE 3-8.
A
or compatibles, i.e. via a flat cable. The pinout which is not identical - P27A supports DTE
A. IBM-AT is a trademark of International Business Machines Inc.
MOTOROLA MSC8101ADS RevB User’s Manual 23
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Installation Instructions
FIGURE 3-7 P27A - Upper RS-232 Serial Port Connector
CD
TX 2
RX 3
DTR
GND
1
4
5
DSR6
N.C.
7
CTS
8
9N.C.
FIGURE 3-8 P27B - Lower RS-232 Serial Port Connector
N.C.
N.C.
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GND
TX 2
RX 3
1
4
5
N.C.6
N.C.
7
N.C.
8
9N.C.
3•8 10/100-Base-T Ethernet Port Connection
The 10/100-Base-T port connector - P12, is an 8-pin, 90o, receptacle RJ45 connector. The connection between the 10/100-Base-T port to the network is done by a standard cable, having two
RJ45/8 jacks on its ends.
3•9 Flash Memory SIMM Installation
To install a memory SIMM, it should be taken out of its package, put diagonally in its socket - U8
and then raised to a vertical position until the metal lock clips are locked. See FIGURE 3-9 "Flash
Memory SIMM Insertion" on page 25.
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Installation Instructions
CAUTION
The memory SIMMs have alignment nibble
near their # 1 pin. It is important to align the
memory correctly before it is twisted, otherwise damage might be inflicted to both the
memory SIMM and its socket.
FIGURE 3-9 Flash Memory SIMM Insertion
(1)
Insert
(2)
Turn
Flash
Metal Lock Clip
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SIMM
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SIMM
SIMM Socket
MOTOROLA MSC8101ADS RevB User’s Manual 25
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Operating Instructions
4 - Operating Instructions
4•1 INTRODUCTION
This chapter provides necessary information to use the MSC8101-ADS in host-controlled and
stand-alone configurations. This includes controls and indicators, memory map details, and
software initialization of the board.
4•2 SWITCHES
The MSC8101ADS has the following switches:
4•2•1 Host I/F Setting - SW1
This switch is using for manually set a Host Bus parameters. When Host Configuration is enable
the DIP switch SW1/1-3 will be connected to Data Bus through tri-state buffers and sampled by the
Processor. The SW1 factory set is all ON.
FIGURE 4-1 Switch SW1 HOST - Description
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SW1
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RESERVED
8/16BIT
DualSingleStrobe
StrobePolarity
Set to ‘0’
ON
<=
4
3
2
1
=> Set to ’1’
4•2•2 Emulator Enable (EE) - SW2
This switch controls lines EE0-EE7,EED, connected to appropriate pins of the Processor. When
Reset Configuration executed, EEs lines, involved in one, are driven by FPGA. In fact, they are
EE0, EE1, EE4 and EE5 which sampled at the rising edge of PORESET~. After configuration is
done level of all EE-signals is set by the switch SW2/1-7. Their status may be read out via
BCSR3/0-6. SW2 is factory set to all ON.
26 MSC8101ADS RevB User’s Manual MOTOROLA
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Operating Instructions
FIGURE 4-2 Switch SW2 - Description
SW2
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RESERVED
EED
EE5
EE4
EE3
EE2
EE1
EE0
Set to ‘0’
ON
<=
8
7
6
5
4
3
2
1
=> Set to ’1’
4•2•3 ABORT Switch - SW3
The ABORT switch is normally used to abort program execution, this by issuing a level 0 nonmaskable interrupt to the Processor. If the ADS is in stand alone mode, it is the responsibility of
the user to provide means of handling the interrupt, since there is no resident debugger with the
MSC8101-ADS. The ABORT switch signal is denounced, and can not be disabled by software.
4•2•4 SOFT RESET (SRESET) Switch - SW4
The SOFT reset switch SW4 performs Soft Reset to the Processor internal modules, maintaining
it’s configuration (clocks & chip-selects) and SDRAMs’ contents. The switch signal is debounced,
and it is not possible to disable it by software.
4•2•5 DATA Bus Width Setting - SW5 & SW6.
Two switches SW5 & SW6 are using together for preparing the SDRAM Memory Banks for Host
Interface Mode when HDI16 interface is provided over Data Bus lines D32-D63. They should be
set in “32bit” position when DIP-Switch SW9/8 HOST CFG set ON (PPC bus supports Host I/F)
and vice versa - “64bit” when Host I/F disable.
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Operating Instructions
FIGURE 4-3 DIP-Switch 64/32 Bit Setting
SW5 SW6
32
BIT
64
4•2•6 HARD RESET (HRESET) - Switch - SW7
HARD reset is generated when switch SW7 is pressed. When the Processor executes HARD reset
sequence, all its configuration is lost, including data stored in the SDRAMs and the Processor has
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to be re-initialized.
4•2•7 Power-On RESET Switch (PRESET) - SW8
The Power-On reset switch SW8 performs Power-On reset to the MSC8101, as if the power was
re-applied to the ADS. When the Processor is reset that way, all configuration and all data residing
in volatile memories are lost. After PORST~ signal is negated, the Processor re-acquires the
power-on reset configuration data from the Flash (Altera) or Host I/F.
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4•2•8 Configuration Switch - SW9
SW9 is a 8-switch DIP-Switch. This switch is connected over Altera device to MODCK(1:6) lines
of the Processor. The combination of the switches composing SW9, sets, during Power-On reset
sequence, the MODCK(1:6) field for the MSC8101. The switch SW9/7 establishes Configuration
Word Source. If SW9/7 is set to ON position Configuration Word will be loaded from the Flash, otherwise from Altera device (default). The Host Configuration will be chosen with SW9/8 set ON,
when SW9/8 is OFF - PPC bus has 64-bit width.
The Switch SW9 is factory set to (1 - OFF, 2 - ON, 3 - OFF, 4 - OFF (X), 5 - ON, 6 - OFF, 7,8 OFF).
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Operating Instructions
FIGURE 4-4 Switch SW9 MODCK - Description
SW9
HOST
CFG
FCFG
MODCK6
MODCK5
MODCK4
MODCK3
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MODCK2
MODCK1
Set to ‘0’
ON
<=
TABLE 4-1. Available Clock Mode Setting
MODCK-
-1 -2 -3 -4 -5 -6
0 0 1 1 1 1 57
0010019
Clock
Mode
a
b
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a. Factory setting.
b. Alternative clock mode for 100MHz bus frequency requires clock oscillator 20MHz
8
7
6
5
4
3
2
1
=> Set to ’1’
Clock In
MHz
55 137.5 55
20 200 100 300
CPM
MHz
PPC Bus
MHz
a
SC140 Core
MHz
275
Frees
4•2•9 Boot Mode Select - SW10
SW10 is a 4-switch Dip-Switch with three poles in use. This switch selects Boot Mode over Altera
FPGA on the Processor inputs EE0, EE4, EE5 during Power-On reset sequence. Setting SW10/1
(DBG) to ON brings holding EE0 at logic 1 during reset that puts the SC140 core into DEBUG
MODE. In doing so BTM’s switch position will be ignored. See TABLE 5-1 on page 40 for more
explanation. SW10 is factory set to all ON.
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Operating Instructions
FIGURE 4-5 Switch SW10 BOOT MODE - Description
SW10
RESERVED
BTM1
BOOT
BTM0
DBG
Set to ‘0’
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4•2•10 Software Options Switch - SW11
SW11 is a 4-switch Dip-Switch with three poles in use. This switch is connected over SWOPT(0:2)
lines which are available at BCSR2 via bus driver U16, S/W options may be manually selected,
according to SW11 state. SW11 is factory set to all ON.
ON
<=
4
3
2
1
=> Set to ’1’
FIGURE 4-6 Switch SW11 S/W Option - Description
SW11
RESERVED
SWOPT2
SWOPT1
SWOPT0
ON
4
3
2
1
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<=
=> Set to ’1’
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4•3 Jumpers
The MSC8101-ADS has the following jumpers:
4•3•1 JP1 - DLL Disable.
J1 set DLLDIS bit 27 in the HCW loaded from BCSR. When Jumper JP1 is open MSC8101 will be
configured without DLL. If JP3 will closed the DLL is ON. Setting of JP3 is depended on jumper
JP2 (see JP2 description). Default set is JP3-OPEN (DLL disable).
4•3•2 JP2 - Clock Buffer Set.
Jumper J2 allows to change mode of Zero-Delay Buffer JP2. When Jumper JP2 is open ZD buffer
operates in normal mode and require DLL disable setting (JP1 is open). For U44 buffer mode (internal PLL is disable) JP2 should be close. If JP2 is close MSC8101 will be configured without
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