Between MCU and system connector all data lines are protected for ESD.
HEAD_DET, Headset detection
Headset is detected by voltage level in XMIC line, it goes to MCU A/D
converter. When headset is not connected HEAD_DET DC level is same
as VL because of pull up resistor. When headset is connected DC level
drops so that if can be detected. In talk mode mic bias current is fed to
headset with HEAD_BIAS control it also increases the voltage level in
XMIC line which must be noticed.
HOOK_DET, Hook detection
Hook in headset is detected with MCU input port. HOOK_DET line goes
low when button is pushed in headset.
THF-12
System Module NH1
CTRLU – PWRU
The MCU controls the watchdog timer in the PSA. It sends a positive
pulse at approximately 1 s interval to XPWROFF pin of the PSA to keep
the power on. If CTRLU fails to deliver this pulse, the PSA will remove
power from the system. CTRLU controls also the charger on/off switching
in the PWRU block. When power off is requested CTRLU leaves PSA
watchdog without reset. After the watchdog has elapsed PSA cuts off the
supply voltages from the phone. Battery charging is controlled by CSW
line.
VBATSW, Battery voltage measurement
Battery voltage can be measured up–to 6.2V with 2.8 V reference voltage. The absolute accuracy is low because of the reference 3 % accuracy and A/D–converter +/– 8 LSB accuracy . This battery voltage measurement must be calibrated with input voltage 4.1 V. The A/D conversion result can be calculated from this equation:
A/D readout = 1024 * (VBAT* ( 0.45)) / VREF VREF=2.8 V
For example:
4.1 V results =674
ICHARG, Charger current measurement
Charger current is calculated from the voltage difference of the ends of
the shunt resistor that the charging current goes thru. The difference of
these voltages are first amplified by factor of 6.8 with op–amp to get more
accuracy to the measurement measured from different ends of charging
current shunt resistor. The absolute accuracy is low because there is very
small change in voltages with different currents . The measurement error
is minimized with calibration of the A/D–converter with 0 A and 0.5 A
charging currents.
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VCHARG , Charger voltage measurement
Charger voltage can be measured up to 16.8 V nominal. The A/D–conversion result can be calculated from equation :
A/D readout = 1024 * (VCHARG*(10/60)) / VREF
VREF=2.8 V
For example:
7.5 Vgives457
BSI, Battery size indication
The battery type can be defined with the BSI resistor value. Batteries
with different capacities and with different cell types can be defined individually, BSI is calibrated with service battery.
BTEMP, Battery temperature measurement
The battery temperature measurement is implemented with 47 kohm
NTC with N value of 4050 and 47 kohm pullup resistor. BTEMP is calibrated with service battery.
PAMS Technical Documentation
CTRLU – AUDIO
The interface between the MCU and the MASI circuit is a bidirectional
8–bit data bus with 5 address lines. MASI is connected to the same address bus as Flash and SRAM memories, MASI has own address space.
MASI has one separate control line XINT for interrupt output to MCU.
CTRLU – UIF
The keyboard is connected directly to the controller. Data lines 0–7 are
input lines and ROW0–2 are output lines. Normally all ROW lines are set
to ’0’ and if any key is pressed the KBINT line indicates it to MASI and
MASI gives an interrupt to MCU which the starts scanning the keys. The
scanning is done by driving one ROW line to 0 V at the time, then the
corresponding data line goes to 0V and phone knows which key is
pressed. ROW(0:2) lines must be in 0 V state when phone is in sleep
mode so that key pressing can be indicated.
Data to LCD Driver is written through a serial port which is used to control RTC and EEPROM too.
Keyboards and LCD lights are controlled by LIGHTS signal.
CTRLU – RX
The RX circuit power is connected on/off by the RXE signal.
Received signal strength is measured over the RSSI and intermediate fre-
quence is measured over the IF.
CTRLU – SYNT
RF temperature is measured over the RFTEMP. Frequency is controlled
by AFC signal. Synthesizer is controlled via synchronous serial bus
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SDAT/SCLK. The data is latched to the synthesizer by the positive edge
of SLE line. TX synthesizer power on/off (TXS/port P3) line is controlled
via PLL circuit.
CTRLU – TX
Transmitter output power level is measured over the TXI. TXE line activates power module. The power is controlled via TXC line which is PWM–
controlled output port.
Main Components
MCU
MCU H8/2322 is a CMOS microcontroller. The CPU is ROMless so all
memory needed is located outside the chip.
MCU operating clock (=14.7456 MHz) is generated in the MASI.
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System Module NH1
Controller Ports
Pin noSymbolDescriptionPin type
1Vcc
2–23A0–A19FLASH,MASI and RAM Address bus address
24Ass
25A20NC I
26PA5NC I
27PA6NC I
28PA7NC I
29P67NC I
30P66HOOK_DET Handset HOOK signal I
31P65HEAD_BIAS Headset microphone bias control I/O
32P64XINT interrupt signal from MASI I/O
33Vcc
34–37,
104Vss
105P17LIM I/O
106P16TXC I/O
107P15CDET I/O
108P14CSW I/O
109P13XPWROFF I/O
110P12FM–ENABLE I/O
111P11SYNTH SDAT I/O
112P10VIBRA I/O
113MD00
114MD10
115MD21
116PG0ROW2 I
117PG1NC I
118PG2RAMCS I
119PG2MASICS I
120PG2FLASHCS I
– FLASH memory 1Mx16 with 16 bit databus
– SRAM memory 16kx8 with 8 bit databus
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SIS
AT90S2343 is the SIS (subscriber identification) circuit connected to the
controller over serial bus IIC..
Table 1. SIS–prosessor signals:
PinDescription
EXTALClock input from MASI
RESETReset input
PD0IIC bus data
PD1IIC bus clock
EEPROM
There is one 16k EEPROMs in phone. EEPROM is a nonvolatile memory
into which is stored the tuning data for the phone. In addition, it contains
the short code memory locations to retain user selectable phone numbers. SDAT line is used for control LCD and RTC too.
PAMS Technical Documentation
PinDescription
SDAIIC bus data
SCLIIC bus clock
RTC
The real time clock is connected to the same IIC bus as the EEPROM.
RTC alarm interrupt is connected to the XPRWON line, so it works even if
phone is powered off. Backup power supply to the RTC is done with a
separate battery which is charged through the CHAPS.
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PWRU
Power Distribution
The main components of the Power Unit are the PSA ( Power Supply
Asic) and the CHAPS ( Charger Power Switch ).
In normal operation the baseband is powered from the phone‘s battery.
The battery consists of three Nickel Metal Hydride cells. There is also a
possibility to use batteries consisting of one Lithium–Ion cell. An external
charger is used for recharging the battery and supplying power to the
phone. The charger can be either a standard charger that can deliver
around 400 mA or a so called performance charger, which can deliver
supply current up to 850 mA.
The baseband contains components that control the power distribution to
the whole phone excluding those parts that use continuous battery supply. The battery feeds power directly to three parts of the system: PSA,
RF–power amplifier, and UI (buzzer and display and keyboard lights).
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System Module NH1
The power management circuit CHAPS provides protection against overvoltages, charger failures and pirate chargers etc. that could otherwise
cause damage to the phone.
Battery charging
Acceptable chargers are detected by the software. The absolute maximum input voltage is 30V due to the transient suppressor that is protecting the charger input. At the phone end there is no difference between a
plug–in charger or a desktop charger. The DC–jack pins and bottom connector charging pads are connected together inside the phone. The
charging block diagram is below.
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PAMS Technical Documentation
LIM
CSW
MCU
MCU
0R22
VBAT
VBATSW
VCHARGSW
PSA
GND
VCHAR
LIM
VOUT
RSENSE
PWM
10k
22p
CHAPS
VCH
GND
TRANSCEIVER
1u
50.3k
10k
10k
Figure 2. Charging block diagram
30V
2A
VIN
CHRG_CTRL
L_GND
CHARGER
NOT IN
ACP–7
Startup charging
When a charger is connected, the CHAPS is supplying a startup current
minimum of 130mA to the phone. The startup current provides initial
charging to a phone with an empty battery. The startup circuit charges
the battery until the battery voltage level reaches 3.0V (+/– 0.1V) and the
PSA releases the PURX reset signal and program execution starts.
Charging mode is changed from startup charging to PWM charging that is
controlled by the MCU software. If the battery voltage reaches 3.55V
(3.75V maximum) before the program has taken control over the charging, the startup current is switched off. The startup current is switched on
again when the battery voltage has decreased to 100mV (nominal).
Table 2. Startup characteristics
ParameterSymbolMinTypMaxUnit
VOUT Start– up mode cutoff limitVstart3.453.553.75V
VOUT Start– up mode hysteresis
NOTE: Cout = 4.7 uF
Start–up regulator output current
VOUT = 0V ... Vstart
Vstarthys80100200mV
Istart130165200mA
Battery overvoltage protection
Output overvoltage protection is used to protect phone from damage.
This function is also used to define the protection cutoff voltage for differ-
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ent battery types (Li or Ni). The power switch is immediately turned OFF if
the voltage in VOUT rises above the selected limit VLIM1 or VLIM2.
Table 3. VLIM characteristics
ParameterSymbolLIM inputMinTypMaxUnit
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System Module NH1
Output voltage cutoff limit (during transmission or Li–battery)
Output voltage cutoff limit (no
transmission or Ni–battery)
The voltage limit (VLIM1 or VLIM2) is selected by logic LOW or logic
HIGH on the CHAPS (N101) LIM– input pin. Default value is lower limit
VLIM1.
When the switch in output overvoltage situation has once turned OFF, it
stays OFF until the the battery voltage falls below VLIM1 (or VLIM2) and
PWM = LOW is detected. The switch can be turned on again by setting
PWM = HIGH.
VCH
VCH<VOUT
VOUT
VLIM1 or VLIM2
VLIM1LOW4.44.64.8V
VLIM2HIGH4.85.05.2V
t
SWITCH
PWM (32Hz)
ONOFF
Figure above: Battery overvoltage protection
Battery removal during charging
Output overvoltage protection is also needed in case the main battery is
removed when a charger connected or a charger is connected before the
battery is connected to the phone.
With a charger connected, if VOUT exceeds VLIM1 (or VLIM2), the
CHAPS turns switch OFF until the charger input has decreased below
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t
ON
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Vpor (nominal 3.0V, maximum 3.4V). The MCU software stops the charging (turn off PWM) when it detects that the battery has been removed.
The CHAPS remains in protection state as long as the PWM stays HIGH
after the output overvoltage situation has occurred.
2. VOUT exceeds limit VLIM(X), switch is turned immediately OFF
3.3VOUT falls (because no battery) , also VCH<Vpor (standard chargers full–rectified
output). When VCH > Vpor and VOUT < VLIM(X) –> switch turned on again (also PWM
is still HIGH) and VOUT again exceeds VLIM(X).
4. Software sets PWM = LOW –> CHAPS does not enter PWM mode
5. PWM low –> Startup mode, startup current flows until Vstart limit reached
6. VOUT exceeds limit Vstart, Istart is turned off
7. VCH falls below Vpor
Figure above: Battery removal during charging
Different PWM frequencies ( 1Hz and 32 Hz)
When a travel charger (2– wire charger) is used, the power switch is
turned ON and OFF by the PWM input when the PWM rate is 1Hz. When
the PWM is HIGH, the switch is ON and the output current Iout = charger
current – CHAPS supply current. When PWM is LOW, the switch is OFF
and the output current Iout = 0. To prevent the switching transients inducing noise in audio circuitry of the phone soft switching is used.
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The performance travel charger (3– wire charger) is controlled with PWM
at a frequency of 32Hz. When the PWM rate is 32Hz CHAPS keeps the
power switch continuously in the ON state.
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System Module NH1
SWITCH
ONONONOFFOFF
PWM (1Hz)
SWITCH
ON
PWM (32Hz)
Figure 3.Switch control with 2Hz and 32 Hz frequencies (in this case 50% duty cycle)
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PAMS Technical Documentation
Vibra
22k
100n
BATTERY
10n
VBAT
BSI
BTEMP
R
T
47k
NTC
GND
Figure 4.Vibra battery
TRANSCEIVER
VA
100k
10k
BTEMP
10n
MCU
10k
VIBRAPWM
Supply voltage regulators and controlling
The heart of the power distribution is the PSA asic. It includes all the voltage regulators and feeds power to the whole system. The baseband digital and analog parts are powered from the VL and VA regulators which
provide the 2.82 V baseband supply. The baseband regulators are active
when the phone is powered on.
The PSA includes also two 2.82 V regulators (VRX and VTX) providing
power to the RF section. These regulators can be controlled by the direct
control signals from the MCU. The VRX regulator can also be controlled
by the signal from the NASTA.
– VTX_ENA ( from MCU ) controls VTX regulator
– PSBS_ENA ( from NASTA ) controls VRX regulator
In addition PSA includes also functions listed bellow:
– Buffer for the M2BUS.
The buffer translates the logical input signal to open–drain output.
Table 4. M2BUS buffer truth table
InputOutput
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– Power on/off and reset logic. The Power off logic can be used as a
watchdog.
– Supply voltage monitor and automatic reset/power–off.
VBATSW is internally divided and buffered battery voltage output. The
A/D –converter input monitoring the battery voltage can be connected
here. The circuit monitors the voltage at the VBAT input and forces
the circuit to Reset if the voltage level is below allowed limit voltage,
VBATcoff–. A hysteresis is included to prevent oscillation between different states.
– Battery charger detection.
Externally divided charger voltage VCHAR goes through PSA internal
switch to VCHARSW output. The A/D –converter input monitoring the
charger voltage can be connected here.
– Automatic on–chip current limiting
– On–chip thermal shutdown, which protects PSA from overheating.
Thermal shutdown includes hysteresis in order to prevent oscillation
during the thermal protection.
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System Module NH1
Table 5. Regulators VA and VL characteristics
Parameter
Test Conditions
Output VoltageVL, VA2.73
Output current of the regulator
(all regulators enabled)
Quiescent current
VL:Iload = 0mA
Iload = 40mA
VA:Iload = 0mA
Iload = 100mA
Quiescent current
Tamb = +25_C, VBAT=3.6V
VL:Iload = 0mA
Iload = 40mA
VA:Iload = 0mA
Iload = 100mA
Quiescent current in Power–Off
VL
VA
Line regulation: VL, VA
IoutVL = 40mA,
IoutVL = 100mA,
3.25VVBAT5.2V
SymbolLimits
MinTypMax
Iout
Iout
Iq
Iq
Iqoff
VL
VL
VA
line
, VA
line
040
0100
2.82
110
130
110
130
Unit
2.90
mA
mA
200
220
200
220
6
15
20mV
A
A
A
A
A
A
A
A
A
A
V
Load regulation: VL, VA
0mAIloadVL40mA,
0mAIloadVA100mA,
3.25VVBAT5.2V
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, VA
load
load
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Table 5. Regulators VA and VL characteristics (continued)
Note 1: Voltage deviation (V) is the output voltage overshoot in tran-
sient response. Recovery time (Trec) is the time from the beginning of the
transient response to the time point when the regulator output voltage first
crosses the final stable value after overshoot.
Note 2: Settling time is defined from the time point of mode change Power–Off to Reset to the time when regulator output voltage is within 5% of
the final value.
Table 6. Regulators VRX and VTX characteristics
Parameter
Test Conditions
Output VoltageVRX, VTX2.73
Output currents of the regulators
(all regulators enabled)
Quiescent current
VRX:Iload = 0A
Iload = 50mA
VTX:Iload = 0A
Iload = 60mA
SymbolLimits
MinTypMax
Iout
Iout
Iq
VRX
VTX
0.0550
0.0260
2.82
2.90
320
360
320
360
Unit
V
mA
mA
A
A
A
A
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Table 6. Regulators VRX and VTX characteristics (continued)
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System Module NH1
Test Conditions
Quiescent current
Tamb = +25_C, VBAT=3.6V
VRX:Iload = 0A
Iload = 50mA
VTX:Iload = 0A
Iload = 60mA
Quiescent current in Power–Off
VRX
VTX
Line regulation: VRX, VTX
IoutVRX = 50mA,
IoutVTX = 60mA,
3.25VVBAT5.2V
Load regulation: VRX, VTX
50AIload
20AIload
VRX
VTX
50mA,
60mA,
3.25VVBAT5.2V
Line transient: VRX, VTX
AC=0.5Vpp square wave
Slew rate = 50 mV/s
f = 500Hz .... 2kHz
3.5VVBAT5.2V
Load transient: VRX, VTX
Iload
50A to 50mA,
VRX
IloadVTX 20A to 60mA in 10s
3.25VVBAT5.2V
SymbolParameter
Iq
Iqoff
VRX
line,
VRX
load,
VRX
linetr,
V
Trec
Note 1
VTX
VTX
VTX
line
load
linetr
UnitLimits
MinTypMax
180
195
180
195
14
17
A
A
A
A
A
A
20mV
30mV
40dB
40
20
mV
s
Current limit (VRX,VTX = 0V)
VRX
VTX
Power supply ripple rejection
3.25VVBAT5.2V
50AIload
20AIload
VRX
VTX
50mA,
60mA,
f = 10Hz.....10kHz
f = 10Hz.....50kHz
f = 10Hz.....100kHz
Settling time,
Cload=1F20%
load current 0mA
Note 1: Voltage deviation (V) is the output voltage overshoot in tran-
sient response. Recovery time (Trec) is the time from the beginning of the
transient response to the time point when the regulator output voltage first
crosses the final stable value after overshoot.
Note 2: Settling time is defined from VTX_ENA/VRX_ENA rise to the time
when regulator output voltage is within 5% of the final value.
I
lim
PSRR
VRX,VTX
ts
Note 2
75225
90270
50
40
35
100s
mA
mA
dB
dB
dB
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Operation modes
The circuit has three operational modes: Power–Off, Reset and Power–
On. The additional modes are the Protection mode and Battery disconnected (VBAT < VRth, master reset threshold). Respective conditions of
the external signals are described in Table 7.
PAMS Technical Documentation
Table 7. Operational modes
MODEPURXVRX_ENAVTX_ENAVLVAVRXVTXVBATSWVCHAR
–SW
Power–
Off
Reset
Power–
n
LOWXXZZZZZLOW
LOWLL2.8VZZZZLOW
LOWHH2.8V2.8V2.8VZZLOW
HIGH
LL2.8VZZVBATSWVCHARXPWRONX
HH2.8V2.8V2.8VVBATSWVCHARXPWRONX
NOTE: VBATSW and VCHARSW are controlled by internal VSW_ENA–
signal during power–on.
NOTE: PWRONBUFF is an inverted (and buffered) PWRONX. A logic
LOW level at PWRONX (active LOW) will force a logic HIGH level at
PWRONBUFF.
Power–Off Mode
In order to be in Power–Off mode VBAT must be above VRth.
During Power–Off mode PURX is at logical low level. VA, VL, VRX and
VTX regulators are disabled and in high–Z low output state.
PWRON-
BUFF
Entering Power–Off Mode
The PSA contains a watchdog counter that is reset by writing ”1” – ”0” sequence to input PWROFFX.
The circuit goes to Power–off mode from Power–On after delay Toff if
watchdog has not been reset during this time.
The other possibility to enter the Power–Off is from Reset, if the PSA can
not enter Power–On mode because VBATcoff+ is not reached. This
means that watchdog elapses before the microcontroller is able to produce a pulse to PWROFFX. If charger is present (VCHAR>VCHARth),
transition from Reset to Power–Off can not occur but the circuit stays in
Reset mode as long as battery has been charged above VBATcoff+.
The circuit goes to battery disconnected mode if battery voltage drops below master reset threshold (VRth–).
For testing purposes the watchdog can be disabled and reset by grounding the WD_DISX pin. In normal use it can be left floating (internal pull
up).
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Charging in Power–Off
Charging is not possible in Power–Off. Connecting a charger during Power–Off generates a rising edge on VCHAR input and the circuit enters Reset mode. Circuit stays in Reset as long as the battery is charged to the
limit VBATcoff+.
If the watchdog elapses during Power–On when charger is connected,
the circuit goes to Power–Off. Because charger detection is level sensitive, charger is detected and the circuit goes via Reset mode to Power–
On mode.
Reset Mode
The circuit goes into Reset mode from Power–Off when:
– the battery voltage is initiated (master reset) or
– logic low voltage in PWRONX is detected or
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System Module NH1
– charger voltage becomes available or
– when recovering from Protection mode
In Reset mode the VL and VA outputs are activated by an internal enable
signal. The VRX and VTX have external enable inputs VRX_ENA and
VTX_ENA. VBATSW and VCHARSW are disabled and PURX is LOW.
The circuit leaves the Reset mode after a delay Trd for Power–On if VBAT
> VBATcoff+. Watchdog is reset when Power–On mode is entered.
The circuit goes into Reset mode from Power–On when the battery voltage VBAT drops below VBATcoff–.
VBAT is monitored internally, hence if voltage VBAT drops below the
threshold (determined by internal resistors), transition from Power–on to
Reset mode is done. If VBAT doesn’t rise back above reset release limit
in time T
the Watchdog elapses and the circuit powers off.
off
To avoid PSA going to RESET mode due to fast transient, transition from
Power–On to Reset mode is not done if VBAT is below VBATcoff– for
shorter time than threshold detection delay T
dd.
The circuit leaves the Reset mode after a delay Trd if VBAT > VBATcoff+.
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VBAT
VBATcoff +
VBATcoff
VBATcoff –
PURX
PAMS Technical Documentation
T>TddT<Tdd
TddTrr
Figure 5.Threshold detection delay Tdd and PURX reaction time T
Power–On Mode
In Power–on mode all the functions are active. VBATSW and VCHARSW
outputs are activated by the internal enable signal VSW_ENA. PURX is
high in Power–On.
From Power–On mode the circuit goes to Power–Off mode after a delay
Toff (watchdog delay set by an external capacitor Cosc) if no writing sequence to PWROFFX from logical high level to low level has detected
during this time.
In Power_on mode the circuit does not react on PWRONX pulse i.e.
the circuit must be switched off by the system by not updating the watchdog writing in time Toff.
rr
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AUDIO BLOCK
The Audio Block comprises the MASI, which is is a single chip audio/signalling processor in a 64 TQFP package for NMT450 system
Main features
– Low power consumption modes
– 8 bit parallel interface with pull ups
– FM demodulator
FFSK modem features
– Full duplex 1200 baud signalling
– FSK indicator and level detector
– FII filter and gain control
– DMS facility
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System Module NH1
Audio features
– Low noise microphone amplifier
– Input for a handset microphone or an accessory
– Microphone sensitivity compensation +24/–7 dB range (5 bits)
– Compander
– RX and TX filters
– Tx hard limiter
– Tx AGC
– Transmitter compensation amplifier with +1.875/–1.875 dB range (4
bits)
– Compensation amplifier for different RX deviations with +7.5/0 dB
range (4 bits)
– Volume control amplifier with –20/+17.5 range (4 bits)
– Earphone amplifier with drive capability for ceramic earpiece
– Buffered output for a handset or an accessory
– Mute switches
– Speech scrambler and descrambler
– Hands free functions
Other features
– Driver for buzzer
– Call continue sensor
– Negative supply voltage for LCD
– Dual and single tone multifrequency generator
– IF counter
– 8 bit general purpose DAC
– Programmable output clocks with clock stop for MCU, LCD and SIS
– Two external interrupt sources
– Programmable timer
– Summing stage for voice/data, signalling and fii
– FM radio
XRESReset line from PSAPWRU
XMRDRead control signalCTRLU
XMCSChip select signalCTRLU
XMWRWrite control signalCTRLU
MA0...A45–bit address busCTRLU
MD0...D78–bit bidirectional data busCTRLU
KBINTKeyboard interruptCTRLU
MBUSINTMBUS interruptCTRLU
HEAD_BIASHeadset microphone bias enableCTRLU
IF(2nd) Intermediate frequency for MASIRX
XMICExternal audio input from accessoriesSYSTEM
MICPMicrophone (positive node)SYSTEM
MICNMicrophone (negative node)SYSTEM
FM_ENABLEFM radio enableCTRLU
FM_ANTENNAFM–Antenna connectionSYSTEM
FMCTRLFM–VCO control voltageSYNT
Table 9. AUDIO internal Signals, Outputs
Signal NameNotesTo
XEARExternal audio output to accessoriesSYSTEM
ACCDETAccessory detection signalSYSTEM
MODAudio output to synthesizerSYNT
AFCVCTCXO controlSYNT
BUZZERBuzzer signalSYSTEM
EARPEarpiece (positive node)UIF
EARNEarpiece (negative node)UIF
CLKSISClock signal for SISCTRLU
CLKLCDClock signal for LCDUIF
CLKMCUClock signal for MCUCTRLU
XINTInterrupt request to MCUCTRLU
FMLOSFM–VCO frequency sampleSYNT
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Table 10. Pin list of MASI
Pin noSymbolPin typeNotes
1VDD1PWR+2.7 ... 3.5 V Supply voltage for digital part
2XCSDIN/pdChip select signal, active state LOW, pull–down > 50 kW
3A4DIN/pu5–bit address bus, MSB, pull–up > 50 kW
4A3DIN/pu5–bit address bus, pull–up > 50 kW
5A2DIN/pu5–bit address bus, pull–up > 50 kW
6A1DIN/pu5–bit address bus, pull–up > 50 kW
7A0DIN/pu5–bit address bus, LSB, pull–up > 50 kW
8D7DIO8–bit bidirectional data bus MSB
9D6DIO8–bit bidirectional data bus
System Module NH1
THF-12
10D5DIO8–bit bidirectional data bus
11D4DIO8–bit bidirectional data bus
12D3DIO8–bit bidirectional data bus
13D2DIO8–bit bidirectional data bus
14D1DIO8–bit bidirectional data bus
15D0DIO8–bit bidirectional data bus LSB
16NMIDOUTNon maskable Interrupt request
17VSS1PWR0 V Supply voltage, ground for digital part
18XCLRDINHW reset input, active state LOW
19TMODEDIN/pdTest mode selection, pull–down > 50 kW
20TSELDIN/pdScan test selection, pull–down > 50 kW
21XINTDOUTInterrupt request to MCU, active state LOW
22EXTINT1DINExternal interrupt request, falling edge active (note: this pin
is test scan select when TMODE is high)
23EXTINT2DINExternal interrupt request, falling edge active
24VDD2PWR+2.7 ... 3.5 V Supply voltage for digital in Analog part
25IFAINIF input
26DAFAINAudio input
27FILOAOUTRxfilter output
28EXPIAINExpander/Descrambler input
29EXPOAOUTExpander/Descrambler output
30VOLIAINVolume control amplifier input
31VSA1PWR0 V Supply voltage, ground for RX Analog
(including EARAMP & EXTEAR)
32EXTEARAOUTBuffered output for handset or an accessory
33EARPAOUTEarphone driver output, positive
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Table 10. Pin list of MASI (continued)
NotesPin typeSymbolPin no
34VDA1PWR+ 2.7 ... 3.5 V Supply voltage for RX Analog
(including EARAMP & EXTEAR)
35EARNAOUTEarphone driver output, negative
36DACOAOUTDA converter output
37CALLCNTAINVoltage sensor input for battery change during call
38REFAOUTInternal analog signal ground, stabilization capasitor
39ATOUTAOUTAnalog test circuit output
40MICAINMicrophone amplifier input,
41BIMICAOUTMicrophone bias output
42CMICAINMicrophone bias current stabilizing capasitor
43EXTMICAINAudio input for a handset or an accessory
PAMS Technical Documentation
44TXPBOAOUTTransmit bandpass filter (scrambler) output
45COMIAINCompressor input
46MODAOUTtransmit path output
47ATSTAOUTAnalog test output
48VDA2PWR+ 2.7 ... 3.5 V Supply voltage for TX Analog & NVSGEN
49NSVAOUTNegative supply voltage, –7V output
50NSV2AOUTnegative supply voltage –4.66V, for external capacitor
51NSV1AOUTnegative supply voltage –2.33V, for external capacitor
52NCPPAOUTNegative supply charge pump (external) capacitor positive
53NCPNAOUTNegative supply charge pump (external) capacitor negative
54VSA2PWR0 V Supply voltage, ground for TX Analog & NVSGEN
55TOUTDOUTTest scan data output
56CLKINCIN14.7456 MHz crystal oscillator input or input for the external
clock
57CLKOUTCOUT14.7456 MHz crystal oscillator output
58VSS2PWR0 V Supply voltage,
ground for digital in Analog part & Buzzer
59BUZZAOUTBuzzer output, open collector
60CLKLCDDOUTClock signal for LCD, 230.4 kHz, 57.6 kHz or 14.4 kHz
61CLKSISDOUTClock signal for SIS processor, 3.6864MHz or 7.3728MHz
62CLKMCUDOUTClock signal for MCU, 3.6864 MHz, 7.3728 MHz or 14.7456
MHz
63XWRDIN/puWrite control signal, active state LOW, pull–up > 50 kW
64XRDDIN/pdRead control signal, active state LOW, pull–down > 50 kW
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Receive (RX) Audio Signal Path
The incoming IF signal is first FM demodulated and then connected to RX
trimmer to compensate variation of nominal frequency deviation in different systems.
Receiving Data Path
The data from RX trimmer is filtered in the modems RX filter (MODRXFIL)
which includes de–emphasis function and from there to FSK discriminator. Further from FSK discriminator data is connected to detecting filter
(DETFIL) and from there to digital phase locked loop (DPLL).
Functional blocks of data reception path:
– FM demodulator
FM demodulated audio signal is connected to the mux (RXMUX). There is
also possibility to select three other signals in the RXMUX (DTMF, rx mute
or audio test loop). Rx audio signal is 1:2 expanded and filtered in bandpass filter (RXFIL). Rx volume level is controlled with amplifier (VOL) in
the range –20 ... +17.5 dB.
If scrambling is in use signal is first expanded and then pre–emphased.
Pre–emphased signal is the descrambled and de–emphased.
Hands free control block (HFCONTR) includes a bandpass filter, window
comparator and controller for rx and tx attenuators. Rx hands free attenuator (RXATT) has selectable minimum gain from –30 ... –21 dB to max 0
dB. Rx and tx attenuation sum is always constant at hf use (–30 ... –21
dB).
There is also an extra filter (EARSFIL) for people who has a hearing defect. This filter emphases frequencies which are most sensitive in human
ear. Frequency response is +6 dB/oct from 0 to 1300 Hz and –3 dB from
1300 to 3400 Hz. This filter can be enabled by a control bit.
Normally signal is going to earphone amplifier (EAR). Signal is also available at the output of accessory buffer (ACC).
Functional blocks of audio rx path:
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– FM demodulator
– RX trimmer
– RX mux
– De–emphasis filter
– Expander
– RX filter
– De–scrambler (in conjugation with extra pre–emphasis and de–em-
phasis)
– RX automatic gain control
– Ear sensitive filter
– Volume control
– Earphone and accessory buffers
RX Trimmer
Rx trimmer range is 0 .. +7 dB and step 0.5 dB.
Antialias filter is a lowpass filter which attenuates high frequency noise
before switched filters (fiifil, modrxfil and rxfil). It’s nominal gain is 0 dB.
PAMS Technical Documentation
Mux and de–emphasis
The input source (DTMF, DAF, ALOOP or mute) selects the input source
by bits RXSRCE(1:0) in register ACRB.
De–emphasis filter’s response is –6 dB/oct between 300 ... 3000 Hz. De–
emphasis is bypassed when BPEMP in ARCA is high and gain is then 0
dB.
Expander
Expander’s ratio is 1:2 in desibel scale. It is expanding dynamic of compressed speech back to normal. Gain in expander is min –24 ... +10 dB.
Expander’s attack time is 4 ms and decay time 9 ms. It can be bypassed
by bit BPEXP in reg ACRA. Bypass gain is +3 dB. Unaffected level is 100
mV (100 mV in gives 100 mV out). Expander can be set to work as compressor by bit RXCOMPEN in reg ACRA.
RX filter
Passband of rx bandpass filter is 300 ... 3000 Hz for speech.
De–scrambler
De–scrambler splits audio band into upper and lower frequency bands,
inverts both bands and sums them for clear signal. Possible splitting frequencies are 1130 Hz, 1380 Hz, 1600 Hz and 2140 Hz. De–scrambling
can be enabled and splitting frequency selected in register ACRI.
RX automatic gain control
The function of RXAGC is to keep level of received signal below specified
reference value.
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Ear sensitive filter
Bandpasses speech spectrum taking attention to sensitivity of ear.
Volume control
Volume is controlled with an adjustable gain amplifier. Range is –20 ...
+17.5 dB and step is 2.5 dB (16 levels). Level is selected by bits VOL(3:0)
in register ACRB.
Earphone and accessory buffers
Earphone buffer is a differential amplifier. It is capable of driving 26 ohm
dynamic earphone. Earphone buffer is enabled by bit ACTEARP in register ACRB.
Accessory buffer is for accessory cable driving. It can be enabled by bit
ACTACC in register ACRB.
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System Module NH1
Transmitting paths
Transmitting data path
The data to be transmitted will be loaded into the transmitting register
TRREG. From the TRREG register the 8 bit data is transformed to serial
data which is sent to the FSK modulator (FSKMOD) and then to the summing block (SUM).
Functional blocks in data transmission path:
– Transmission controller
– Transmitters register
– FSK modulator with pre–emphasis
Transmitting audio path
Microphone signal is fed to microphone amplifier (MICAM). Signal source
is selected with a mux (TXMUX). Possible sources are own mic, accessories or DTMF generator. Tx hands free attenuator (TXATT) has selectable
minimum gain from –30 ... –21 dB. The maximum gain is 0 dB. In mictrimmer (MICTRI) signal from different sources is tuned for nominal deviation.
After the bandpass filter (TXBP) signal and 2:1 compressed in amplitude
compressor (COMPR) and then pre–emphasised +6dB/oct (PREEM).
Maximum level is set in AGC and limitter (LIM) blocks. Signal from LIM
block is lowpass filtered (TXLP) and fed to trimmer for speech maximum
deviation tuning. Output signal from TXLP is added to data and fii signals
in SUM block..
If scrambling is in use signal is first emphased and then scrambled and
de–emphased. Scrambled signal is then compressed and emphased
once more.
DTMF generator (DTMFGEN) generates dual and single tones for rx and
tx lines. Tolerance of DTMF frequencies is +–1.0 %.
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Functional blocks of audio tx path:
– Mic amplifier and mux
– Mic trimmer and bandpass filter
– Scrambler (in conjugation with extra pre–emphasis and de–emphasis)
– Compressor
– Pre–emphasis
– Soft limitter
– Tx hard limiter
– Tx lowpass filter and tx trimmer
– Summing unit, digital to analog converter and post filters
Mic amplifier and mux
Mic amplifier is a low noise amplifier. The gain is 26 dB for normal microphone use. The microphone bias current can be cut off, bit XMICBIA in
reg ACRE. Input source is selected in TXMUX1 block by bits
TXSRCE(1:0) in reg ACRA. Possible sources are MIC, EXTMIC, DTMF or
mute.
PAMS Technical Documentation
Mic trimmer and bandpass filter
Bandpass filter is 300 ... 3000 Hz for speech. It includes a trimmer (bits
MIC(4:0)) for mic/extmic level setting (nom deviation). Trimmer range is
–7 ... +24 dB and step 1 dB. The output of TXBP can be used as a sidetone signal and can be added to the earphone and accessory signals.
Scrambler
Scrambler splits audio band into upper and lower frequency bands, inverts both bands and sums them for clear signal. Possible spitting frequencies are 1130 Hz, 1380 Hz, 1600 Hz and 2140 Hz. Scrambling can
be enabled and splitting frequency selected in register ACRI.
Compressor
Compressing ratio is 2:1 in dB scale. Its purpose is to suppress speech
dynamic range to avoid RF noise at air interface between phone and
base station. Compressor has gain min –10 ... +22 dB. Dynamic area
(max gain) is limited to get smaller residual noise. Compressor’s attack
time 3 ms and decay time 14 ms. It can be bypassed by bit BYPASSC in
register ACRA. Bypass gain is –3 dB. Unaffected level is 100 mV (100 mV
in gives 100 mV out).
Pre–emphasis
Pre–emphasis filter gives +6 dB/oct emphasis between 300 ... 3000 Hz. It
is a bandpass type filter having a pole at 4000 Hz. Filter gain is +3 dB
(1kHz). Pre–emphasis is bypassed when control bit BPEMP in register
ACRF is high and gain is then 0 dB.
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Automatic Gain Control
Soft limitter is needed in order to suppress intermodulation. AGC measuring circuitry measures signal strength (rms) and signal will be attenuated
if it’s level exceeds the threshold value.
Tx hard limiter
Limiting point is at 85% (400mVrms) of max level with 1 kHz signal.
Tx lowpass filter
The corner frequency of tx lowpass filter is 3400 Hz. Amplitude attenuation is 12 dB/oct after the corner point.
Tx audio level control
Additional limiter after lowpass filter.
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System Module NH1
Tx trimmer
Trimmer is for speech max level (deviation) setting. Speech level is referred to data level. TXTRI trimmer range is +–1.75 dB and step 0.5 dB.
Summing unit and trimmer
Summing unit combines speech, data and fii signals.
TRCOM trimmer is used for modulation sensitivity compensation.
FII path
The FII signal is filtered and amplified with a 4 kHz bandpass filter (FIIFIL). The filtered FII is then fed to summing block (SUM).
Fii filtering and gain control
Fii signal at input pin IF is FM demodulated and filtered, amplified and
looped to output MOD if control bits FIIEN and TALK are set. Fii filter is a
4 kHz bandpass filter. Fii loop gain can be controlled with control bits
GCFII0...GCFII4 for temperature compensation. After reset (GCFII(4:0) =
0x0H) the gain is + 4.7 dB, which is the minimum value. Nominal gain of
the loop is + 9.5 dB, which corresponds to control bit combination
GCFII(4:0) = 0x10H. Maximum gain of + 14.0 dB is obtained when
GCFII(4:0) = 0x1FH.
Hands free system
Hands free system detects the receiving signal and controls rx tx attenuators. If the level of received signal is high, the rx attenuation is low and the
tx attenuation is high. The sum of these two attenuations is constant and
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selectable by bits SELHF(1:0) in register ACRA. Hands free operation is
activated by bit ACTHF in register ACRA.
Functional blocks of hands free system
Hands free controller
A bandpass filter of the hands free controller filters drum and noise away.
Hands free controller‘s audio signal is taken after volume control, so the
volume level changes the hf detector sensitivity.
Window comparator detects (peak detector) the received audio level and
opens rx line referred to that level. Control block is controlling RX TX attenuator gains. When the rx level is high (160 mV after volume) enough
then RXATT gain goes to it‘s maximum 0 dB value. Hands free attack
time is about 25 ms and decay time about 1200 ms. Slow attack time is
for eliminating fast noise bursts.
PAMS Technical Documentation
– Hands free controller
– Hands free attenuators
Hand free functions are active when control bit ACTHF in register ACRA
is high.
Hands free attenuators
Rx and tx lines has a hands free attenuator. Maximum attenuation is selectable from four levels: –30, –27, –24 or –21 dB. The TX (mic) gain lowest steps are bigger, because it gives a better duplex feeling to discussion.
Buzzer driver
Buzzer driver is a ’semi PWM’ signal generator. It detects rising edges of
DTMF signal and generates a pulse on every rising edge. The length of
the pulse can be set by writing length control word to the register BUZZVOL. The length is N * 2.17 us, where N is a value in BUZZVOL register.
BUZZ is an open collector (open source) type buffer. Pin BUZZ sinks current during the pulse being otherwise in high impedance state.
Value 0x0H in BUZZVOL register disables buzzer driver i.e. BUZZP =
BUZZN.
Clock divider
Page 40
Clock divider generates internal clock frequencies by dividing master
clock frequency which is created by an internal crystal oscillator and an
external 14.7456 MHz crystal. External clock signal can also be used. If
the external clock is used the oscillator output CLKOUT must not be
loaded. Buffered crystal frequency can be obtained at pin CLKMCU directly or divided by two or four. 230.4kHz / 57.6kHz /14.4 kHz clock can
be obtained at pin CLKLCD. Frequency can be selected with control bit
SELLCDC.
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Further clock signal for SIS processor is provided at pin CLKSIS and frequencies are 3.6864 MHz or 7.3728 MHz.
Call continue sensor
There is a requirement in NMT system specification that if battery voltage
disappears during a call, call must be rebuild if battery voltage comes
back in certain period of time. It should be possible even change battery
during the call. For that purpose MCU sw must be able to check if call
must be rebuild i.e. check if absense of battery voltage has been shorter
than specified time (7 seconds). Measurement is made in a way that
charge of a external capacitor is discharged via an external resistor during the absense of battery voltage. When battery voltage is back and
CPU sw runs again it reads CALLCNT bit from status register. CALLCNT
is a result of comparison of voltage at pin CALLCNT (voltage over the capacitor) with preset threshold. If the voltage at pin CALLCNT is higher
than threshold CALLCNT is low, otherwise high.
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FM radio
There is a FM radio included in the audio block for receiving 87–108 MHz
band during non–conversation mode. The radio is used from UI menus
and the headset must be connected to the phone.
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RF Module
Introduction
The RF module is designed for handportable cellular phone which operates in the NMT–450i system. The purpose of the module is to receive
and demodulate the radio frequency signal from base station and to
transmit modulated RF signal to base station.
The modulation method used in the phone is FM modulation (F3E).
PAMS Technical Documentation
Name of submodule
Rx module
Tx module
Synthesizer module
All submodules are only functional blocks, They are constructed on same
PCB and have no material codes by themselves.
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450 kHz FILTER
RSSI
IF CIRCUIT
IF
TX BUFFER
TX VCO
MOD
LOOP FILTER
PLL
SLE
SCLK
SDATA
FMLOS
AFC
TXC
VCTCXO 14.85 MHz
TXE
FMCTRL
VRX
VBAT
VTX
TXSYNE
IF AMPLIFIER
45 MHz
CRYSTAL FILTER
DIODE MIXER
RX–FILTER
LNA
UMA 1015
SYNTHESIZER IC
TANK CIRCUIT FOR 2.ND LO
PLL
LOOP FILTER
RX LO BUFFER
AGC
RX VCO
AMPLIFIER MODULE
VPLL
TX POWER CONTROL
POWER DETECTOR
ANTENNA
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DUPLEX–FILTER
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DIR_COUPLER
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Technical Specifications
Maximum ratings
The maximum battery voltage during transmission must not exceed 4.5
V. Higher battery voltages may destroy the power amplifier module.
Table 11. Maximum ratings
ParameterValue
Battery voltage 5.3 V
Regulated supply voltage 2.73 – 2.90V
Operating temperature range –25 ... +55 ° C
RX
PAMS Technical Documentation
SYNT
TX
The RX module receives and demodulates the radio frequency signal from
the base station.
The transmitter synthesizer generates a frequency modulated RF signal for
the transmitter section. The transmission frequency is generated by a
phase–locked loop (PLL). The synthesizer circuit contains VCO, synthesizer
logic and loop filter.
The receiver synthesizer generates the first injection frequency to the receiver module. The local frequency is generated by a phase–locked loop
as in transmitter synthesizer. The synthesizer circuit contains VCO, synthesizer logic and loop filter.
The Transmitter module generates and amplifies the RF signal to be transmitted to the base station.
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)
Current Consumption
In the following table the RF current consumption can be seen in different
modes.
Table 12. Control signals
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System Module NH1
control signals
RXETXSYNETXE
HHH1050
HHL85RX on, TX–syn-
HLL49RX on
LLL0.150all RF parts pow-
current con-
sumption (mA
500
Notes
power level 2
power level 0, 1
thesizer on
ered down
The current consumption of different RF parts can be seen in the following block diagram.
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Current Consumption
VRX
12 mA
2 mA
2 mA
PAMS Technical Documentation
LNA
TXE
IF amplifier
IF circuit
Battery
Battery
3.6 V
regulator
2.7 V
VPLL
regulator
2.7 V
7
LO buffer
15 mA
RX–VCO
10 mA
Synthesizer IC
4 mA
VCTCXO
TXSYNE
15 mA
TX–VCO
Page 46
20 mA
regulator
2.7 V
20 mA
VTX
3 mA
950 mA
Nokia Mobile Phones Ltd.
TX buffer
TX power
control
PA
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System Module NH1
Connections
Connections to Baseband sub–module
Table 13. Connections to BB module
Signal NameTypeFunction
AFCAnalog inThe reference oscillator frequency adjust.
FMCTRLAnalog.outFM radio VCO control
FMLOSAnalog.inFM radio VCO signal for PLL
IFAnalog out2nd IF signal
MODAnalog inModulation signal for transmitter (Audio + data)
RFTEMPAnalog outRF temperature, which is determined by NTC resistor.
THF-12
RSSIAnalog outReceived signal strength indicator. Voltage measurement.
SCLKDigital inSerial clock for synthesizer. Active state: Rising edge
SDATADigital inSerial data for synthesizer. Active state: High
SLEDigital inSynthesizer enable. Active state: High
TXCPWM inTransmitter power control
TXEDigital inTransmitter on/off. High when on.
TXSYNEAnalog outTX synthesizer power control
VBATPowerBattery voltage
VPLLPowerRegulated voltage for synthesizer IC
VRXPowerRegulated voltage for receiver & receiver synth
The phone is fitted with a retractable antenna. The electrical length of antenna is 1/4 wave length.
Receiver
The receiver is a dual–conversion superheterodyne using two intermediate frequencies, 45 MHz and 450 kHz.
PAMS Technical Documentation
Table 26. VBAT voltage
The RF signal from the duplexer RX port is applied to the low noise RF
amplifier. The amplifier comprises the transistor V310. The amplifier
stage input matching comprises C301, C302 and L301. R301 and R311
are included for biasing. The output matching comprises L311, C312
and C313.
The AGC circuit comprises V320 and V321. The AGC–off current is adjusted by R323. The AGC–on current is determined by R323 and R324.
Next the signal is filtered with Z330. After the filter the signal is fed to a
single balanced diode mixer, comprising Z331, Z332, Z350 and V330.
After the mixer the 45 MHz IF signal is filtered with the crystal filter Z340.
Matching between the mixer and the filter comprises L340, R340, C340
and C341. Next the IF signal is amplified by V360. The input matching
comprises R341. The biasing comprises R360, R361 and R363. Capacitors C360 and C361 are included for RF bypassing.
The second mixer, IF amplifier and quadrature detector are all integrated
in the circuit N370. The second LO frequency, 44.55 MHz, is the third
harmonic of the VCTCXO frequency. The LO signal tank circuit comprises C372 and L371. After the mixer the 450kHz IF signal is filtered
with the ceramic filter Z370.
The RSSI and 2nd IF signal (450 kHz) are fed to the audio/logic unit.
RX Synthesizer
The first injection frequency is generated by a digital phase locked loop
(PLL). The PLL comprises a VCO, a loop filter and a PLL IC which includes reference and main dividers. The output frequency of the loop
(LO) is obtained from a voltage–controlled oscillator (VCO) G520. Output
level of VCO is 0 dBm +/– 2 dB. The VCO output signal is amplified by
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transistor V350 and fed to the receiver mixer via Z350. A portion of output signal is fed back to the synthesizer.
The overall divisor of the chain is selected according to the desired channel.
The internal dividers of N400 are programmed with 17 bits, which are
transferred serially on the SDATA (synthesizer data) line from the processor into an internal shift register also located in N400. Data transfer is
timed with SCLK clock pulses.
The divided frequency is compared with a highly stable reference frequency from VCTCXO by a phase comparator in the PLL circuit (N400).
The phase comparator controls the VCO frequency by means of a DC
voltage through the loop filter so as to keep the divided frequency applied
to the phase comparator equal to the fixed reference frequency.
The reference frequency is 12.5 kHz. This reference frequency is obtained from voltage controlled temperature compensated crystal oscillator
(VCTCXO). The oscillator frequency is 14.85 MHz. The VCTCXO frequency is divided by 1188.
THF-12
System Module NH1
RX loop filter
The Phase comparator output is pin 3. If the VCO frequency is too high,
the output goes low and discharge integrator capacitor C421. After this,
the DC control voltage and the VCO frequency will decrease.
If the VCO frequency is too low, the output goes high and charge the integrator capacitor C421. Thereafter the DC control voltage and the VCO
frequency will go up.
Output pulses from the phase detector are fed to the loop filter. The function of the integrator is to convert positive and negative pulses to DC voltage. The remaining ripple and AC components are filtered in a three
stage lowpass filter.
TX Synthesizer
The transmitter synthesizer generates a frequency modulated transmitter
signal to the transmitter section. The injection frequency for transmitter is
generated by a digital phase locked loop (PLL). The modulated TX frequency is generated in TX–VCO (G430). The output level of the VCO is
0 dBm +/– 2 dB. After the VCO the TX signal is amplified in the TX buffer
V440 before power amplifier module. The gain in the TX buffer is about 8
dB.
If there is a problem with transmitter PA output power, adaptive gain control of TX buffer will increase the injection signal level to transmitter PA. If
the PA control voltage rises over 2.3 V, it is assumed that PA is not capable to obtain 750 mW output power anymore. In that case the network of
the double operation amplifier N401 will change the V440 biasing point to
maximize TX output power.
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TX Loop Filter
Output pulses from the phase detector N400 pin 17 are supplied to the
loop filter. The integrator, which constitutes R433, C435 and C436, converts positive and negative pulses to DC voltage. The remaining ripple is
filtered in a three stage low–pass filter.
Transmitter
The transmitter constitutes a power amplifier module (N611). The modulated RF signal from the TX synthesizer is applied to the 50 ohm input of
the transmitter module. The power level is controlled by a voltage which
is supplied to pin 16 of the PA module. A voltage proportional to the output power is rectified from a coupler strip by the DC–biased Schottky
diode V634. This rectified voltage is fed to a differential amplifier which
comprises transistors V631 and V632 .
PAMS Technical Documentation
The reference voltage to control the PA module is filtered from the PWM
signal TXC to DC voltage by a two stage lowpass filter. The differential
amplifier adjusts the collector voltage of the transistor V630 so that the
reference voltage and the voltage proportional to the output power are
equal. The transmitter is switched on when TXE goes high (logic 1),
which enables the transmitter power control circuit by transistor V611.
When the transmitter is inactive (TXE low) the RF level from the transmitter is reduced below –57 dBm.
RF Characteristics
Ambient temperature
Line SymbolMinimumTypical /
Nominal
Operating temperature–25+55°C
MaximumUnit / Notes
Duplexer
TransmitterReceiver
Frequency453...457.475 MHz463...467.475 MHz
Insertion loss max2.8 dB6 dB
Ripple at BW max1.5 dB1.5 dB
Termination impedance50 W50 W
Permissible input power2.5 W
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RX submodule
Table 27. RX Specification
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System Module NH1
N=Normal
E=Extreme
conditions
NRF–sensitivity< –113 dBm (SINAD 20 dB)
ERF–sensitivity< –110 dBm (SINAD 20 dB)
NAdjacent channel selectivity> 67 dB (25 kHz)
EAdjacent channel selectivity> 60 dB (25 kHz)
NSpurious response rejection> 67 dB
NIntermodulation rejection> 67 dB
N / ENoise & hum< –35 dB
N / ERSSI dynamic range> 65 dB
N / EAGC attenuation5...10 dB
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Preamplifier
PAMS Technical Documentation
Table 28. Preamplifier specifications
MinimumTypical /
Nominal
Supply voltage2,7V
Frequency band463467,475MHz
Current consumption (AGC off)97mA
Current consumption (AGC on)2mA
Insertion gain (AGC off)1922dB
Insertion gain (AGC on)14dB
Gain flatness±1dB
Noise figure1.61.8dB
Reverse isolation3040dB
IIP3–5dBm
Input return loss (Z0=50W)–4dB
Output return loss (Z0=50W)–11dB
MaximumUnit / Notes
RX–filter
Table 29. RX–filter specification
MinimumTypical /
Nominal
Center frequency, f
Bandwidth (–0,8 dB)±3MHz
Stopband attenuation
0805
L3713645027Chip coil470 n10 % Q=25/25 MHz
0805
L4403641548Chip coil100 n10 % Q=40/150 MHz
0805
L4423641544Chip coil68 n10 % Q=40/200 MHz
0805
L4433641548Chip coil100 n10 % Q=40/150 MHz
0805
L6213641548Chip coil100 n10 % Q=40/150 MHz
0805
L6233641548Chip coil100 n10 % Q=40/150 MHz
0805
L6513641548Chip coil100 n10 % Q=40/150 MHz
0805
L7803645019Chip coil82 n5 % Q=18/100 MHz
0805
L7813641544Chip coil68 n10 % Q=40/200 MHz
0805
B0015140087 Buzzer 85db 2600hz 3.6v 10x10x3.10x10x3.5
B1004510159 Crystal32.768 k+–20PPM
B7014510155 Crystal14.7456 M+–50PPM
G4104510171VCTCXO14.85 M+–2PPM 3.0V
F1025119011SM, fuse f2a 63v 1201206
F1505119011SM, fuse f2a 63v 1201206
Z1003640035Filt z>450r/100m 0r7max 0.2a 06030603
Z1013640035Filt z>450r/100m 0r7max 0.2a 06030603
Z1023640035Filt z>450r/100m 0r7max 0.2a 06030603
Z1303640035Filt z>450r/100m 0r7max 0.2a 06030603
Z1313640035Filt z>450r/100m 0r7max 0.2a 06030603
Z3404510085XTAL filter45 M+–7.5KHZ 4POLE
Z3704550063Cer. filt 450+–6khz 7.5x11.5 7.5x11.5
V0284100278 Diode x 2BAV7070 V 200 mA COMCAT.SOT23
V1014100189 Schottky diodeBAS70–0570 V 15 mA SOT23
V1134119902Diode x 4IMP1180 V 0.3 A IMD
V1144119902Diode x 4IMP1180 V 0.3 A IMD
V1154100189Schottky diodeBAS70–0570 V 15 mA SOT23
V1204210100 TransistorBC848Wnpn 30 V SOT323
V1214210100 TransistorBC848Wnpn 30 V SOT323
V1224210100 TransistorBC848Wnpn 30 V SOT323
V1404219922 Transistor x 2UM6
V1504113651Trans. supr.QUAD6 V SOT23–5
V1514113651Trans. supr.QUAD6 V SOT23–5
V1704210102 TransistorBC858Wpnp 30 V 100 mA
200MWSOT323
V1714210102 TransistorBC858Wpnp 30 V 100 mA
200MWSOT323
PAMS Technical Documentation
Page 80
Nokia Mobile Phones Ltd.
Issue 3 02/2000
THF-12
PAMS Technical Documentation
V1724210100 TransistorBC848Wnpn 30 V SOT323
V3104210074 TransistorBFP420npn 4. V SOT343
V3204210102 TransistorBC858Wpnp 30 V 100 mA
200MWSOT323
V3214219922 Transistor x 2UM6
V3304100567 Sch. diode x 2BAS70–0470V15 mA SERSOT23
V3504210066 TransistorBFR93AWnpn 12 V 35 mA
SOT323
V3604210066 TransistorBFR93AWnpn 12 V 35 mA
SOT323
V4404210091 TransistorBFG540W/Xnpn 15 V SOT343
V4414110072Diode x 2BAV99W70 V 0.2 A SOT323
V4424219922 Transistor x 2UM6
V4434210102 TransistorBC858Wpnp 30 V 100 mA
200MWSOT323
V6114210100TransistorBC848Wnpn 30 V SOT323
V6304210102 TransistorBC858Wpnp 30 V 100 mA
200MWSOT323
V6314210100 TransistorBC848Wnpn 30 V SOT323
V6324210100 TransistorBC848Wnpn 30 V SOT323
V6344100567 Sch. diode x 2BAS70–0470V15 mA SERSOT23
V6354116536Zener diodeBZX845 % 2.4 V 0.3 W
SOT23
V6374116536Zener diodeBZX845 % 2.4 V 0.3 W
SOT23
V7314210100 TransistorBC848Wnpn 30 V SOT323
V7324210100 TransistorBC848Wnpn 30 V SOT323
V7804210102 TransistorBC858Wpnp 30 V 100 mA
200MWSOT323
V7814111092Cap. diodeBB63930 V SOD323
V7824210066 TransistorBFR93AWnpn 12 V 35 mA
SOT323
V7834210066 TransistorBFR93AWnpn 12 V 35 mA
SOT323
V7844210100 TransistorBC848Wnpn 30 V SOT323
D2014370501IC, MCUTQFP120
D2214340273IC, SRAMSTSOP32
D2414370405IC, MCU8S2
D2514340357IC, EEPROMSO8
N1004370165Chaps charger control SO16
N1014370471Power asic for etacs/nmt450
N1024340623Pcf8563 clock/calendar 1–5.5v SO8
N1034340059IC, lp opamp+3/15v r&r sLMC7101SSOP5
N1234340663IC, regulatorLP29853.3 V 150 mA
SOT23–5
N2444340663IC, regulatorLP29853.3 V 150 mA
0805
L4423641544Chip coil68 n10 % Q=40/200 MHz
0805
L4433641548Chip coil100 n10 % Q=40/150 MHz
0805
L6213641548Chip coil100 n10 % Q=40/150 MHz
0805
L6233641548Chip coil100 n10 % Q=40/150 MHz
0805
L6513641548Chip coil100 n10 % Q=40/150 MHz
0805
L7803645019Chip coil82 n5 % Q=18/100 MHz
0805
L7813641544Chip coil68 n10 % Q=40/200 MHz
0805
B0015140087 Buzzer 85db 2600hz 3.6v 10x10x3.10x10x3.5
B1004510159 Crystal32.768 k+–20PPM
B7014510155 Crystal14.7456 M+–50PPM
G4104510171VCTCXO14.85 M+–2PPM 3.0V
F1025119011SM, fuse f2a 63v 1206
F1505119011SM, fuse f2a 63v 1206
Z1003640035Filt z>450r/100m 0r7max 0.2a 06030603
Z1013640035Filt z>450r/100m 0r7max 0.2a 06030603
Z1023640035Filt z>450r/100m 0r7max 0.2a 06030603
Z1303640035Filt z>450r/100m 0r7max 0.2a 06030603
Z1313640035Filt z>450r/100m 0r7max 0.2a 06030603
Z3404510085XTAL filter 45 M+–7.5KHZ 4POLE
Z3704550063Cer. filt 450+–6khz 7.5x11.5
V0284100278 Diode x 2BAV7070 V 200 mA COMCAT.SOT23
V1014100189 Schottky diodeBAS70–0570 V 15 mA SOT23
V1134119902Diode x 4IMP1180 V 0.3 A IMD
V1144119902Diode x 4IMP1180 V 0.3 A IMD
V1154100189Schottky diodeBAS70–0570 V 15 mA SOT23
V1204210100 TransistorBC848Wnpn 30 V SOT323
V1404219922 Transistor x 2UM6
V1504113651Trans. supr.QUAD6 V SOT23–5
V1514113651Trans. supr.QUAD6 V SOT23–5
V1704210102 TransistorBC858Wpnp 30 V 100 mA
200MWSOT323
V1714210102 TransistorBC858Wpnp 30 V 100 mA
200MWSOT323
V1724210100 TransistorBC848Wnpn 30 V SOT323
V3104210074 TransistorBFP420npn 4. V SOT343
V3204210102 TransistorBC858Wpnp 30 V 100 mA
200MWSOT323
V3214219922 Transistor x 2UM6
V3304100567 Sch. diode x 2BAS70–0470V15 mA SER-
System Module NH1
Issue 3 02/2000
Nokia Mobile Phones Ltd.
Page 91
THF-12
System Module NH1
SOT23
V3504210066 TransistorBFR93AWnpn 12 V 35 mA
SOT323
V3604210066 TransistorBFR93AWnpn 12 V 35 mA
SOT323
V4404210091 TransistorBFG540W/Xnpn 15 V SOT343
V4414110072Diode x 2BAV99W70 V 0.2 A SOT323
V4424219922 Transistor x 2UM6
V4434210102 TransistorBC858Wpnp 30 V 100 mA
200MWSOT323
V6114210100TransistorBC848Wnpn 30 V SOT323
V6304210102 TransistorBC858Wpnp 30 V 100 mA
200MWSOT323
V6314210100 TransistorBC848Wnpn 30 V SOT323
V6324210100 TransistorBC848Wnpn 30 V SOT323
V6344100567 Sch. diode x 2BAS70–0470V15 mA SERSOT23
V6354116536Zener diodeBZX845 % 2.4 V 0.3 W
SOT23
V6374116536Zener diodeBZX845 % 2.4 V 0.3 W
SOT23
V7314210100 TransistorBC848Wnpn 30 V SOT323
V7324210100 TransistorBC848Wnpn 30 V SOT323
V7804210102 TransistorBC858Wpnp 30 V 100 mA
200MWSOT323
V7814111092Cap. diodeBB63930 V SOD323
V7824210066 TransistorBFR93AWnpn 12 V 35 mA
SOT323
V7834210066 TransistorBFR93AWnpn 12 V 35 mA
SOT323
V7844210100 TransistorBC848Wnpn 30 V SOT323
D2014370501IC, MCUTQFP120
D2114340261 IC, FLASH TSO48
D2214340273IC, SRAMSTSOP32
D2414370405IC, MCU8S2
D2514340357IC, EEPROMSO8
N1004370165Chaps uba2006t/n2,118 SO16
N1014370471Power asic for etacs/nmt450
N1024340623Pcf8563 clock/calendar 1–5.5v SO8
N1034340059IC, lp opamp+3/15v r&r LMC7101SSOP5
N1234340663IC, regulatorLP29853.3 V 150 mA
SOT23–5
N2444340663IC, regulatorLP29853.3 V 150 mA
SOT23–5
N3704349694IC, if amp+fm detector TA31136SSO16
N4004340393IC, 2xsynth 1.1ghz UMA1015AMSSOP20
N4014340403IC, 2xop amp 2.7–3v sLMC6572AIMSO8
N6114340629 IC Rf2117 pw amp 450mhzSO16S