Nokia TFF-3 System Module
PAMS Technical Documentation
TFF-3 WLL Terminal
System Module JM1
Issue 2 02/00 E Nokia Mobile Phones Ltd.
TFF-3
System Module JM1
PAMS Technical Documentation
CONTENTS
Terminal TFF–3 System Module JM1 3 – 5. . . . . . . . . . . . . . . . . . . . . .
Introduction 3 – 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Module 3 – 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CTRLU 3 – 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block description 3 – 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MCU Processor 3 – 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SIS MCU 3 – 9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EEPROM 3 – 10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flash memory and Flash programming 3 – 10. . . . . . . . . . . . .
RAM 3 – 10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Immobilizer 3 – 10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PWRU 3 – 11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input supply voltage 3 – 11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PSA 3 – 12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PSA pinout 3 – 12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional descriptions 3 – 13. . . . . . . . . . . . . . . . . . . . . . . . . . .
Separate regulators 3 – 14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AUDIO 3 – 15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MASI ASIC 3 – 15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MASI Pinout 3 – 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SLIC block 3 – 18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Immobilizer 3 – 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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RF Module 3 – 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Introduction 3 – 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Technical Specifications 3 – 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum ratings 3 – 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Control Signals 3 – 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power consumption Diagram 3 – 23. . . . . . . . . . . . . . . . . . . . . .
Connections 3 – 25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Connections to Baseband sub–module 3 – 25. . . . . . . . . . . . . . . .
Key RF components 3 – 27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Antenna 3 – 28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receiver 3 – 28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RX Synthesizer 3 – 29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RX loop filter 3 – 29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TX Synthesizer 3 – 29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TX Loop Filter 3 – 30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmitter 3 – 30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RF Characteristics 3 – 31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Temperature range 3 – 31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Duplexer specification 3 – 31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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RX submodule specifications 3 – 31. . . . . . . . . . . . . . . . . . . . . . . .
Preamplifier 3 – 32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RX–filter 3 – 32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1st mixer 3 – 33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1st IF–filter 3 – 33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IF–amplifier 3 – 33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2nd IF–filter 3 – 34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IF–circuit 3 – 34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TX submodule specification 3 – 35. . . . . . . . . . . . . . . . . . . . . . . . .
Power amplifier 3 – 35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power control and 2nd TX buffer 3 – 35. . . . . . . . . . . . . . . . . . .
Coupler lines 3 – 35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Synthesizer submodule specifications 3 – 36. . . . . . . . . . . . . . . . .
PLL 3 – 36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RX VCO 3 – 36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TX VCO 3 – 36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Isolation amplifier (1st TX buffer) 3 – 37. . . . . . . . . . . . . . . . . . .
VCTCXO 3 – 37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TFF-3
System Module JM1
Parts list of WN1 Basic Module (EDMS Issue 3.3) 3 – 38. . . . . . . . . . .
Parts list of WN1 Basic Module (EDMS Issue 3.8) 3 – 49. . . . . . . . . . .
Parts list of WN1F Variation Module (EDMS Issue 1.1) 3 – 60. . . . . . .
Parts list of WN1F Variation Module (EDMS Issue 1.4) 3 – 60. . . . . . .
Parts list of WN1T Variation Module (EDMS Issue 1.3) 3 – 61. . . . . . .
Parts list of WN1C Variation Module (EDMS Issue 1.4) 3 – 61. . . . . . .
Schematic Diagrams
Block Diagram of JM1 Module (Version 06 Edit 195) 3A–1. . . . . . . . .
Circuit Diagram of SLIC (Version 06 Edit 59) 3A–2. . . . . . . . . . . . . . .
Circuit Diagram of CTRLU (Version 06 Edit 254 ) 3A–3. . . . . . . . . .
Circuit Diagram of PWRU (Version 06 Edit 237 ) 3A–4. . . . . . . . . . .
Circuit Diagram of Audio (Version 06 Edit 346) 3A–5. . . . . . . . . . . . .
Circuit Diagram of Receiver (Version 06 Edit 17) 3A–6. . . . . . . . . . .
Circuit Diagram of Synthesizer (Version 06 Edit 66) 3A–7. . . . . . . . .
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Circuit Diagram of Transmitter (Version 06 Edit 176) 3A–8. . . . . . . .
Layout Diagram of JM1 1/2 3A–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Layout Diagram of JM1 2/2 3A–10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Diagram of JM1 Module (Version 07 Edit 195) 3A–11. . . . . . . . .
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System Module JM1
Circuit Diagram of SLIC (Version 07 Edit 60) 3A–12. . . . . . . . . . . . . . .
Circuit Diagram of CTRLU (Version 07 Edit 255 ) 3A–13. . . . . . . . . .
Circuit Diagram of PWRU (Version 07 Edit 241 ) 3A–14. . . . . . . . . . .
Circuit Diagram of Audio (Version 07 Edit 349) 3A–15. . . . . . . . . . . . .
Circuit Diagram of Receiver (Version 07 Edit 17) 3A–16. . . . . . . . . . . .
Circuit Diagram of Synthesizer (Version 07 Edit 68) 3A–17. . . . . . . . .
Circuit Diagram of Transmitter (Version 07 Edit 179) 3A–18. . . . . . . .
Layout Diagram of JM1 1/2 3A–19. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Layout Diagram of JM1 2/2 3A–20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAMS Technical Documentation
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PAMS Technical Documentation
Terminal TFF–3 System Module JM1
Introduction
The Baseband module controls the internal operation of the phone. It
controls the user interface and audio interface functions. The module per-
forms all signalling towards the system and carries out audio–frequency
signal processing. The module controls the operation of the transceiver
and stores the tuning data for the phone. Also the subscriber line inter-
face between the WLL terminal and a land–line phone is performed in the
baseband module. In addition there is an immobilizer switch to detect
movement of the terminal after mounting.
System Module
All functional blocks of the baseband are mounted on a single multi layer
printed circuit board. This board contains also the RF–parts. The chassis
of the transceiver unit comprises separating walls for baseband and RF.
Components of the baseband are surface mounted, except a few. The
surface mountable components are soldered using reflow and the axial
ones manually. The connections to accessories are fed through the sys-
tem connector of the transceiver unit. There is no physical connector be-
tween the RF and baseband.
TFF-3
System Module JM1
Name of submodule Notes
CTRLU
PWRU
AUDIO
SLIC
RX
TX
SYNTH
These blocks are only functional blocks and therefore have no type nor
material codes. The circuit diagram is found in the Schematics section.
The nominal supply voltage is 13.5V. Actual supply voltage can vary
10.6V to 14.5V. The baseband and logic supply voltage is nominal 2.8V.
Control Unit for the phone
Power supply unit
Audio unit
Subscriber Line Interface module for land–line phone
Receiver
Transmitter
Synthesizer
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TFF-3
System Module JM1
CTRLU
The control block controls all of the functions of the phone and it com-
prises the memories and the SIS–processor. An immobilizer switch is in-
cluded.
Block description
– CTRLU – PWRU
The MCU controls the watchdog timer in the PSA. It sends a positive
pulse at approximately 1 s intervals to the XPWROFF pin of the PSA to
keep the power on. If the CTRLU fails to deliver this pulse, the PSA will
remove power from the system. After the watchdog has elapsed the PSA
cuts off the supply voltages from the phone and starts again.
The flash voltage control connects programming voltage to the flash
memory and also disables the watchdog reset.
PAMS Technical Documentation
– CTRLU – AUDIO
The interface between the MCU and the MASI circuit is a bidirectional
8–bit data bus with 4 address lines. Address, data and control lines are
used in the MCU as I/O–port pins. Data lines direction must be controlled
with the MCU data direction register. Interface includes address outputs
MA0–4, data inputs (read) / outputs (write) MD0–7, chip select control
output XCS , read control output XRD, write control output XWR and in-
terrupt input XINT. When CPU is in sleep state , control signals XRD and
XCS must be in ’0’ state and address output NA0–3 and NWR in ’1’ state
and data lines ND0–7 must be in ‘0‘ state.
A valid DTMF tone is detected from interrupt line via DTMF receiver.
DTMF receiver sends the valid DTMF tone code via 4–bit bus.
– CTRLU – SLIC
The MCU sets and controls the SLIC circuit and detects actions. There is
only one landline port connected to connector.
The MCU generates the clock signal for SLIC DC/DC converter for syn-
chronization purposes.
The metering pulse is controlled by MCU for payphone usage.
– CTRLU – RECEIVER
The RX circuit power is connected on/off by RXE signal.
The received signal strength is measured over the RSSI and intermediate
frequency is measured over the IF. The LNA gain is controlled by the
AGC signal.
– CTRLU – SYNTHESIZER
The RF temperature is measured over the RFTEMP. The frequency is
controlled by the AFC signal. The synthesizer is controlled via the syn-
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chronous serial bus SDAT/SCLK. The data is latched to the synthesizer
by the positive edge of the SLE line. The TX synthesizer power on/off
(TXSYNE) line is controlled via the PLL circuit. The 1st buffer is switched
on/of via the TXBUFF signal.
– CTRLU – TRANSMIT
The TXE line activates the power module. The power is controlled via the
TXC line which is a PWM–controlled output port.
MCU Processor
H8/2322 is a CMOS microcontroller. The CPU is ROMless version so all
memory needed is located outside the chip.
MCU operating clock (=7.3728 or 14.7456 MHz) is generated in the
MASI.
The MCU pins are listed in the table below.
NC=not connected, I=Input, O=Output, I/O=Input/Output.
TFF-3
System Module JM1
Pin number Symbol Description Pin type
1 Vcc to VL
2–5,
7–14,
16–25
6, 15, 24 Vss
26 PA5 SLIC_DET I
27 PA6 NC
28 PA7 NC
29 P67 NC
30 P66 NC
31 P65 NC
32 _IRQ0 XINT, interrupt signal from MASI I
33 Vcc to VL
34–37,
39–46,
48–51
38, 47 Vss GND
52 Vcc to VL
A0–A20 FLASH, MASI and RAM addresses
(A20, pin 25 not connected)
D0–D15 Data bus Data
Address
53 P30/TxD0 MSBUSTX, serial data to M2BUS O
54 P31/TxD1 TXBUFF O
55 P32/RxD0 MBUSRX, serial data from M2BUS I
56 P33/RxD1 FLASH_PROG, flash voltage control and PSA
watchdog disable
57 P34/SCK0 IMMO_SET, Immobilizer set signal O
58 P34/SCK1 AGC I/O
59 Vss GND
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O
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System Module JM1
60 P60/CS4/_DREQ0 NC I
61 P61/CS5/TEND0 NC I
62 P62/_DREQ1 ECLK, serial clock (EEPROM) I
PAMS Technical Documentation
Pin typeDescriptionSymbolPin number
63 P63/_TEND1 SISDATA,
(SIS serial data)
64 P27 SLE, synthesizer enable O
65 P26 SLIC_CLK2 SLIC gate clock for SMPS O
66 P25 MBUSRX, timeout timer start signal from M2BUS I
67 P24 SCLK serial clock for synthesizer O
68 P23 SDAT, synthesizer data O
69 P22 TXE I/O
70 P21 SIS RESET O
71 P20 RXE O
72 WDTOVF NC
73 _RES XRES reset for MCU, FLASH, MASI from PSA I
74 NMI 1 I
75 STDBY 1 I
76 Vcc to VL
77 XTAL NC
78 EXTAL CLKMCU from MASI I
79 Vss GND
I/O
80 PF7 DTMF (4) I
81 Vcc VL
82 AS NC
83 RD FLASH, MASI, SRAM Read
84 HWR MASI, SRAM Write
85 LWR FLASH Write
86 PF2 DTMF (3) I
87 PF1 DTMF (2) I
88 PF0 DTMF (1) I
89 P50/TxD2 FBUSTX O
90 P51/RxD2 FBUSRX I
91 P52/SCK2 MBUSRX for FBUS CLK I
92 P53 Serial Clock for SIS O
93 AVcc VA
94 Vref VA
95 AN0
96 AN1 VCHARSW Analog
VBATSW, not used
Analog
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97 AN2 RSSI Analog
98 AN3 NC Analog
99 AN4 NC Analog
100 AN5 NC Analog
101 AN6 RFTEMP Analog
102 AN7 IMMO_DET Analog
103 AVss GND
104 Vss GND
105 P17 RING_CLK O
106 P16 TTX_CLK O
107 P15 SDA (serial data, EEPROM) I/O
108 P14 TXC O
109 P13 SEL1 O
System Module JM1
Pin typeDescriptionSymbolPin number
110–111 P12–P11 SLIC_CTRL (1–0) I/O
112 P10 XPWROFF O
113 MD0 0 (mode 4) I
114 MD1 0 (mode 4) I
115 MD2 1 (mode 4) I
116 PG0 NC
117 PG1 NC
118 PG2 RAMCS O
119 PG3 MASICS O
120 PG4 FLASHCS O
SIS MCU
AT90S2343 is a SIS (subscriber identification) circuit connected to the
controller over serial bus IIC.
Pin no. Symbol Description
1 _RESET Reset input
2 XTAL1 Clock input from MASI
4 GND GND
5 MOSI IIC bus data
7 SCL/T0 IIC bus clock
8 Vcc VSIS
EEPROM
There is one 16k EEPROMs in phone. EEPROM is a nonvolatile memory
into which is stored the tuning data for the phone.
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Pin no. Pin Description
4 GND GND
5 SDA IIC bus data
6 SCL IIC bus clock
8 Vcc VL
PAMS Technical Documentation
Flash memory and Flash programming
Flash memory size is 512kx16 (8MB). The Flash is a nonvolatile memory
for the program code.
Flash memory has a pre–programmed boot program. This program controls itself when the final program is stored in the memory via the FBUS
and the MBUS.
During programming only the system connector is used and the TFF–3 is
powered via the flash loading adapter (FLA–5).
RAM
The MCU has no internal memories, instead there is a SRAM circuit connected to the parallel data bus and the address bus. The size of the
SRAM is 64kB.
Immobilizer
The immobilizer uses two I/O pins of the MCU. The Output pin is used for
writing to the immobilizer and the input pin is used to read the state of the
flip–flop.
When the immobilizer is activated, the state of the flip–flop is set by the
switch and by the software via MCU output pin. After that, in the run–
time, the state of the flip–flop is read every 4 seconds. As long as the terminal stays in its original location, the state is ”1”.
When the terminal is moved, the immobilizer switch opens and causes a
state transition. After that the state of the flip–flop is found to be ”0” and
the software sets the terminal to ”terminal moved” –state. In that state
the message ”terminal moved” can be seen in the service PC software.
The operating voltage of the immobilizer (VSLIM) is obtained from the
voltage supply (VS). There is also a 0.5mAh lithium battery for backup
purpose, which is used as power supply in the situations when the terminal is not powered. This means, that the terminal can not be moved even
if it has no power. In this case the flip–flop will change its state when the
switch is opened. When the terminal is powered again the movement will
be detected.
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PWRU
The main function of the PWRU is to feed suitable voltages in every
block. It consists of Input voltage connectors, protection circuits, separate regulators and the PSA ASIC. The PSA circuit has also another
function, the MBUS handling and watchdog.
The Power distribution diagram is below.
TFF-3
System Module JM1
PSA
VL (2.8V)
40mA
VA (2.8V)
100mA
VB
Input voltage
protection
Regulator
5V /0.5A
Regulator
3.3V 150mA
Regulator
3.3V 150mA
Regulator
8V/0.5A
to power amplifier and SLIC
The input voltage is protected against accidental interference and fault
actions. The RF –power amplifier and SLIC functions use this unregulated voltage.
Supply voltages for PSA, flash programming, SIS MCU and RF transmitter are fed from separate regulators.
VTX (2.8V)
60mA
VRX (2.8V)
50mA
VS
VSIS
VPROG
VPC
VB
10.6–14.5V
max. 2.8A
Input supply voltage
Input voltage is protected against overcurrent, overvoltage and reverse
voltage.
Also the input voltage is protected against overvoltage and reverse voltage. RF –power amplifier and SLIC functions use this unregulated voltage.
Overcurrent:
There is slow type fuse, breakdown value 5A
Overvoltage and reverse voltage:
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System Module JM1
There is transient suppressor diode which work as fast Zener voltage
over 16V nom. (max. 20V). Also it work like diode in forward direction.
Also input voltage is filtered against interference from external power supply unit.
PSA
The PSA is a multi function Power Supply and charging control circuit for
Analog handportable phones. It has two separate power supplies for
baseband (VL,VA) and two externally controllable power supplies for RF
(VRX, VTX). The main functions are voltage regulators, power on/off and
charge control and reset logic (including watchdog), supply voltage and
charger detection functions and buffer for the M2BUS.
Main features of PSA:
– Voltage outputs are isolated from other regulators and from each other
– Buffer for the M2BUS
PAMS Technical Documentation
– Power on/off and reset logic
– Power off logic can be used as a watchdog
– Supply voltage monitor and automatic reset/power–off
– Battery charger detection
– Automatic on–chip current limiting
– On–chip thermal shutdown
– Surface mounted package SSOP28
PSA pinout
Control pins:
Signal Pin
number
PWRONX 22 IN PoWeR ON control input (pulled down )
VRX_ENA 2 IN VRX regulator ENAble
VTX_ENA 27 IN VTX regulator ENAble
WD_DISX 24 IN WatchDog DISable (internal pull up)
PWROFFX 23 IN Watchdog reset from MCU
PURX 16 OUT Power Up Reset signal
Type Description
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Input pins:
Signal Pin
number
VBAT1 3 Battery voltage for VRX regulator
VBAT2 11 Battery voltage for VL regulator, battery voltage monitor-
ing and internal logic
VBAT3 18 Battery voltage for VA regulator and internal analog func-
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System Module JM1
Signal
number
VBAT4 26 Battery voltage for VTX regulator
GND1 1 Ground for VRX regulator
GND2 6 Ground for internal reference voltage
GND3 12 Ground for VL regulator and internal logic
GND4 19 Ground for VA regulator and internal analog functions
GND5 28 Ground for VTX regulator
TEST 5 Test specific pin (internal pull down)
M2BUSIN 14 M2BUS data input
VCHAR 9 Divided CHARger input Voltage
DescriptionPin
Output pins:
Signal Pin
number
VA 17 Output Voltage for Analog circuitry (2.8V@100mA)
VL 13 Output Voltage for Logic circuitry (2.8V@40mA)
VRX 4 Output Voltage for RF or Analog circuitry
(2.8V@50mA)
VTX 25 Output Voltage for RF or Analog circuitry
(2.8V@60mA)
VBATSW 20 SWitched internally divided VBAT voltage
VCHARSW 8 SWitched VCHAR voltage
COSC 10 Connection for an external timing Capacitor defining
watchdog elapse time
CREF 7 Connection for an external Capacitor of the internal REF-
erence voltage
M2BUSOUT 15 M2BUS data out (open drain)
PWRONBUFF 21 inverted PWRONX state
Description
PWRONX and WD_DISX inputs have internal pull–up resistors.
M2BUSIN, VRX_ENA, VTX_ENA, TEST and PWROFFX inputs have in-
ternal pull–down resistors.
Functional descriptions
PSA
The linear regulators are high performance regulators. Regulators have
internal current limiting. All the regulators have low quiescent currents
thus extending the battery life.
VA and VL are intended for baseband circuits, VRX and VTX for RF circuitry.
Voltage monitor
This function is used to monitor VBAT voltage level. The threshold level
is set by internal resistor divider.
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System Module JM1
The circuit monitors the voltage at the VBAT input and forces the circuit to
Reset if the voltage level is below allowed limit voltage, VBATcoff–. A
hysteresis is included to prevent oscillation between different states.
Thermal protection
Thermal shutdown protects PSA from overheating. Thermal shutdown includes hysteresis in order to prevent oscillation during the thermal protection.
Power supply voltage detection
Thermal shutdown protects PSA from overheating. Thermal shutdown includes hysteresis in order to prevent oscillation during the thermal protection.
M2BUS buffer
M2BUS is a serial bus between mobile and accessories.
M2BUS baud rate is 9600 bps.
PAMS Technical Documentation
The buffer translates the logical input signal to open–drain output.
Rgw M2BUS buffer thruth table is below.
Separate regulators
Separate supply voltages:
– Regulator 5V is for PSA and some RF purposes.
– Regulator 8V is used for RF TX buffers
– Regulator 3.3V is used for flash programming
– Regulator 3.3V is used for SIS MCU
Input Output
LOW LOW
HIGH Z
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AUDIO
The Audio block includes the MASI ASIC, the DTMF circuitry and the
SYSTEM connector.
MASI ASIC
MASI is a single chip audio/signalling processor in a 64 TQFP package
for the NMT450 system.
Main features
– Low power consumption modes
– 8 bit parallel interface with pull ups
– FM demodulator
TFF-3
System Module JM1
FFSK modem features
– Full duplex 1200 baud signalling
– FSK indicator and level detector
– FII filter and gain control
– DMS facility
Audio features
– Low noise microphone amplifier
– Input for a handset microphone or an accessory
– Microphone sensitivity compensation +24/–7 dB range (5 bits)
– Compander
– RX and TX filters
– Tx hard limiter
– Tx AGC
– Transmitter compensation amplifier with +1.875/–1.875 dB range (4
bits)
– Compensation amplifier for different RX deviations with +7.5/0 dB
range (4 bits)
– Volume control amplifier with –20/+17.5 range (4 bits)
– Earphone amplifier with drive capability for ceramic earpiece
– Buffered output for a handset or an accessory
– Mute switches
– Speech scrambler and descrambler
Other features
– Dual and single tone multifrequency generator
– IF counter
– 8 bit general purpose DAC
– Programmable output clocks with clock stop for MCU, LCD and SIS
– Two external interrupt sources
– Programmable timer
– Summing stage for voice/data, signalling and fii
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PAMS Technical Documentation
MASI Pinout
Pin no Symbol Pin type Notes
1 VDD1 PWR +2.7 ... 3.5 V Supply voltage for digital part
2 XCS DIN/pd Chip select signal, active state LOW, pull–down > 50 kW
3 A4 DIN/pu 5–bit address bus, MSB, pull–up > 50 kW
4 A3 DIN/pu 5–bit address bus, pull–up > 50 kW
5 A2 DIN/pu 5–bit address bus, pull–up > 50 kW
6 A1 DIN/pu 5–bit address bus, pull–up > 50 kW
7 A0 DIN/pu 5–bit address bus, LSB, pull–up > 50 kW
8 D7 DIO 8–bit bidirectional data bus MSB
9 D6 DIO 8–bit bidirectional data bus
10 D5 DIO 8–bit bidirectional data bus
11 D4 DIO 8–bit bidirectional data bus
12 D3 DIO 8–bit bidirectional data bus
13 D2 DIO 8–bit bidirectional data bus
14 D1 DIO 8–bit bidirectional data bus
15 D0 DIO 8–bit bidirectional data bus LSB
16 NMI DOUT Non maskable Interrupt request
17 VSS1 PWR 0 V Supply voltage, ground for digital part
18 XCLR DIN HW reset input, active state LOW
19 TMODE DIN/pd Test mode selection, pull–down > 50 kW
20 TSEL DIN/pd Scan test selection, pull–down > 50 kW
21 XINT DOUT Interrupt request to MCU, active state LOW
22 EXTINT1 DIN External interrupt request, falling edge active (note: this pin
is test scan select when TMODE is high)
23 EXTINT2 DIN External interrupt request, falling edge active
24 VDD2 PWR +2.7 ... 3.5 V Supply voltage for digital in Analog part
25 IF AIN IF input
26 DAF AIN Audio input
27 FILO AOUT Rxfilter output
28 EXPI AIN Expander/Descrambler input
29 EXPO AOUT Expander/Descrambler output
30 VOLI AIN Volume control amplifier input
31 VSA1 PWR 0 V Supply voltage, ground for RX Analog
(including EARAMP & EXTEAR)
32 EXTEAR AOUT Buffered output for handset or an accessory
33 EARP AOUT Earphone driver output, positive
34 VDA1 PWR + 2.7 ... 3.5 V Supply voltage for RX Analog
(including EARAMP & EXTEAR)
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NotesPin typeSymbolPin no
35 EARN AOUT Earphone driver output, negative
36 DACO AOUT DA converter output
37 CALLCNT AIN Voltage sensor input for battery change during call
38 REF AOUT Internal analog signal ground, stabilization capacitor
39 ATOUT AOUT Analog test circuit output
40 MIC AIN Microphone amplifier input,
41 BIMIC AOUT Microphone bias output
42 CMIC AIN Microphone bias current stabilizing capacitor
43 EXTMIC AIN Audio input for a handset or an accessory
44 TXPBO AOUT Transmit bandpass filter (scrambler) output
45 COMI AIN Compressor input
46 MOD AOUT transmit path output
47 ATST AOUT Analog test output
System Module JM1
TFF-3
48 VDA2 PWR + 2.7 ... 3.5 V Supply voltage for TX Analog & NVSGEN
49 NSV AOUT Negative supply voltage, –7V output
50 NSV2 AOUT negative supply voltage –4.66V, for external capacitor
51 NSV1 AOUT negative supply voltage –2.33V, for external capacitor
52 NCPP AOUT Negative supply charge pump (external) capacitor positive
53 NCPN AOUT Negative supply charge pump (external) capacitor negative
54 VSA2 PWR 0 V Supply voltage, ground for TX Analog & NVSGEN
55 TOUT DOUT Test scan data output
56 CLKIN CIN 14.7456 MHz crystal oscillator input or input for the external
clock
57 CLKOUT COUT 14.7456 MHz crystal oscillator output
58 VSS2 PWR 0 V Supply voltage,
ground for digital in Analog part & Buzzer
59 BUZZ AOUT Buzzer output, open collector
60 CLKLCD DOUT Clock signal for LCD, 230.4 kHz, 57.6 kHz or 14.4 kHz
61 CLKSIS DOUT Clock signal for SIS processor, 3.6864MHz or 7.3728MHz
62 CLKMCU DOUT Clock signal for MCU, 3.6864 MHz, 7.3728 MHz or 14.7456
MHz
63 XWR DIN/pu Write control signal, active state LOW, pull–up > 50 kW
64 XRD DIN/pd Read control signal, active state LOW, pull–down > 50 kW
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PAMS Technical Documentation
SLIC block
The TFF–3 line adapter hardware is implemented using the STLC3065
SLIC custom–designed for wireless applications. The pins of the
STLC3065 are listed below.
Pin no Symbol Pin type Notes
1 D0 I Control interface,input bit 0
2 D1 I Control interface,input bit 1
3 D2 I Control interface,input bit 2
4 P1 I Control interface, port selection bit
5 P2 I Control interface, port selection bit
6 _DET1 O Logic interface output of the line port 1 detector, open drain
7 _DET2 O Logic interface output of the line port 2 detector, open drain
8 _DET O Logic interface output of the supervision line detector, open
drain
9 CKTTX I Metering pulse clock input
10 CTTX1 Metering burst shaping external capacitor
11 CTTX2 Metering burst shaping external capacitor
12 RTTX O Metering pulse cancellation buffer output
13 FTTX O Metering pulse buffer
14 RX I 4 wire input port (RX input)
15 ZAC1 O RX buffer output
16 ZAC I AC impedance synthesis
17 RS Protection resistor image
18 ZB Balance network for 2 to 4 wire conversion
19 CAC I AC feedback input
20 TX O 4 wire output (TX output)
21 VF I Feedback input for DC/DC converter controller
22 CLK I Power switch controller clock
23 GATE O Driver for external PowerMOSFET
24 RSENSE I Voltage input for current sensing
25 VPOS I Positive supply input voltage
26 CVCC Internal positive voltage supply filter
27 AGND Analog ground
28 RLIM I Constant current feed programming pin.
29 IREF I Internal bias current setting pin
30 RTH I Off–hook threshold programming pin
31 RD I DC feedback and ring trip input
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NotesPin typeSymbolPin no
32Imm ILTF O Transversal line current image output
33 CSVR Battery supply filter capacitor
34 BGND Battery ground
35 VBAT Regulated battery voltage self generated
36 RING2 2 wire port 2, RING wire (Ib is the current sunk into this pin)
37 RING1 2 wire port 1, RING wire (Ib is the current sunk into this pin)
38 NC
39 NC
40 NC
41 TIP1 2 wire port 1, TIP wire (Ia is the current source from this pin)
42 TIP2 2 wire port 2, TIP wire (Ia is the current source from this pin)
43 CREV Reverse polarity transition time control
44 VBAT1 Frame connection
System Module JM1
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