Layout Diagram of US4U (Layout version 08)3/A3–8. . . . . . . . . . . . . .
Original 10/98
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NHX-7
PAMS
Baseband Module JP3
System Module JP3: Introduction
This document specifices the System module JP3 of the NHX–7 ETACS
cellular phone.
The JP3 System Module comprises the baseband and the RF functions of
the phone.
Baseband Sub-module
The Baseband submodule controls the internal operation of the phone. It
controls the user interface, i.e. LCD driver, keyboard and audio interface
functions. The module performs all signalling towards the system and carries out audio–frequency signal processing. In addition, it controls the operation of the transceiver and stores tuning data for the phone.
The baseband architecture is basically similar to the previous generation.
However, the system specified logical voltage level used is 2.82V and
new features include a improved charging circuit CHAPS and a new power supply circuit PSA.
Technical Documentation
The baseband architecture supports a power saving function called ”extended standby mode”. This sleep mode shuts off the Receiver and part
of the NASTA blocks. The phone is woken up at every FOCC:s first word
and it is ”sleeping” the rest of the time.
The nominal battery voltage in NHX–7 is 3.6V. The actual battery voltage
varies between 3.0 to 4.2V/5.3V depending on the used cell type (Li-Ion
or NiMH) and whether the phone is connected to a charger (limit on 5.3V
with NiMH battery in idle).
Battery charging is controlled by a PWM signal from the MCU. The PWM
duty cycle is determined by a charging software. The PWM signal is fed
to the CHAPS charging switch and through the charging pins to an external charger. There can be two types of chargers connected to the phone.
Standard chargers (two wires) provide coarse supply power, which is
switched by the CHAPS for suitable charging voltage and current.
Advanced chargers (three wires) are equipped with a control input,
through which the phone gives PWM charging control signal to the charger.
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Technical Documentation
Block Diagram of baseband
Rf power
supply
EEPROM
4k byte
32 byte
OTP
Rf control Mod/Daf Ref
Clock
VCTCXO
System
14.85 MHz
Baseband Module JP3
Clock
UI
MCU
H8 3093
4kx8 RAM
192k ROM
8 ADC
I/O Ports
Serial ports
PWM
outputs
PSA
Power
Supply
Asic
Data
NASTA
Audio/
Audio
control
McuClk
Rows, Cols, Disp data, Lights, Buzz
Power supply VL,VA
Signalling
BSI, BTEMP
BaseBand
Asic
LcdClk
CHAPS
Charger
Asic
Vbat
Earp
Earn
Ichar
Current
Shunt
Connector
UI Board
Display/
Driver
Keypads
Earphone
Buzzer
Lights
Battery
Battery
Connector
Original 10/98
System Connector:
Mbus,Xmic,Xear ,Mic
Bottom connector
Charger Connector:
Vcharg, Charger cntl, Gnd
Figure 1.
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Baseband Module JP3
Technical summary
The baseband module consists of VCTCXO module and four ASIC circuits, PSA, CHAPS, NASTA 4.5, EEPROM, and some standard circuits,
DUAL BILATERAL SWITCH (TC7W66F), AUDIO POWER AMPLIFIER
(LM4862) and a Hitachi H8 series controller (H8/3093 MCU).
The MCU includes memories, 192 kbytes ROM and 4 kbytes RAM. It
controls all transceiver functions.
The EEPROM type is 4 kbytes with 32 bytes. The OTP memory is a seri-
2
C–bus type.
al I
The baseband is running from a 2.8 V power rail, which is supplied by a
power controlling asic. In the PSA asic there are two separate power supplies for BaseBand ( VA,VL ) and two externally controllable power supplies for RF (VRX, VTX).
The CHAPS is a charging control ASIC. It is essentially
power switch for controlling charging current, in a mobile phone. CHAPS
is designed for 3 cell Nickel or 1 cell Lithium battery packs.
Technical Documentation
an integrated
The NASTA circuit integrates the Audio and Modem operations. Because
the NASTA supports only one microphone, there are two bilateral
switches to connect the internal microphone or the headset microphone
to the NASTA MIC input. There is an audio power amplifier for EAR and
XEAR lines each. The internal earphone amplifier is a dual ended type
output which is in EAR line and there is transistor buffer in XEAR line.
The VCTCXO module is a voltage and temperature controlled oscillator
which operates as system clock for RF and BaseBand.
All functional blocks of the baseband are mounted on a single multi layer
printed circuit board. All components of the baseband are surface mountable. This board contains also the RF–parts. The B–cover side ( battery
side ) EMC shielding is implemented by using a metallic RF–shields on
the RF–blocks. On the other side the engine is shielded with a aluminium
frame, which makes a contact to a ground ring of the engine board and a
ground plane of the UI–board.
The connections from BaseBand to UI board are fed through a 28–way
2–row board to board spring connector.
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NHX-7
Technical Documentation
Modes of Operation
Power off, Standby, Listening and Conversation modes.
– In Power off mode only the circuits needed for power up are supplied.
– In Standby mode the MCU and needed blocks of the NASTA are ac-
tive.
– In Listening mode the receiver and some blocks of the NASTA are ac-
tive.
– In Conversation mode all ICs are active.
Baseband Module JP3
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Baseband Module JP3
CTRLU Circuit
The Control block CTRLU controls all functions of the phone.
Block Description
– CTRLU – PWRU
CTRLU controls the watchdog timer in PSA. It sends a negative pulse at
approximately 0,1 s to XPWROFF pin of the PSA to keep the power on. If
CTRLU fails to deliver this pulse, the PSA will remove power from the
system. When power off is requested CTRLU leaves PSA watchdog without reset. After the watchdog has elapsed PSA cuts off the supply voltages from the phone. CTRLU controls also the charger on/off switching in
the PWRU block. Battery charging is controlled by CSW line, which is
PWM–controlled output port.
Technical Documentation
– CTRLU – AUDIO
Interface between microcontroller and the NASTA circuit is bidirectional
8–bit data bus with 4 address lines. Address, data and control lines are
used in microcontroller as I/O–port pins. Data lines direction must be controlled with microcontroller data direction register. Interface includes address outputs NA0–3, data inputs (read) / outputs (write) ND0–7, chip select control output XNCS , read control output XNRD, write control output
XNWR and interrupt input XINT. To minimize power consumption, control
signals XRD and XCS should be in ’0’ state and address output NA0–3
and NWR in ’1’ state and data lines ND0–7 should be inputs .Buzzer is
controlled by BUZZ_DRV PWM signal. Headset adapter is detected by
HSCONN input.
– CTRLU – UIF and DISPLAY
Keyboard is connected directly to the controller. COL 0:3 are output lines
and ROW 0:3 are input lines. Watchdog is updated same time with keyboard scanning (XPWROFF). Keyboard scanning is done by driving one
COL to 0 V at time and ROWs are used to read which key is pressed.
Keyboards lights are controlled by KEYBLIGHT signal and LCD lights by
LCDBLIGHT signal.
LCD controller interface to microcontroller is a bidirectional data line
LCDDA, data serial clock line SCLK output, chip select control LCDENX
output, command or display data control LCDDC output and reset control
LCDRES output.
– CTRLU – RECEIVER
Received signal strength is measured over the RSSI line and intermediate frequency is measured over the IF line.
RX synthesizer and receiver are powered on/off by PSBS_EN line.
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Technical Documentation
– CTRLU – SYNTHESIZER
Frequency is controlled by the AFC signal. The synthesizer is controlled
via the synchronous serial bus SDAT/SCLK. The data is latched to the
synthesizer by the positive edge of the SLE line. The TX synthesizers
power on/off is controlled by VTX_ENA signal.
– CTRLU – TRANSMITTER
The transmitter on/off state is detected over the TXI line. The TXE line activates the power module. The power is controlled via the TXC line which
is a PWM–controlled output port (frequency about 9.4 kHz).
Extended standby mode for power saving
The extended standby mode is automatically activated when the phone is
working in the control channel (FOCC). The NASTA runs this function,
switching on/off the receiver’s power supply.
PSPS_EN signal:
– The signal connects the RX regulator on via the PSA when it is in ”1”
state, in ”0” state the RX regulator is off.
Baseband Module JP3
HPD_EN signal:
– The signal controls the RX synthesizers hardware power down function.
When it is in ”1” state the RX synthesizer is powered up, in ”0” state the
RX synthesizer is powered down.
Main Components
MCU
The H8/3093 is a CMOS microcontroller. All the memory needed 192kB
ROM, 4kB RAM) except the EEPROM, is located in the controller. The
MCU operating clock (2.4 MHz) is generated on the NASTA and the
VCTCXO. The H8/3093 is operating in single–chip normal mode (mode
3) 192kbyte address space, so all input/output pins are used as I/O–ports.
Serial interface (M2BUS)
Serial data clock for EEPROM
Parallel data bus for NASTA
Address line for NASTA
Address line for NASTA
Address line for NASTA
Address line for NASTA
NASTA chip select
Write control to NASTA
Read control to NASTA
Keypad outputs
Keypad inputs (Input pullup used)
Serial data clock for lcd driver
Chip select signal for lcd driver
Display or Command data
Data line for lcd driver
TX synthesizer enable. Active
high
Mode selection
Reset from PSA
51EXTALCLKMCU
52XTALNC
53VCCVL
54P63TXE
55P64LIM
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External system clock from
NASTA
Transmitter on/off
Battery cut off limit selection
Battery voltage
Charger voltage
Charging current measurement
Battery temperature
Received signal strength
Transmitter state monitor
Headset detecting voltage
Battery size indicator
Interrupt request from NASTA
LCD reset signal
LCD backlight control
Headset switch indicator
Internal microphone control
LCD clock from NASTA
PWM output for buzzer
Serial clock for synthesizer
Charging control PWM
Eeprom data line
Transmitter power control
Headset microphone control
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Baseband Module JP3
EEPROM
There is one 4kbyte EEPROM with 32byte OTP memory in the phone.
The EEPROM is a nonvolatile memory in which the tuning data for the
phone is stored. In addition, it contains the short code memory locations
to retain user selectable phone numbers. The OTP memory is ROM area
for identification and security purposes.
Table 1. EEPROM signals:
Pin NoSignalDescription
5SDA
6SCL
I2C bus data
I2C bus clock
PWRU Circuit
Technical Documentation
Power Distribution
The main components of the Power Unit are the PSA ( Power Supply
Asic) and the CHAPS ( Charger Power Switch ).
In normal operation the baseband is powered from the phone‘s battery.
The battery consists of three Nickel Metal Hydride cells. There is also a
possibility to use batteries consisting of one Lithium–Ion cell. An external
charger is used for recharging the battery and supplying power to the
phone. The charger can be either a standard charger that can deliver
around 400 mA or a so called performance charger, which can deliver
supply current up to 850 mA.
The baseband contains components that control the power distribution to
the whole phone excluding those parts that use continuous battery supply. The battery feeds power directly to three parts of the system: PSA,
RF–power amplifier, and UI (buzzer and display and keyboard lights).
The power management circuit CHAPS provides protection against overvoltages, charger failures and pirate chargers etc. that could otherwise
cause damage to the phone.
Signal
name
VBATTBattery
From
To
RF/UIF
Table 2. DC Characteristics of PWRU signals
ParameterMini-
mum
Voltage3.03.65.0/5.3 V
Current3500mA
Typi-
cal
Maxi-
mum
UnitFunction
Supply voltage for RF
and UIF
XRESPSA
MCU,NAST A,UIF
Page 2 – 14
Logic high ”1”0.7*VLVLVPSA is Power On
Mode
Logic low ”0”00.3*VL VPSA is Power Off or
Reset Mode
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CHAPS
S
d
NHX-7
Technical Documentation
Table 2. DC Characteristics of PWRU signals (continued)
Signal
PSA
MCU
PSA
MCU
To
Logic high ”1”VL–0.5VLVCutoff limit 5.0 V
Logic low ”0”00.4VCutoff limit 4.6 V
Logic high ”1”0.7*
Logic low ”0”01.2VPower On switch
Logic high ”1”VL–0.5VLVWatchdog counter not
Logic low ”0”00.4VWatchdog counter re-
Logic high ”1”0.7*VLVLVPSA is in Power On
Logic low ”0”00.3*VL VPSA is in Power Off or
name
LIMMCU
XPWRONUIF
XPWR
OFF
PWRONPSA
Baseband Module JP3
ParameterFrom
Minimum
VBAT
Typi-
cal
mum
VBATVPower On switch
open
closed
reset
set ”1” –> ”0”
Mode
Reset mode
FunctionUnitMaxi-
PSBS_EN
(Phone
upporte
Battery
Save)
HPD_ENNAST A
VTX_ENAMCU
VBATSWPSA
VCHARGPSA
ICHARAMPLIFI-
NASTA
PSA
PLL circuit
PSA
MCU
MCU
ER
MCU
Logic high ”1”2.02.90VVRX Enabled
Logic low ”0”00.5VVRX Disabled
Logic high ”1”2.02.90VHarware power down
disabled on PLL circuit
Logic low ”0”00.4VHardware power down
enabled on PLL circuit
Logic high ”1”VL–0.5VLVTX VCO and synthe-
sizer powered on
Logic low ”0”00.4VTX VCO and synthe-
sizer powered off
Voltage02.45V
VBATSW/VBAT di-
vision ratio
Voltage02.8V
VCHRSW switch
resistance
Voltage02.90VCharger Current Mea-
0.4360.450.464
00.251.0Kohm
Switched internally di-
vited VBA T voltage
Switched Charger volt-
age
surement over the
shunt resistor.
TXDMCU
PSA
Original 10/98
Logic high ”1”VL–0.5VLVM2BUS data output,
PSA M2BUS output is
in high–Z state.
Logic low ”0”00.4VM2BUS data output,
PSA M2BUS output is
LOW
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MCU
PSA
ACP–9
l
PAMS
Baseband Module JP3
Table 2. DC Characteristics of PWRU signals (continued)
Signal
name
To
RXDPSA
CSWMCU
Battery charging
Acceptable chargers are detected by the software. The absolute maximum input voltage is 30V due to the transient suppressor that is protecting the charger input. At the phone end there is no difference between a
plug–in charger or a desktop charger. The DC–jack pins and bottom connector charging pads are connected together inside the phone. The
charging block diagram is below.
Technical Documentation
ParameterFrom
Minimum
Logic high ”1”2.02.90V
Logic low ”0”00.5V
Logic high ”1”2.02.90V
When a charger is connected, the CHAPS is supplying a startup current
minimum of 130mA to the phone. The startup current provides initial
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Technical Documentation
Baseband Module JP3
charging to a phone with an empty battery. The startup circuit charges
the battery until the battery voltage level reaches 3.0V (+/– 0.1V) and the
PSA releases the PURX reset signal and program execution starts.
Charging mode is changed from startup charging to PWM charging that is
controlled by the MCU software. If the battery voltage reaches 3.55V
(3.75V maximum) before the program has taken control over the charging, the startup current is switched off. The startup current is switched on
again when the battery voltage has decreased to 100mV (nominal).
Table 3. Startup characteristics
ParameterSymbolMinTypMaxUnit
VOUT Start– up mode cutoff limitVstart3.453.553.75V
VOUT Start– up mode hysteresis
NOTE: Cout = 4.7 uF
Start–up regulator output current
VOUT = 0V ... Vstart
Vstarthys80100200mV
Istart130165200mA
Battery overvoltage protection
Output overvoltage protection is used to protect phone from damage.
This function is also used to define the protection cutoff voltage for different battery types (Li or Ni). The power switch is immediately turned OFF if
the voltage in VOUT rises above the selected limit VLIM1 or VLIM2.
Table 4. VLIM characteristics
ParameterSymbolLIM inputMinTypMaxUnit
Output voltage cutoff limit (dur-
ing transmission or Li–battery)
Output voltage cutoff limit (no
transmission or Ni–battery)
VLIM1LOW4.44.64.8V
VLIM2HIGH4.85.05.2V
The voltage limit (VLIM1 or VLIM2) is selected by logic LOW or logic
HIGH on the CHAPS (N101) LIM– input pin. Default value is lower limit
VLIM1.
When the switch in output overvoltage situation has once turned OFF, it
stays OFF until the the battery voltage falls below VLIM1 (or VLIM2) and
PWM = LOW is detected. The switch can be turned on again by setting
PWM = HIGH.
Original 10/98
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Baseband Module JP3
VCH
VCH<VOUT
VOUT
VLIM1 or VLIM2
SWITCH
ONOFF
Technical Documentation
t
t
ON
PWM (32Hz)
Figure above: Battery overvoltage protection
Battery removal during charging
Output overvoltage protection is also needed in case the main battery is
removed when a charger connected or a charger is connected before the
battery is connected to the phone.
With a charger connected, if VOUT exceeds VLIM1 (or VLIM2), the
CHAPS turns switch OFF until the charger input has decreased below
Vpor (nominal 3.0V, maximum 3.4V). The MCU software stops the charging (turn off PWM) when it detects that the battery has been removed.
The CHAPS remains in protection state as long as the PWM stays HIGH
after the output overvoltage situation has occurred.
2. VOUT exceeds limit VLIM(X), switch is turned immediately OFF
3.3VOUT falls (because no battery) , also VCH<Vpor (standard chargers full–rectified
4. Software sets PWM = LOW –> CHAPS does not enter PWM mode
5. PWM low –> Startup mode, startup current flows until Vstart limit reached
6. VOUT exceeds limit Vstart, Istart is turned off
7. VCH falls below Vpor
ON
OFF
2
output). When VCH > Vpor and VOUT < VLIM(X) –> switch turned on again (also PWM
is still HIGH) and VOUT again exceeds VLIM(X).
5
4
Figure above: Battery removal during charging
Different PWM frequencies ( 2Hz and 32 Hz)
When a travel charger (2– wire charger) is used, the power switch is
turned ON and OFF by the PWM input when the PWM rate is 2Hz. When
the PWM is HIGH, the switch is ON and the output current Iout = charger
current – CHAPS supply current. When PWM is LOW, the switch is OFF
and the output current Iout = 0. To prevent the switching transients inducing noise in audio circuitry of the phone soft switching is used.
6
7
t
The performance travel charger (3– wire charger) is controlled with PWM
at a frequency of 32Hz. When the PWM rate is 32Hz CHAPS keeps the
power switch continuously in the ON state.
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Baseband Module JP3
SWITCH
PWM (2Hz)
SWITCH
Technical Documentation
ONONONOFFOFF
ON
PWM (32Hz)
Figure 3. Switch control with 2Hz and 32 Hz frequencies (in this case 50% duty cycle)
Charger Current measurement
The charging current measurement is based on the reading of differential
voltages over the shunt resistor at the CHAPS output lines. The voltage is
measured and amplified by a differential amplifier and it is carried to the
MCU A/D converter. Measurement area is up to 1400 mA and 1 A/D bit
equals 1.85 mA. The charging current calibration is done with 0 mA and
500 mA in production test line. When charger is connected the current
measurement connection is activated. The A/D–conversion result and
charging current can be calculated from equations :
A/D readout = 1024 * V
Charging current:
I=(V
ICHAR
– V
(0mA)) * (500mA/(V
ICHAR
ICHAR
/ VREF
(500mA) – V
ICHAR
ICHAR
(0mA))
whereVREF=2.82 V
Page 2 – 20
V
ICHAR
= voltage in ICHAR line
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ICHAR
NHX-7
Technical Documentation
NameMinTypMaxUnitNotes
V
ICHAR
From Charger input line
0.460.690.92V
163250334A/D
1.221.441.65V
443522598A/D
1.982.192.39V
718795867A/D
Baseband Module JP3
Table 5. Charger current measurement
Charging current is 0 mA. ( Calibration point )
Charging current is 500 mA. ( Calibration point )
Charging current is 1000 mA.
680k
100k
0R22
CHAPS
Ichar
Battery identification
Different battery types are identified by a pull-down resistor inside the battery pack. The BSI line inside transceiver has a 22k pull-up to VA. The
MCU can identify a battery by reading the BSI line DC–voltage level with
a MCU (D201) A/D–converter.
22k
100k
680k
3k9
12k
+VA
Figure 4. Charger current measurement
1u
Ichar
A/D
conv.
MCU
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Baseband Module JP3
Table 6. Battery Identification
NameMinTypMaxUnitNotes
BSI
02.8VBattery size indication
22k pullup resistor to VA in phone
14.21515.8kohmIndication of a BMS–2V vibra battery (900mAh
9.51010.5kohmIndication of a BMS–2S battery (900mAh NiMH)
373941kohmIndication of a BLS–2 battery (900mAh LiIon)
48.55153.5kohmIndication of a BLS–4 battery (1600mAh LiIon)
–55%Indication resistor and pullup resistor tolerance
Technical Documentation
NiMH)
BVOLT
BATTERY
BTEMP
2.8V
TRANSCEIVER
BSI
R
s
BGND
Battery voltage measurement, VBATSW
Battery voltage can be measured up to 6.27 V from the VBATSW line.
The absolute accuracy is low because of the voltage reference and
A/D–converter +/– 8 LSB accuracy . This battery voltage measurement
offset error must be calibrated with input voltage 4.1 V. The A/D conversion result can be calculated from equation:
A/D readout = 1024 * (VBAT* ( 0.45)) / VREF VREF=2.82 V
For example:
4.1 Vresults670 = 29Dh
3.6 V results 588 = 24Ch
3.0 V results490 = 1EAh
22k
10k
10n
BSI
A/D
Conv.
MCU
Charger voltage measurement, VCHARG
Charger voltage can be measured up to 17.00 V from VCHARG line. The
absolute accuracy is low because of the voltage reference and A/D–con-
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Technical Documentation
Baseband Module JP3
verter +/– 8 LSB accuracy. The A/D–conversion result can be calculated
from equation :
A/D readout = 1024 * (VCHARG*(10/60.3)) / VREF VREF=2.82 V
For example:
8.4 Vresults506 = 1F9h
Battery temperature
The battery temperature is measured with a NTC inside the battery pack.
The BTEMP line inside transceiver has a 100k pullup to VA. The MCU
can calculate the battery temperature by reading the BTEMP line DC–
voltage level with a MCU (D201) A/D–converter.
Table 7. Battery temperature
PinNameMinTypMaxUnitNotes
3BTEMP
02.90VBattery temperature indication
100k pullup resistor to VA in phone
Battery package has NTC pull down resis-
tor:
47k +/–5%@+25C , B=4050+/–3%
–11%100k pullup resistor tolerance
BATTERY
R
T
NTC
BVOLT
BSI
BTEMP
BGND
TRANSCEIVER
VA
100k
10k
1k
BTEMP
MCU
CSW
10k
VibraPWM
ON/OFF
Battery temperature monitoring schematic diagram above
Based on 47k ± 5 % NTC with B = 4090 ±1.5 %. Without any alignment,
with that and 1 % pull–up resistor, ± 2.5 C accuracy is achieved between
– 20 and +60 C (± 3.5 C @ –40 ... +85 C).
Original 10/98
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Baseband Module JP3
Table 8. Battery temperature vs. AD readings and NTC resistance
A vibra alerting device is used for giving silent signal to the user of an incoming call. The device is not placed in the phone but it will be added to a
special battery pack. The vibra is controlled with a PWM signal by the
MCU via the BTEMP battery terminal.
A 15kohm BSI resistor is needed to detect the vibra battery. It is only used
to enable vibra selection in user menu. When alerting, VibraPWM signal
is delivered to battery.
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Technical Documentation
Vibra
22k
10n
100n
BATTERY
R
T
47k
NTC
VBAT
BSI
BTEMP
GND
VA
100k
R3
1k
Baseband Module JP3
TRANSCEIVER
10k
BTEMP
MCU
CSW
10k
VIBRAPWM
ON/OFF
Figure 5. Vibra battery
Supply voltage regulators and controlling
The heart of the power distribution is the PSA asic. It includes all the voltage regulators and feeds power to the whole system. The baseband digital and analog parts are powered from the VL and VA regulators which
provide the 2.82 V baseband supply. The baseband regulators are active
when the phone is powered on.
The PSA includes also two 2.82 V regulators (VRX and VTX) providing
power to the RF section. These regulators can be controlled by the direct
control signals from the MCU. The VRX regulator can also be controlled
by the signal from the NASTA.
– VTX_ENA ( from MCU ) controls VTX regulator
– PSBS_ENA ( from NASTA ) controls VRX regulator
In addition PSA includes also functions listed bellow:
– Buffer for the M2BUS.
The buffer translates the logical input signal to open–drain output.
Table 10. M2BUS buffer truth table
Original 10/98
InputOutput
LOWLOW
HIGHZ
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Baseband Module JP3
– Power on/off and reset logic. The Power off logic can be used as a
watchdog.
– Supply voltage monitor and automatic reset/power–off.
VBATSW is internally divided and buffered battery voltage output. The
A/D –converter input monitoring the battery voltage can be connected
here. The circuit monitors the voltage at the VBAT input and forces
the circuit to Reset if the voltage level is below allowed limit voltage,
VBATcoff–. A hysteresis is included to prevent oscillation between different states.
– Battery charger detection.
Externally divided charger voltage VCHAR goes through PSA internal
switch to VCHARSW output. The A/D –converter input monitoring the
charger voltage can be connected here.
– Automatic on–chip current limiting
– On–chip thermal shutdown, which protects PSA from overheating.
Thermal shutdown includes hysteresis in order to prevent oscillation
during the thermal protection.
Technical Documentation
Table 11. Regulators VA and VL characteristic
Parameter
Test Conditions
Output VoltageVL, V A2.732.822.90V
Output current of the regulator
(all regulators enabled)
Quiescent current
VL:Iload = 0mA
Iload = 40mA
VA:Iload = 0mA
Iload = 100mA
Quiescent current
Tamb = +25C, VBAT=3.6V
VL:Iload = 0mA
Iload = 40mA
VA:Iload = 0mA
Iload = 100mA
Quiescent current in Power–Off
VL
VA
Line regulation: VL, VA
IoutVL = 40mA,
IoutVL = 100mA,
3.25VVBAT5.2V
SymbolLimits
MinTypMax
Iout
Iout
Iq
Iq
Iqoff
VL
line
VL
VA
, VA
line
040
0100
200
220
200
220
110
130
110
130
6
15
20mV
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Load regulation: VL, VA
0mAIloadVL40mA,
0mAIloadVA100mA,
3.25VVBAT5.2V
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VL
load
, VA
load
30mV
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Table 11. Regulators VA and VL characteristic (continued)
0mAIloadVL40mA,
0mAIloadVA100mA
f = 10Hz ... 10kHz
Settling time
Cload=1mF20%
load current 0mA
ts
Note 2
160ms
Note 1: Voltage deviation (V) is the output voltage overshoot in tran-
sient response. Recovery time (Trec) is the time from the beginning of the
transient response to the time point when the regulator output voltage first
crosses the final stable value after overshoot.
Note 2: Settling time is defined from the time point of mode change Power–Off to Reset to the time when regulator output voltage is within 5% of
the final value.
Table 12. Regulators VRX and VTX characteristic
Parameter
Test Conditions
Output VoltageVRX, VTX2.732.822.90V
SymbolLimits
MinTypMax
Unit
Output currents of the regulators
(all regulators enabled)
Quiescent current
VRX:Iload = 0A
Iload = 50mA
VTX:Iload = 0A
Iload = 60mA
Original 10/98
Iout
Iout
Iq
VRX
VTX
0.0550
0.0260
320
360
320
360
mA
mA
mA
mA
mA
mA
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Table 12. Regulators VRX and VTX characteristic (continued)
Test Conditions
Quiescent current
Tamb = +25C, VBAT=3.6V
VRX:Iload = 0A
Iload = 50mA
VTX:Iload = 0A
Iload = 60mA
Quiescent current in Power–Off
VRX
VTX
Line regulation: VRX, VTX
IoutVRX = 50mA,
IoutVTX = 60mA,
3.25VVBAT5.2V
Load regulation: VRX, VTX
50mAIload
20mAIload
3.25VVBAT5.2V
VRX
VTX
50mA,
60mA,
SymbolParameter
Iq
Iqoff
VRX
VRX
line,
load,
VTX
VTX
line
load
Technical Documentation
UnitLimits
MinTypMax
180
195
180
195
14
17
20mV
30mV
mA
mA
mA
mA
mA
mA
Line transient: VRX, VTX
AC=0.5Vpp square wave
Slew rate = 50 mV/ms
f = 500Hz .... 2kHz
3.5VVBAT5.2V
Load transient: VRX, VTX
Iload
50mA to 50mA,
VRX
IloadVTX 20mA to 60mA in 10ms
3.25VVBAT5.2V
Current limit (VRX,VTX = 0V)
VRX
VTX
Power supply ripple rejection
3.25VVBAT5.2V
50mAIload
20mAIload
VRX
VTX
50mA,
60mA,
f = 10Hz.....10kHz
f = 10Hz.....50kHz
f = 10Hz.....100kHz
Settling time,
Cload=1mF20%
load current 0mA
VRX
linetr,
V
Trec
Note 1
I
lim
PSRR
ts
Note 2
VTX
VRX,VTX
linetr
40dB
40
20
75225
90270
50
40
35
mV
ms
mA
mA
dB
dB
dB
100ms
Note 1: Voltage deviation (V) is the output voltage overshoot in tran-
sient response. Recovery time (Trec) is the time from the beginning of the
transient response to the time point when the regulator output voltage first
crosses the final stable value after overshoot.
Note 2: Settling time is defined from VTX_ENA/VRX_ENA rise to the time
when regulator output voltage is within 5% of the final value.
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Baseband Module JP3
Operation modes
The circuit has three operational modes: Power–Off, Reset and Power–
On. The additional modes are the Protection mode and Battery disconnected (VBAT < VRth, master reset threshold). Respective conditions of
the external signals are described in the NO TAG.
Table 13. Operational modes
MODEPURXVRX_ENAVTX_ENAVLVAVRXVTXVBATSW VCHAR
–SW
Power–
Off
Reset
Power–
n
LOWXXZZZZZLOW
LOWLL2.8VZZZZLOW
LOWHH2.8V2.8V2.8VZZLOW
HIGH
LL2.8VZZVBATSWVCHARXPWRONX
HH2.8V2.8V2.8VVBATSWVCHARXPWRONX
PWRON-
BUFF
NOTE: VBATSW and VCHARSW are controlled by internal VSW_ENA–
signal during power–on.
NOTE: PWRONBUFF is an inverted (and buffered) PWRONX. A logic
LOW level at PWRONX (active LOW) will force a logic HIGH level at
PWRONBUFF.
Power–Off Mode
In order to be in Power–Off mode VBAT must be above VRth.
During Power–Off mode PURX is at logical low level. VA, VL, VRX and
VTX regulators are disabled and in high–Z low output state.
Entering Power–Off Mode
The PSA contains a watchdog counter that is reset by writing ”1” – ”0” sequence to input PWROFFX.
The circuit goes to Power–off mode from Power–On after delay Toff if
watchdog has not been reset during this time.
The other possibility to enter the Power–Off is from Reset, if the PSA can
not enter Power–On mode because VBATcoff+ is not reached. This
means that watchdog elapses before the microcontroller is able to produce a pulse to PWROFFX. If charger is present (VCHAR>VCHARth),
transition from Reset to Power–Off can not occur but the circuit stays in
Reset mode as long as battery has been charged above VBATcoff+.
The circuit goes to battery disconnected mode if battery voltage drops below master reset threshold (VRth–).
For testing purposes the watchdog can be disabled and reset by grounding the WD_DISX pin. In normal use it can be left floating (internal pull
up).
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Charging in Power–Off
Charging is not possible in Power–Off. Connecting a charger during Power–Off generates a rising edge on VCHAR input and the circuit enters Reset mode. Circuit stays in Reset as long as the battery is charged to the
limit VBATcoff+.
If the watchdog elapses during Power–On when charger is connected,
the circuit goes to Power–Off. Because charger detection is level sensitive, charger is detected and the circuit goes via Reset mode to Power–
On mode.
Reset Mode
The circuit goes into Reset mode from Power–Off when:
– the battery voltage is initiated (master reset) or
– logic low voltage in PWRONX is detected or
– charger voltage becomes available or
Technical Documentation
– when recovering from Protection mode
In Reset mode the VL and VA outputs are activated by an internal enable
signal. The VRX and VTX have external enable inputs VRX_ENA and
VTX_ENA. VBATSW and VCHARSW are disabled and PURX is LOW.
The circuit leaves the Reset mode after a delay Trd for Power–On if VBAT
> VBATcoff+. Watchdog is reset when Power–On mode is entered.
The circuit goes into Reset mode from Power–On when the battery voltage VBAT drops below VBATcoff–.
VBAT is monitored internally, hence if voltage VBAT drops below the
threshold (determined by internal resistors), transition from Power–on to
Reset mode is done. If VBAT doesn’t rise back above reset release limit
in time T
the Watchdog elapses and the circuit powers off.
off
To avoid PSA going to RESET mode due to fast transient, transition from
Power–On to Reset mode is not done if VBAT is below VBATcoff– for
shorter time than threshold detection delay T
dd.
The circuit leaves the Reset mode after a delay Trd if VBAT > VBATcoff+.
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VBAT
VBATcoff +
VBATcoff
VBATcoff –
PURX
Figure 6. Threshold detection delay Tdd and PURX reaction time T
Baseband Module JP3
T>TddT<Tdd
TddTrr
rr
VBATcoff +
VBATcoff
VBATcoff –
Power–On Mode
In Power–on mode all the functions are active. VBATSW and VCHARSW
outputs are activated by the internal enable signal VSW_ENA. PURX is
high in Power–On.
From Power–On mode the circuit goes to Power–Off mode after a delay
Toff (watchdog delay set by an external capacitor Cosc) if no writing sequence to PWROFFX from logical high level to low level has detected
during this time.
VBAT
Hyst +
Hyst –
Power–onResetReset
Figure 7. Reset limits and hysteresis
In Power_on mode the circuit does not react on PWRONX pulse i.e.
the circuit must be switched off by the system by not updating the watchdog writing in time Toff.
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AUDIO
Audio Control
Most of audio control is performed by the NASTA 4.5 IC, which contains
audio and signalling processors. Internal and headset microphones signals are connected to same input of the NASTA via bilateral switch. The
EAR signal of the NASTA is fed to an external amplifier ( LM4862 ) with a
dual ended type output. The XEAR signal of NASTA is carried to the transistor buffer.
Internal microphone
The internal microphone is connected to the bottom connector by means
of mounting springs for automatic assembly. The microphone requires a
bias current to operate. The bias current is generated in the NASTA.
Technical Documentation
Internal earphone
The internal earphone is connected to the UI board. The low impedance,
dynamic type earphone is connected to a differential output of the audio
amplifier ( LM4862 ). Keypress and user function response beeps are
generated with the internal earphone.
Buzzer
Alerting tones and/or melodies as a signal of an incoming call are generated with a buzzer that is controlled with a PWM signal by the MCU. The
buzzer is a SMT device and is placed on the UI board.
Headset detection
The external headset device is connected to the system connector, from
which the signals are routed via bilateral switch to the NASTA microphone
input and via transistor buffer to the NASTA XEAR output. In the XMIC
line there is a 47 k
phone is low compared to the transceiver pullup. When there is no call
going the XMIC is pulled up. When a headset is connected, the XMIC is
pulled down. The XMIC is connected to HSCON line which is one of
MCU’s A/D inputs. MCU is scanning the HSCON line and it detects both
connection and disconnection. When headset is detected the headset microphone will get the DC bias current from transistor V740.
Ω pullup in the transceiver. Resistance of the micro-
Headset Switch detection
In the XEAR line there is a 47 kΩ pullup in the transceiver. Resistance of
the earphone is low compared to the transceiver pullup. When a remote
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Technical Documentation
control switch of the headset is open, there is a capacitor in series with
the earphone, so the XEAR is pulled up by the phone. When the switch is
closed, the XEAR is pulled down via the earphone. The XEAR is connected to HEADSW which is one of MCU input line. So both press and
release of button gives an interrupt.
NASTA ASIC
The NASTA 4.5 is a single chip audio/signalling processor in a 64 TQFP
package for AMPS and TACS systems.
Main features
– Single chip 2.8 V supply and Internal signal ground generation
– 8 bit parallel interface with pull ups
– Low noise microphone amplifier
– Input for a handset microphone or an accessory
– Microphone sensitivity compensation +4.8/–4.2 dB range (4 bits)
– Compandor
– RX and TX filters
– Tx hard limiters
– Internal reference compensation +1.00/–0.75 dB range(3 bits)
– Summing stage for voice and signalling data and SAT and ST
– Transmitter compensation amplifier with +3.75/–3.75 dB range (4 bits)
– TX speech max deviation trimmer with +1.75/–1.75 dB range (3 bits)
– Receiver compensation amplifier with +3.75/–3.75 dB range (4 bits)
– Volume control amplifier with –20/+17.5 range (4 bits)
– Earphone amplifier with drive capability for ceramic earpiece
– Buffered output for a handset or an accessory
– Audio mute switches
– Dual and single tone multifrequency generator
– 4.8 MHz oscillator/PLL–VCO circuitry for clock generation
– Driver for buzzer amplifier
– Hardware implemented hands free
– Synchronization to the received wide band signalling from base station
– Data validity detection
– Continuous word sync validity check
– Manchester encoding and decoding
– 3/5 majority vote and bch decoding for the received messages
– SAT filtering, detection and regeneration
– ST signal generation
– Transmitted data,ST and SAT filtering
– Programmable output clock with clock stop
– Low power consumption modes, Extended standby drivers
– Programmable timer
– AFC function
Baseband Module JP3
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Table 14. Pin list of the NASTA ASIC
Pin noSymbolPin typeNotes
1VDD1+ 2.8 V Supply voltage, digital
2XRDDIN/puRead control signal, active state LOW, pull–up > 50 k
3XCSDIN/puChip select signal, active state LOW, pull–up > 50 k
4A3DIN4–bit address bus, MSB
5A2DIN4–bit address bus
6A1DIN4–bit address bus
7A0DIN4–bit address bus, LSB
8D7DIO8–bit bidirectional data bus MSB
9D6DIO8–bit bidirectional data bus
10D5DIO8–bit bidirectional data bus
11D4DIO8–bit bidirectional data bus
12D3DIO8–bit bidirectional data bus
Technical Documentation
13D2DIO8–bit bidirectional data bus
14D1DIO8–bit bidirectional data bus
15D0DIO8–bit bidirectional data bus LSB
16VDD2+ 2.8 V Supply voltage, digital
17TOUTDOUTTest Output, Digital
18XCLRDINHW reset input, active state LOW
19TMODEDIN/pdTest mode selection, pull–down > 50 k
20TSELDIN/pdTest select, pull–down > 50 k
21XINTDOUTInterrupt request, active state LOW
22SYNBIASDOUTSynthetizer on/off control, HIGH = power on
23RXBIASDOUTReceiver on/off control, HIGH = power on
24IFAINIF input
25VSS20 V Supply voltage, digital ground
26VSA20 V Supply voltage, analog
27DAFAINSignal input
28FILOAOUTRxfilter output
29EXPIAINExpander input
30EAMPBOAOUTExpander Amplifier B output
31EWCIAINExpander Window Comparator input
32EXPOAOUTExpander output
33VDA2+ 2.8 V Supply voltage, analog
34VOLIAINVolume control ampl. input (Volume)
35XEARAOUTBuffered output for handset or an accessory
36EVGNDAINEarphone driver virtual ground
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Table 14. Pin list of the NASTA ASIC (continued)
NotesPin typeSymbolPin no
37EARMAOUTEarphone driver output
38EARPAOUTEarphone driver output
39CWCIAINCompander window control input
40DACOAOUTDA converter output
41SIDEARAOUTSidetone output
42REFAINInternal analog signal ground 1.40 V
43MICAINMicrophone amplifier input
44BIMICAOUTMicrophone bias current output
45CMICAINMicrophone current stabilization capacitor
46XMICAINAudio input for a handset or an accessory
47ATTOAOUTTransmit HF attenuator output (TXATT)
48VDA1+ 2.8 V Supply voltage, analog
Baseband Module JP3
49COMIAINCompressor input
50COMOAOUTCompressor output
51EMPIAINPre emphasis input
52EMPOAOUTPre emphasis output
53LPINAINTransmit lowpass filter input
54ATSTAOUTAudio Filter Test output
55MODAOUTTransmit path output
56VSA10 V Supply voltage, analog
57VSS10 V Supply voltage, digital ground
58BUZZAOUTBuzzer output
59ATOUTAOUTTest pin
60CLKOUTCOUT14.85 MHz system clock output
61CLKINCIN14.85 MHz system clock input
62CLKLCDDOUTClock signal for LCD, 80 kHz, tristate when
MCS1=MCS2=0
63CLKMCUDOUTClock signal for MCU, 4.8 MHz or 2.4 MHz
64XWRDIN/puWrite control signal, active state LOW, pull–up > 50 k
Transmit (TX) audio signal path
The TX audio signal is processed in the NASTA circuit and fed via the
MOD line to the TX synthesizer on SYNTHESIZER module.
The NASTA ASIC contains the following stages for TX signal processing:
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MICAM:
The signal input level from the microphone is 2.4mVrms nom.,
max. 40mVrms. The signal fed to this stage and amplified up to
200 mVrms.
TXMUX + TXAAF:
TX source selection (exmic/mic/dmmf/muted). Txaafil prevents
aliasing in TXBP filter.
TXATT:
TXATT is a hands free attenuator. Maximum attenuation is selectable from four levels: –30, –27, –24 or –21 dB.
MICTRI:
MICTRI is for different microphone (phone microphone, headset and handset etc.) sensitivity compensation. It is used also
for dtmf level setting. Gain 16 levels, step 0.6 dB, range –4.2 –
+4.8dB.
Technical Documentation
BANDPASS:
Tx bandpass filter (300 – 3000Hz) filters high freq noise and
low freq hum.
COMPR:
It compresses speech dynamic area to avoid noise at tx and
radio path. It is a amplitude compressor and ratio is 2:1 in dB
scale. It can be bypassed for measurement or dtmf purposes.
LIM1:
Hard limiter. It cuts the signal transients at +–439 mVpp levels.
PRE–EMP:
Pre–emphasis filter gives +6 dB/oct emphasis at the frequency
band of 300 – 3000Hz.
LIM2:
Hard limiter. it cuts the signal transients at +–439mV levels.
TXLP:
The corner frequency of tx lowpass filter is 3000 Hz. Amplitude
attenuation is 12 dB/oct after the corner point. Filter includes
notch at 6 kHz.
TXTRI:
TXPOSTFIL:
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TXTRI is for nominal deviation tuning. Gain 8 levels, step 0.5
dB, range –+1.75dB.
Postfil eliminates filter clock.
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SUM:
SUM block makes d/a conversion of all generated signals.
Then it sums all used signals and speech together.
WTRFIL:
This block is a lowpass filter for SAT, ST and data. Transmitter
Compensation Amplifier is these too. Gain 16 levels, step 0.5
dB.
WPOSFIL:
WPOSFIL filters out the replicates of the output spectrum
around WTRFIL clock frequency and its harmonics.
RECEIVE (RX) AUDIO SIGNAL PATH
The NASTA contains the following stages for RX signal processing:
RXTRI:
Baseband Module JP3
RXTRI is for demodulation sensitivity compensation. Gain 16
levels, step 0.5 dB, range –+3.75dB.
RXAAF:
RX aa filter filters out noise and other high frequency components from the incoming signal. It prevents aliasing in SATFIL
and RXFIL.
RXMUX+AAFIL:
Rxmux selects speech from DAF–pin or DTMF from generator
or all mute. Aafil prevents aliasing in RXFIL.
DEEMP+ RXFIL:
Rx filter filters out high frequency noise and low frequency
hum. It has de–emphasis –6 dB/oct for the received speech
signal (300–3000). There is a notch at 6kHz.
EXP:
Expands the speech dynamic back to normal. It is a amplitude
expander and ratio is 1:2 in dB scale. It can be bypassed for
measurement or DTMF purposes.
VOL:
RXATT:
Original 10/98
VOL is for earphone or accessory speaker/earphone volume
control. Volume Control Amplifier. Gain 16 levels over –20 to
+17.5 dB in 2.5 dB steps.
RXATT is a hands free attenuator. Maximum attenuation is selectable from four levels: –30, –27, –24 or –21 dB.
Hands free controller (HF CONTR) measures peak–to–peak
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level of the received audio and controls gains of the transmit
and receive attenuators as a function of measured signal level.
EAR:
The earpiece amplifier is a single input, differential output amplifier for a ceramic earpiece.
ACC:
Buffer for accessory line is capable of driving high capacitive
load. Gain and response of the buffer are fixed.
SIDEAR:
Audio output to be summed with EAR amplifier. Earphone amplifier gives extra +6dB gain to SIDEAR.
Transmitting data path
The data to be transmitted is loaded into the transmitting register DTR. From
the DTR register the 8 bit data is fed into PISO–register , which changes the
8–bit data bytes to serial form. The serial NRZ–data is fed to the Manchester
encoder (MANEN) and then to the summing block (SUM). Timing signals
needed for data transmission are generated internally.
Technical Documentation
Receiving data path
The data from anti alias filter is connected through the comparator (DATAC) to a Manchester decoder (MANDEC) which decodes Manchester
data to the NRZ (Non Return to Zero) format. The modem is synchronized to the receiving data with a digital phase locked loop (DPLL) and a
word synchronization detection block (RECBUF). Data validity (DATVAL)
is continuously detected (DFLAG), and this information is used internally
when word synchronization detection is accepted. The serial data from
the Manchester decoder is 3/5 majority voted (VOTE), BCH–decoded
(BCH), corrected (CORR) and shifted to the receiver register (RREG).
The final data word consists of 28 bits. 4 status bits are added to RREG
to make up a 32 bit register, which is read in 8 bit bytes via status multiplexer (SMUX). The Receiver timing block (RECTIM) extracts the data
from the received frames on control and voice channels and generates
the data transfer interrupts (WFLAG). It also generates the repeat interrupts RFLAG. It maintains bit and word synchronization during different
frames and passes the synchronization staus (SFLAG) forward to the status register. On FOCC (Forward Control Channel) signalling mode it separates the multiplexed data streams (channel A and B) and Busy/Idle–information (XBOI). On FVC (Forward Voice Channel) signalling mode it extracts data repeats from voice channel message frames.
IF
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The Intermediate Frequency Counter (IFCTR) is located on the modem
to measure the frequency of IF signal.
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Technical Documentation
AFC
The AFC makes the synthesizer fine tuning. It can be used for channel sidestep also.
The AFC DA–converter output DC level tunes the RF oscillator (VCXO).
ST signalling tone generator
The signalling tone generator is two bit D/A converter that produces an 8
kHz sine wave. The tolerance of the frequency is +– 1 Hz.
Receiving SAT path
The SAT signal is filtered and amplified with a bandpass filter (SATFIL).
SATFIL (Supervisory Audio Tone input FILter) is a 6 kHz bandpass filter.
It separates the 5970, 6000, 6030 Hz SAT signal from the incoming voice
and noise during voice channel operation. The signal is converted to digital square wave signal with a comparator (SATCOMP). The SAT detection
is executed with a digital PLL/detection circuitry (SATDET). The logic
compares the SCC code given by control register bits SCC0 and SCC1 to
the incoming SAT frequency and indicates the result with a status register
bit (SATVAL). The regenerated SAT is then fed to summing block (SUM).
Baseband Module JP3
Clock divider
The main function of the the NASTA baseband clock generator is to generate a 4.8 MHz clock signal with selectable frequency shift (approx. 80
ppm) from 14.85 MHz master clock.
NHX–7 employs a 2.4 MHz clock for MCU (CLKMCU) and a 80kHz kHz
clock for LCD display CLKLCD.
Standby Modes for Power Saving
The normal standby mode (receiver and synthetizer are continuously ON,
audio paths OFF) is automatically activated when the circuit is initialized
working in control channel (COXV = 1) and the extented standby is disabled
(ESTDBY = 0).
The extented standby mode (receiver and synthetizer ON/OFF times controlled by the NASTA) is activated when the circuit is initialized working in
control channel, extented standby is enabled and synthesizer and receiver
hardware controls are enabled (COXV=ESTDBY=SPHE=RPHE=1). In extented standby mode the interrupts from control filler messages can be
masked (FIME=1). The maximum number of consecutive received filler
messages without interrupt is 31. After the interrupt the number of masked
interrupts (filler) is available in SRB (RFMC0...4).
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RF Section
Technical Summary
The purpose of the RF sub–module is to receive and demodulate the radio frequency signal from a base station and transmit modulated RF signal to a base station. The RF section comprises the RX–submodule, the
TX submodule and the Synthesizer submodule.
EMC leakage is prevented with sheet metal boxes covering the critical
blocks of the transceiver.
Basic Specification
Technical Documentation
Table 15. Basic Specifications
ParameterValue
RX frequency band917 – 950 MHz
TX frequency band872 – 905 MHz
RX LO frequency band962 – 995 MHz
Duplex spacing45 MHz
Channel numbers 1329...2047, 0...600
Number of channels1320
Channel spacing25 kHz
TX output power6 levels; 6.5 (+2/–4) dBm to 26.5 (+2/–4) dBm
Method of frequency synthesisDual PLL with two UHF signals for RX LO and TX
Frequency controlAFC with +/– 2.5 kHz limits
Receiver typeSuperheterodyne with double IF
Modulator typeFM–modulator
Current consumption, reception50 mA
Current consumption, standby30 mA
Current consumption, transmission550 mA
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Baseband Module JP3
RF Module Characteristics
Maximum ratings
The maximum battery voltage during transmission must not exceed 5.85
V. Higher battery voltages may destroy the power amplifier module.
Table 16. Maximum ratings
ParameterValue
Battery voltage ( Ni–Mh Battery ) nom. 3.6 V, min. 3.1 V, max. 4.6 V
Battery voltage ( Li–Ion Battery ) nom. 3.6 V, min. 3.1 V, max. 4.1 V
Regulated supply voltage 2.82 V +/– 0.09V
Operating temperature range –10 ... +55 deg.C
DC Characteristics
Regulator
The PSA regulator module in the BB unit regulates voltages VA, VRX and
VTX to the fixed 2.82 V level for the RF unit.
Battery Save at Reception Mode
The receiver and receiver synthesizer blocks are switched on/off during
stand–by mode. This switching is controlled by the NASTA – audio module. If the received signal is strong enough, it switches PSA’s VRX_ENA
off for about half of time. This powers down all the receiver blocks and
RX–VCO. Also the synthesizer module is switched to power off mode
during battery save.
Control Signals
The following table describes the RF current consumption with different
status of the control signals. RX and TX synthesizer phase locked loops
are switched on/off by a control byte that is loaded to the PLL circuit.
Table 17. Control Signals and Current Consumtion
VRX_ENA + SW
powerup for RX
synthesizer
HHH550 mAPower Level 2
VTX_ENA + SW
powerup for TX
synthesizer
TXETypical Current
Consumption /mA
Note
HHL70 mA
HLL50 mASynthesizer TX part
has been powered
off
LLL8 mAAll RF parts have
been powered off
Original 10/98
Page 2 – 41
Page 42
Page 2 – 42
Battery
3.6 V
VTX_ENA
Power Distribution Diagram
NHX-7
Baseband Module JP3
Power
Amplifier
Original 10/98
500 mA25 mA
2. TX–
buffer
1.st TX–
Buffer
VTX
2.7 V
10 mA10 mA
TX–VCO
PSA
LNA
VRX
5 mA
2.7 V
1 mA
IF Amp.
VA 2.7 V
10 mA
RX–VCO
10 mA
6 mA / 10 mA
RX on / RX + TX on
VRX_ENA
3 mA
IF CircuitLO Buf f.
PLL
IC
2 mA
VCTCXO
TXE
Technical Documentation
PAMS
Page 43
PAMS
NHX-7
Technical Documentation
Baseband Module JP3
Connections
Connections to Baseband module
Signal NameTypeFunction
AFCAnalog outThe reference oscillator frequency adjust.
DAFAnalog inDemodulated received signal (audio + data)
GNDPowerCommon ground
IFAnalog out2nd IF signal (450 kHz)
MODAnalog outModulation signal for transmitter (audio + data)
RSSIAnalog inReceived signal strength indicator. Voltage measurement.
SCLKDigital outSerial clock for synthesizer. Active state: Rising edge
SDATDigital outSerial data for synthesizer. Active state: High
SLEDigital outSynthesizer latch enable. Active state: Low
HPD_EN
RXS_LDDigital in
TXCPWM outTransmitter power control
TXEDigital outTransmitter enable. Active state: High
TXIAnalog in”TX power on” –indicator
VAPowerRegulated voltage to synthesizer circuit and VCTCXO
VBAT
VRXPowerRegulated voltage to receiver
VTXPowerRegulated voltage to TX–VCO, 1st.TX–LO buffer and power
DC–level0.2...2.3 V
Source impedance56 k (typical)
SCLKSerial clock for synthesizer
Typedigital signal
Pulse width> 1 us
SDATSerial data for synthesizer
Typedigital signal
Pulse width> 1 us
VALUES:
Page 2 – 44
Original 10/98
Page 45
PAMS
NHX-7
Technical Documentation
Serial data for synthesizerSDAT
Control bytex110 011x x001 11xx
Reference divider1188
Divider formulas for RX oscilla-
tor (ch 1329...2047)
Divider formulas for RX oscilla-
tor (ch 0...600)
Divider formulas for TX oscilla-
tor (ch 1329...2047)
Divider formulas for TX oscilla-
tor (ch 0...600)
SLESynthesizer enable
TypeDigital signal
Function0 = synthesizer enabled
Baseband Module JP3
(x = don‘t care bit)
N = 2 ( ch – 1329 ) + 73361
N = 2 ch + 78399
N = 2 ( ch – 1329 ) + 69761
N = 2 ch + 71199
1 = syntheziser disabled
HPD_ENPLL Hardware power down
TypeDigital signal
Function0 = Power down enabled
1 = Power down disabled
RXS_LDRX–Synthesizer lock detect
TypeDigital signal
Function0 = Unlocked
1 = Locked
TXCTransmitter power control
TypePWM signal
FunctionDuty cycle of the TXC signal
defines the TX power level
PWM frequency9.4 kHz
Number of duty cycle steps256
Load impedance> 100 kohm
TXETransmitter on/off control
TypeDigital signal
Function0 = TX off
1 = TX on
Original 10/98
Page 2 – 45
Page 46
NHX-7
PAMS
Baseband Module JP3
TXI”TX power on” –indicator
TypeAnalog signal
Source impedance33 k
Level< 1 V = TX off
VARegulated voltage for synthe-
sizer
Nominal value2.7 V " 4%
Max. current100 mA
VBATBattery voltage
Nominal value3.6 V
Minimum value3.1 V
Absolute maximum4.6 V
Max. current800 mA
Technical Documentation
> 1 V = TX on
VRXRegulated voltage for receiv-
er
Nominal value2.82 V (–0.09V /+0.08V)
Max. current50 mA
VTXRegulated voltage for TX
Nominal value2.82 V (–0.09V /+0.08V)
Max. current60 mA
Antenna
The phone includes a helix antenna. The electrical length of the helix antenna is 3/8 wave length.
Page 2 – 46
Original 10/98
Page 47
PAMS
NHX-7
Technical Documentation
Baseband Module JP3
Functional description of radio sub–module
Block diagram
DAF
RSSI
IF
PHASE SHIFTER
TX VCO
TX LO BUFFER
MOD
SLE
SCLK
SDATA
AFC
VCTCXO 14.85 MHz
TXC
TXE
TXI
HPD_EN
RXS_LD
450 kHz FILTER
IF AMPLIFIER
45 MHz
CRYSTAL FILTER
DIODE MIXER
IF CIRCUIT
TANK CIRCUIT FOR 2.ND LO
UMA 1015AM
SYNTHESIZER IC
LOOP FILTER
RX LO BUFFER
LOOP FILTER
PLL
PLL
TX BUFFER
RX VCO
RF9102
AMPLIFIER MODULE
TX POWER CONTROL
Original 10/98
SAW–FILTER
LNA
ANTENNA
DUPLEX–FILTER
POWER DETECTOR
DIR_COUPLER
Page 2 – 47
Page 48
NHX-7
PAMS
Baseband Module JP3
RF components
Antenna:0660184
Antenna clip:9510480
Duplexer:4512085
45 MHz IF filter:4510129
450 kHz IF filter:4550045
SAW filter:4511034
VCTCXO:4510171
FM detector IC:4349694
PLL IC:4340393
RX VCO:4350113
TX VCO:4350115
Power amplifier:4370099
Receiver
The receiver is a dual–conversion superheterodyne using two intermediate
frequencies, 45 MHz and 450 kHz.
Technical Documentation
The RF signal from the duplexer RX port is applied to the RF amplifier.
Next the signal is filtered with SAW–filter Z321. The filter is followed by a
single balanced diode mixer, which has 6 dB conversion loss.
After that mixer signal is filtered with the crystal filter Z350, which has 15 kHz
bandwidth. Next the IF signal is amplified by V380. From the amplifier the
IF–signal is applied to the second mixer.
The second mixer, the LO buffer transistor, IF amplifier and quadrature
detector are all integrated in the circuit N370. The second LO frequency,
44.55 MHz, is third harmonic of the VCTCXO frequency. LO signal is
realized with tank circuit C372 and L371. After the mixer the 450kHz IF
signal is filtered with ceramic filter Z370. The IF amplifier output signal is
phase shifted by resonance circuit. After this the signal is fed to a quadrature
detector.
Signal DAF is low pass filtered by R372 and C379. The DAF, RSSI and 2nd
IF signal (450 kHz) are fed to the audio/logic unit.
During battery–save mode the voltage VRX is down and all the receiver
blocks and the RX synthesizer are powered down.
RX Synthesizer
The first injection frequency for receiver is generated by a digital phase
locked loop (PLL). The output frequency of the loop (LO) is obtained from
a voltage–controlled oscillator (VCO) G530. The VCO output signal is
amplified by RX–LO–buffer and fed to the receiver mixer . The injection level
required by the receiver mixer is about +3 dBm. In addition, the signal is fed
back to the dualsynthesizer circuit N820.
The overall divisor of the chain is selected according to the desired channel.
Page 2 – 48
Original 10/98
Page 49
PAMS
NHX-7
Technical Documentation
The internal dividers of N820 are programmed with 17 bits, which are
transferred serially on the SDAT (synthesizer data) line from the processor
into an internal shift register also located in N820. Data transfer is timed with
SCLK clock pulses.
The divided frequency is compared with a highly stable reference frequency
by a phase comparator in the PLL circuit. The phase comparator controls the
VCO frequency by means of a DC voltage through the loop filter so as to keep
the divided frequency applied to the phase comparator equal to the fixed
reference frequency.
The reference frequency is 12,5 kHz. This reference frequency is obtained
from voltage controlled crystal oscillator (VCTCXO). Oscillator frequency is
14.85 MHz. The VCTCXO frequency is divided by 1188.
RX loop filter
Phase comparator output is pin 3. If the VCO (G530) frequency is too high,
the output goes low and discharge integrator capacitor C521. After this, the
DC control voltage and the VCO frequency will decrease.
Baseband Module JP3
If the VCO frequency is too low, the output goes high and charge the
integrator capacitors C522 and C523. Thereafter the DC control voltage and
the VCO frequency will go up.
Output pulses from the phase detector have to be supplied to the loop filter.
The function of the integrator is to convert positive and negative pulses to DC
voltage. The remaining ripple and AC components are filtered in the lowpass
filter.
TX Synthesizer
The transmitter synthesizer generates a frequency modulated transmitter
signal for the transmitter section. The modulated TX injection frequency is
generated in TX–VCO (G430). The TX modulated TX signal is amplified in
TX–buffer before the transmitter.
TX Loop Filter
Output pulses from the phase detector N820 pin 17 have to be supplied to
the loop filter. The integrator, which consists of R420 and C421, converts
positive and negative pulses to DC voltage. The remaining ripple is filtered
in the low–pass filter.
Transmitter
The transmitter comprises a power amplifier module. The modulated RF
signal from the TX synthesizer is applied to the 50 ohm input of the module.
The power level is controlled by the voltage supplied to the pin 8. Amplifier
module has two output pins ( pins 13 and 12 ). The real part of the output
impedance is 7 ohms. The amplified RF signal is fed to the duplex filter via
Original 10/98
Page 2 – 49
Page 50
NHX-7
PAMS
Baseband Module JP3
Technical Documentation
a 50 ohm impedance matching circuit. Harmonics generated by the
transmitter are attenuated in the matching circuit and duplex filter. A voltage
proportional to the output power is rectified from a directional coupler by
DC–biased Schottky diode V640. This rectified voltage is fed to a differential
amplifier which consists of transistor V650. The reference voltage is filtered
from the PWM signal provided by the TXC line. The differential amplifier
adjusts the control voltage so that the reference voltage and the voltage
proportional to the output power are equal. The transmitter is switched on
when TXE goes high (logic 1). TXE enables the transmitter power control
circuit by transistor V641. When the transmitter is inactive (TXE low) the RF
level from the transmitter is reduced below –60 dBm.
RF Characteristics
Temperature rangeMinimumTypical /
Nominal
Operating temperature–10+55°C
MaximumUnit / Notes
Duplexer
TransmitterReceiver
Frequency872...905 MHz917...950 MHz
Insertion loss max 3.5 dB4.8 dB
Ripple at BW max 3.0 dB3.0 dB
Termination im-
N1000 MHz ... 4000 MHz< –47 dBm
NRX–band< –70 dBm
NTX–band< –60 dBm
N / EAudio harmonic distortion< –30 dB (third harmonic)
N/ENoise & Hum< –32 dB
Audio frequency response
N300 Hz...500 Hz+0.5/–1 dBm
N500 Hz...2 kHz0.5 dB
N2 kHz... 3 kHz+0.5/–1 dB
N10 kHz–6 dB (max.)
N / ERSSI dynamic range> 65 dB
N /ERSSI starting level> –113 dBm /–110 dBm
N/ERSSI linearity< 5 (10) dB
Preamplifier
MinimumTypical /
Nominal
Supply voltage2.7V
MaximumUnit / Notes
Frequency band917950MHz
Current consumption5.56.5mA
Insertion gain141516dB
Gain flatness0,5dB
Noise figure2.3dB
Reverse isolation20dB
Original 10/98
Page 2 – 51
Page 52
NHX-7
PAMS
Baseband Module JP3
Minimum
Nominal
IIP3–8,0dBm
Input return loss
(Z0=50)
Output return loss
(Z0=50)
10dB
10dB
Technical Documentation
SAW–filter
MinimumTypical /
Nominal
Center frequency, f
Bandwidth"16,5MHz
Attenuation:
DC – 850MHz35dB
Supply voltage3.153.64.6V
Drive current10mA
Power control range20dB
MaximumUnit / Notes
Synthesizer submodule
PLL circuit for RX local oscillator signal and TX injection
PLL Synthesizer specification
MinimumTypical / Nomi-
nal
Frequency band (RX LO)962995MHz
MaximumUnit / Notes
Frequency band (TX)872905MHz
Channel separation25kHz
VCTCXO frequency14.85MHz
VCTCXO input level1Vpp (10k)
Frequency stability± 2.5ppm
RF signal level from VCO
to prescaler
Supply voltage2.7V
Current consumption8.5mA
50mVrms
RX local oscillator signal
MinimumTypical /
Nominal
Frequency band962995MHz
Output level+3+5+7dBm / 50
Output return loss10dB
Phase noise –112dBc / Hz (25 kHz)
Tuning voltage limits14V
MaximumUnit / Notes
Tuning voltage at center frequency
Tuning voltage sensitivity
Temperature stability"10MHz (all conditions)
Locking time to ±1
channel
151821MHz / V
Page 2 – 56
2.5V
20ms
Original 10/98
Page 57
PAMS
NHX-7
Technical Documentation
Minimum
Nominal
Locking time to any
channel
RF signal level from
VCO to prescaler
Supply voltage2.7V
Current consumption22mA
50mVrms
40ms
Baseband Module JP3
Unit / NotesMaximumTypical /
TX VCO
MinimumTypical /
Nominal
Frequency band872905MHz
Output level–30+3dBm / 50
Output return loss10dB
MaximumUnit / Notes
Phase noise–102dBc / Hz (25 kHz)
Tuning voltage limits04V
Tuning voltage at cen-
ter frequency
Tuning voltage sensitiv-
ity
Locking time to " 1
channel
Locking time to any
channel
Modulation
Input impedance100k
deviation error10% (in all conditions)
mod. frequency0,310kHz
mod. sensitivity200mV
RF signal level from
VCO to prescaler
Supply voltage2.7V
Current consumption10mA
151821MHz / V
50mVrms
2,5V
20ms
40ms
(2.3 kHz dev.)
rms
TX buffers
MinimumTypical /
Nominal
Frequency range872905MHz
1.st buffer
Output level–24dBm
MaximumUnit / Notes
Original 10/98
Page 2 – 57
Page 58
NHX-7
PAMS
Baseband Module JP3
Supply voltage2.7V
Current con–
sumption
2.nd buffer
Output level812dBm
Supply voltage3.13.64.6V
Current con–
sumption
Minimum
Nominal
10mA
35mA
Technical Documentation
VCTCXO
MinimumTypical /
Nominal
Frequency14.85MHz
MaximumUnit / Notes
Unit / NotesMaximumTypical /
Control voltage0.52,5V
Controlled frequency
area
Control step1.5Hz
Frequency accuracy 2.5ppm (all conditions)
Output level1Vpp
Supply voltage2.7V
Current consumption2mA
f01,25Hz
Page 2 – 58
Original 10/98
Page 59
PAMS
NHX-7
Technical Documentation
Baseband Module JP3
Parts list of JP3 (EDMS Issue 4.3)Code: 0201185
ITEMCODEDESCRIPTIONVALUETYPE
R1021422881 Chip resistor0.22 5 % 1 W 1218
R1051430778 Chip resistor10 k5 % 0.063 W 0402
R1061430187 Chip resistor47 k1 % 0.063 W 0402
R1071430764 Chip resistor3.3 k5 % 0.063 W 0402
R1101430778 Chip resistor10 k5 % 0.063 W 0402
R1111430778 Chip resistor10 k5 % 0.063 W 0402
R1401430778 Chip resistor10 k5 % 0.063 W 0402
R1411430788 Chip resistor22 k5 % 0.063 W 0402
R1421430804 Chip resistor100 k5 % 0.063 W 0402
R1431430145 Chip resistor100 k1 % 0.063 W 0402
R1441430145 Chip resistor100 k1 % 0.063 W 0402
R1451430842 Chip resistor680 k1 % 0.063 W 0402
R1461430842 Chip resistor680 k1 % 0.063 W 0402
R1471430788 Chip resistor22 k5 % 0.063 W 0402
R1481430766 Chip resistor3.9 k5 % 0.063 W 0402
R1491430780 Chip resistor12 k5 % 0.063 W 0402
R1611430770 Chip resistor4.7 k5 % 0.063 W 0402
R1621430770 Chip resistor4.7 k5 % 0.063 W 0402
R1631430734 Chip resistor220 5 % 0.063 W 0402
R1721430770 Chip resistor4.7 k5 % 0.063 W 0402
R2021430145 Chip resistor100 k1 % 0.063 W 0402
R2031430778 Chip resistor10 k5 % 0.063 W 0402
R2061430754 Chip resistor1.0 k5 % 0.063 W 0402
R2071430778 Chip resistor10 k5 % 0.063 W 0402
R2081430690 Chip jumper0402
R2101430804 Chip resistor100 k5 % 0.063 W 0402
R2111430776 Chip resistor8.2 k5 % 0.063 W 0402
R2121430690 Chip jumper0402
R2311430121 Chip resistor22 k1 % 0.063 W 0402
R2321430778 Chip resistor10 k5 % 0.063 W 0402
R2411430790 Chip resistor27 k5 % 0.063 W 0402
R2511430792 Chip resistor33 k5 % 0.063 W 0402
R2521430792 Chip resistor33 k5 % 0.063 W 0402
R2611430754 Chip resistor1.0 k5 % 0.063 W 0402
R2621430832 Chip resistor2.7 k5 % 0.063 W 0402
R3201430778 Chip resistor10 k5 % 0.063 W 0402
R3221430744 Chip resistor470 5 % 0.063 W 0402
R3231430772 Chip resistor5.6 k5 % 0.063 W 0402
R3331430700 Chip resistor10 5 % 0.063 W 0402
R3401430776 Chip resistor8.2 k5 % 0.063 W 0402
R3411430770 Chip resistor4.7 k5 % 0.063 W 0402
R3421430700 Chip resistor10 5 % 0.063 W 0402
R3431430734 Chip resistor220 5 % 0.063 W 0402
Original 10/98
Page 2 – 59
Page 60
NHX-7
PAMS
Baseband Module JP3
R3611430778 Chip resistor10 k5 % 0.063 W 0402
R3621430778 Chip resistor10 k5 % 0.063 W 0402
R3631430756 Chip resistor1.2 k5 % 0.063 W 0402
R3661430714 Chip resistor33 5 % 0.063 W 0402
R3701430758 Chip resistor1.5 k5 % 0.063 W 0402
R3711430770 Chip resistor4.7 k5 % 0.063 W 0402
R3721430762 Chip resistor2.2 k5 % 0.063 W 0402
R3731430714 Chip resistor33 5 % 0.063 W 0402
R3811430770 Chip resistor4.7 k5 % 0.063 W 0402
R4201430774 Chip resistor6.8 k5 % 0.063 W 0402
R4211430786 Chip resistor18 k5 % 0.063 W 0402
R4221430690 Chip jumper0402
R4231430690 Chip jumper0402
R4301430718 Chip resistor47 5 % 0.063 W 0402
R4311430734 Chip resistor220 5 % 0.063 W 0402
R4341430700 Chip resistor10 5 % 0.063 W 0402
R4401430720 Chip resistor56 5 % 0.063 W 0402
R4411430774 Chip resistor6.8 k5 % 0.063 W 0402
R4421430764 Chip resistor3.3 k5 % 0.063 W 0402
R4431430700 Chip resistor10 5 % 0.063 W 0402
R4441430744 Chip resistor470 5 % 0.063 W 0402
R4501430726 Chip resistor100 5 % 0.063 W 0402
R4511430770 Chip resistor4.7 k5 % 0.063 W 0402
R4521430770 Chip resistor4.7 k5 % 0.063 W 0402
R4531430700 Chip resistor10 5 % 0.063 W 0402
R4541430724 Chip resistor82 5 % 0.063 W 0402
R4551430690 Chip jumper0402
R5201430774 Chip resistor6.8 k5 % 0.063 W 0402
R5211430784 Chip resistor15 k5 % 0.063 W 0402
R5221430770 Chip resistor4.7 k5 % 0.063 W 0402
R5231430690 Chip jumper0402
R5301430724 Chip resistor82 5 % 0.063 W 0402
R5311430734 Chip resistor220 5 % 0.063 W 0402
R5321430700 Chip resistor10 5 % 0.063 W 0402
R6411430726 Chip resistor100 5 % 0.063 W 0402
R6421430770 Chip resistor4.7 k5 % 0.063 W 0402
R6431430770 Chip resistor4.7 k5 % 0.063 W 0402
R6441430690 Chip jumper0402
R6451430792 Chip resistor33 k5 % 0.063 W 0402
R6461430770 Chip resistor4.7 k5 % 0.063 W 0402
R6471430700 Chip resistor10 5 % 0.063 W 0402
R6481430804 Chip resistor100 k5 % 0.063 W 0402
R6511430796 Chip resistor47 k5 % 0.063 W 0402
R6521430786 Chip resistor18 k5 % 0.063 W 0402
R6531430754 Chip resistor1.0 k5 % 0.063 W 0402
R6541430778 Chip resistor10 k5 % 0.063 W 0402
R6551430808 Chip resistor150 k5 % 0.063 W 0402
Technical Documentation
Page 2 – 60
Original 10/98
Page 61
PAMS
NHX-7
Technical Documentation
R6561430778 Chip resistor10 k5 % 0.063 W 0402
R6581430690 Chip jumper0402
R6591430778 Chip resistor10 k5 % 0.063 W 0402
R6601430690 Chip jumper0402
R7311430766 Chip resistor3.9 k5 % 0.063 W 0402
R7411430804 Chip resistor100 k5 % 0.063 W 0402
R7421430762 Chip resistor2.2 k5 % 0.063 W 0402
R7431430796 Chip resistor47 k5 % 0.063 W 0402
R7451430762 Chip resistor2.2 k5 % 0.063 W 0402
R7461430804 Chip resistor100 k5 % 0.063 W 0402
R7471430804 Chip resistor100 k5 % 0.063 W 0402
R7521430804 Chip resistor100 k5 % 0.063 W 0402
R7531430804 Chip resistor100 k5 % 0.063 W 0402
R7541430804 Chip resistor100 k5 % 0.063 W 0402
R7551430710 Chip resistor22 5 % 0.063 W 0402
R7601430812 Chip resistor220 k5 % 0.063 W 0402
R7671430764 Chip resistor3.3 k5 % 0.063 W 0402
R7681430794 Chip resistor39 k5 % 0.063 W 0402
R7691430796 Chip resistor47 k5 % 0.063 W 0402
R7701430788 Chip resistor22 k5 % 0.063 W 0402
R7711430776 Chip resistor8.2 k5 % 0.063 W 0402
R7751430690 Chip jumper0402
R7771430690 Chip jumper0402
R7901430778 Chip resistor10 k5 % 0.063 W 0402
R7911430788 Chip resistor22 k5 % 0.063 W 0402
R7921430700 Chip resistor10 5 % 0.063 W 0402
R7931430700 Chip resistor10 5 % 0.063 W 0402
R7941430804 Chip resistor100 k5 % 0.063 W 0402
R7951430726 Chip resistor100 5 % 0.063 W 0402
R7961430796 Chip resistor47 k5 % 0.063 W 0402
R7971430812 Chip resistor220 k5 % 0.063 W 0402
R8111430754 Chip resistor1.0 k5 % 0.063 W 0402
R8121430754 Chip resistor1.0 k5 % 0.063 W 0402
R8161430700 Chip resistor10 5 % 0.063 W 0402
R8201430792 Chip resistor33 k5 % 0.063 W 0402
R8211430690 Chip jumper0402
R8221430690 Chip jumper0402
R8261430788 Chip resistor22 k5 % 0.063 W 0402
R8291430778 Chip resistor10 k5 % 0.063 W 0402
R8301430778 Chip resistor10 k5 % 0.063 W 0402
R8311430778 Chip resistor10 k5 % 0.063 W 0402
C1002320546 Ceramic cap.27 p5 % 50 V 0402
C1012604127 Tantalum cap.1.0 u20 % 35 V
3.5x2.8x1.9
C1022604209 Tantalum cap.1.0 u20 % 16 V
3.2x1.6x1.6
C1032611668 Tantalum cap.4.7 u20 % 10 V
Baseband Module JP3
Original 10/98
Page 2 – 61
Page 62
NHX-7
PAMS
Baseband Module JP3
3.2x1.6x1.6
C1042604209 Tantalum cap.1.0 u20 % 16 V
3.2x1.6x1.6
C1052604209 Tantalum cap.1.0 u20 % 16 V
3.2x1.6x1.6
C1062604209 Tantalum cap.1.0 u20 % 16 V
3.2x1.6x1.6
C1072604209 Tantalum cap.1.0 u20 % 16 V
3.2x1.6x1.6
C1082604209 Tantalum cap.1.0 u20 % 16 V
3.2x1.6x1.6
C1112320530 Ceramic cap.5.6 p0.25 % 50 V 0402
C1122320584 Ceramic cap.1.0 n5 % 50 V 0402
C1132320584 Ceramic cap.1.0 n5 % 50 V 0402
C1142320584 Ceramic cap.1.0 n5 % 50 V 0402
C1152320584 Ceramic cap.1.0 n5 % 50 V 0402
C1162320584 Ceramic cap.1.0 n5 % 50 V 0402
C1172320584 Ceramic cap.1.0 n5 % 50 V 0402
C1182320584 Ceramic cap.1.0 n5 % 50 V 0402
C1192320546 Ceramic cap.27 p5 % 50 V 0402
C1202320584 Ceramic cap.1.0 n5 % 50 V 0402
C1212320584 Ceramic cap.1.0 n5 % 50 V 0402
C1222320584 Ceramic cap.1.0 n5 % 50 V 0402
C1232320620 Ceramic cap.10 n5 % 16 V 0402
C1242320131 Ceramic cap.33 n10 % 16 V 0603
C1252604209 Tantalum cap.1.0 u20 % 16 V
3.2x1.6x1.6
C1262320083 Ceramic cap.1.0 n5 % 50 V 0603
C1272320560 Ceramic cap.100 p5 % 50 V 0402
C1282320107 Ceramic cap.10 n5 % 50 V 0603
C1292320546 Ceramic cap.27 p5 % 50 V 0402
C1302320546 Ceramic cap.27 p5 % 50 V 0402
C1312320546 Ceramic cap.27 p5 % 50 V 0402
C1322320546 Ceramic cap.27 p5 % 50 V 0402
C1332320620 Ceramic cap.10 n5 % 16 V 0402
C1402320131 Ceramic cap.33 n10 % 16 V 0603
C1412320131 Ceramic cap.33 n10 % 16 V 0603
C1612320546 Ceramic cap.27 p5 % 50 V 0402
C2012307816 Ceramic cap.47 n20 % 25 V 0805
C2022307816 Ceramic cap.47 n20 % 25 V 0805
C2032307816 Ceramic cap.47 n20 % 25 V 0805
C2102320781 Ceramic cap.47 n20 % 16 V 0603
C2282320620 Ceramic cap.10 n5 % 16 V 0402
C2292320620 Ceramic cap.10 n5 % 16 V 0402
C2312320779 Ceramic cap.100 n10 % 16 V 0603
C2322320620 Ceramic cap.10 n5 % 16 V 0402
C2512307816 Ceramic cap.47 n20 % 25 V 0805
Technical Documentation
Page 2 – 62
Original 10/98
Page 63
PAMS
NHX-7
Technical Documentation
C2602320560 Ceramic cap.100 p5 % 50 V 0402
C2612320560 Ceramic cap.100 p5 % 50 V 0402
C2622320560 Ceramic cap.100 p5 % 50 V 0402
C2632320560 Ceramic cap.100 p5 % 50 V 0402
C2642320560 Ceramic cap.100 p5 % 50 V 0402
C2652320560 Ceramic cap.100 p5 % 50 V 0402
C2662320560 Ceramic cap.100 p5 % 50 V 0402
C2672320560 Ceramic cap.100 p5 % 50 V 0402
C2682320560 Ceramic cap.100 p5 % 50 V 0402
C2692320560 Ceramic cap.100 p5 % 50 V 0402
C2702320560 Ceramic cap.100 p5 % 50 V 0402
C2712320560 Ceramic cap.100 p5 % 50 V 0402
C2722320560 Ceramic cap.100 p5 % 50 V 0402
C2732320560 Ceramic cap.100 p5 % 50 V 0402
C2742320560 Ceramic cap.100 p5 % 50 V 0402
C2752320560 Ceramic cap.100 p5 % 50 V 0402
C2762320560 Ceramic cap.100 p5 % 50 V 0402
C2772320560 Ceramic cap.100 p5 % 50 V 0402
C2782320560 Ceramic cap.100 p5 % 50 V 0402
C2792320560 Ceramic cap.100 p5 % 50 V 0402
C2802320560 Ceramic cap.100 p5 % 50 V 0402
C2812320560 Ceramic cap.100 p5 % 50 V 0402
C3202320546 Ceramic cap.27 p5 % 50 V 0402
C3212320532 Ceramic cap.6.8 p0.25 % 50 V 0402
C3222320546 Ceramic cap.27 p5 % 50 V 0402
C3242320538 Ceramic cap.12 p5 % 50 V 0402
C3252320534 Ceramic cap.8.2 p0.25 % 50 V 0402
C3282611668 Tantalum cap.4.7 u20 % 10 V
3.2x1.6x1.6
C3312320620 Ceramic cap.10 n5 % 16 V 0402
C3402320520 Ceramic cap.2.2 p0.25 % 50 V 0402
C3412320538 Ceramic cap.12 p5 % 50 V 0402
C3422320526 Ceramic cap.3.9 p0.25 % 50 V 0402
C3432320526 Ceramic cap.3.9 p0.25 % 50 V 0402
C3442320546 Ceramic cap.27 p5 % 50 V 0402
C3452320546 Ceramic cap.27 p5 % 50 V 0402
C3502320544 Ceramic cap.22 p5 % 50 V 0402
C3542320530 Ceramic cap.5.6 p0.25 % 50 V 0402
C3602320620 Ceramic cap.10 n5 % 16 V 0402
C3612320620 Ceramic cap.10 n5 % 16 V 0402
C3622320620 Ceramic cap.10 n5 % 16 V 0402
C3702320584 Ceramic cap.1.0 n5 % 50 V 0402
C3712320584 Ceramic cap.1.0 n5 % 50 V 0402
C3722320546 Ceramic cap.27 p5 % 50 V 0402
C3732320620 Ceramic cap.10 n5 % 16 V 0402
C3742320620 Ceramic cap.10 n5 % 16 V 0402
C3752604329 Tantalum cap.4.7 u20 % 10 V
Baseband Module JP3
Original 10/98
Page 2 – 63
Page 64
NHX-7
PAMS
Baseband Module JP3
3.5x2.8x1.9
C3762320620 Ceramic cap.10 n5 % 16 V 0402
C3772310490 Ceramic cap.360 p2 % 50 V 0805
C3782320556 Ceramic cap.68 p5 % 50 V 0402
C3792320584 Ceramic cap.1.0 n5 % 50 V 0402
C3802320620 Ceramic cap.10 n5 % 16 V 0402
C3812320620 Ceramic cap.10 n5 % 16 V 0402
C3822320560 Ceramic cap.100 p5 % 50 V 0402
C4202320120 Ceramic cap.22 n10 % 25 V 0603
C4212604209 Tantalum cap.1.0 u20 % 16 V
3.2x1.6x1.6
C4242320618 Ceramic cap.4.7 n5 % 25 V 0402
C4302611668 Tantalum cap.4.7 u20 % 10 V
3.2x1.6x1.6
C4312320546 Ceramic cap.27 p5 % 50 V 0402
C4322320546 Ceramic cap.27 p5 % 50 V 0402
C4402320548 Ceramic cap.33 p5 % 50 V 0402
C4422320548 Ceramic cap.33 p5 % 50 V 0402
C4432320530 Ceramic cap.5.6 p0.25 % 50 V 0402
C4442320520 Ceramic cap.2.2 p0.25 % 50 V 0402
C4472320602 Ceramic cap.4.7 p0.25 % 50 V 0402
C4482320548 Ceramic cap.33 p5 % 50 V 0402
C4492320602 Ceramic cap.4.7 p0.25 % 50 V 0402
C4502320514 Ceramic cap.1.2 p0.25 % 50 V 0402
C4512320514 Ceramic cap.1.2 p0.25 % 50 V 0402
C4522320620 Ceramic cap.10 n5 % 16 V 0402
C4532320548 Ceramic cap.33 p5 % 50 V 0402
C4542320532 Ceramic cap.6.8 p0.25 % 50 V 0402
C4552320620 Ceramic cap.10 n5 % 16 V 0402
C5202320620 Ceramic cap.10 n5 % 16 V 0402
C5222310784 Ceramic cap.100 n10 % 25 V 0805
C5232320781 Ceramic cap.47 n20 % 16 V 0603
C5242320594 Ceramic cap.2.7 n5 % 50 V 0402
C5252320618 Ceramic cap.4.7 n5 % 25 V 0402
C5302611668 Tantalum cap.4.7 u20 % 10 V
3.2x1.6x1.6
C5312320546 Ceramic cap.27 p5 % 50 V 0402
C5322320546 Ceramic cap.27 p5 % 50 V 0402
C6012320620 Ceramic cap.10 n5 % 16 V 0402
C6022320548 Ceramic cap.33 p5 % 50 V 0402
C6032320548 Ceramic cap.33 p5 % 50 V 0402
C6042320602 Ceramic cap.4.7 p0.25 % 50 V 0402
C6052604209 Tantalum cap.1.0 u20 % 16 V
3.2x1.6x1.6
C6062320584 Ceramic cap.1.0 n5 % 50 V 0402
C6252604209 Tantalum cap.1.0 u20 % 16 V
3.2x1.6x1.6
Technical Documentation
Page 2 – 64
Original 10/98
Page 65
PAMS
NHX-7
Technical Documentation
C6312320532 Ceramic cap.6.8 p0.25 % 50 V 0402
C6332320620 Ceramic cap.10 n5 % 16 V 0402
C6342320548 Ceramic cap.33 p5 % 50 V 0402
C6352320530 Ceramic cap.5.6 p0.25 % 50 V 0402
C6412320532 Ceramic cap.6.8 p0.25 % 50 V 0402
C6422320538 Ceramic cap.12 p5 % 50 V 0402
C6432320548 Ceramic cap.33 p5 % 50 V 0402
C6442320548 Ceramic cap.33 p5 % 50 V 0402
C6452320548 Ceramic cap.33 p5 % 50 V 0402
C6462320598 Ceramic cap.3.9 n5 % 50 V 0402
C6482320620 Ceramic cap.10 n5 % 16 V 0402
C6502320131 Ceramic cap.33 n10 % 16 V 0603
C6522320620 Ceramic cap.10 n5 % 16 V 0402
C6602320602 Ceramic cap.4.7 p0.25 % 50 V 0402
C7012320584 Ceramic cap.1.0 n5 % 50 V 0402
C7032320131 Ceramic cap.33 n10 % 16 V 0603
C7042320131 Ceramic cap.33 n10 % 16 V 0603
C7052320131 Ceramic cap.33 n10 % 16 V 0603
C7062320131 Ceramic cap.33 n10 % 16 V 0603
C7102320131 Ceramic cap.33 n10 % 16 V 0603
C7112320131 Ceramic cap.33 n10 % 16 V 0603
C7122320131 Ceramic cap.33 n10 % 16 V 0603
C7132320131 Ceramic cap.33 n10 % 16 V 0603
C7142320131 Ceramic cap.33 n10 % 16 V 0603
C7152320131 Ceramic cap.33 n10 % 16 V 0603
C7162310784 Ceramic cap.100 n10 % 25 V 0805
C7172320131 Ceramic cap.33 n10 % 16 V 0603
C7212320131 Ceramic cap.33 n10 % 16 V 0603
C7312320546 Ceramic cap.27 p5 % 50 V 0402
C7322320131 Ceramic cap.33 n10 % 16 V 0603
C7332320131 Ceramic cap.33 n10 % 16 V 0603
C7402320131 Ceramic cap.33 n10 % 16 V 0603
C7412320131 Ceramic cap.33 n10 % 16 V 0603
C7422320131 Ceramic cap.33 n10 % 16 V 0603
C7532320584 Ceramic cap.1.0 n5 % 50 V 0402
C7602320131 Ceramic cap.33 n10 % 16 V 0603
C7622320779 Ceramic cap.100 n10 % 16 V 0603
C7632604209 Tantalum cap.1.0 u20 % 16 V
3.2x1.6x1.6
C7662320131 Ceramic cap.33 n10 % 16 V 0603
C7672320620 Ceramic cap.10 n5 % 16 V 0402
C7702320594 Ceramic cap.2.7 n5 % 50 V 0402
C7712320764 Ceramic cap.6.8 n10 % 25 V 0402
C7722320109 Ceramic cap.15 n5 % 25 V 0603
C7812320779 Ceramic cap.100 n10 % 16 V 0603
C7902320779 Ceramic cap.100 n10 % 16 V 0603
C7912320131 Ceramic cap.33 n10 % 16 V 0603
Baseband Module JP3
Original 10/98
Page 2 – 65
Page 66
NHX-7
PAMS
Baseband Module JP3
C7922312296 Ceramic cap.Y5 V 1210
C7932320131 Ceramic cap.33 n10 % 16 V 0603
C7942320779 Ceramic cap.100 n10 % 16 V 0603
C8122604209 Tantalum cap.1.0 u20 % 16 V
3.2x1.6x1.6
C8132320534 Ceramic cap.8.2 p0.25 % 50 V 0402
C8142320598 Ceramic cap.3.9 n5 % 50 V 0402
C8152320598 Ceramic cap.3.9 n5 % 50 V 0402
C8202320618 Ceramic cap.4.7 n5 % 25 V 0402
C8212611668 Tantalum cap.4.7 u20 % 10 V
3.2x1.6x1.6
C8232604209 Tantalum cap.1.0 u20 % 16 V
3.2x1.6x1.6
C8242320598 Ceramic cap.3.9 n5 % 50 V 0402
C8252604209 Tantalum cap.1.0 u20 % 16 V
V1021825003 Chip varistor vwm5.5v vc15.5 08050805
V1034113651 Trans. supr.QUAD6 V SOT23–5
V1204100567 Sch. diode x 2BAS70–0470V15 mA SERSOT23
V1404219922 Transistor x 2UM6
V2004210102 TransistorBC858Wpnp 30 V 100 mA
200MWSOT323
V2104100567 Sch. diode x 2BAS70–0470V15 mA SERSOT23
V3204210004 TransistorBFG67Xnpn 20 V 50 mA
7.5GHZSOT143
V3404115802 Sch. diode x 24V30 mA SOT23
V3414210090 TransistorBFG540/Xnpn 15 V 129 mA
SOT143
V3804210066 Transistor BFR93AWnpn 12 V 35 mA SOT323
V4304210066 Transistor BFR93AWnpn 12 V 35 mA SOT323
V4404210090 Transistor BFG540/Xnpn 15 V 129 mA SOT143
V6404110014 Sch. diode x 2BAS70–0770 V 15 mA SOT143
V6414219922 Transistor x 2UM6
V6504219904 Transistor x 2UMX1npn 40 V SOT363
V6514210102 Transistor BC858Wpnp 30 V 100 mA 200MWSOT323
V7404210100 Transistor BC848Wnpn 30 V SOT323
V7414100567 Sch. diode x 2 BAS70–0470V15 mA SERSOT23
V7904219922 Transistor x 2UM6
D0024340251 IC, EEPROMNMP40251SO8S
D7004340387 IC, 2xbilateral switch sso TC7W66FUSSOP8
N1004370165 Chaps charger control so16SO16
N1014370471 Power asic for etacs/nmt450
N1404340059 IC, lp opamp+3/15v r&r sso LMC7101SSOP5
N3704349694 IC, if amp+fm detector sso TA31136SSO16
N6014370099 Rf9102 pw amp 824–849mhz SO16SQB
N7014370469 Nasta 4.5 mas1020a
N7614340331 IC, Power amp.LM4862P W SO8S
N8204340393 IC, 2xsynth 1.1ghz ssop UMA1015AMSSOP20
X0995460021 SM, conn 2x14m spring p1.0 pcb/pPCB/PCB
X1015469069 SM, batt conn 2pol spr p3.5 100v100V2A
X1025469069 SM, batt conn 2pol spr p3.5 100v100V2A
X1035469061 SM, system conn 6af+3dc+mic+jack
A3009517011 Shield assembly–4 dmc00508
A4009517010 Shield assembly–3 dmc00507
A5009517010 Shield assembly–3 dmc00507
A6009517011 Shield assembly–4 dmc00508
9510480 Antenna clip dmd04121 nhx–7
9854322 PCB JP3 41.0X111.95X1.0 M4 4/PA
0240775 SW program MCU for NHX–7
Baseband Module JP3
Original 10/98
Page 2 – 67
Page 68
NHX-7
PAMS
Baseband Module JP3
Technical Documentation
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Original 10/98
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