Nokia Ringo2 System Module 03

PAMS Technical Documentation

NHN–6N Series Transceivers

Chapter 3

System Module

Original 11/97

NHN–6N

PAMS

System Module

Technical Documentation

CONTENTS

Introduction 3 – 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

List of Sub–modules 3 – 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Modes of Operation 3 – 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DC Characteristics 3 – 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Connections 3 – 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Battery/Service Connector 3 – 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Charger Connector 3 – 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Audio Specifications 3 – 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Headset Connector 3 – 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Circuit Description 3 – 9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CTRLU 3 – 9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CTRLU Internal Signals, Inputs 3 – 9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CTRLU Internal Signals, Outputs 3 – 9. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Block description 3 – 10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

RFTEMP, RF temperature measurement 3 – 12. . . . . . . . . . . . . . . . . . . . . .

Main components 3 – 12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PWRU 3 – 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Block description 3 – 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MUUMI Block diagram 3 – 19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

AUDIO 3 – 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Introduction 3 – 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Main features 3 – 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Technical specifications 3 – 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

NIPA Block Diagram 3 – 24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Transmit (TX) audio signal path 3 – 25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

RF Section 3 – 29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Technical Summary 3 – 29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Functional Description 3 – 29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Basic Specifications 3 – 29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Module Characteristics 3 – 30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Connections 3 – 30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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Maximum ratings 3 – 30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DC Characteristics 3 – 30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Connections to Baseband module 3 – 30. . . . . . . . . . . . . . . . . . . . . . . . . . . .

Digital control signal values 3 – 31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Block diagram 3 – 35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Receiver 3 – 36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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RX Synthesizer 3 – 36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

RX loop filter 3 – 36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TX Synthesizer 3 – 37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TX Loop Filter 3 – 37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Transmitter 3 – 37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Regulators 3 – 37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

AFC function 3 – 38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

UIF Module 3 – 38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

UIF internal Signals, Inputs 3 – 38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

UIF internal Signals, Outputs 3 – 38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Parts List of JR9B EDMS Issue 2.3 version 01 Code: 0201178 3 – 39. . . .

Schematic Diagrams of JR9B: layout version 01

System Module

Block Diagram of System/RF Blocks (Version: 01; Edit: 89) 3A–1. .

Circuit Diagram of Connector (Version: 02; Edit: 89) 3A–2. . . . . . . .

Circuit Diagram of CTRLU Section (Version: 02; Edit: 119) 3A–3. . .

Circuit Diagram of PWRU Section (Version: 02; Edit: 101) 3A–4. . . .

Circuit Diagram of Audio Section (Version: 02; Edit: 228) 3A–5. . . . .

Circuit Diagram of Keyboard Section (Version: 02; Edit: 72) 3A–6. .

Circuit Diagram of Display Section (Version: 02; Edit: 18) 3A–7. . . .

Circuit Diagram of Receiver Section (Version: 02; Edit: 131) 3A–8. .
Circuit Diagram of Transmitter Section (Version: 02; Edit: 81) 3A–9.
Circuit Diagram of Synthesizer Section (Version: 02; Edit: 114) 3A–10

Layout Diagram (Version 01) 3A–11. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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Introduction

The baseband submodule controls the internal operation of the phone. It
controls the user interface, i.e. LCD driver, keyboard, and audio interface
functions. The module performs all signalling towards the system, and
carries out audio–frequency signal processing. In addition, it controls the
operation of the transceiver and stores tuning data for the phone.

All functional blocks of the baseband are mounted on a single multi layer
printed circuit board. This board also contains RF–parts. The chassis of
the radio unit contains separating walls for baseband and RF. All compo­nents of the baseband are surface mountable. They are reflow soldered .
The connections to the Display–module are fed through a flex to the
board connector.

The Baseband Module includes power supply, modem, audio filters, mi­cro–controller, nonvolatile memory, SIS–processor, and keyboard. The
display is a separate module. Power supply circuits like regulators, volt­age detection and charging control, are integrated to the custom MUUMI
circuit . The modem and audio operations are integrated into NIPA ASIC.
The micro–controller is a Hitachi H8 series controller with 64 kbytes ROM
and 2 kbytes RAM. The 2 kbytes EEPROM memory is of serial I
type. The SIS–processor is a Motorola MC68HC11A8 connected to the
controller over serial bus I2C.

Technical Documentation

2

C–bus

List of Sub–modules

Name of submodule Notes

CTRLU
PWRU
AUDIO
UIF
RECEIVER
TRANSMITTER
SYNTHESIZER

These blocks are only functional blocks and therefore have no type nor
material codes.

Control Unit for the phone
Power supply
Audio
User interface
Receiver
Transmitter
Synthesizer

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Modes of Operation

The module has three operating modes: stand–by, listening, and con­versation mode.

Standby mode:

CPU‘s clock is switched off, only NIPA timer is running to take care of bat­tery save timings.

If charger is connected CPU doesn‘t go to standby mode.
Listening mode:
In the listening mode, some blocks of the audio IC (NIPA) are in standby

state.
Conversation mode:

System Module

In the conversation mode all ICs are active.

DC Characteristics

Pin / Conn. Line Symbol Minimum Typical /

Nominal

VCS

VCS

VBA T 4.5V 4.8V 6.8V
VRF 4.5V 4.8V 6.8V VBAT for RF mod-

VA 3.1V 3.3V 3.5V Imax = 20mA
VL2 3.1V 3.3V 3.5V Imax = 40mA
VL3 3.84V 4.0V 4.16V Imax = 100mA
VREF 3.2V 3.3V 3.42V Imax = 5mA

9.5V 10.5V 10.5V LCH–6; ACH–6
740mA

10.5V 12.0V 16.5V ACH–8
265mA

Maximum Unit / Notes

ule

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Connections

Battery/Service Connector

Technical Documentation

Pin Line

Symbol

1 VBAT 4.2V 4.8V 6.8V Battery voltage for transceiver.
2 MBUS Mbus line
3 XEAR External earphone
4 XMIC External microphone
5 GND Power supply ground.

Mini-

mum

Typical
/ Nomi-

nal

Maxi-

mum

Minimum Typical /

Nominal

Maximum

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Charger Connector

System Module

Pin Line

Symbol

2 VCS

3 GND Power Supply Ground
4 TERMI-

NAL

Mini­mum

9.5V 10.5V 10.5V LCH–6 and ACH–6

10.5V 12.0V 16.5V ACH–8

Typical
/ Nomi-

nal

740mA

265mA

Maxi-

mum

Unit / Notes

S0001227

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Audio Specifications

Typical / Nomi-

nal

MIC (NIPA ’s input pin) 0.25 mV Mic amplifier input

EARP, EARM 760 mV Earphone amplifier output
XEAR 170mV

XMIC 260mV

rms

rms

Maximum Unit / Notes

(NIPA’s input pin)

Via Battery / Service
Connector

2600mV

rms

Via Battery / Service
Connector

Headset Connector

The handsfree headset is connected by a 2,5 mm TC – Jack. The exter­nal earphone and microphone use the same audio lines and the same
amplifier as the internal earphone and microphone.

Pin Line

Symbol

1 GND Power Supply Ground

Unit / Notes

2 XMIC Bias from NIPA, external microphone
3 XEAR Audio from amplifier, external earphone
4 MIC Internal microphone
5 EAR Internal earphone

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System Module

Circuit Description

CTRLU

The Control block controls all phone functions, and SIS–processor too.

CTRLU Internal Signals, Inputs

Signal Name Notes From

VL2 Logic supply voltage Max 40 mA PWRU
VL3 SIS processor and earphone amplifier supply voltage PWRU
VREF Reference voltage 3.3V 2%. Max. 5mA. PWRU
PWRON Signal from power button. PWRU
XRES Reset line from MUUMI PWRU
VCHARG Charger voltage to A/D converter PWRU
VBATSW Battery voltage to A/D converter . PWRU
BTEMP Battery temperature CTRLU
RFTEMP RF temperature SYNTHESIZER
RSSI Received signal strenght indication RECEIVER
TXI Transmitter output power level indication TRANSMITTER
RXD Serial interface (M2BUS) PWRU
XINT Interrupt request from NIPA AUDIO
NMI No maskable Interrupt request from NIPA AUDIO
CLKMCU Clock for controller AUDIO
HSCONN Headset recognition AUDIO

CTRLU Internal Signals, Outputs

Signal Name Notes To

TXD Serial interface (M2BUS) PWRU
CSW Charger control PWRU
AGC Gain control RECEIVER
RXE RX Circuit power on/off RECEIVER
SCLK Synchronous data clock for synthesizers SYNTHESIZER
SDAT Synchronous data for synthesizers SYNTHESIZER
SLE Synthesizer data latch enable SYNTHESIZER
TXE Transmitter control (on/off) TRANSMITTER
TXC Transmitter Power Control TRANSMITTER
TXS TX synthesizer enable SYNTHESIZER
EAREN Earphone enable AUDIO
XNCS NIPA chip select signal AUDIO
XNWR NIPA write control signal AUDIO

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XNRD NIPA read control signal AUDIO
NA(3:0) NIPA address bus AUDIO
ND(7:0) NIPA data bus AUDIO
LIGHTS Backlights on/off UIF
COL0/

XPWROFF
COL1–4 Lines for keyboard read (keypad outputs) UIF
ROW0–2 Lines for keyboard read (keypad inputs). Input pullup used UIF
LCDD0–3 Lcd driver data UIF
E Lcd driver chip select signal UIF
RW Lcd driver read/write select signal UIF
RS Lcd driver register select signal UIF
LCDRES Lcd driver reset signal UIF
MBUSEN Mbus enable AUDIO

Line for keyboard read/
Power off control

Technical Documentation

UIF

ToNotesSignal Name

Block description

CTRLU – PWRU

CTRLU controls the watchdog timer in MUUMI. It sends a positive pulse
at approximately 1 s intervals to the XPWROFF pin of MUUMI to keep the
power on. If CTRLU fails to deliver this pulse, the MUUMI will cut off pow­er from the system. CTRLU also controls the charger on/off switching in
the PWRU block. When power off is requested, CTRLU leaves the
MUUMI watchdog without reset. After the watchdog has elapsed, MUUMI
cuts off the supply voltages from the phone. Battery charging is controlled
by CSW line, which is a PWM–controlled output port (frequency about 11
Hz).

VBATSW, Battery voltage measurement

The battery voltage can be measured up to 9.075 V nominal with 3.3 V
reference voltage. The absolute accuracy is low because of the reference
3 % accuracy, and A/D–converter +/– 8 LSB accuracy . This battery volt­age measurement offset error must be calibrated with input voltage 4.8 V.
The A/D conversion result can be calculated from the equation:

A/D readout = 1024 * (VBATSW* ( 4/11)) / VREF VREF=3.3V

Page 3 – 10

For example:

6.9 V results 778 = 30AH

4.8 V results 542 = 21EH

4.0 V results 451 = 1C3H

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VCHARG, Charger voltage measurement

The charger voltage can be measured up to 21.6 V nominal. The
A/D–conversion result can be calculated from the equation :

A/D readout = 1024 * (VCSW*(18/118)) / VREF VREF=3.3 V
For example:

BTEMP , Battery temperature measurement

Battery temperature measurement is implemented with 15 kohm NTC
and 47 kohm pull–up resistor. The A/D conversion readout can be calcu­lated from the equation:

11 V gives 520 = 208H
10 V gives 473 = 1D9H

4.8 V gives 227 = 0E3H

A/D readout= 1024* ( R

NTC

/( R

NTC

System Module

+47k))

CTRLU – AUDIO

The interface between micro–controller and NIPA circuit is a bi–directional
8–bit data bus with 4 address lines. Address, data, and control lines are
used in micro–controller as I/O–port pins. Data line direction must be con­trolled with the micro–controller data direction register. The Interface in­cludes address outputs NA0–3, data inputs (read) / outputs (write)
ND0–7, chip select control output XNCS, read control output XNRD, write
control output XNWR, and interrupt inputs XINT and NMI. To minimize
power consumption in battery stand by mode, control signals XRD and
XCS should be in ’0’ state, address output NA0–3 and NWR in ’1’ state,
and data lines ND0–7 should be inputs .

CTRLU – UIF

The keyboard is connected directly to the controller. COL0–4 are output
lines and ROW0–2 are input lines. The watchdog is updated at the same
time as keyboard scanning (XPWROFF). Keyboard scanning is done by
driving one COL to 0 V at time, and ROWs are used to read which key is
pressed.

For example:

+25°C gives 247 = 0F7H ( About 0.8 V )

The keyboard and LCD lights are controlled by the LIGHTS signal.
The LCD controller interface to the micro–controller are 4 bi–directional

data lines DD0–3, register select control RS output, read/write control RW
output, and bus enable control E output. The data lines LCDD0–3 and
control signals RS, RW must be set to high state during standby opera-

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tion because of the pull–up resistors in the LCD controller. LCD controller
resetting requires clock signal during XRES active low which is controlled
by LCDRES line. The MCU disables LCDRES after it has set LCDCLK
frequency to 57.6 kHz.

CTRLU – RECEIVER

The RECEIVER circuit power is connected on/off by the RXE signal.
Received signal strength is measured over the RSSI line, and the inter-

mediate frequency is measured over the IF line.

CTRLU – SYNT

The frequency is controlled by the AFC signal. The synthesizer is con­trolled via the synchronous serial bus SDAT/SCLK. The data is latched to
the synthesizer by the positive edge of the SLE line. The TX synthesizer
power on/off (TXS) line is controlled via PLL circuit. Control information is
programmed by using the SDAT line.

Technical Documentation

RFTEMP, RF temperature measurement

RF temperature measurement is implemented with 15 kohm NTC and
47 kohm pull–up resistor. The A/D conversion readout can be calculated
from the equation:

A/D readout= 1024* ( R

For example:

25 C gives 247 = 0F7H ( about 0.8 V )

CTRLU – TRANSMITTER

The transmitter output power level is measured over the TXI line. The
TXE line activates the power module. The power is controlled via the TXC
line which is a PWM–controlled output port (frequency about 5.1 kHz).

Main components

H8/3032 is a CMOS micro–controller. All memory needed (64kB ROM,
2kB RAM) except the EEPROM, is located in the controller. The MCU op­erating clock (3.6864 MHz) is generated on NIPA. H8/3032 is operating in
single–chip normal mode (mode 2) 64 kbyte address space, so all input/
output pins are used as I/O–ports.

NTC

/( R

NTC

+47k))

Pin Number Port Signal Description

1 PB0 SDAT
2 PB1

3 PB2
4 PB3 RXD

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Serial data for synthesizer

M2BUS net free timer input

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5 PB4 EAREN
6 PB5 LCDRES
7 PB6 PWRON
8 PB7 SLE
9 P90 TXD
10 P92 RXD
11 P94 ECLK
12 VSS GND

13 – 20 P30 – P37 ND0 – ND7
21 VCC VL2

22 P10 NA0
23 P11 NA1

System Module

DescriptionSignalPortPin Number

Earphone enable
Reset for Lcd driver
Power button state
RX/TX synthesizer latch
Serial interface (M2BUS)
Serial interface (M2BUS)
Serial clock for EEPROM

Parallel data bus for NIPA

Address line for NIPA
Address line for NIPA

24 P12 NA2
25 P13 NA3
26 P14 XNCS
27 P15 XNWR
28 P16 XNRD
29 P17 LIGHTS
30 VSS GND

31 – 34 P20 – P23 LCDD0 – LCDD3
35 – 37 P24 – P26 ROW0 – ROW2

38 P27 COL4
39 P50 COL0/XPWROFF

40 – 42 P51 – P53 COL1 – COL3
43 P60 TXS

Address line for NIPA
Address line for NIPA
NIPA chip select
Read/write control to NIPA
Read/write control to NIPA
Backlight control

Lcd driver data
Keypad inputs (Input pullup

used)

Keypad output
Keypad output /

Watchdog control
(XPWROFF)

Keypad outputs
TX synthesizer enable. Ac-

tive high

44 – 45 MD0 – MD1
46
47 STBY

48 RES XRES
49 NMI NMI

50 VSS GND

NC

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Mode selection

Reset from MUUMI
Interrupt request from

NIPA

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51 EXTAL CLKMCU

52 XTAL
53 VCC VL2
54 P63 TXE

55 P64 AGC
56 P65 RXE
57 RESO

58 AVSS GND
59 P70 VBATSW

60 P71 VCHARG
61 P72 RSSI

Technical Documentation

DescriptionSignalPortPin Number

External system clock from
NIPA

Transmitter on/off
Receiver gain control
RX circuit power on/off

Battery voltage
Charger voltage
Received signal strength

62 P73 TXI
63 P74 BTEMP
64 P75 HSCONN
65 P76 RFTEMP
66 P77

67 VREF VREF
68 AVCC VREF
69 P80 XINT

70 P81 RS
71 P82 RW
72 P83 E
73 PA0 SISCLK

74 PA1 SISD

Transmitter power monitor
Battery temperature
Headset recognition
RF temperature

Interrupt request from
NIPA

Lcd driver register select
Lcd driver read/write
Lcd driver chip select
Serial clock for SIS–pro-

cessor
Serial data for SIS–proces-

sor

75 PA2 EDATA

76 PA3 SCLK
77 PA4 CSW
78 PA5 MBUSEN
79 PA6 TXC
80 PA7

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Serial data to/from EE­PROM

Serial clock for synthesizer
Charging control
Mbus enable
Transmitter power control

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Technical Documentation

MC68HC11A8

MC68HC11A8 is a SIS (subscriber identification) circuit connected to the
controller over serial bus I2C.

SIS–processor signals

Pin No Signal From

31 EXTAL Clock input from the NIPA
43 RESET Reset input
47 PD0

50 PD1

EEPROM

I2C bus clock
I2C bus data

There is one 2k EEPROM in the phone. EEPROM is a nonvolatile
memory into which the tuning data for the phone is stored. In addition, it
contains the short code memory locations to retain user selectable phone
numbers.

System Module

EEPROM signals

Pin No Signal Description

5 SDA
6 SCL

I2C bus data
I2C bus clock

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