After Sales Technical Documentation
TFK–1 Series Transceiver
Chapter 4
SYSTEM MODULE
Original, 34/96
TFK–1
After Sales
System Module
CHAPTER 4 – SYSTEM MODULE
Contents
Introduction Page 4–4
Technical Section Page 4–4
External Connections Page 4–4
System Connector X120 Page 4–4
SIM Connector X300 Page 4–6
Baseband Block Page 4–7
Introduction Page 4–7
Modes of Operation Page 4–8
Circuit Description Page 4–8
Power Supply Page 4–8
MCU Page 4–12
MCU Flash Loading Page 4–13
Flash, D430 Page 4–15
SRAM D440 Page 4–15
MCU and Peripherals Page 4–16
Baseband A/D Converter Channels usage in N450 and D420 Page 4–16
Audio Control Page 4–17
DSP Page 4–19
RFI2 N450 Operation Page 4–21
SIM Interface Page 4–23
Line Adapter Page 4–25
Line Adapter Power Supply Page 4–26
RF Block Page 4–27
Introduction Page 4–27
Receiver Page 4–27
Pre–Filters Page 4–28
Pre–Amplifier Page 4–28
RX Interstage Filter Page 4–28
First Mixer Page 4–29
First IF Amplifier Page 4–29
First IF Filter Page 4–29
2nd Mixer Page 4–29
2nd IF Amplifier Page 4–29
2nd IF Filter Page 4–30
Receiver IF Circuit, RX part of CRFRT Page 4–30
Last IF Filter Page 4–30
Transmitter Page 4–30
Technical Documentation
Page 4–2
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Technical Documentation
Modulator Circuit TX, part of CRFRT Page 4–31
Up–conversion Mixer Page 4–32
TX Interstage Filters Page 4–33
1st TX Buffer Page 4–33
2nd TX Buffer Page 4–33
Power Amplifier Page 4–33
Power Control Circuits Page 4–34
Frequency Synthesizers Page 4–35
Reference Oscillator Page 4–35
VHF PLL Page 4–36
VHF VCO + Buffer Page 4–36
UHF PLL Page 4–37
UHF VCO + Buffer Page 4–37
UHF VCO Buffers Page 4–37
PLL Circuit Page 4–38
Interconnection Diagram of Baseband Page 4–39
Block Diagram of RF Page 4–40
RF Frequency Plan Page 4–41
Power Distribution Diagram of RF Page 4–42
Block Diagram of Baseband Page 4–43
Circuit Diagram of Connectors Page 4–44
Circuit Diagram of Line Adapter Power Supply Unit Page 4–45
Circuit Diagram of 2 to 4 Wire Interface Page 4–46
Circuit Diagram of MCU Memory Block Page 4–47
Circuit Diagram of Power Supply Page 4–48
Circuit Diagram of Audio Page 4–49
Circuit Diagram of ASIC Page 4–50
Circuit Diagram of DSP Memory Block Page 4–51
Circuit Diagram of RFI Page 4–52
Circuit Diagram of Receiver Page 4–53
Circuit Diagram of Transceiver Page 4–54
Layout Diagrams of WT3 Page 4–55
Parts list of WT3 (EDMS Issue 2.8) Page 4–56
System Module
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System Module
Introduction
WT3 is the baseband/RF module TFK–1 cellular transceiver. The WT3 module
carries out all the system and RF functions of the transceiver. The system module WT3 is designed for a WLL terminal, that operate in the PCN system.
Technical Section
All functional blocks of the system module are mounted on a single multi layer
printed circuit board. The chassis of the radio unit has separating walls for
baseband and RF. The connections to accessories are taken through the system connector of the radio unit. There is no physical connector between the RF
and baseband sections.
External Connections
The system module has two connectors, an external system connector, and
SIM connector.
Technical Documentation
System Connector X120
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Technical Documentation
Accessory Connector
Pin: Name: Description:
1 RS_RX Serial RX (Receive data for serial communica–
2 RS_TX Serial TX (Transmit data for serial communica–
3 SCK_RTS Serial Clock (Serial Clock for synchronous
4 WDDIS • ”0”; min/max 0...0.6 V Watchdog disable,
System Module
tion)
• ”0”; min/max 0...0.6 V
• ”1”; min/max 2.4...3.2 V
tion)
• ”0”; min/max 0...0.6 V
• ”1”; min/max 2.4...3.2 V
communication / RS_RTS)
• ”0”; min/max 0...0.6 V
• ”1”; min/max 2.4...3.2 V
Flash mode
• ”1”; min/max 2.4...7.15 V, Normal mode
5 PCMDCLK Audio Clock (512 kHz) clock for audio data
• ”0”; min/max 0...0.6 V
• ”1”; min/max 2.4...3.2 V
6 MBUS Serial control bus (General Purpose Control
and Test Control Bus)
• ”0”; min/max 0...0.5 V
• ”1”; min/max 2.4...3.2 V
7 VPP Programming Voltage (Programming voltage is
applied before entering the programming state)
• active; min/max 11.6...12.6 V
• inactive; min/max 0...3.2 V
8 DBUS_RXD DBUS Interface (Receive data for DAI)
• ”0”; min/max 0...0.6 V
• ”1”; min/max 2.4...3.2 V
9 DBUS_TXD DBUS Interface (Transmit data for DAI)
• ”0”; min/max 0...0.6 V
• ”1”; min/max 2.4...3.2 V
10 PCMSCLK Audio Clock (8 kHz slot clock for audio data)
• ”0”; min/max 0...0.6 V
• ”1”; min/max 2.4...3.2 V
11 VL Logic Supply Voltage (3 V Logic voltage)
12 FBUS_TX FBUS TX (FBUS transmit)
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• typical; 3.2 V
• ”0”; min/max 0...0.5 V
• ”1”; min/max 2.4...3.2 V
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Pin: Name: Description:
13 FBUS_RX FBUS RX
14 VBATT Battery supply voltage
15 DGND Digital ground
16 RS_CTS RS232 (Handshake signal for RS–232 serial
17 HOOK_DTR Accessory detection
18 AGND Analog ground
19 XMIC_ID External Microphone Input (Audio in e.g. ser-
vice handset)
Technical Documentation
• FBUS receive ”0”; min/max 0...0.6 V
• Pull–up on base band ”1”; min/max 2.4...3.2 V
• min/max 6.45...7.15 V
interface)
• active; min/max 0...0.5 V
• inactive; min/max 2.4...3.2 V
• typical 200 mV
20 XEAR_DSR External Speaker (Audio out e.g. service
SIM Connector X300
Pin: Name: Description:
1 GND Ground for SIM
2 VSIM SIM voltage supply
3 SDATA Serial data for SIM
4 SRES Reset for SIM
5 CLK Clock for SIM data (clock frequency minimum
handset)
• min/typ/max: 4.8...4.9...5.0 V
1 MHz if clock stopping not allowed)
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Technical Documentation
Baseband Block
Introduction
The WT3 module is used in TFK–1 products. The baseband is built around one
DSP, System ASIC and the MCU. The DSP performs all speech and GSM/PCN
related signal processing tasks. The baseband power supply is 3V, except for
the A/D and D/A converters that are the interface to the RF section, and to the
comparators in the LAPWRU.
The audio codec is a separate device which is connected to both the DSP and
the MCU. The audio codec supports the internal audio from line adapter and
external audio from the service handset.
The baseband clock reference is derived from the RF section, and the reference frequency is 13 MHz. A low level sinusoidal wave form is fed to the ASIC
which acts as the clock distribution circuit. The DSP is running at 39 MHz using
an internal PLL. The clock frequency supplied to the DSP is 13 MHz. The MCU
bus frequency is the same as the input frequency. The system ASIC provides
both 13 MHz and 6.5 MHz as alternative frequencies. The MCU clock frequency is programmable by the MCU. The baseband uses 13 MHz as the MCU operating frequency. The RF A/D, D/A converters are operated using the 13 MHz
clock supplied from the system ASIC
System Module
The power supply IC contains three different regulators. The output voltage
from each regulator is 3.15V nominal. One of the regulators uses an external
transistor as the boost transistor.
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Modes of Operation
The baseband can operate only in the active mode in WLL terminal.
Circuit Description
Power Supply
+6.6 V
5,21,44,39,37
VBAT
N300
43
35
40
V300
Technical Documentation
VBATT
+6.6 V
VL +3.2V
VA +3.2 V
VSL +3.2 V
DGND
4,20,38
6,32
AGND
The baseband has one power supply circuit N300 delivering power to the different parts in the baseband. There are two logic power supplies and one analog
power supply. The analog power supply VA is used for analog circuits such as
audio codec. Due to the current consumption and the baseband architecture
the digital supply is divided into to parts.
Both digital power supply VSL and VL from the N300 PSCLD are used to distribute the power dissipation inside N300 PSCLD. The main logic power supply
VL has an external power transistor, V300 to handle the power dissipation.
D400, ASIC, and the MCU SRAM D440 are connected to the same logic supply
voltage. All other digital circuits are connected to the main digital supply. The
analog voltage supply is connected to the audio codec.
N350
VCC
+5.0 V
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Technical Documentation
Power Supply Regulator PSCLD, N300
The power supply regulators are integrated into the same circuit N300. The
power supply IC contains three different regulators. The main digital power supply regulator is implemented using an external power transistor V300. The other two regulators are completely integrated into N300.
PSCLD, N300 External Components
N300 performs the required power–on timing. The PSCLD N300 internal power on and reset timing is defined by the external capacitor C318. This capacitor
determines the internal reset delay, which is applied when the PSCLD N300 is
initially powered by applying the power supply. The baseband power–on delay
is determined by C315. With a value of 10 nF, the power–on delay after a power–on request has been active is in the range of 50–150 ms. C311 determines
the PSCLD N300 internal oscillator frequency, and the minimum power–off
time when power is switched off.
The sleep control signal from the ASIC D400 is connected via PSCLD N300.
During normal operation, the baseband sleep function is controlled by the ASIC
D400, but since the ASIC is not powered up during the startup phase, the sleep
signal is controlled by PSCLD N300 as long as the PURX signal is active. This
arrangement ensures that the 13 MHz clock provided from RF to the ASIC
D400 is started and stable before the PURX signal is released, and the baseband exits reset. When PURX is inactive high, the sleep control signal is controlled by the ASIC D400.
System Module
N300 requires capacitors on the input power supply as well as on the output
from each regulator to keep each regulator stable during different load and temperature conditions. Due to EMC precautions, a filter using C301, L302 and
L303 has been inserted into the supply rail. This filter reduces the high frequency components present at the VBAT from exiting the baseband into the power
supply. The regulator outputs also have filter capacitors for power supply filtering and regulator stability. A set of different capacitors are used to achieve a
high bandwidth in the suppression filter.
PSCLD, N300 Control Bus
The PSCLD, N300 is connected to the baseband common serial control bus.
This bus is a serial control bus from the ASIC D400 to several devices on the
baseband. This bus is used by the MCU to control the operation of N300 and
other devices connected to the bus. N300 has two internal 8 bit registers and
the PWM register used for charging control. The registers contain information
for controlling reset levels, charging HW limits, watchdog timer length, and
watchdog acknowledgement.
The control bus includes three wires: clock, serial data, and chip select for each
device on the bus. From the PSCLD N300 point of view, the bus can be used
for writing only. It is not possible to read data from PSCLD N300 by using this
bus.
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The MCU can program the HW reset levels when the baseband exits/enters reset. The programmed values are retained until PSCLD N300 is powered off,
i.e. the power supply is cut off. At initial power–on, when PSCLD is powered–
on, the default reset level is used. The default value is 5.1 V, with the default
hysteresis of 400 mV. This means that reset is exit at 5.5 V when the PSCLD
N300 is powered for the first time.
The watchdog timer length can be programmed by the MCU using the serial
control bus. The default watchdog time is 32 s with a 50 % tolerance. The complete baseband is reset if the watchdog is not acknowledged within the specified time. The watchdog is running while PSCLD N300 is powering–up the system but PURX is active. This arrangement ensures that if for any reason the
supply voltage doesn’t increase above the reset level within the watchdog time
the system is reset by the watchdog. As the time PURX is active is not exactly
known, and depends upon startup conditions, the watchdog is internally acknowledged in PSCLD when PURX is released. This gives the MCU always the
same time to respond to the first watchdog acknowledge.
The PSCLD N300 also contains a switch for connecting and the supply voltage
to the baseband A/D converters. The switch state can be changed by the MCU
via the serial control bus. When PURX is active, the switch is open to prevent
the supply voltage from being applied to the baseband measurement circuitry,
which is powered off. Before any measurement can be performed, the switch
must be closed by MCU.
Technical Documentation
SIM Interface and Regulator in N300
The SIM card regulator and interface circuit is integrated into PSCLD N300.
The benefit from this is that the interface circuits are operating from the same
supply voltage as the card, avoiding the voltage drop caused by the external
switch used in previous designs. The PSCLD N300 SIM interface also acts as
voltage level shifting between the SIM interface in the ASIC D400 operating at
3V and the card operating at 5V. Interface control in PSCLD is direct from
ASIC, D400 SIM interface. The MCU can select the power supply voltage for
the SIM using the serial control bus. The default value is 3V which needs to be
changed to 5V before power–up of the SIM interface in ASIC D400. The regulator enable and disable is controlled by the ASIC via SIMI(2).
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Power–Up Sequence
PSCLD
N300
VBAT
Watchdog
disable
5,21,37
39,44
25
23
28
30
16,18,19
C310
VL VSL VA
40
35
26 120
17 130
14
13
CRFCONT
N601
Purx
Serial Bus
VCXO Enable
CHARGAlarm
1415
129
VCXO
SRAM, FLASH
D440 D430
22
13 MHz
Address Bus
ASIC
D400
Watchdog
Register
32 kHz
125 126
Data Bus
System Module
83
84
MCU Clock
82
MCU Reset
81
48 51
DSP Reset
DSP Clock
MCU
D420
Power–On Reset Operation
The system power–up reset is generated by the regulator IC N300. The reset
is connected to the ASIC D400 that is reset whenever the reset signal PURX is
low. The ASIC D400 then resets the DSP D360, the MCU D420, and the digital parts in N450. When reset is removed, the clock supplied to the ASIC D400
is enabled inside the ASIC. At this point the 32 kHz oscillator signal is not enabled inside the ASIC, since the oscillator is still in the startup phase. To start
up the block requiring 32 kHz clock, the MCU must enable the 32 kHz clock.
The MCU reset counter is now started and the MCU reset is still kept active
low. A 6.5 MHz clock is started to MCU in order to put the MCU D420 into reset. The MCU is a synchronous reset device and needs a clock to reset. The
reset to MCU is set inactive after 128 MCU clock cycles, and MCU is started.
DSP D360 and N450 reset is kept active when the clock inside the ASIC D400
is started. A13 MHz clock is started to DSP D360 and puts it into reset. D360
is a synchronous reset device, and requires a clock to enter reset. The N450
digital parts are reset asynchronously and do not need a clock to be supported
to enter reset.
As both the MCU D420 and DSP D360 are synchronous reset devices, all interface signals connected between these devices and ASIC D400 which are
used as I/O are set into input mode on the ASIC D400 side during reset. This
avoids bus conflicts occurring before the MCU D420 and the DSP D360 are
actually reset.
The DSP D360 and N450 reset signal remains active after that the MCU has
exited reset. The MCU writes to the ASIC register to disable the DSP reset.
This arrangement allows the MCU to reset the DSP D360 and N450 whenever
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needed. The MCU can put DSP into reset by writing the reset active in the
ASIC D400 register
MCU
The baseband uses a Hitachi H3001 type of MCU. This is a 16–bit internal
MCU with 8–bit external data bus. The MCU is capable of addressing up to 16
MByte of memory space linearly, depending upon the mode of operation. The
MCU has a non multiplexed address/data bus which means that memory access can be done using less clock cycles thus improving the performance but
also tightening up memory access requirements. The MCU is used in mode 3
which means 8–bit external data bus and 16 Mbyte of address space. The
MCU operating frequency is equal to the supplied clock frequency. The MCU
has 512 bytes of internal SRAM. The MCU has one serial channel, USART that
can operate in synchronous and asynchronous mode. The USART is used in
the MBUS implementation. The clock required for the USART is generated by
the internal baud rate generator. The MCU has 5 internal timers that can be
used for timing generation. Timer TIOCA0 input pin 71 is used for generation of
netfree signal from the MBUS receive signal which is connected to the MCU
USART receiver input on pin 2.
Technical Documentation
The MCU contains 4 10–bit A/D converters channels that are used for baseband monitoring.
The MCU, D420 has several programmable I/O ports which can be configured
by SW. In this case, the data bus lines D0–D7 are used for baseband control
functions. It is not used as part of the data bus.
MCU Access and Wait State Generation
The MCU can access external devices in 2 state access or 3 state access. In
two state access the MCU uses two clock cycles to access data from the external device In 3 state access the MCU uses 3 clock cycles to access the external device or more if wait states are enabled. The wait state controller can operate in different modes. In this case, the programmable wait mode is used.
This means that the programmed amount of wait states in the wait control register are inserted when an access is performed to a device located in that area.
The complete address space is divided into 8 areas each area covering 2
MByte of address space. The access type for each area can be set by bits in
the access state control register. Furthermore, the wait state function can be
enabled separately for each area by the wait state controller enable register.
This means that in 3 state access, two types of access can be performed with a
fixed setting:
Page 4–12
– 3 state access without wait states
– 3 state access with the amount of wait states inserted determined by the
wait control register
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Technical Documentation
If the wait state controller is not enabled for a 3 state access area, no wait
states are inserted when accessing that area even if the wait control register
contains a value that differs from 0 states.
MCU Flash Loading
The flash loading equipment is connected to the baseband by means of the
service adapter. The power supply for the baseband is supplied via the adapter
and controlled by the flash programming equipment. The baseband module is
powered up when the power is connected to the power supply connector.
Five signals are required for the flash programming, with the addition of the
power supply. The baseband MCU will automatically wait for flash down–loading to be performed if one of the two following criteria are met.
– The flash is found to be empty when tested by the MCU
– The serial clock line at the baseband MCU is forced low when the MCU is
exiting reset
The second alternative is used for reprogramming as the flash is not empty in
this case. To allow the serial clock line to be forced low during MCU initial boot
there is a requirement that the flash prommer can control the power on of the
baseband module. This is done by controlling the switching of the power supply. This arrangement allows the baseband module to operate in normal mode
even if the flash prommer is connected but not active. The flash prommer also
disables the power supply watchdog during flash programming to prevent unwanted reset of the baseband. The programming voltage to the flash is applied
when the flash prommer has detected that the baseband module is powered.
This detection is performed by monitoring the serial interface RS_RX line from
the baseband. The RS_RX line is pulled high by a pull–up resistor in idle. The
VPP voltage is set to 5V as it is not known at this point what type of device is
used.
System Module
The following diagram shows the block diagram for the baseband flash programming circuitry.
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X120
7
VPP
1
RS_RX
2
RS_TX
3
SCK_RTS
4
WDDis
15
GND
VBAT
Flash Prommer
5... 22
PSCLD
N301
26
VL,VSL
40
FLASH pin11 Vpp
PSCLD pin 22 WDDis
GND
Programming Voltage Vpp
ASIC pin 120
PurX
ASIC pin 130 PwrDown
VLC
R436
11
FLASH
D430
ASIC pin 51 CSelX
2,71
1
3
MCU pin 55 RdX
MCU
D420
Internal
RAM
38(9)37(24)9(24)12(10)
MCU pin 56 WrX
Technical Documentation
PSCLD pin 26 PurX
Master Reset
56
55
MCUResX
51 82
MCUClk
MCUAdrress
MCUData
WrX
RdX
SRAM
D440
55
56
8148
49
RAMCSelX
30
5
32
120
ASIC
D400
BOOT
ROM
MCU pin 56 WrX
MCU pin 55 RdX
The interface lines between the flash prommer and the baseband are in low
state when power is not connected by the flash prommer. The data transfer between the flash programming equipment and the base band is synchronous,
and the clock is generated by the flash prommer. The same MCU USART that
is used for MBUS communication is used for the serial synchronous communication. The PSCLD watchdog is disabled when the service adapter and flash
prommer are connected.
After the service adapter has been connected to the board the power to the
baseband module can be connected by the flash prommer or the test equipment. All interface lines are kept low, except for the data transmit from the
baseband that is in reception mode on the flash prommer side, this signal is
called RS_TX. The MCU boots from ASIC and investigates the status of the
synchronous clock line. If the clock input line from the flash prommer is low or
no valid SW is located in the flash, MCU forces the initially high RS_TX line low
acknowledging to the flash prommer that it is ready to accept data.
The flash prommer sends data length, 2 bytes, on the RS_RX data line to the
baseband. The MCU acknowledges the 2 data byte reception by pulling the
RS_TX line high. The flash prommer now transmits the data on the RS_RX line
to the MCU. The MCU loads the data into the internal SRAM. After having received the transferred data correctly MCU puts the RS_TX line low and jumps
into internal SRAM and starts to execute the code. After a guard time of 1 ms
the RS_TX line is put high by the MCU. After 1 ms the RS_TX is put low indicating that the external SRAM test is going on. After a further 1 ms, the RS_TX
is put high indicating that external SRAM test has passed. The MCU performs
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the flash memory identification based upon the identifiers specified in the Flash
Programming Specifications. In case of an empty device, identifier locations
shows FFH, the flash device code is read and transmitted to the Flash Prommer.
Internal SRAM
Reset
RS_TX
Boot OK
Length OK
execution begin External SRAM
External SRAM
test going on
1 ms
System Module
Ready to send
Flash ID
test passed
After that, the device mounted on baseband has been identified, and the Flash
Prommer down–loads the appropriate algorithm to the baseband. The programming algorithm is stored in the external SRAM on the baseband module,
and after having down–loaded the algorithm and data transfer SW, the MCU
jumps to the external SRAM and starts to execute the code.
The MCU now asks the prommer to connect the flash programming power supply. This SW loads the data to be programmed into the flash, and implements
the programming algorithm that has been down loaded.
Flash, D430
A 8 MBit Boot Block flash is used as the main program memory D430. The device is 3 V read/program with external 12V VPP for programming. The device
has a lockable boot sector. This function is not used since the complete code is
reprogrammed. The Boot sector is located at the ”bottom”, definition by Intel,
address 00000H–03FFFH. The block is unlocked by a logic high state on pin
12. This logic high level is generated from VPP. The device can be programmed by a VPP of 5V but the programming procedure takes longer. To improve programming, the programming voltage used is 12V. The speed of the
device is 150 ns. The MCU operating at 6.5 MHz will access the flash in 2 state
access, requiring 150 ns access time from the memory.
SRAM D440
The baseband is designed to take two different size of SRAMs, 64kx8 and
128kx8, not at the same time. The required speed is 150 ns as the MCU will
operate at 6.5 MHz and the SRAM will be accessed in 2 state access. The
SRAM has no battery backup which means that the content is lost even during
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short power supply disconnections. As shown in the memory map, the SRAM is
not accessible after boot until the MCU has enabled the SRAM access by writing to the ASIC register.
EEPROM D445
The baseband is designed to take an 2kx8 serial EEPROM. TFK–1 will use the
2kx8 serial device over the I2C bus. The I2C bus protocol is implemented in
SW and the physical implementation is performed on MCU Port 4.
MCU and Peripherals
MCU Port P4 Usage
MCU, D420 port 4 is used for baseband control.
Port Pin MCU pin Control Function Remark
P40 5 SLIC–CTRL 0
P41 6 SLIC–CTRL 1
Technical Documentation
P42 7 SLIC–CTRL 2
P43 8 RS_DSR
P44 9 EEPROM SCK
P45 10 EEPROM SDA
P46 11 EEPROM write enable Active low
P47 12 RS_CTS
Baseband A/D Converter Channels usage in N450 and D420
The auxiliary A/D converter channels inside RFI2 N450 are used only for measuring of the system board temperature by the MCU.
The MCU has 4 10 bit A/D channels which are used for baseband voltage monitoring. The MCU can measure supply voltage, accessory detection (ID), loop
current (IBBDET) and loop voltage (VBBDET) by using it‘s own converters.
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Baseband N450 A/D Converter Channel Usage
Name: Usage: Input volt. range
Chan 0 System board temperature 0...3.2 V
Chan 1–7 not used
MCU Baseband A/D Converter Channel Usage
Name: Usage: Input volt. range
Chan 0 Supply voltage 0...3.2 V
Chan 1 Accessory detection 0...3.2 V
Chan 2 IBBDET 0...3.2 V
Chan 3 VBBDET 0...3.2 V
Supply Voltage Measurement
The supply voltage is measured using MCU N420 A/D converter channel 0.
The supply voltage supplied to the A/D converter input is switched off when the
baseband is powered off. The supply voltage measurement voltage is supplied
by PSCLD N300, which performs switch–off, and scaling with a scaling factor
of R1(R1+R2). The measurement voltage is filtered by a capacitor to achieve
an average value that is not depending upon the current consumption behavior
of the baseband. To be able to measure the supply voltage during transmission
pulse, the time constant must be short. The value for the filtering capacitor is
set to 1 nF C319. The scaling factor used to scale the supply voltage must
be 1:3, which means that a 9V supply voltage will give 3V A/D converter input
voltage. The A/D converter value in decimal can be calculated using the following formula:
System Module
A/D = 1023xR1xU
where K is the scaling factor. K = R1/((R1+R2)xU
Audio Control
The audio codec N130 is controlled by the MCU D420. The ASIC generates a
512 kHz data clock, and a 8 kHz synchronization signal for the PCM data bus.
Data is put out on the bus at the rising edge of the clock and read in at the falling edge. Data from the DSP D360 to the audio codec N130 is transmitted as
a separate signal from data transmitted from the audio codec, N130 to the DSP
D360. The communication is full duplex synchronous. The transmission is
started at the falling edge of the synchronization pulse. 16 bits of data is transmitted after each synchronization pulse.
/((R1+R2)xU
BAT
) = 1023xU
ref
BAT
ref).
xK
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System Module
LATX
C132
XEAR
LARX
C134
R133 C133
C135
14
8
6
25
24
CODEC
N130
CLK
CSX
DATA
11
12
13,16
23
22
20
19
10
17
C140
Serial Bus
AUDIO DATA IN
AUDIO DATA OUT
X120
SYSTEM
CONNECTOR
17
C137
CLK 512 kHz
SYNC 8 kHz
VLC
R113
Technical Documentation
MCU
D420
293727
3341
31
DSP
D360
EXT EQUIPM. INDICATION
R208
IRQ1X
68
Data, Addr Bus
A/D Converters
Data, Addr Bus
78
42,44,46
40
41
R115
MCU pin 64
ASIC
D400
122
The 512 kHz clock is generated from 13 MHz using a PLL type of approach,
which means that the output frequency varies as the PLL adjusts the frequency.
The average frequency is 512 kHz. The clock is not supplied to the codec when
it is not needed. The clock is controlled by both MCU and DSP. DTMF tones
are generated by the audio codec and for that purpose, the 512 kHz clock is
needed. The MCU must switch on the clock before the DTMF generation control data is transmitted on the serial control bus.
The serial control bus uses clock, data, and chip select to address the device
on the bus. This interface is built into the ASIC, and the MCU writes the destination and data to the ASIC registers. The serial communication is then initiated by the ASIC. Data can be read form the audio codec N130 via this bus.
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Technical Documentation
DSP
The DSP used in TFK–1 is the TI 320LC546. This is a 16 bit DSP that can use
external and/or internal memory access. The DSP can operate in two modes
microprocessor mode or micro–controller mode. The difference between the
two modes is that in microprocessor mode the DSP boots from external
memory, while in the micro–controller mode the DSP boots from internal ROM.
The DSP external memory access is divided into data, program, and I/O access. The type of access is indicated on three control pins that can be used for
memory control.
The DSP D360 executes code from the internal ROM. The baseband also provides external memories for the DSP, D371, D372, D381, and D382 (Note:
These memories are not fitted in all transceivers). The DSP is capable of addressing 64 kword of memory. The memory area is divided into a code execution area and a data storage area. The code execution area is located at address 4000H–FFFFH in the internal ROM. The external memories are arranged
in such a way that the DSP can access the external memories both as data
storage and code execution. The memory chip select is taken from the memory
access strobe signal from the DSP. This means that the memory is active during any memory access. The SRAMs are configured in chip select controlled
write mode. This means that both the write signal and the output enable signal
are active at the same time, and the actual write occurs at the rising edge of the
chip select signal. This implementation is required since the DSP supports only
one signal for write/read control.
System Module
The DSP is operating from the 13 MHz clock. In order to get the required performance, the frequency is internally increased by a PLL by a factor of 3. The
PLL requires a settling time of 50 us after that the clock has been supplied before proper operation is established. This settling counter is inside the DSP although the ASIC D400 contains a counter that will delay the interrupt with a
programmable amount of clock cycles before the interrupt causing the clock to
be switched on is presented to the DSP. The DSP has full control over the clock
supplied to it. When the DSP is to enter the sleep mode the clock is switched
off by setting a bit in the ASIC register. The clock is automatically switched on
when an interrupt is generated.
The DSP also has two synchronous serial channels for communication. One
channel is used for data transmission between the DSP and the audio codec.
This channel is operating at 512 kbits, and clock and synchronization signal is
provided by the ASIC D400. The other channel is used for debugging purposes, and uses the same clock and synchronization signals. The DSP has an
interrupt controller servicing four interrupts and one non maskable interrupt,
NMI. The interrupts have fixed priority which can only be changed by changing
the interconnection between the interrupt sources by HW
The ASIC contains DSP support functions as modulator, encryption/decryption
using algorithms A5/A51, RF power ramp generation/AGC control, AFC control,
synthesizer serial interface, frame counters, timer, RFI2 interface, and RX and
TX power control timing. The RF power ramp timing/AGC control, AFC control,
.
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and synthesizer control are timed to the value of the frame counter. This means
that data is loaded into the registers, and transferred when the frame counter
and the reference values match. This allows timing of the synthesizer control
power ramp and start of TX data to be controlled very precisely.
As the receiver and the transmitter is not operating at the same time, the TX
power ramp function is used to control the AGC in the receiver during the reception. This requires the DSP to continuously modify the values in the TX
ramp SRAM to fit the ramp during TX and the AGC value during reception.
DSP ASIC Access
The DSP is accessing the ASIC in the DSP I/O area. 2 wait states are required
for the ASIC access. Some of the DSP registers located in the ASIC are retimed to the internal ASIC clock and requires special handling with respect to
consecutive writing. This means that the same register can not be written again
until a specified time has passed. To cope with this, DSP is inserting NOP
instructions to satisfy this requirement.
DSP Interrupts
Technical Documentation
The DSP supports 4 external interrupts. Three interrupts are used. The ASIC,
D400 generates two of the interrupts. One interrupt is generated by the RFI2
N450 auxiliary A/D converter. This interrupt is generated when a baseband
measurement A/D conversion is completed. The interrupts to the DSP are active low.
INT0, which is the highest priority interrupt, is used for data reception from the
receiver and is generated by the ASIC. The INT1 signal is used for auxiliary
A/D channel conversions generated by the RFI2. This interrupt is generated by
RFI2 and is a result of measurement requests from the DSP. INT3 is a low
priority interrupt generated by the ASIC timer. The DSP programs the timer value and an interrupt is given when the timer expires. The interrupt must be active at least 1 DSP clock cycle as it is sampled on the rising/falling edge by the
DSP. All interrupts are active low.
Unused interrupt controller inputs are tied high.
DSP Serial Communications Interface
The DSP contains two synchronous serial communications interfaces. One of
the interfaces is used to communicate with the audio codec N130. The 512
kHz clock required for the data transfer is provided by D400 as well as the 8
kHz synchronization signal. Data is transferred on to lines, RX and TX creating
a full duplex connection. Data is presented on the bus on the first rising edge of
the clock after the falling edge of the synchronization pulse. Data is read in by
each device on the falling edge of the clock. Data transfer is 16 bits after each
synchronization pulse.
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Technical Documentation
The DSP D360 has control over the clock provided to the audio codec. The
DSP can switch on the clock to start the communication, and switch it off when
it is not needed. This clock is also under control of MCU D420.
RF Synthesizer Control
The synthesizer control is performed by the DSP D360 using the ASIC D400
as the interfacing and timing device. Different synthesizer interfaces are supported, and the required interface can be selected by the DSP at the initialization stage of the ASIC. The synthesizer interface also includes timing registers
for programming synthesizer data. The DSP loads the synthesizer data into the
transmission registers in the ASIC synthesizer interface together with the timing
information. The system timing information is used for synthesizer data loading.
When the system timing register, frame counter, value matches the timing value
programmed into the synthesizer interface, the interface transmits the loaded
data to the RF synthesizer, and the VCO frequency is changed accordingly. As
the synthesizer may be powered off when not needed, the interface pins towards the synthesizer can be put in tri–state or forced low when the interface is
not active.
System Module
RFI2 N450 Operation
The RFI2 N450 contains the A/D and D/A converters to perform the A/D conversion from the received signal and the D/A converters to perform the conversion for the modulated signal to be supplied to the transmitter section. In addition, the RFI2 chip also contains the D/A converter for providing AFC voltage to
the RF section. This AFC voltage controls the frequency of the 13 MHz VCXO
which supplies the system clock to the baseband. The RFI2 N450 also contains
the D/A converter to control the RF transmitter power control. The power control values are stored in the ASIC D400 and at the start of each transmission,
the values are read from the ASIC D400 to the D/A converter producing the
power control pulse. This D/A converter is used during the reception to provide
AGC for the receiver RF parts.
The RFI2 contains the interface between the baseband and the RF. The RFI2
circuit contains the A/D converters required for the receiver and the D/A converters required for the transmission. In addition, the RFI2 contains a 10 bit D/A
converter for AFC control, and one of the receiver A/D converters has a multiplexed input for 8 additional channels used for baseband monitoring functions.
The A/D converters are 12 bit sigma delta type. This means that the digital output is centered around the reference voltage and the output value is both negative and positive. The RFI2 has an internal reference voltage for the A/D and
D/A converters that can be switched off to save power. The reference has external filtering capacitors to improve the converter performance. The transmitter
D/A converters are followed by interpolator and post filter. The filter is of switch
capacitor type and the filter parameters are taken into account when modulator
parameters are calculated. The AFC D/A converter is static and requires no
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clock for operation. This means that the RFI2 clock can be switched off and the
AFC value will be kept.
One of the A/D converters used for receiver signal conversion can be used as
an auxiliary converter that supplies 8 channels for baseband measurement purposes. When the converter is used in this mode, each conversion generates an
interrupt directly to the DSP. The DSP operates this converter via the ASIC
D400.
Data communication between the ASIC D400 and RFI2 N450 is carried out on
a 12 bit parallel data bus. The ASIC D400 uses 4 address lines to access RFI2
N450. Depending on the direction of the communication, either the write control
signal is used to write data to RFI2 N450 or the read signal is used to read
data from RFI2 N450. The ASIC D400 supplies 13 MHz clock to the RFI2
N450. This clock is used as reference for the A/D and D/A converters. Communication between the ASIC D400 and the RFI2 N450 is related to the clock.
The auxiliary channels supported by the RFI2 uses one of the receiver A/D
converters as the A/D converter. Due to the type of converter used for the receiver converters, the value read from the auxiliary channels can be negative.
The input voltage applied to the auxiliary channels must be within 0.5–3.0 V.
A 12 bit value is received from the auxiliary channel measurement. The auxiliary channel conversion complete is sent direct to the DSP as an interrupt, INT1.
The DSP reads the value using direct access through the ASIC to the RFI2
converter. The conversion is started by the DSP writing the address of the
channel to be measured to the ASIC register. The ASIC then writes the selected channel to RFI2, and the conversion is started. The DSP may sample
the same channel for more than one value as the A/D converter will produce
continuously new values. Several samples may be used for example in supply
voltage measurement to calculate an average value from the results.
Technical Documentation
The RFI2 N450 digital supply is taken from the baseband main digital supply.
The analog power supply, 4.5V is generated by a regulator supplied from the
RF section. The analog power supply is always supplied as long as the baseband is powered, if R311 is assembled. The RFI2 N450 analog power supply
can be switched off during sleep by removing R311 and adding R312. In this
case the RFI2 N450 analog power supply is in the control of the PSCLD N300
sleep control signal.
Receiver Timing and AGC
RF receiver power on timing is performed by the ASIC D400. The DSP D360,
can program the time when the receiver is to be powered on. The timing information is taken from the system timing that is based upon the frame counter
inside the ASIC D400, which is synchronized to the base station carrier frequency using AFC to tune the receiver. As transmission and reception takes
place at different times, the D/A converter used for transmitter power control is
used to control the AGC of the receiver during reception. This requires the DSP
D360 to alter the content of the SRAM containing the information that is written
to the D/A converter for the reception and the transmission.
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