NOTE: Do not attempt to remove the antenna from the B–cover.
NSD–3
Disassembly / Troubleshooting Instructions
1.
Remove battery
3.
Remove back cover screws (4pcs).
NOTE! When assembling the B
cover screws, use 17 Ncm torque.
Remove dust cap
2.
by finger nail
Turn around and remove
UI module screws (2 pcs)
Issue 1 06/1999
5.
4.
Carefully remove A–cover, keymat, power keymat and speaker will follow. Note snap fixings !
Nokia Mobile Phones Ltd.
Page 3
NSD–3
Disassembly / Troubleshooting Instructions
6.
Remove UI–module and frame.
PAMS Technical Documentation
7.
Remove engine module screw (1 pc).
NOTE! When assembling the screw use
17 Ncm torque.
Remove vibra motor.
9.
8.
Remove engine module
Remove microphone
Page 4
Nokia Mobile Phones Ltd.
Issue 1 06/1999
PAMS Technical Documentation
Disassembly / Troubleshooting Instructions
Trouble Shooting
Baseband Troubleshooting
Each main portion of the circuit will be described in enough detail for the
troubleshooter to determine whether or not that part of the circuit being
evaluated is functional. It will be helpful to use the placement diagram,
which illustrates all of the necessary testpoints in the baseband circuit, to
troubleshoot the phone. The placement diagram is intended to be used
concurrently with this document.
Main Circuit Sections
Power Circuitry
NSD–3
There are two ASICs in the baseband section, which supply power to
most of the phone. CCONT is the main power management ASIC, and
PENTA is used to supply additional switchable regulators for use in RF.
Two discrete linear regulators are used as well.
CCONT
CCONT is the main power management ASIC. It’s features include eight
2.8V linear regulators, a linear regulator with adjustable output, a reference voltage output, a 5V switch mode regulator, an 8 channel A/D converter, and 32kHz clock circuitry. Each of the main functions and signals
are described below, including information on how to verify correct operation.
Vbat
CCONT is powered directly from the battery voltage, Vbat. Since CCONT
is a uBGA, the physical connection of CCONTs power pins can not be verified. Vbat must be checked instead at the closest external component,
which is shown as TP1. Valid voltages are 3.1–4.1V and should always be
powered; assuming voltage is applied to the battery terminals.
Vref
Vref is used as a reference voltage both internal and external to CCONT. It
is switchable between the nominal voltages of 1.500V and 1.251V, with
the default at power up being 1.500V. The phone uses the 1.251V reference, so once flash software is running Vref should switch to 1.251V.
Check Vref at TP2. Valid voltages are 1.478 – 1.523V and 1.244 – 1.258V,
respectively.
Linear Regulators
1. Vbb
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Page 5
NSD–3
Disassembly / Troubleshooting Instructions
Vbb supplies power to most of the baseband circuitry. This regulator
should be on at all times during CCONTs power on, reset, and sleep
modes. Nominal voltage is 2.8V, but anything in the range 2.7–2.87V is
valid. Vbb is found at TP3.
2. RF Regulators (VR1–VR7)
VR1 through VR7 are referred to as the RF regulators. Most are switch-
able, and all should be within 2.67 – 2.85V when they are on (2.8V nominal). VR1 and VR6 are always on during CCONTs power on mode. The
rest of the regulators are switchable and are normally on during one or
more of the various phone states, but may be turned on at any time with
the service software in order to verify their output. The RF regulators can
be checked at the following test points.
a) VR1 – TP10
b) VR1_SW – TP11
c) VR2 – TP32
d) VR3 – TP30
e) VR4 – TP4
f) VR5 – TP31
g) VR6 – TP9
h) VR7 – TP33
PAMS Technical Documentation
3. V2V (VMAD)
The V2V regulator is intended to power the MAD4 ASIC core. The output
is adjustable from 1.3V to 2.65V in 0.225V steps, and is used with MAD4
ver 3 (but not MAD4 ver 2). The output at V2V when MAD4 ver 3 is
stuffed should be 1.750V ±5% and can be checked on TP2.
Switch mode regulator
1. V5V (+5V_POWER)
V5V is a 5V switch mode regulator, which always remains on during
CCONT power on mode. Valid voltages are 4.8V to 5.2V, and it can be
checked at TP13.
2. VSIM (3V_5V)
VSIM is powered by the same switch mode regulator as V5V, however, it
is switchable between 3V and 5V. The phone uses VSIM as the 3V
FLASH programming voltage, so it should remain off unless the phone is
being flashed. Valid voltages are 2.8V to 3.2V, and it can be checked at
TP7.
A/D Conversion
CCONT contains a 10–bit A/D converter that is multiplexed between 8 different inputs. They are used mainly for battery and charger monitoring.
The 8 inputs are Vbat (battery voltage), ICHAR (charger current), VCHAR
(charger voltage), BSI (battery type), BTEMP (battery temperature),
VCXOTEMP (PA temperature), RSSI (AMPS receive signal strength), and
EAD (accessory detection). These readings can be accessed through the
service software. Check for shorts or opens on the resistor networks connected to these signals if the flash align test software reports that they are
out of range.
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Issue 1 06/1999
PAMS Technical Documentation
Watchdog
CCONTs watchdog circuitry consists of an eight bit down counter that
causes CCONT to power down when zero is reached. The counter may
be reset by loading a new, non–zero value into the watchdog register via
CCONTs serial bus. It is difficult to verify the watchdog function, but the
serial bus may be verified.
There is a watchdog disable pin which allows the watchdog timer to expire without shutting down the phone, but this pin is mainly used as one of
the methods to turn on CCONT from power off mode. While the phone
power key is pressed, this pin should be pulled low and can be checked
at TP29.
The watchdog can be disabled by pulling down the above mentioned
pin(WDDISX) by installing a 0 Ohm resistor at R307, and removing R325.
Serial bus
Since the serial bus is used to control almost all of CCONTs functions,
any shorts or open circuits on these three lines would cause CCONT to
be completely nonfunctional. The main symptoms are the following:
CCONT will turn on when the power key is pressed (verify this by checking Vbb), but will then power off after 32 seconds. All three serial bus signals (CCONTCSX, UIF_CCONT_SDIO, and UIF_CCONT_SCLK) should
toggle when attempting to write to a CCONT register.
NSD–3
Disassembly / Troubleshooting Instructions
Note: If the LCD does not come on during this time, however, it may indicate that the serial bus is functional, but phone does not have valid flash
code.
PENTA
PENTA supplies power to the RF section. It has 5 independently switchable regulators that are controlled via separate enable pins. There is also
a common enable pin that must be active in order to turn on any of the
regulators. Each of the regulators, P1–P5, should have output voltages
between 2.7V and 2.85V (2.8V nominal). These can be checked at the following test points.
a) P1 – TP16
b) P2 – TP15
c) P3 – TP17
d) P4 – TP18
e) P5 – TP19
External regulators
There are three regulators used in addition to CCONT and PENTA. One
is controlled by CCONTs VR7 regulator output and used as a low noise
power source for RF. This regulator is 2.8V nominal and can be checked
at TP8.
The second regulator is used to power the data cable accessory, so output is enabled only when a data cable accessory is detected. This regulator is also 2.8V nominal and can be checked at TP42 (shares SGND).
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NSD–3
Disassembly / Troubleshooting Instructions
The third regulator is used to power the DSP portion of MAD4. It is enabled by Vbb, and difference between the rise times of the DSP regulator
and Vbb should be less than 200usec. This regulator is 2.8V nominal and
can be checked on pin 1, 30, or 115 of the MAD4 ASIC.
Clocks
Sleep Clock
The 32kHz sleep clock is generated by CCONT, and can be checked at
TP26. The 32kHz square wave will be present only after the phone is
turned on. If no signal is present on this line, check the output of the oscillator at R304. This signal should be a 2Vp–p clipped signal riding on 1.5V
DC.
System Clock
The 19.2MHz system clock is generated by the VCTXO in the RF section,
and then squared in CAFE. Check TP20, which should be approximately
a 0.5V sinewave riding on 1.8V DC. Check TP22, which should be a 2.8V
squarewave. This clock is not active during the phone’s sleep mode
(CLK_EN is low during sleep mode).
PAMS Technical Documentation
CDMA clock
The CDMA clock is 9.8MHz and is generated in CAFE with a PLL. This
should be a 2.8V square wave and can be verified at TP21.
Charging Circuit
The charging switch, CHAPS, is controlled by a PWM from CCCONT.
This PWM can be at 1Hz or at 32Hz, with varying duty cycles, and should
only be active when a charger is detected. The frequency should be 1Hz
when an ACP–7 is detected and 32Hz when an ACP–9 is detected. To
verify correct operation of CHAPS, monitor the charging current (ICHAR)
with the service software. When the PWM is off, current should be
approximately 200uA. When the PWM is on, it should be greater than
approximately 300mA.
CAFE
The CAFE ASIC performs various functions with respect to the RF circuitry and audio. It digitizes the analog voice signals from the microphone as
well as converts received digital data to voice signals to be sent to the earpiece. This also includes accessory microphones and speakers. It also
generates and decodes I and Q data for CDMA, and demodulates FM
(AMPS) signals. CAFE also acts as a clock squaring circuit and CDMA
clock generator.
Page 8
Microphones
The internal microphone is biased using transistor V201, which is powered by VR1_SW (TP11 2.75VDC). Check also the output of V201).
Nokia Mobile Phones Ltd.
Issue 1 06/1999
PAMS Technical Documentation
V201, R220 and C212 should be installed, and R202 should not be
installed. MICP should be about 1.7VDC, and MICN should be about
0.4VDC. Internal microphone bias should only be active during a call.
The XMIC is biased by the AUXOUT signal (pin 75) through R209 and
R208. The output voltage at pin 75 is about 1.5V.
Earpiece and XEAR
The internal earpiece is driven differentially from pins 77 and 80 (EARP
and EARN). The DC voltage on these two pins is 1.35V. The difference
in the DC voltage between these two pins should not be more than 50mV.
The XEAR signal drives audio to the external accessories. The CAFE
signal name is HF (pin 81). The DC level on this pin should be 1.35V.
HFCM (pin 82) should also be at 1.35V. The difference in DC voltage between these two pins should not be more than 50mV.
Note that SGND is the return path for XMIC and XEAR.
Clock circuit
A 19.2MHz sinusoid should appear on pin 25 (Also TP20). This is from
the VCTCXO in the RF. The CAFE will then produce a 19.2MHz clock at
pin 18 (TP22), and a 9.83MHz clock on pin 19 (TP21). See also Clocks
section.
NSD–3
Disassembly / Troubleshooting Instructions
MAD4
AMPSMOD
AMPSMOD is the voice signal to modulate (FM) the RF carrier for transmission. It is the voice signal that has been processed by the DSP
(MAD4) for transmission in AMPS mode. It represents a modified version
of the signal produced by the microphone (CAFÉ pin 58).
Transmit and Receive RF Signals
In CDMA mode, receive I and Q channel RF signals [RXIQ(3:0)] come
into CAFÉ at pins 44, 45, 47, and 48. C207, C208, C209, and C210 can
also be checked for these signals since they are in series with the CAFÉ
pins. Transmit I and Q RF signals [TXIQ(3:0)] can be seen at pins 55, 56,
59, and 60 and C201, C204, C222, and C224.
In AMPS mode, the modulated receive RF signals (LIM_P and LIM_N)
can be seen coming into pins 23 and 24 and C216 and C217. For the
AMPS Transmit signal, see AMPSMOD above.
The MAD4 ASIC is the core of the baseband functionality and basically
contains the DSP, MCU, and CDMA logic. The DSP is used to perform
functions such as RF control, DTMF tone generation, and it implements
the vocoder. The MCU is used to perform functions that do not require as
much power. These are higher level functions such as UI software (key
presses, backlighting, LCD functions, etc.) and mode control.
DSP
The DSP sends control signals to the RF via PDMs. In order to control
RF parameters such as TX_VCO_CAL or TX_LIM_ADJUST, a continu-
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Page 9
NSD–3
Disassembly / Troubleshooting Instructions
ously variable analog signal must be used. Since the DSP outputs only
digital signals, a PDM RC circuit is used to convert the digital output signal to an average analog voltage. A PDM line will always have a series
resistor followed by a shunt capacitor. The output of the MAD4 PDM lines
will appear as squarewave signals. However, after the shunt capacitor the
signals will appear to be DC with perhaps a slight ripple. The RC circuit
acts as an integrator in order to yield the average value (DC) of the
squarewave signal.
The transmit data bus (TXD(7:0)) is 8 bits wide. In CDMA this bus is multiplexed between sending I and Q data. The signals required to transfer
TX data are TXGATE, CLK9M80, and IQSEL. TXGATE must be high to
transfer data, and the data is clocked by CLK9M80, which is running at
9.8MHz. In AMPS mode, CLK9M80 is running at 120kHz, therefore, data
is being transferred from MAD4 to CAFE at 120kHz.
The JTAG lines are intended to be used to operate the DSP (and/or
MCU) externally.
External Regulator
PAMS Technical Documentation
Failures
A separate 2.8V external regulator was added to power the Lead (DSP)
independently due to noise on VBB. Eventually, the next version of MAD4
will be used and the Lead may be powered by VMAD from CCONT. See
External Regulators section under CCONT/Linear Regulators. Note: This
regulator is also mentioned in section Power Circuitry.
MCU
The MCU is used to perform functions that require less processing power
than the DSP. It runs UI software, mode control, interfaces to MBUS,
downloads code to flash, reads and writes the EEPROM, controls charging, and interprets A/D data from CCONT.
Memories
MAD4 interfaces to three memories—Flash, SRAM, and EEPROM. All of
them are powered by 2.8V (Vbb). During Flash programming, Vpp (signal
name is Vff on schematic) is driven with 12V in the factory, and 3V at the
PC flash stations.
Most of the failures will be due to SMD errors. Either solder got where it
wasn’t supposed to be, parts slid off their pads, or possibly the parts were
placed incorrectly. A good visual inspection will uncover a large percentage of failing phones.
Won’t power up
Do a visual inspection. Verify that all parts are on the board correctly, and
that none are missing.
Check that the 32kHz clock turns on when attempting to power up.
Check the power circuitry. This includes VBAT, Vref, and all of the linear
regulators, as well as the Penta regulators. Verify also that the external
regulator that powers MAD4 (LEADVCC) is functional.
Page 10
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PAMS Technical Documentation
Flash Align
Test 9
High current: This indicates that the problem is likely caused by a shorted
component. Check orientation of major components (including RF), and
check for shorts. Likely components are those which are powered directly
from Vbat such as CCONT, the PAs, and various capacitors.
Low current: This indicates that CCONT is not powering on. Verify
CCONT circuitry.
Test 10
Flash: Failure to flash is the main baseband failure. Check all the CCONT
regulators, especially Vbb, VR1, and VR6 for shorts. Check clocks and
reset circuitry. Check for shorts on the address, data, and chip enable
lines on the memories and MAD4. If a short is detected, it may be that it is
beneath the BGA flash and may have to be replaced.
NOTE: Unfortunately, there is no ROM software that can be run when the
phone does not flash. Typically, this software would be used to test all of
the interfaces between MAD4 and its peripherals. Therefore, it must be
visually (or by Ohmmeter) determined whether there is a possible short
between two or more of the address or data lines.
NSD–3
Disassembly / Troubleshooting Instructions
In the field
Solder joints may be adequate for passing manufacturing requirements,
however, they may not hold up to mechanical stress or heat cycling.
Cracked or broken solder may cause failures to occur from simple use.
Reflowing some of the major components may fix problems where the
phone exhibits strange behavior (some buttons may not work, the phone
may not ring, etc.) or may not power on anymore.
Battery will not charge
If the battery won’t charge (phone won’t allow the battery to charge),
check CHAPS and the charging circuit. It may also be necessary to verify
the A/D functionality of CCONT since this is the method of detecting battery type, charger type, etc
Audio failures
If audio fails to be heard from the earpiece (or XEAR), it could be a number of possible problems. Check the following:
Check earpiece contacts.
Verify that the CAFÉ EARP and EARN bias is on. If necessary, check the
entire receive path—Rx voice data comes from the RF through the RXIQ
bus (CDMA) or LIM_P and LIM_N (AMPS), then to MAD4 through RXD
(11:0) (Refer to schematic). See the Baseband section of the Service
Manual for more detail on RXD bus usage.
The Rx voice data then goes back to CAFE on CAFESIO (0), and then to
the earpiece or XEAR. CAFESIO (2) must also be active.
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NSD–3
Disassembly / Troubleshooting Instructions
Conversely, if the transmit audio is not working, the fault could be anywhere in the transmit path. Check the following:
Check microphone contacts.
Microphone bias.
Tx voice data is transferred from CAFÉ to MAD4 on CAFESIO (1). CAFE-
SIO (2) must also be active. Tx voice data is then sent back to CAFÉ on
the TXD bus (See schematic). See the Baseband section of the Service
Manual for more detail on RXD bus usage.
Tx voice data is then sent to RF on the TXIQ bus (CDMA) or AMPSMOD
(AMPS).
PAMS Technical Documentation
Test Point Desig-
nator
31SleepClock32.768 KHz typical Square waveformFrom CCONT to MAD4
25Clk19m2019.2 MHz Square waveformFrom CAFÉ to MAD4
23Clk19M2rf (D201–25)19.2 MHz Sinusoidal waveformFrom RF Synthesizer to CAFÉ and other RF Synthesiz-
24Clk9m89.8 MHz Square waveformFrom CAFÉ to MAD4
36CRB32Khz – 2.8VFrom 32K crystal to CCONT
14MemRdX0 / 2.8 V (active low)From MAD4 to Flash and RAM output enables
15MemWrx0 / 2.8 V (active low)From MAD4 to Flash and RAM write enables
13ROM1SelX0 / 2.8 V (active low)From MAD4 to Flash chip enable
5Clk_En0 / 2.8From MAD4 to FLASH, CCONT and CAFE
1PurX ( D101–116 )0 / 2.8 V (active low)From CCONT to MAD4
35WdDisX2.8 V (active low)CCONT test point for phone diagnosis mode
34PwrOnX0 / 2.8 V (active low)From UI Power Key to MAD4 and CCONT
33ResetX0 / 2.8 V (active low)From MAD4 to CAFE
30Vbat3.1 – 4.1 V valid battery range
3Vbb2.8 V typical (2.7 – 2.87 V)From CCONT to MAD4 and Memories
2VmadN / AFrom CCONT to MAD4
11Vr12.8 V typical (2.67 –2.85 V)From CCONT to 19.2MHz VCTCXO
12Vr1_Sw (MIC bias)0 / 2.75VFrom CCONT to V201 to CAFE
40Vr20 / 2.8 V typical (2.67 –2.85 V)From CCONT to CELL Receiver
38Vr30 / 2.8 V typical (2.67 –2.85 V)From CCONT to RF Receiver
4Vr42.8 V typical (2.67 –2.85 V)From CCONT to PCS Transmitter
39Vr50 / 2.8 V typical (2.67 –2.85 V)From CCONT to CELL Transmitter
10Vr62.8 V typical (2.67 –2.85 V)From CCONT to CAFE
41Vr70 / 2.8 V typical (2.67 –2.85 V)From CCONT to RF Synthesizer
9Vr7a0 / 2.8 V
6Vref1.251 typical (1.244 – 1.258)From CCONT to CAFE
16+5_Power (V5V)5 V typical (4.8 – 5.2 V)From CCONT to CELL and PCS Transmitters
73V_5V (VSIM)0 / 2.8 – 3.2 VFrom CCONT to Flash
18P10 / 2.8 V typical (2.7 – 2.85)From PENTA to CELL Synthesizer
17P20 / 2.8 V typical (2.7 – 2.85)From PENTA to AMPS Receiver
19P30 / 2.8 V typical (2.7 – 2.85)From PENTA to PCS Synthesizer
21P40 / 2.8 V typical (2.7 – 2.85)From PENTA to CELL Receiver
22P50 / 2.8 V typical (2.7 – 2.85)From PENTA to PCS Receiver
43V_inACP–7: 3.5VAC(rms) to 8.5VAC(rms)
44L_Gnd0VFrom Bottom Connector, through an inductor to Phone
45V_inACP–7: 3.5VAC(rms) to 8.5VAC(rms)
46Chrg_Ctrl0 / 2.8 VFrom MAD4 to CHAPS
47Chrg_Ctrl0 / 2.8 VFrom MAD4 to CHAPS
Signal NameGeneral
Characteristics
(3.1 – 5.2 with charger connected)
ACP–9 : 4.3VDC to 8VDC
ACP–9 : 4.3VDC to 8VDC
General Signal Destination
ers
From Battery connector to CCONT and other various
parts of phone
From Bottom Connector to CHAPS
Note: Lower VBA T = lower Vin levels
Ground
From Bottom Connector to CHAPS
Note: Lower VBA T = lower Vin levels
Page 12
Nokia Mobile Phones Ltd.
Issue 1 06/1999
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