Nokia NHE-5 System Module
After Sales Technical Documentation
NHE–5 Series Transceiver
Chapter 4
SYSTEM MODULE GT8
Original 02/97
NHE–5
After Sales
System Module GT8
CHAPTER 4 – SYSTEM MODULE
Contents
Introduction Page 4–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External and Internal Connections Page 4–4. . . . . . . . . . . . . . . . . . . . . . . .
System Connector X103 Page 4–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
UI Connector X101 Page 4–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flash Connector X103 Page 4–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SIM Connector X102 Page 4–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Baseband Block Page 4–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Introduction Page 4–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Modes of Operation Page 4–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Circuit Description Page 4–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Supply Page 4–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MCU Page 4–17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MCU Flash Loading Page 4–18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flash Prommer Connection Using Dummy Battery Page 4–21. . . . . .
Flash, D400 Page 4–21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SRAM D402, D403 Page 4–21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MCU and Peripherals Page 4–22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Baseband A/D Converter Channels usage in N450 and D150 Page 4–22
Keyboard Interface Page 4–26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Keyboard and Display Light Page 4–27. . . . . . . . . . . . . . . . . . . . . . . . .
Audio Control Page 4–27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Internal Audio Page 4–28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Audio Page 4–29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DSP Page 4–30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RFI2, N450 Operation Page 4–33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SIM Interface Page 4–36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BART ASIC Page 4–37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RF Block Page 4–39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Technical Documentation
Introduction Page 4–39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receiver Page 4–39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Duplex Filter Page 4–39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pre–Amplifier Page 4–40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RF Interstage Filter Page 4–40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
First Mixer Page 4–41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
First IF Amplifier Page 4–41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
First IF Filter Page 4–41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receiver IF Circuit, RX part of CRFRT Page 4–42. . . . . . . . . . . . . . . .
Last IF Filter Page 4–42. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmitter Page 4–42. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Modulator Circuit, TX part of CRFRT Page 4–43. . . . . . . . . . . . . . . . . .
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Up–conversion Mixer Page 4–44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TX Interstage Filters Page 4–44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1st TX Buffer Page 4–45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2nd TX Buffer Page 4–45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Amplifier Page 4–45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Control Circuitry Page 4–46. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Frequency Synthesizers Page 4–47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference Oscillator Page 4–47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VHF PLL Page 4–48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VHF VCO + Buffer Page 4–48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
UHF PLL Page 4–49. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
UHF VCO + Buffer Page 4–49. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
UHF VCO Buffers Page 4–49. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PLL Circuit Page 4–50. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interconnection Diagram of Baseband Page 4–51. . . . . . . . . . . . . . . . . . . . .
Block Diagram of RF Page 4–52. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RF Frequency Plan Page 4–53. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Distribution Diagram of RF Page 4–54. . . . . . . . . . . . . . . . . . . . . . . . .
Circuit Diagram of 4 MBit Flash Memory (Version 5.0/5.4 ; Edit 44) Page 4–55
Circuit Diagram of Baseband (Version 5.0 ; Edit 155) Page 4–56
Circuit Diagram of Power Supply and Charging (V. 5.0 ; Edit 207) Page 4–57
Circuit Diagram of Charger Control (Version 5.0 ; Edit 41) Page 4–58
Circuit Diagram of Central Processing Unit (Version 5.0 ; Edit 172) Page 4–59
Circuit Diagram of MCU Memory Block (Version 5.0 ; Edit 110) Page 4–60
Circuit Diagram of Keyboard Display Interface (Version 5.0 ; Edit 85) Page 4–61
Circuit Diagram of Audio (Version 5.0 ; Edit 136) Page 4–62
Circuit Diagram of DSP Memory Block (Version 5.0 ; Edit 68) Page 4–63
Circuit Diagram of RFI (Version 5.0 ; Edit 90) Page 4–64
Circuit Diagram of Receiver (Version 5.0 ; Edit 209) Page 4–65
Circuit Diagram of Transceiver (Version 5.0 ; Edit 249) Page 4–66
Layout Diagrams of GT8 (Version: 30) Page 4–67
Circuit Diagram of Baseband (Version 5.4 ; Edit 167) Page 4–69
Circuit Diagram of Power Supply and Charging (V. 5.4 ; Edit 214) Page 4–70
Circuit Diagram of Charger Control (Version 5.4 ; Edit 47) Page 4–71
Circuit Diagram of Central Processing Unit (Version 5.4 ; Edit 180) Page 4–72
Circuit Diagram of MCU Memory Block (Version 5.4 ; Edit 116) Page 4–73
Circuit Diagram of Keyboard Display Interface (Version 5.4 ; Edit 92) Page 4–74
Circuit Diagram of Audio (Version 5.4 ; Edit 144) Page 4–75
Circuit Diagram of DSP Memory Block (Version 5.4 ; Edit 2) Page 4–76
Circuit Diagram of RFI (Version 5.4 ; Edit 99) Page 4–77
Circuit Diagram of Receiver (Version 5.4 ; Edit 209) Page 4–78
Circuit Diagram of Transceiver (Version 5.4 ; Edit 251) Page 4–79
Layout Diagrams of GT8 (Version: 34) Page 4–80
Parts list of GT8 (EDMS Issue 5.4) for layout version 30 Page 4–81
Parts list of GT8 (EDMS Issue 6.2) for layout version 34 Page 4–94
System Module GT8
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NHE–5
After Sales
System Module GT8
Introduction
GT8 is the baseband/RF module NHE–5 cellular transceiver. The GT8 module
carries out all the system and RF functions of the transceiver. System module
GT8 is designed for a handportable phone, that operate in GSM system.
Technical Section
All functional blocks of the system module are mounted on a single multi layer
printed circuit board. The chassis of the radio unit has separating walls for
baseband and RF. All components of the baseband section are surface mountable. They are soldered using reflow. The connections to accessories are taken
through the bottom connector of the radio unit. The connections to the User Interface module (UIF) are fed through a connector. There is no physical connector between the RF and baseband sections.
External and Internal Connections
The system module has two connector, external bottom connector and internal
display module connector.
Technical Documentation
System Connector X103
S0001130
13
18
15
14
16
7
12
16
17 20
19
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Accessory Connector
Pin: Name: Description:
1 GND Digital ground
2 V_OUT Accessory output supply
3 XMIC External microphone input and accessory
ID Accessory identification
4 NC No connection
System Module GT8
• min/typ/max: 3.25...10 V
(output current 50 mA)
identification
• nom/max: 8...50 mV (the maximum value
corresponds to 0 dBm network level with input
amplifier gain set to 20 dB, typical value is
maximum value –16 dB)
• 1.7...2.05 V headset adapter connected
• 1.15...1.4 V compact handsfree unit connected
5 NC No connection
6 MBUS Serial control bus
• logic low level: 0...0.5 V
• logic high level: 2.4...3.2 V
7 NC No connection
8 SGND Signal ground
9 XEAR External audio output and mute control
• min/nom/max: 0...32...500 mV (typical level
corresponds to –16 dBm0 network level with
volume control in nominal position 8 dB below
maximum. Maximum 0 dBm0 max. volume
codec gain –6 dB)
• mute on (HF speaker mute): 0...0.5 V d.c.
• mute off (HF speaker active): 1.0...1.7 V d.c.
10 HOOK Hook control, accessory connection detect
• hook off (handset in use) : 0...0.5 V
• hook on, (handset not in use): 2.4...3.2 V
11 NC No connection
12 V_IN Charging supply voltage
• max: 16 V
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System Module GT8
Battery Connector
Pin: Name: Description:
13 BGND Battery ground
14 BSI Battery size indicator
15 BTEMP Battery temperature
16 VB Battery voltage
Charging connectors
Pin: Name: Description:
17, 19 V_IN Charging voltage input
Technical Documentation
(used also for SIM card detection)
• R2=47k pull–up resistor in
(used also for vibration alert)
• 47 kΩ NTC in battery to gnd,
47 kΩ pull–up in module
• min/typ/max: 5.3...6...8.6 V
• ACH–6 min/nom/max: 9.8...10.3...10.8 V
• ACH–8 min/nom/max: 12...14...16 V
module
18, 20 GND Charger ground
UI Connector X101
Pin: Name: Description:
1 EARP Earphone positive signal
2 EARN Earphone negative signal
3 VBKEY Battery supply
4 BUZZER Alert buzzer (audio codec PWM controlled)
5–7 ROW(0–2) Input
8–10 GND Shield ground
• min/typ/max: 0...14...220 mV (typical level
corresponds to –16 dBm0 network level with
volume control giving nominal RLR (=+2 dB)
8 dB below maximum. Maximum 0 dBm0
with max. volume (codec gain –11 dB)
• min/typ/max: 0...14...220 mV (see above)
• min/max: 5.3...8.5 V
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11–13 ROW(3–5) Input
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Technical Documentation
Pin: Name: Description:
14 LIGHTC Keyboard light
15–18 COL(0–3) Output
19 PWRKEY Power on/off
20 GND Digital ground
Flash Connector X103
Pin: Name: Description:
1 WDDIS Watchdog disable, signal pulled down to
2 FCLK Flash serial clock, test point J303
3 VPP Flash programming voltage
System Module GT8
disable watchdog, test point J300
• min/typ/max: 11.4...12...12.6 V
(values when VPP active), test point J304
4 FTX Flash acknowledge transmit, test point J302
5 FRX Flash data receive, test point J301
SIM Connector X102
Pin: Name: Description:
1 GND Ground for SIM
2 VSIM SIM voltage supply
3 SDATA Serial data for SIM
4 SRES Reset for SIM
5 CLK Clock for SIM data (clock frequency minimum
• min/typ/max: 4.8...4.9...5.0 V
1 MHz if clock stopping not allowed)
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NHE–5
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System Module GT8
Baseband Block
Introduction
The GT8 module is used in NHE–5 products. The baseband is built around one
DSP, System ASIC and the MCU. The DSP performs all speech and GSM/PCN
related signal processing tasks. The baseband power supply is 3V except for
the A/D and D/A converters that are the interface to the RF section. The A/D
converters used for battery monitoring are integrated into the same device as
the signal processing converters.
The audio codec is a separate device which is connected to both the DSP and
the MCU. The audio codec support the internal and external microphone/earpiece functions. External audio is connected in a dual ended fashion to improve
audio quality together with accessories.
The baseband implementation support a 32 kHz sleep clock function for power
saving. The 32 kHz clock is used for timing purposes during inactive periods
between paging blocks. This arrangement allows the reference clock, derived
from RF to be switched off.
Technical Documentation
The baseband clock reference is derived from the RF section and the reference
frequency is 13 MHz. a low level sinusoidal wave form is fed to the ASIC which
acts as the clock distribution circuit. The DSP is running at 39 MHz using an internal PLL. The clock frequency supplied to the DSP is 13 MHz. The MCU bus
frequency is the same as the input frequency. The system ASIC provides both
13 MHz and 6.5 MHz as alternative frequencies. The MCU clock frequency is
programmable by the MCU. The baseband uses 6.5 MHz as the MCU operating frequency. The RF A/D, D/A converters are operated using the 13 MHz
clock supplied from the system ASIC
The power supply and charging section supplies several types of battery
technologies. such as , NiCd, NiMH and Lithium. The battery charging unit is
designed to accept constant current type chargers, that are approved by NMP.
The power supply IC contains three different regulators. The output voltage
from each regulator is 3.15V nominal. One of the regulator uses an external
transistor as the boost transistor.
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Modes of Operation
The baseband in operates in the following Modes
– Active, as during a call or when baseband circuitry is operating
– Sleep, in this mode the clock to the baseband is stopped and timing is kept
by the 32 KHz oscillator. All Baseband circuits are powered
– Acting dead, in this mode the battery is charged but only necessary func-
tions for charging are running
– Power off, in this mode all baseband circuits are powered off. The regulator
IC N301 is powered
Circuit Description
Power Supply
L308
CRFCONT
VBAT
5.3 ... 8.6 V
CHARGER
16.5 V max.
L301
CHARGND
BATGND
Not Assembled
L300
CHARGER
UNIT
N601
V305
AGND
L302
L304
L309
BGND
L310
L311
5,21,37
39,44
6,32
V450
41
VBAT to RF
Not Assembled
PSCLD
N301
35
VA
3.16 V
N200
VSIM
L451
4.50 V
40
VRF
N450
4,20,38
VSL
L152
L151
43
42
VSLRC
3.16 V
D151; pin 124
VSLC
D151
D402
D404
System Module GT8
VB (to illumination leds)
V306
GND
3.16 V
VL
L306
L150
Not Assembled
L410
L153
VLDSP
D152
L450
VLCD
3.16 V3.16 V
VLC
3.16 V
D150
D400
VLCRAM
3.16 V
D410
D411
VLRFI
3.16 V
N450
The power supply for the baseband is the main battery. The main battery consists of 5 NiCd or NiMH cells with a nominal voltage of 6.0V. A charger input is
used to charge the battery. Two different chargers can be used for charging the
battery. A switch mode type fast charger that can deliver 780 mA and a standard charger that can deliver 265 mA. The idle voltage for the fast and standard
charger see NO TAG. Both chargers are of constant current type.
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System Module GT8
The baseband has one power supply circuit, N301 delivering power to the different parts in the baseband. There are two logic power supply and one analog
power supply. The analog power supply VA is used for analog circuits such as
audio codec, N200 and microphone bias circuitry. Due to the current consumption and the baseband architecture the digital supply is divided into to parts.
Both digital power supply rails from the N301, PSCLD is used to distribute the
power dissipation inside N301, PSCLD. The main logic power supply VL has an
external power transistor, V306 to handle the power dissipation that will occur
when the battery is fully charged or during charging.
D151, ASIC and the MCU SRAM, D402/D403 are connected to the same logic
supply voltage. All other digital circuits are connected to the main digital supply.
The analog voltage supply is connected to the audio codec.
Charging Control Switch Functional Description
The charging switch transistor V304 controls the charging current from the
charger input to the battery. During charging the transistor is forced in saturation and the voltage drop over the transistor is 0.2–0.4V depending upon the
current delivered by the charger. Transistor V304 is controlled by the PWM output from N301, pin 23 via resistors R309, R308 and transistor V303. The output
from N301 is of open drain type. When transistor V304 is conducting the output
from N301 pin is low. In this case resistors R305 and R306 are connected in
parallel with R304. This arrangement increases the base current through V304
to put it into saturation.
Technical Documentation
Transistors V304, V302, V303 and V312 forms a simple voltage regulator circuitry. The reference voltage for this circuitry is taken from zener diode V301.
The feedback for the regulator is taken from the collector of V304. When the
PWM output from N301 is active, low, the feedback voltage is determined by
resistors R308 and R309. This arrangement makes the charger control switch
circuitry to act as a programmable voltage regulator with two output voltages
depending upon the state of the PWM output from N301. When the PWM is inactive, in high impedance the feedback voltage is almost the same as on the
collector of V304. Due to the connection the voltage on V303 and V302 emitters are the same. The influence of the current thru R305 and R306 can be neglected in this case.
The charging switch circuit diagram is shown in following figure. The figure is
for reference only.
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System Module GT8
This feedback means that the system regulates the output voltage from V304 in
such a way that the base of V303 and V302 are at the same voltage. The voltage on V302 is determined by the V301 zener voltage. The darlington connection of V312 and V302 service two purposes 1 the load on the voltage reference V301 is decreased, 2 the output voltage on V304 is decreased by the
VBE voltage on V312 which is a wanted feature. The voltage reduction allows a
relative temperature stable zener diode to be used and the output voltage from
V304 is at a suitable level when the PWM output from N301 is not active.
The circuitry is self starting which means that an empty battery is initially
charged by the regulator circuitry around the charging switch transistor. The
battery is charged to a voltage of maximum 8.4V. This charging switch circuit
allows for both NiCd, NiMH and Lithium type of batteries to be used.
When the PWM output from N301 is active the feedback voltage is changed
due to the presence of R308 and R309. When the PWM is active the charging
switch regulator voltage is set to 10.5V maximum. This means that even if the
voltage on the charger input exceeds 11.5V the battery voltage will not exceed
10.5 V. This protects N301 from over voltage even if the battery was to be detached while charging.
V305 is a schottky diode that prevents the battery voltage from reverse bias
V304 when the charger is not connected. The leakage current for V305 is increasing with increasing temperature and the leakage current is passed to
ground via R308, V303 and R304. This arrangement prevents V304 from being
reversed biased as the leakage current increases at high temperatures.
V300 is a 16V transient suppressor. V300 protects the charger input and in particular V304 for over voltage. The cut off voltage is 16V with a maximum surge
voltage up to 25V. V300 also protects the input for wrong polarity since the transient suppressor is bipolar.
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System Module GT8
Power Supply Regulator PSCLD, N301
The power supply regulators are integrated into the same circuit N301. The
power supply IC contains three different regulators. The main digital power supply regulator is implemented using an external power transistor V306. The other two regulators are completely integrated into N301.
Technical Documentation
PSCLD, N301 External Components
N301 performs the required power on timing. The PSCLD, N301 internal power on and reset timing is defined by the external capacitor C330. This capacitor
determines the internal reset delay, which is applied when the PSCLD, N301 is
initially powered by applying the battery. The baseband power on delay is determined by C311. With a value of 10 nF the power on delay after a power on
request has been active is in the range of 50–150 ms. C310 determines the
PSCLD, N301 internal oscillator frequency and the minimum power off time
when power is switched off.
The sleep control signal from the ASIC, D151 is connected via PSCLD, N301.
During normal operation the baseband sleep function is controlled by the ASIC,
D151 but since the ASIC is not power up during the startup phase the sleep
signal is controlled by PSCLD, N301 as long as the PURX signal is active. This
arrangement ensures that the 13 MHz clock provided from RF to the ASIC,
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Technical Documentation
D151 is started and stable before the PURX signal is released and the baseband exits reset. When PURX is inactive, high, sleep control signal is controlled
by the ASIC D151.
N301 requires capacitors on the input power supply as well as on the output
from each regulator to keep each regulator stable during different load and temperature conditions. C305 and C335 are the input filtering capacitors. Due to
EMC precautions a filter using C337, L310, C335, L311, C338 and C339 has
been inserted into the supply rail. This filter reduces the high frequency components present at the battery supply from exiting the baseband into the battery
pack. The regulator outputs also have filter capacitors for power supply filtering
and regulator stability. A set of different capacitors are used to achieve a high
bandwidth in the suppression filter.
PSCLD, N301 Control Bus
The PSCLD, N301 is connected to the baseband common serial control bus,
SCONB(5:0). This bus is a serial control bus from the ASIC, D151 to several
devices on the baseband. This bus is used by the MCU to control the operation
of N301 and other devices connected to the bus. N301 has two internal 8 bit
registers and the PWM register used for charging control. The registers contain
information for controlling reset levels, charging HW limits, watchdog timer
length and watchdog acknowledge.
System Module GT8
The control bus is a three wire bus with chip select for each device on the bus
and serial clock and data. From PSCLD, N301 point of view the bus can be
used for writing only. It is not possible to read data from PSCLD, N301 by using
this bus.
The MCU can program the HW reset levels when the baseband exits/enters reset. The programmed values remains until PSCLD is powered off, the battery is
removed. At initial PSCLD, N301 power on the default reset level is used. The
default value is 5.1 V with the default hysteresis of 400 mV. This means that reset is exit at 5.5 V when the PSCLD, N301 is powered for the first time.
The watchdog timer length can be programmed by the MCU using the serial
control bus. The default watchdog time is 32 s with a 50 % tolerance. The complete baseband is powered off if the watchdog is not acknowledged within the
specified time. The watchdog is running while PSCLD, N301 is powering up the
system but PURX is active. This arrangement ensures that if for any reason the
battery voltage doesn’t increase above the reset level within the watchdog time
the system is powered off by the watchdog. This prevents a faulty battery from
being charged continuously even if the voltage never exceeds the reset limit.
As the time PURX is active is not exactly known, depends upon startup condition, the watchdog is internally acknowledged in PSCLD when PURX is released. This gives the MCU always the same time to respond to the first watchdog acknowledge.
Baseband power off is initiated by the MCU and power off is performed by writing the smallest value to the watchdog timer register. This will power off the
baseband within 0.5 ms after the watchdog write operation.
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After Sales
System Module GT8
The PSCLD, N301 also contains switches for connecting the charger voltage
and the battery voltage to the baseband A/D converters. Since the battery voltage is present and the charger voltage might be present in power off the A/D
converter signals must be connected using switches. The switch state can be
changed by the MCU via the serial control bus. When PURX is active both
switches are open to prevent battery/charger voltage from being applied to the
baseband measurement circuitry which is powered off. Before any measurement can be performed both switches must be closed by MCU.
Charger Detection
A charger is detected if the voltage on N301 pin 28 is higher than 0.5V. The
charger voltage is scaled externally to PSCLD, N301 using resistors R302 and
R303. With the implemented resistor values the corresponding voltage at the
charger input is 2.8V. Due to the multi–function of the charger detection signal
from PSCLD, N301 to ASIC, D151 the charger detection line is not forced ,active high until PURX is inactive. In case PURX is inactive the charger detection
signal is directly passed to D151. The active high on pin 14 generates and interrupt to MCU which then starts the charger detection task in SW.
Technical Documentation
SIM Interface and Regulator in N301
The SIM card regulator and interface circuitry is integrated into PSCLD, N301.
The benefit from this is that the interface circuits are operating from the same
supply voltage as the card, avoiding the voltage drop caused by the external
switch used in previous designs. The PSCLD, N301 SIM interface also acts as
voltage level shifting between the SIM interface in the ASIC, D151 operating at
3V and the card operating at 5V. Interface control in PSCLD is direct from
ASIC, D151 SIM interface using SIMI(5:0) bus. The MCU can select the power
supply voltage for the SIM using the serial control bus. The default value is 3V
which needs to be changed to 5V before power up the SIM interface in ASIC,
D151. Regulator enable and disable is controlled by the ASIC via SIMI(2). For
further operation of the SIM interface see section NO TAG.
Power Up Sequence
The baseband can be powered up in three different ways.
– When the power switch is pressed input pin 25 to PSCLD, N301 is con-
nected to ground and this switches on the regulators inside PSCLD.
– An other way to power up is to connect the charger. Connecting the charger
causes the baseband to power up and start charging the battery.
Page 4–14
– The third way to power the system up is to attach the battery.
Original 02/97
After Sales
NHE–5
Technical Documentation
PSCLD
N301
VBAT
Pwr
Switch
Watchdog
disable
CHARGER
UNITCHARGER
5,21,37
39,44
25
23
28
30
16,18,19
C310
VL VSL VA
40
35
26 120
17 130
14
13
CRFCONT
N601
Purx
Serial Bus
VCXO Enable
CHARGAlarm
1415
129
VCXO
SRAM, FLASH
D403 D400
22
13 MHz
Address Bus
ASIC
D151
Watchdog
Register
32 kHz
125 126
Data Bus
System Module GT8
83
84
82
81
MCU Clock
MCU Reset
48 51
DSP Reset
DSP Clock
MCU
D150
Power up using Power on Button
This is the most common way to power the system up. This power up is successful if the battery voltage is higher than power on reset level set by the
MCU, default value 5.5V in PSCLD, N301. The power up sequence is started
when the power on input pin 25 at PSCLD is activated, low. The PSCLD then
internally enters the reset state where the regulators are switched on. At this
state the PWM output from PSCLD is forced active to support additional power
from any charger connected. The sleep control output signal is forced high enabling the regulator to supply the VCO and startup the clock. After the power on
reset delay of 50–150 ms PURX is released and the system exits reset. The
PWM output is still active until the MCU writes the first value to the PWM register. The watchdog has to be acknowledged within 16 s after that PURX has
changed to inactive state
Power Up with Empty Battery using Charger
When the charger is inserted into the DC jack or charger voltage is supplied at
the system connector surface contacts/pins PSCLD , N301 powers up the
baseband. The charging control switch is operating as a linear regulator, the
output voltage is 4.5V–5V. This allows the battery to be charged immediately
when the charger is connected. This way of operation guarantees successful
power up procedure with empty battery. In case of empty battery the only power source is the charger. When the battery has been initially charged and the
voltage is higher than the PSCLD, N301 switch on voltage the sleep control signal which is connected to the PSCLD for power saving function sleep mode,
enters inactive state, high, to enable the regulator that controls the power supply to the VCO to be started. The ASIC, D151 which normally controls the sleep
control line has the sleep output inactive, low as long as the system reset,
PURX is active, low, from PSCLD. After a delay of about 5–10 ms the system
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NHE–5
After Sales
System Module GT8
reset output PURX from PSCLD enters high state. This delay is to ensure that
the clock is stable when the ASIC exits reset. The sleep control output from the
PSCLD that has been driving an output until now, returns the control to the
sleep signal from the ASIC as the PURX signal goes inactive. When the PURX
signal goes inactive, high, the charge detection output at PSCLD, that is in input mode when PURX is active, switches to output and goes high indicating
that a charger is present. When the system reset, PURX, goes high the sleep
control line is forced inactive, high, by the ASIC, D151 via PSCLD, N301.
Once the system has exited reset the battery is initially charged until the MCU
writes a new value to the PWM in PSCLD. If the watchdog is not acknowledged
the battery charging is switched off when the PSCLD shuts off the power to the
baseband. The PSCLD will not enter the power on mode again until the charger
has been extracted and inserted again or the power switch has been pressed.
The battery is charged as long as the power on line, PWRONX is active low.
This is done to allow the phone to be started manually from the power button
with the charger inserted not having to extract the charger to get a power up if
the battery is empty.
Power On Reset Operation
Technical Documentation
The system power up reset is generated by the regulator IC, N301. The reset is
connected to the ASIC, D151 that is put into reset whenever the reset signal,
PURX is low. The ASIC, D151 then resets the DSP, D152 the MCU, D150 and
the digital parts in N450. When reset is removed the clock supplied to the ASIC,
D151 is enabled inside the ASIC. At this point the 32 kHz oscillator signal is not
enabled inside the ASIC, since the oscillator is still in the startup phase. To start
up the block requiring 32 kHz clock the MCU must enable the 32 kHz clock.
The MCU reset counter is now started and the MCU reset is still kept active,
low. 6.5 MHz clock is started to MCU in order to put the MCU, D150 into reset,
MCU is a synchronous reset device and needs clock to reset. The reset to
MCU is put inactive after 128 MCU clock cycles and MCU is started.
DSP, D152 and N450 reset is kept is kept active when the clock inside the
ASIC, D151 is started. 13 MHz clock is started to DSP, D152 and puts it into reset, D152 is a synchronous reset device and requires clock to enter reset.
N450 digital parts are reset asynchronously and do not need clock to be supported to enter reset.
As both the MCU, D151 and DSP, D152 are synchronous reset devices all interface signals connected between these devices and ASIC D151 which are
used as I/O are set into input mode on the ASIC, D151 side during reset. This
avoids bus conflicts to occur before the MCU, D150 and the DSP, D152 are actually reset.
Page 4–16
The DSP, D152 and N450 reset signal remains active after that the MCU has
exited reset. The MCU writes to the ASIC register to disable the DSP reset.
This arrangement allows the MCU to reset the DSP, D152 and N450 when ever
needed. The MCU can put DSP into reset by writing the reset active in the
ASIC, D151 register
Original 02/97
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Technical Documentation
MCU
The baseband uses a Hitachi H3001 type of MCU. This is a 16–bit internal
MCU with 8–bit external data bus. The MCU is capable of addressing up to 16
MByte of memory space linearly depending upon the mode of operation. The
MCU has a non multiplexed address/data bus which means that memory access can be done using less clock cycles thus improving the performance but
also tightening up memory access requirements. The MCU is used in mode 3
which means 8–bit external data bus and 16 Mbyte of address space. The
MCU operating frequency is equal to the supplied clock frequency. The MCU
has 512 bytes of internal SRAM. The MCU has one serial channel, USART that
can operate in synchronous and asynchronous mode. The USART is used in
the MBUS implementation. Clock required for the USART is generated by the
internal baud rate generator. The MCU has 5 internal timers that can be used
for timing generation. Timer TIOCA0 input pin 71 is used for generation of netfree signal from the MBUS receive signal which is connected to the MCU
USART receiver input on pin 2.
The MCU contains 4 10–bit A/D converters channels that are used for baseband monitoring. For A/D converter channel usage see section NO TAG.
System Module GT8
The MCU, D150 has several programmable I/O ports which can be configured
by SW. Port 4 which multiplexed with the LSB part of the data bus is used
baseband control. In the mode the MCU is operating this port can be used as
an I/O port and not as part of the data bus, D0–D7.
MCU Access and Wait State Generation
The MCU can access external devices in 2 state access or 3 state access. In
two state access the MCU uses two clock cycles to access data from the external device In 3 state access the MCU uses 3 clock cycles to access the external device or more if wait states are enabled. The wait state controller can operate in different modes. In this case the programmable wait mode is used.
This means that the programmed amount of wait states in the wait control register are inserted when an access is performed to a device located in that area.
For area split see NO TAG. The complete address space is divided into 8 areas
each area covering 2 MByte of address space. The access type for each area
can be set by bits in the access state control register. Further more the wait
state function can be enabled separately for each area by the wait state controller enable register.
This means that in 3 state access two types of access can be performed with a
fixed setting:
– 3 state access without wait states
– 3 state access with the amount of wait states inserted determined by the
Original 02/97
wait control register
Page 4–17
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