Nokia LA-5301P Schematics

A

1 1

B

C

D

E

Compal Confidential

2 2

NYU00 LA-5301P R02 Schematics Document

Menlow-Silverthorne with Poulsbo

3 3

Monday, April 06, 2009

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDEN TIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMA TION IT C ONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPA L ELEC TRONICS, INC.

C

2008/05/30 2011/05/30

Compal Secret Data

Deciphered Date

Title

Size Docu ment Number Re v

Custom

D

Date: Sheet

Compal Electronics, Inc.

Cover Sheet

NYU00 LA-5301P

E

128

0.2

of

A

Compal Confidential

Model Name :

B

C

D

E

CPU Regulator

LA-5301P CPU-Board

1 1

10.1" LCD Connector

Page 15

HDMI Connector

SATA

Conn.

2 2

40,60,80G1.8"

Page 19

HDD

BIOS SST25LF080A

Page 20

TouchPad

Conn.

Page 19

KeyBoard

Conn.

Page 18

TMDS

SATA

SPI Flash

PS/2

Matrix

SDVO->HDMI SiI1392

Page 17

PATA->SATA GL831

EC

ENE KB926

Page 18

LED

3 3

G-Sensor

SMBUS

MMA7455

Light Sensor

SMBUS

TSL2561FN

LVDS I/F

SDVO I/F

PATA

LPC BUS

PCIE

WLAN Arcadyan Atheros XB63

CPU-Silverthrone

1.33G/1.6G

H_A#( 3..35)

H_D#(0..63)

FSB

533MHz

SCH- Poulsbo

Page 6~10

HDA I/F

Audio Codec

ALC 269

Page 16

HP/MIC Jack

Page 4,5

USB2.0

DMIC-IN

DDR2-533

SingleChannel

DDR2 64MX16X8pcs

HY5PS1G1631CFP-S6

Page 11,12

Clock Gen. 9UMS9610

Page 13

SDIO

USB2.0

SD Card Socket

Ext.USB 2.0 X3

USB2.0

3G-Module

BlueTooth

Camera(1.3M)

Lite-On

(Reserve)

Page 15

Page 22

+1.8V

+1.05VS

+0.9VS

+1.5VS

SIM Connector

DCIN/CHARGER

BATT Conn/OTP

+3VALW

Speaker X2

ZZZ LA-5301P

4 4

PCB

DA80000EN00

USB2.0

NFC

PN533 (Reserve)

+5VALW

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDEN TIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMA TION IT C ONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPA L ELEC TRONICS, INC.

C

2008/11/10 2011/11/10

Compal Secret Data

Deciphered Date

Title

Size Docu ment Number Re v

Custom

D

Date: Sheet

Compal Electronics, Inc.

Block Diagram

NYU00 LA-5301P

E

228Monday, Apr il 06, 2009

0.2

of

Voltage Rails

A

O MEANS ON X MEANS OFF

power plane

State

S0

S3

S5 S4/AC

S5 S4/ Battery only

S5 S4/AC & Battery don't exist

O MEANS ON

X MEANS OFF

+VBAT

O

X

S3 : STR S4 : STD

+5VALW

+3VALW

+1.8V

+0.9V

O

X

XXX

+5VS

+3VS

+1.8VS

+1.5VS

+CPU_CORE

+VCCP

OO

O

X

XX

X

CLOCK

O

X

S5 : SOFT OFF

1 1

EC SM Bus1 address

AddressDevice

G SENSOR MMA745 5

0001_1101

EC SM Bus2 address

Device

THERMAL SENSOR 1 EMC1402-1-ACZL-TR

THERMAL SENSOR 2 EMC1402-2-ACZL-TR

LIGHT SENSOR

TSL2561FN

Address

100_1100

100_1101

ADDRSEL

GND

0101001

BOM Structure USB PORT LIST

MARK FUNCTION

Address

NC FOR ALL@

PORT DEVICE

HOST LEFT1

0

HOST LEFT2

1 2

HOST RIGHT1

3

3G

4

BT

CAM

5

(RESERVE)

6

(RESERVE)

7

Poulsbo SM Bus address

Device

Clock Generator (ICS9UMS9610BKLF-T)

1101 001Xb

Address

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDEN TIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMA TION IT C ONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPA L ELEC TRONICS, INC.

A

2008/05/30 2011/05/30

Compal Secret Data

Deciphered Date

Title

Size Docu ment Number Re v

Custom

Date: Sheet

Compal Electronics, Inc.

Notes List

NYU00 LA-5301P

of

328Monday, April 06, 2009

0.2

5

4

3

2

1

Silverthrone Host Data Interface Silverthrone Host Data Interface

H_D#[0..1 5]<6>

D D

H_DSTBN#0<6> H_DSTBP#0<6>

H_DINV#0<6>

H_D#[16..31]<6>

H_DSTBN#1<6> H_DSTBP#1<6>

C C

H_DINV#1<6>

CPU_BSEL2<6,13>

H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_DSTBN#0 H_DSTBP#0 H_DINV#0

H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_DSTBN#1 H_DSTBP#1 H_DINV#1

+CPU_GTLREF

CPU_BSEL2

U2B

Y27

D[0]#

AH27

D[1]#

Y31

D[2]#

AC30

D[3]#

AE30

D[4]#

AF29

D[5]#

AA26

D[6]#

AB31

D[7]#

W30

D[8]#

AC28

D[9]#

AD31

D[10]#

AF27

D[11]#

AD27

D[12]#

AG28

D[13]#

AB25

D[14]#

AC26

D[15]#

AA28

DSTBN[0]#

AA30

DSTBP[0]#

AE28

DINV[0]#

AE24

D[16]#

AC24

D[17]#

AJ20

D[18]#

AE20

D[19]#

AJ22

D[20]#

AF25

D[21]#

AH25

D[22]#

AH23

D[23]#

AH19

D[24]#

AF23

D[25]#

AE18

D[26]#

AH17

D[27]#

AD19

D[28]#

AJ24

D[29]#

AJ18

D[30]#

AF19

D[31]#

AF21

DSTBN[1]#

AH21

DSTBP[1]#

AE22

DINV[1]#

AJ26

GTLREF

MISC

P31

TEST1

T31

TEST2

R30

BSEL[0]

M31

BSEL[1]

U28

BSEL[2]

SILVERTHORNE_FCBGA8-441

DATA GRP 0 DATA GRP 1

D[32]# D[33]# D[34]# D[35]# D[36]# D[37]# D[38]# D[39]# D[40]# D[41]# D[42]# D[43]#

DATA GRP 2

D[44]# D[45]# D[46]#

D[47]# DSTBN[2]# DSTBP[2]#

DINV[2]#

D[48]#

D[49]#

D[50]#

D[51]#

D[52]#

D[53]#

D[54]#

D[55]#

D[56]#

D[57]#

D[58]#

D[59]#

D[60]#

D[61]#

DATA GRP 3

D[62]#

D[63]# DSTBN[3]# DSTBP[3]#

DINV[3]#

COMP[0] COMP[1] COMP[2] COMP[3]

DPRSTP#

DPSLP#

DPWR#

PWRGOOD

SLP#

RSVD12

AE8 AD7 AH15 AF9 AH9 AE10 AJ16 AF13 AF7 AF15 AH13 AJ14 AJ12 AH7 AJ8 AJ10 AH11 AF11 AE12

AH5 AB5 AJ6 Y1 AF5 AG4 AF3 AC6 AE6 AE4 W4 AC2 AE2 AD1 AA2 AC4 AB1 AA4 Y5

AE14 AD13 E16 F15

G2 G6 V31 G4 J2 K27

<NO_STUFF>

H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_DSTBN#2 H_DSTBP#2 H_DINV#2

H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 H_DSTBN#3 H_DSTBP#3 H_DINV#3

COMP0

R11 27.4_0402_1%

COMP1

R15 54.9_0402_1%

COMP2

R13 27.4_0402_1%

COMP3

R14 54.9_0402_1%

H_DPRSTP# H_DPSLP# H_DPWR# H_PW RGOOD H_CPUSLP#

1 2 1 2 1 2 1 2

layout note: Route TEST3 & TEST5 traces on ground referenced layer to the TPs

CPU_BSEL CPU_BSEL2 CPU_BSEL1

100

133

B B

Close to CPU pin AD26 within 500mils.

+CPU_GTLREF

1

C4

0.1U_0402_16V7K

2

XDP Reserve

XDP_TDI

XDP_TMS

A A

XDP_TDO

XDP_BPM#5

10

0

+1.05VS_C6

12

R20 1K_0402_1%

12

R27 2K_0402_1%

R19 56_0402_5%

1 2

R21 56_0402_5%

1 2

R23 56_0402_5%@

1 2

R25 56_0402_5%@

1 2

0

+1.05VS

CPU_BSEL0

1

T34

TPC24

Resistor placed within

0.5" of CPU pin.Trace should be at least 25 mils away from any other toggling signal. COMP[0,2] trace width is 18 mils. COMP[1,3] trace width is 4 mils.

XDP_BPM#5

T25 T26

T27 T28

T29 T30

T31

T32

T33

T35 T36 T37 T38

T39

XDP_BPM#4

XDP_BPM#3 XDP_BPM#2

XDP_BPM#1 XDP_BPM#0

H_PW RGOOD_0

SLPIOVR#_0

R122 1K_0402_1%

12

XDP_TDO XDP_TRST# XDP_TDI XDP_TMS

XDP_TCK

H_RESET#H_RESET#_0

TPC24 TPC24

TPC24

TPC24 TPC24 TPC24 TPC24

TPC24

H_D#[32..47] <6>

H_DSTBN#2 <6> H_DSTBP#2 <6> H_DINV#2 <6> H_D#[48..63] <6>

H_DSTBN#3 <6> H_DSTBP#3 <6> H_DINV#3 <6>

H_DPRSTP# <6,25>

H_DPSLP# <6> H_DPWR# <6> H_PWRGOOD <6>

H_CPUSLP# <6>

R587 1K_0402_5%

H_PW RGOOD

12

R96 1K_0402_5%

12

+1.05VS

SLPIOV R# <8,22>

U2

1.33G@ SA00002BA20

H_A#[3..16]<6>

H_ADSTB#0<6>

H_REQ#0<6> H_REQ#1<6> H_REQ#2<6> H_REQ#3<6> H_REQ#4<6>

H_A#[17..31]<6>

H_ADSTB#1<6>

H_A20M#<18>

H_PBE#<6>

H_STPCLK#<6> H_INTR<6>

H_NMI<6> H_SMI#<6>

+1.05VS_C6

H_THERMTRIP#

C1

0.1U_0402_16V7K

+1.05VS_C6

H_ADS# <6> H_BNR# <6>

H_BPRI# <6>

H_DEFER# <6> H_DRDY# <6> H_DBSY# <6>

H_BR0# <6>

H_INIT # <6,18>

H_LOCK# <6>

H_RESET# <6>

H_RS#0 <6>

H_RS#1 <6>

H_RS#2 <6>

H_TRDY# <6>

H_HIT# <6> H_HITM# <6>

R12 56_0402_5%

H_THERMDA, H_THERMDC routing together, Trace width / Spacing = 10 / 10 mil

CLK_CPU_BCLK <13> CLK_CPU_BCLK# <13>

+1.05VS_C6

1

2

H_ADSTB#0

H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4

1 2

R16 10K_0402_5%

H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16

H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_ADSTB#1

H_A20M# H_PBE# H_IGNNE#

H_STPCLK# H_INTR H_NMI H_SMI#

1 2

R1 120_0402_5%

1 2

R2 1K_0402_1%

1 2

R4 1K_0402_5%

1 2

R593 56_0402_5%

U2A

E22

A[3]#

A22

A[4]#

D21

A[5]#

E24

A[6]#

B17

A[7]#

A18

A[8]#

B23

A[9]#

A16

A[10]#

E18

A[11]#

D15

A[12]#

B19

A[13]#

A20

A[14]#

D17

A[15]#

B15

A[16]#

D19

ADSTB[0]#

B25

REQ[0]#

D23

REQ[1]#

E20

REQ[2]#

A24

REQ[3]#

B21

REQ[4]#

B5

A[17]#

A12

A[18]#

D5

A[19]#

E12

A[20]#

B9

A[21]#

A6

A[22]#

B13

A[23]#

E14

A[24]#

A10

A[25]#

B7

A[26]#

D13

A[27]#

A8

A[28]#

C4

A[29]#

A14

A[30]#

B11

A[31]#

D11

ADSTB[1]#

G30

A20M#

J28

FERR#

H27

IGNNE#

K1

STPCLK#

H31

LINT0

L28

LINT1

J26

SMI#

AE16

RSVD7

AF17

RSVD8

AD15

RSVD9

AD17

RSVD10

D9

RSVD0

D7

RSVD1

E8

RSVD2

E10

RSVD3

L30

RSVD4

J30

RSVD5

K29

RSVD13

SILVERTHORNE_FCBGA8-441

H_PBE#

H_A20M#

H_IGNNE#

XDP_BPM#5

ADDR GROUP

0

ADDR GROUP 1

NC

ADS# BNR#

BPRI#

DEFER#

DRDY# DBSY#

BR0#

IERR#

INIT#

LOCK#

CONTROL

RESET#

RS[0]# RS[1]# RS[2]#

TRDY#

HIT#

HITM#

BPM[0]# BPM[1]# BPM[2]# BPM[3]#

PRDY# PREQ#

TCK

TDO TMS

TRST#

RSVD14

XDP/ITP SIGNALSH CLK

PROCHOT#

THRMDA THRMDC

THERM

THERMTRIP#

BCLK[0] BCLK[1]

VSS0

RSVD11

RSVD6

RSVD15

TEST4

TEST3

CMREF[1]

Intel CRB1_5

H_INIT#

1 2

R3 1K_0402_1%

H_ADS#

C26

H_BNR#

H25

H_BPRI#

G24

H_DEFER#

B27

H_DRDY#

W28

H_DBSY#

D29

H_BR0#

C28

H_IERR#

H1

H_INIT#

F31

H_LOCK#

D25

H_RESET#

M5

H_RS#0

D27

H_RS#1

E28

H_RS#2

E26

H_TRDY#

F25

H_HIT#

E30

H_HITM#

F29

XDP_BPM#0

F1

XDP_BPM#1

E2

XDP_BPM#2

F5

XDP_BPM#3

D3

XDP_BPM#4

E4

XDP_BPM#5

F7

XDP_TCK

L2

XDP_TDI

N2

TDI

XDP_TDO

M1

XDP_TMS

P1

XDP_TRST#

J4 G26

H5 T5 U4

T1

P29 R28

K31

A26 E6

G28 U30

V27 AE26

.

H_THERMDA H_THERMDC

+CMREF

T1 TPC1 2

Thermal Sensor

+3VS

C2

0.1U_0402_16V4Z

C3 2200P_0402_50V7K

1 2

+3VS +3VS

R26 10K_0402_5%

1 2

H_THERMDC

THERM#

U3

1

VDD

2

DP

3

DN

4

THERM#

EMC1402-1-ACZL-TR_MSOP8

Address:100_1100

SMCLK

SMDATA

ALERT#

GND

EC_SMB_CK2

8

EC_SMB_DA2H_THERMDA

7

THERM_SCI#

6

5

R24 0_0402_5%@

1 2

R22 10K_0402_5%

12

R5 56_0402_5%

12

+1.05VS

PROCHOT# <8,25>

H_THERMTRIP# <6>

12

R17 1K_0402_1%

12

R18 1K_0402_1%

EC_THERM# <7,8,18>

Check : to sb

+1.05VS

EC_SMB_CK2 <14,18,20>

EC_SMB_DA2 <14,18,20>

XDP_TRST#

XDP_TCK

R28 56_0402_5%

1 2

R29 56_0402_5%

1 2

5

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDEN TIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMA TION IT C ONTAINS

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPA L ELEC TRONICS, INC.

3

2008/05/30 2011/05/30

Compal Secret Data

Deciphered Date

Title

Size Docu ment Number Re v

Custom

2

Date: Sheet

Compal Electronics, Inc.

Silverthorne(1/2)-AGTL+/XDP

NYU00 LA-5301P

1

428Monday, Apr il 06, 2009

0.2

of

5

4

3

2

1

+1.05VS

12

C60.1U_0402_16V4Z

12

C70.1U_0402_16V4Z

+1.05VS_C6

12

C6620.1U_0402_16V4Z

12

C160.1U_0402_16V4Z

12

C181U_0402_6.3V6K

12

C201U_0402_6.3V6K

12

C221U_0402_6.3V6K

12

C241U_0402_6.3V6K

+1.05VS_C6

U2C

AA14

VCCP35

J16

VCCP36

M27

VCCP0

H7

VCCPC61

H9

VCCPC62

J8

VCCPC63

AA8

VCCP1

AA10

VCCP2

AA12

VCCP3

AA16

VCCP4

AA18

VCCP5

AA20

VCCP6

AA22

VCCP7

AB7

VCCP8

AB9

VCCP9

AB11

VCCP10

AB13

VCCP11

AB15

VCCP12

AB17

VCCP13

AB19

VCCP14

AB21

VCCP15

AB23

VCCP16

H11

VCCP17

H13

VCCP18

H15

VCCP19

H17

VCCP20

H19

VCCP21

H21

VCCP22

H23

VCCP23

J10

VCCP24

J12

VCCP25

J14

VCCP26

J18

VCCP27

J20

VCCP28

J22

VCCP29

L26

VCCP30

N26

VCCP31

R26

VCCP32

U26

VCCP33

W26

VCCP34

VCCSENSE

VSSSENSE

SILVER THORNE_FCBGA8-441

VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7 VCC8

VCC9 VCC10 VCC11 VCC12 VCC13 VCC14 VCC15 VCC16 VCC17 VCC18 VCC19 VCC20 VCC21 VCC22 VCC23 VCC24 VCC25 VCC26 VCC27 VCC28 VCC29 VCC30 VCC31 VCC32 VCC33 VCC34 VCC35 VCC36 VCC37 VCC38 VCC39 VCC40 VCC41 VCC42 VCC43 VCC44 VCC45 VCC46 VCC47 VCC48

VCCA

VID[0]

VID[1]

VID[2]

VID[3]

VID[4]

VID[5]

VID[6]

D D

U2D

A4

VSS1

A28

VSS2

AA6

VSS4

AA24

VSS5

AB3

VSS6

AB27

VSS7

AB29

VSS8

AC8

VSS9

AC10

VSS10

AC12

VSS11

AC14

VSS12

AC16

VSS13

AC18

VSS14

AC20

VSS15

AC22

VSS16

AD3

VSS17

AD5

VSS18

AD9

VSS19

AD11

VSS20

AD21

VSS21

AD23

VSS22

AD25

VSS23

AD29

VSS24

AF1

VSS25

AF31

VSS26

AG2

VSS27

AG6

VSS28

AG8

VSS29

AG10

C C

B B

AG12 AG14 AG16 AG18 AG20 AG22 AG24 AG26 AG30

AH3

AH29

AJ28

C10 C12 C14 C16 C18 C20 C22 C24 C30

D31

G10 G12 G14 G16 G18 G20 G22

H29

VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS41 VSS42

AJ4

VSS45 VSS46

B3

VSS48

B29

VSS49

C2

VSS51

C6

VSS52

C8

VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62

D1

VSS63 VSS64

F3

VSS65

F9

VSS66

F11

VSS67

F13

VSS68

F17

VSS69

F19

VSS70

F21

VSS71

F23

VSS72

F27

VSS73

G8

VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80 VSS81

H3

VSS82 VSS83

J6

VSS84

VSS162 VSS161 VSS160 VSS159 VSS158 VSS157 VSS156 VSS155 VSS154 VSS153 VSS152 VSS151 VSS149 VSS148 VSS147 VSS146 VSS145 VSS144 VSS143 VSS142 VSS141 VSS140 VSS139 VSS138 VSS137 VSS136 VSS135 VSS134 VSS133 VSS132 VSS131 VSS130 VSS129 VSS128 VSS127 VSS126 VSS125 VSS124 VSS123 VSS122 VSS121 VSS120 VSS119 VSS118 VSS117 VSS116 VSS115 VSS114 VSS113 VSS112 VSS111 VSS110 VSS109 VSS108 VSS107 VSS106 VSS105 VSS104 VSS103 VSS102 VSS101 VSS100

VSS99 VSS98 VSS97 VSS96 VSS95 VSS94 VSS93 VSS92 VSS91 VSS90 VSS89 VSS88 VSS87 VSS86 VSS85

Y29 Y25 Y23 Y21 Y19 Y17 Y15 Y13 Y11 Y9 Y7 Y3 W6 V29 V25 V23 V21 V19 V17 V15 V13 V11 V9 V7 V5 V3 T29 T27 T25 T23 T21 T19 T17 T15 T13 T11 T9 T7 T3 P27 P25 P23 P21 P19 P17 P15 P13 P11 P9 P7 P3 N28 M29 M25 M23 M21 M19 M17 M15 M13 M11 M9 M7 M3 L6 K25 K23 K21 K19 K17 K15 K13 K11 K9 K7 K3 J24

L8 L10 L12 L14 L16 L18 L20 L22 L24 N6 N8 N10 N12 N14 N16 N18 N20 N22 N24 R6 R8 R10 R12 R14 R16 R18 R20 R22 R24 U6 U8 U10 U12 U14 U16 U18 U20 U22 U24 W8 W10 W12 W14 W16 W18 W20 W22 W24

N30

P5 R4 N4 K5 L4 R2 U2

W2

V1

+CPU_CORE

C5 220U_B2_2.5VM_R15M C550 220U_B2_2.5VM_R15M

1 2

C136 10U_0603_6.3V6M

C9 10U_0603_6.3V6M

C10 10U_0603_6.3V6M

C656 10U_0603_6.3V6M

C658 10U_0603_6.3V6M

C660 10U_0603_6.3V6M

C14 1U_0402_6.3V6K

C15 1U_0402_6.3V6K

C17 1U_0402_6.3V6K

C19 1U_0402_6.3V6K

C21 1U_0402_6.3V6K

C23 1U_0402_6.3V6K

C25 1U_0402_6.3V6K

CPU_VID0 CPU_VID1 CPU_VID2 CPU_VID3 CPU_VID4 CPU_VID5 CPU_VID6

VCCSENSE

VSSSENSE

+

1 2

C8

220U_B2_2.5VM_R15M

CPU_VID[0..6] <25>

+CPU_CORE

+

12

C12310U_0603_6.3V6M

12

C12110U_0603_6.3V6M

12

C12210U_0603_6.3V6M

12

C65710U_0603_6.3V6M

12

C65910U_0603_6.3V6M

12

C66110U_0603_6.3V6M

12

C111U_0402_6.3V6K

12

C121U_0402_6.3V6K

12

C131U_0402_6.3V6K

12

C1401U_0402_6.3V6K

12

C1391U_0402_6.3V6K

12

C1381U_0402_6.3V6K

12

C1371U_0402_6.3V6K

1

C26

0.1U_0402_16V4Z

2

Near pin N30

+1.5VS

Length match within 25 mils. The trace width/space/other is 20/7/25.

+CPU_CORE

R30 100_0402_1%

1 2

R31 100_0402_1%

1 2

VCCSENSE

VSSSENSE

VCCSENSE <25>

VSSSENSE <25>

Close to CPU pin within 500mils.

SILVERTHORNE_FCBGA8-441

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDEN TIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMA TION IT C ONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPA L ELEC TRONICS, INC.

3

2008/05/30 2011/05/30

Compal Secret Data

Deciphered Date

Title

Size Docu ment Number Re v

Custom

2

Date: Sheet

Compal Electronics, Inc.

Silverthorne(2/2)-PWR/GND

NYU00 LA-5301P

1

528Monday, Apr il 06, 2009

0.2

of

5

H_D#[0..6 3]<4> H_A#[3..31] <4>

D D

C C

H_NMI<4> H_SMI#<4>

H_PBE#<4>

H_STPCLK#<4>

B B

H_INIT#<4,18> H_INTR<4>

H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63

R33 24_0402_5%

1 2

+H_SWNG

+H_RCOMP

H_THERMTRIP_R#

U4A

V8

H_D0#

AF4

H_D1#

V2

H_D2#

AA1

H_D3#

AC1

H_D4#

AD2

H_D5#

V4

H_D6#

Y2

H_D7#

U1

H_D8#

Y8

H_D9#

AB2

H_D10#

AF2

H_D11#

AB4

H_D12#

AF8

H_D13#

AE1

H_D14#

AB8

H_D15#

AJ1

H_D16#

AH2

H_D17#

AM8

H_D18#

AN1

H_D19#

AK4

H_D20#

AG1

H_D21#

AH8

H_D22#

AK8

H_D23#

AP8

H_D24#

AK2

H_D25#

AR1

H_D26#

AT8

H_D27#

AT2

H_D28#

AH4

H_D29#

AP4

H_D30#

AP2

H_D31#

AV4

H_D32#

BB6

H_D33#

AV6

H_D34#

AY8

H_D35#

BA1

H_D36#

AU1

H_D37#

AT6

H_D38#

AV8

H_D39#

BB4

H_D40#

AT4

H_D41#

AY6

H_D42#

AV10

H_D43#

AV2

H_D44#

BC1

H_D45#

BB2

H_D46#

AY2

H_D47#

BD2

H_D48#

BH4

H_D49#

BD10

H_D50#

BK10

H_D51#

BD6

H_D52#

BD4

H_D53#

BF2

H_D54#

BE1

H_D55#

BD8

H_D56#

BF4

H_D57#

BH10

H_D58#

BK6

H_D59#

BB8

H_D60#

BF6

H_D61#

BF10

H_D62#

BH6

H_D63#

AB10

H_NMI

AB6

H_SMI#

AH6

H_PBE#

V6

H_SWING

AD10

H_STPCLK#

AK6

H_TESTIN#

T10

H_RCOMPO

AT10

RESERVED5

AP10

RESERVED4

AM6

H_THRMTRIP#

AF10

H_INIT#

AF6

H_INTR

POULSBO_FCBGA1249

HOST

layout note:

Route H_SCOMP and H_SCOMP# with trace width, spacing and impedance (55 ohm) same as FSB data traces

Layout Note: H_RCOMP / H_VREF / H_SWNG

trace width and spacing is 10/20

R47 100_0402_1%

+1.05VS

12

R42 221_0603_1%

1

2

+H_SWNG+H_VREF

C30

0.1U_0402_16V7K

+1.05VS

12

R41 1K_0402_1%

A A

R45

12

2K_0402_1%

C29

1

0.1U_0402_16V7K

2

+H_RCOMP

12

R46

24.9_0402_1%

Near B3 pinwithin 100 mils from NB

5

4

H_A#3

M2

H_A3# H_A4# H_A5# H_A6# H_A7# H_A8#

H_A9# H_A10# H_A11# H_A12# H_A13# H_A14# H_A15# H_A16# H_A17# H_A18# H_A19# H_A20# H_A21# H_A22# H_A23# H_A24# H_A25# H_A26# H_A27# H_A28# H_A29# H_A30# H_A31#

H_ADS# H_ADSTB0# H_ADSTB1#

H_GVREF

H_BNR#

H_BPRI#

H_BREQ0#

H_CPURST#

H_CGVREF

H_CLKINN H_CLKINP

H_DBSY#

H_DEFER#

H_DINV0# H_DINV1# H_DINV2# H_DINV3#

H_DPWR#

H_DRDY# H_DSTBN0# H_DSTBN1# H_DSTBN2# H_DSTBN3# H_DSTBP0# H_DSTBP1# H_DSTBP2# H_DSTBP3#

H_HIT#

H_HITM# H_LOCK# H_REQ0# H_REQ1# H_REQ2# H_REQ3# H_REQ4#

H_RS0# H_RS1# H_RS2#

H_CPUSLP#

H_TRDY#

H_CPUPWRGD

H_DPSLP#

H_DPRSTP#

CFG0 CFG1

BSEL2

FSB BSEL2

100

13310

CFG1 10K pull-down is required.

H_THERMTRIP_R#

4

M8 K4 P2 F4 G1 M4 F6 H6 D2 H2 J1 F2 D4 D12 H12 G11 A7 A9 A11 B6 H8 F10 B10 D6 D10 B12 B4 D8

K6 H4 B8 Y10 R1 P10 L1 M6 AD4

K10 M10 H10 AD6 AD8 AM2 AY10 BK8 P6 J9 Y4 AL1 AW1 BH8 W1 AM4 AY4 BF8

V10 T6 Y6 P4 N1 K8 P8 K2 T4 T2 T8 AH10 F12

AP6 F8 AK10

J27 B34 F28

1 2

R48 24_0402_5%

H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31

H_ADS# H_ADSTB#0 H_ADSTB#1 +H_VREF H_BNR# H_BPRI# H_BR0# H_RESET#

CLK_MCH_BCLK# CLK_MCH_BCLK H_DBSY# H_DEFER# H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3 H_DPWR# H_DRDY# H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3 H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3

H_HIT# H_HITM# H_LOCK# H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 H_RS#0 H_RS#1 H_RS#2 H_CPUSLP# H_TRDY#

CFG0

100

133

H_ADS# <4> H_ADSTB#0 <4> H_ADSTB#1 <4>

H_BNR# <4> H_BPRI# <4> H_BR0# <4> H_RESET# <4>

CLK_MCH_BCLK# <13> CLK_MCH_BCLK <13> H_DBSY# <4> H_DEFER# <4> H_DINV#0 <4> H_DINV#1 <4> H_DINV#2 <4> H_DINV#3 <4> H_DPWR# <4> H_DRDY# <4> H_DSTBN#0 <4> H_DSTBN#1 <4> H_DSTBN#2 <4> H_DSTBN#3 <4> H_DSTBP#0 <4> H_DSTBP#1 <4> H_DSTBP#2 <4> H_DSTBP#3 <4>

H_HIT# <4> H_HITM# <4> H_LOCK# <4> H_REQ#0 <4> H_REQ#1 <4> H_REQ#2 <4> H_REQ#3 <4> H_REQ#4 <4> H_RS#0 <4> H_RS#1 <4> H_RS#2 <4> H_CPUSLP# <4> H_TRDY# <4>

H_PW RGOOD <4> H_DPSLP# <4> H_DPRSTP# <4,25>

R35 10K_0402_5%

1 2

R36 10K_0402_5%@

1 2

R37 10K_0402_5%

1 2

CPU_BSEL2 <4,13>

CFG0DDRFSB

DDRFSBFSB

100

13310 100

+1.05VS

12

133

within 2" from R48

R44 120_0402_5%

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDEN TIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMA TION IT C ONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPA L ELEC TRONICS, INC.

3

+1.05VS

H_THERMTRIP# <4>

Issued Date

3

DDR_A_D[0..63]<11,12>

+H_CGVREF

C27

0.1U_0402_16V7K

In pre-ES R571=2k H_CGVREF=2/3VCCP In ES R571 choose 1k

2008/05/30 2011/05/30

DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8

DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63

+1.05VS

12

R38 1K_0402_1%

12

1

R40 1K_0402_1%

2

Compal Secret Data

Deciphered Date

U4D

BG49 BG47 BE45 BC43 BE47 BC47 BC45 BK44 BK42 BG41 BK40 BC41 BG43

BJ43

BJ39 BG39 BC39 BK38 BG37 BK36

BJ37 BG35

BJ35 BC35 BK34 BG31 BG33 BK30 BC33

BJ33

BJ31 BC31

BJ29 BG29 BK28 BC29 BE27 BK26 BG25

BJ25 BC25 BG23 BK22

BJ21 BK24

BJ23 BG21 BC21 BK20

BJ19 BG17

BJ17 BG19 BC19 BC17 BK16 BG15 BC15

BJ13 BK12 BK14

BJ15 BC13 BC11

POULSBO_FCBGA1249

SM_DQ0 SM_DQ1 SM_DQ2 SM_DQ3 SM_DQ4 SM_DQ5 SM_DQ6 SM_DQ7 SM_DQ8 SM_DQ9 SM_DQ10 SM_DQ11 SM_DQ12 SM_DQ13 SM_DQ14 SM_DQ15 SM_DQ16 SM_DQ17 SM_DQ18 SM_DQ19 SM_DQ20 SM_DQ21 SM_DQ22 SM_DQ23 SM_DQ24 SM_DQ25 SM_DQ26 SM_DQ27 SM_DQ28 SM_DQ29 SM_DQ30 SM_DQ31 SM_DQ32 SM_DQ33 SM_DQ34 SM_DQ35 SM_DQ36 SM_DQ37 SM_DQ38 SM_DQ39 SM_DQ40 SM_DQ41 SM_DQ42 SM_DQ43 SM_DQ44 SM_DQ45 SM_DQ46 SM_DQ47 SM_DQ48 SM_DQ49 SM_DQ50 SM_DQ51 SM_DQ52 SM_DQ53 SM_DQ54 SM_DQ55 SM_DQ56 SM_DQ57 SM_DQ58 SM_DQ59 SM_DQ60 SM_DQ61 SM_DQ62 SM_DQ63

2

DDR_A_BS#0

BC27

SM_BS0 SM_BS1 SM_BS2

SM_CK0 SM_CK1

SM_CK0# SM_CK1#

SM_CKE0 SM_CKE1

SM_DQS0 SM_DQS1 SM_DQS2 SM_DQS3 SM_DQS4 SM_DQS5 SM_DQS6 SM_DQS7

SM_MA0 SM_MA1 SM_MA2 SM_MA3 SM_MA4 SM_MA5 SM_MA6 SM_MA7 SM_MA8

SM_MA9 SM_MA10 SM_MA11 SM_MA12 SM_MA13 SM_MA14

SM_VREF

SM_RAS# SM_CAS#

SM_WE#

SM_CS0# SM_CS1#

DDR SYSTEM MEMORY

SM_RCOMPO

SM_RCVENIN

SM_RCVENOUT

Title

Size Docu ment Number Re v

Custom

2

Date: Sheet

DDR_A_BS#1

BE25

DDR_A_BS#2

BA35

BG45 BE11

BJ45 BG11

BE39 BE37

DDR_A_DQS0

BJ47

DDR_A_DQS1

BJ41

DDR_A_DQS2

BC37

DDR_A_DQS3

BK32

DDR_A_DQS4

BG27

DDR_A_DQS5

BE23

DDR_A_DQS6

BK18

DDR_A_DQS7

BG13

DDR_A_MA0

BJ27

DDR_A_MA1

BA19

DDR_A_MA2

BA27

DDR_A_MA3

BA25

DDR_A_MA4

BE29

DDR_A_MA5

BC23

DDR_A_MA6

BE31

DDR_A_MA7

BA31

DDR_A_MA8

BA33

DDR_A_MA9

BA29

DDR_A_MA10+H_CGVREF

BE17

DDR_A_MA11

BE35

DDR_A_MA12

BE33

DDR_A_MA13

BE19 BA37

+SM_VREF

BE43

DDR_A_RAS#

BE21

DDR_A_CAS#

BA13

DDR_A_WE#

BA17

BA23 BA15

BE13

BA39 BE41

1 2

R32 30.1_0402_1%

Layout Note: V_DDR_MCH_REF trace width and spacing is 20/20.

C28

0.1U_0402_16V7K

Compal Electronics, Inc.

Poulsbo(1/5)-HOST/DDR

NYU00 LA-5301P

+SM_VREF

1

2

1

DDR_A_BS#0 <11,12> DDR_A_BS#1 <11,12> DDR_A_BS#2 <11,12>

M_CLK_DDR0 <11,12> M_CLK_DDR1 <11,12>

M_CLK_DDR#0 <11,12> M_CLK_DDR#1 <11,12>

M_CKE0 <11> M_CKE1 <12>

DDR_A_DQS[0..7] <11,12>

DDR_A_MA[0..13] <11,12>

DDR_A_RAS# <11,12> DDR_A_CAS# <11,12>

DDR_A_WE# <11,12>

M_CS#0 <11>

M_CS#1 <12>

+0.9VS

+1.8V

R39 10K_0402_1%

1 2

R43 10K_0402_1%

1 2

628Monday, April 06, 2009

1

0.2

of

5

4

3

2

1

+3VS

1 2

R49 10K_0402_5%

1 2

R50 8.2K_0402_5%

D D

1 2

R51 10K_0402_5%

1 2

R52 10K_0402_5%

1 2

R56 100K_0402_5%

1 2

R115 100K_0402_5%

C C

B B

LPC_CLKRUN#

SIRQ

EDID_CLK_LCD

EDID_DAT_LCD

ENBKL

GMCH_LVDD EN

MINSD_CD#<14>

MINSD_CLK<14> MINSD_CMD<14>

MINSD_WP<14>

MINSD_PWR#<14>

MINSD_DATA[0..3]<14>

CLK_PCI_LPC<18>

+3VS

MINSD_DATA0 MINSD_DATA1 MINSD_DATA2 MINSD_DATA3

INVT_PW M<15>

LPC_AD[0 ..3]<18>

R55 22_0402_5%

1 2

LPC_FRAME#<18>

R588

ENBKL<18>

EDID_CLK_LCD<15> EDID_DAT_LCD<15>

GMCH_LVDD EN<15>

LVDSAC+<15> LVDSAC-<15>

LVDSA0-<15> LVDSA1-<15> LVDSA2-<15>

LVDSA0+<15> LVDSA1+<15> LVDSA2+<15>

R118 10K_0402_5%

R175 47_0402_5% R179 47_0402_5% R117 22K_0402_5%

R174 47_0402_5% R176 47_0402_5% R177 47_0402_5% R178 47_0402_5%

1 2

R53 10K_0402_5% R57 10K_0402_5%

1 2

1 2 1 2 1 2

1 2 1 2 1 2 1 2

1 2

+3VS

R116 10K_0402_5%

1 2

+3VS

R478 39K_0402_5%

1 2

R62 10K_0402_5%

1 2

+3VS

R63 10K_0402_5%

1 2

+3VS

R64 39K_0402_5%

SIRQ<18>

0_0402_5%

1 2 1 2

EDID_CLK_LCD EDID_DAT_LCD

GMCH_LVDD EN

LVDSAC+ LVDSAC-

LVDSA0LVDSA1LVDSA2-

LVDSA0+ LVDSA1+ LVDSA2+

R65

0_0402_5%

LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3

LPC_CLKOUT0

LPC_CLKRUN# SIRQ

INVT_PWM_SCH

MINSD_CD# MINSD_CLK_R MINSD_CMD_R

MINSD_DATA0_R MINSD_DATA1_R MINSD_DATA2_R MINSD_DATA3_R

T16TPC12 T17TPC12 T18TPC12 T19TPC12

SD1_CMD_R

SD2_CMD_R

12

U4B

K38

LPC_AD0

J39

LPC_AD1

A35

LPC_AD2

L39

LPC_AD3

F38

LPC_CLKOUT0

B36

LPC_CLKOUT1

D38

LPC_CLKOUT2

D36

LPC_CLKRUN#

B38

LPC_SERIRQ

K40

LPC_FRAME#

A33

L_BKLTCTL

A31

L_BKLTEN

D28

L_CTLA_CLK

K26

L_CTLB_DATA

A27

L_DDCCLK

H28

L_DDCDATA

D30

L_VDDEN

AF48

LA_CLKP

AF50

LA_CLKN

AJ43

LA_DATAN0

AK48

LA_DATAN1

AH48

LA_DATAN2

AG45

LA_DATAN3

AJ45

LA_DATAP0

AK50

LA_DATAP1

AH50

LA_DATAP2

AG43

LA_DATAP3

B18

SD0_CD#

D18

SD0_CLK

J15

SD0_CMD

H18

SD0_LED

F18

SD0_WP

H20

SD0_PWR#

H16

SD0_DATA0

A17

SD0_DATA1

K18

SD0_DATA2

F16

SD0_DATA3

K16

SD0_DATA4

B16

SD0_DATA5

D16

SD0_DATA6

K20

SD0_DATA7

B22

SD1_CD#

H22

SD1_CLK

F20

SD1_CMD

A21

SD1_LED

B20

SD1_WP

D20

SD1_PWR#

F22

SD1_DATA0

J19

SD1_DATA1

K22

SD1_DATA2

D22

SD1_DATA3

K24

SD2_CD#

D26

SD2_CLK

B24

SD2_CMD

D24

SD2_LED

B26

SD2_WP

A19

SD2_PWR#

J23

SD2_DATA0

A25

SD2_DATA1

F26

SD2_DATA2

A23

SD2_DATA3

F24

SD2_DATA4

H24

SD2_DATA5

H26

SD2_DATA6

E25

SD2_DATA7

G21

RESERVED18

POULSBO_FCBGA1249

LPC BUS

LVDS

SDIO / MMC

RESERVED8

RESERVED0 RESERVED1

MISC SIGNALSSYSTEM MGMTSDVOPCIE

RESERVED2 RESERVED3

INTVRMEN

RTC

DPRSLPVR

SDVO_CTRLCLK

SDVO_CTRLDATA

SDVOB_CLK

SDVOB_CLK#

SDVOB_INT

SDVOB_INT#

SDVOB_STALL

SDVOB_STALL#

SDVOB_TVCLKIN

SDVOB_TVCLKIN#

SDVOB_RED

SDVOB_RED#

SDVOB_GREEN

SDVOB_GREEN#

SDVOB_BLUE

SDVOB_BLUE#

PCIE_PERn1 PCIE_PERp1 PCIE_PETn1 PCIE_PETp1

PCIE_PERn2 PCIE_PERp2 PCIE_PETn2 PCIE_PETp2

PCIE_CLKINN PCIE_CLKINP

PCIE_ICOMP I

PCIE_ICOMP O

RTC_X1 RTC_X2

RTCRST#

EXTTS

PWROK

SLPRDY#

SLPMODE

RSMRST#

BK50

E49 B32 BE15 BA21

F48 F50 F46 H48

D32

ICH_POK

C49 J49

D34

L45

L43

SDVO_CTRLCLK

F30

SDVO_CTRLDATA

A29

SDVO_CLK

AV48

SDVO_CLK#

AV50 AU47 AU49 AN45 AN43 AP48 AP50

SDVO_RED

AM50

SDVO_RED#

AM48

SDVO_GREEN

AT50

SDVO_GREEN#

AT48

SDVO_BLUE

AR45

SDVO_BLUE#

AR43

PCIE_WLANTX_IRX_C_N2

AW45

PCIE_WLANTX_IRX_C_P2

AW43

PCIE_ITX_WLANRX_N2

BB48

PCIE_ITX_WLANRX_P2

BB50

BA43 BA45 BE49 BD50

CLK_PCIE_ICH#

AY48

CLK_PCIE_ICH

AY50

BA47 BA49

R58 10K_0402_5%

1 2

ICH_RTCX1 ICH_RTCX2

ICH_RTCRST#

R60 10K_0402_5%

1 2

R61 10K_0402_5%

1 2

+PCIE _ICOMP

1 2

SDVO_CTRLCLK <17> SDVO_CTRLDATA <17> SDVO_CLK <17> SDVO_CLK# <17> SDVO_INT <17> SDVO_INT# <17>

SDVO_RED <17> SDVO_RED# <17> SDVO_GREEN <17> SDVO_GREEN# <17> SDVO_BLUE <17> SDVO_BLUE# <17>

C34 0.1U_0402_16V7K

1 2

C35 0.1U_0402_16V7K

1 2

T66 TPC24 T67 TPC24

R66 24.9_0402_1%

C669 22P_0402_50V8J

C670 22P_0402_50V8J

1 2

R59 10K_0402_5%

+3VS

1 2

+RTCVCC

1 2

R54 20K_0402_1%

+RTCVCC

EC_THERM# <4,8,18>

ICH_POK <18>

PM_SLPRDY# <18>

DPRSLPVR <25>

PM_SLPMODE <18>

EC_RSMRST# <18>

PCIE_WLANTX_IRX_C_N2 <14>

PCIE_WLANTX_IRX_C_P2 <14> PCIE_ITX_C_WLANRX_N2 <14> PCIE_ITX_C_WLANRX_P2 <14>

+1.5VS

ICH_RTCRST#

1

C31 1U_0402_6.3V6K

2

ICH_RTCX1

R67

10M_0402_5%

ICH_RTCX2

12

X1

32.768KHZ_12.5P_1TJE125DP1A000M

!!Input from CPU thermal sensor

WLAN

RF Solution

CLK_PCIE_ICH# <13> CLK_PCIE_ICH <13>

C3610P_0402_50V8J

C3710P_0402_50V8J

RTC Reset SW (Place under door)

JRTC1

112

JUMP_43X39

A A

5

2

ICH_RTCRST#

1

C274

0.01U_0402_16V7K

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDEN TIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMA TION IT C ONTAINS

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPA L ELEC TRONICS, INC.

3

2008/05/30 2011/05/30

Compal Secret Data

Deciphered Date

Title

Size Docu ment Number Re v

Custom

2

Date: Sheet

Compal Electronics, Inc.

Poulsbo(2/5)-LVDS/SDVO/SDIO/PCIE

NYU00 LA-5301P

728Monday, April 06, 2009

1

of

0.2

5

USB (LEFT)

USB (RIGHT)

3G

BT

D D

CAM

(RESERVE)

USB20_N0<15> USB20_P0<15> USB20_N1<15> USB20_P1<15> USB20_N2<14> USB20_P2<14> USB20_N3<14> USB20_P3<14> USB20_N4<20> USB20_P4<20> USB20_N5<20> USB20_P5<20>

(RESERVE)

+3VALW

R68 10K_0402_5%

1 2

R69

22.6_0402_1%

1 2

C C

B B

A A

PD_DREQ<19> PD_IORDY<19> PD_IRQ<19> PD_DACK#<19> PD_IOW#<19> PD_IOR#<19> PD_CS#3<19> PD_CS#1<19>

PD_A2<19> PD_A1<19> PD_A0<19>

PD_D15<19> PD_D14<19> PD_D13<19> PD_D12<19> PD_D11<19> PD_D10<19> PD_D9<19> PD_D8<19> PD_D7<19> PD_D6<19> PD_D5<19> PD_D4<19> PD_D3<19> PD_D2<19> PD_D1<19> PD_D0<19>

+3VS

4

USB20_N0 USB20_P0 USB20_N1 USB20_P1 USB20_N2 USB20_P2 USB20_N3 USB20_P3 USB20_N4 USB20_P4 USB20_N5

USB20_P5

T81TPC24 T82TPC24 T87TPC24 T88TPC24

USB20_N6

USB20_P6

USB20_N7

USB20_P7

+USB_RBIAS

R70

4.7K_0402_5%

R123 10K_0402_5%

PD_DREQ PD_IORDY PD_IRQ PD_DACK# PD_IOW# PD_IOR# PD_CS#3 PD_CS#1

PD_A2 PD_A1 PD_A0

PD_D15 PD_D14 PD_D13 PD_D12 PD_D11 PD_D10 PD_D9 PD_D8 PD_D7 PD_D6 PD_D5 PD_D4 PD_D3 PD_D2 PD_D1 PD_D0

PD_IORDY

12

PD_IRQ

12

AE47 AE49 AD48 AD50 AB50 AB48 AA49 AA47

W45

AA45 AA43

W43

AC45 AC43

Y48 Y50 V50 V48 U47 U49 T50 T48

R43

R45 U43

U45

J43 D46 G45 B46 A37 F44 C47 E47

K42 J45 H40

B40 E43 H42 D42 F40 A43 A41 J41 A39 B42 F42 D44 L41 B44 G43 D40

U4C

USB_DN0 USB_DP0 USB_DN1 USB_DP1 USB_DN2 USB_DP2 USB_DN3 USB_DP3 USB_DN4 USB_DP4 USB_DN5 USB_DP5 USB_DN6 USB_DP6 USB_DN7 USB_DP7

USB_OC0# USB_OC1# USB_OC2# USB_OC3# USB_OC4# USB_OC5# USB_OC6# USB_OC7#

USB_RBIASN USB_RBIASP

PATA_DDREQ PATA_IORDY PATA_IDEIRQ PATA_DDACK# PATA_DIOW# PATA_DIOR# PATA_DCS3# PATA_DCS1#

PATA_DA2 PATA_DA1 PATA_DA0

PATA_DD15 PATA_DD14 PATA_DD13 PATA_DD12 PATA_DD11 PATA_DD10 PATA_DD9 PATA_DD8 PATA_DD7 PATA_DD6 PATA_DD5 PATA_DD4 PATA_DD3 PATA_DD2 PATA_DD1 PATA_DD0

USB I/F PATA/IDE

JTAG

SYSTEM GPIOsHD AUDIOCLOCK I/F

No-Connect

SMB Termination Voltage

POULSBO_FCBGA1249

3

VTT_1 VTT_2 VTT_3 VTT_4 VTT_5 VTT_6 VTT_7 VTT_8

VTT_9 VTT_10 VTT_11 VTT_12 VTT_13 VTT_14 VTT_15 VTT_17 VTT_18 VTT_19 VTT_20 VTT_21 VTT_22 VTT_23 VTT_24 VTT_25 VTT_26 VTT_27 VTT_28 VTT_29 VTT_16

TRST#

STPCPU#

RSTRDY#

RESET#

RSTWARN

GPIOSUS0 GPIOSUS1 GPIOSUS2 GPIOSUS3

WAKE#

SMI#

THRM#

GPE#

GPIO0

GPIO1

GPIO2

GPIO3

GPIO4

GPIO5

GPIO6

GPIO7

GPIO8

GPIO9

SPKR

HDA_CLK

HDA_SYNC

HDA_RST#

HDA_SDI0 HDA_SDI1 HDA_SDO

HDA_DOCKEN#

HDA_DOCKRST#

RESERVED6

RESERVED7 DA_REFCLKINN DA_REFCLKINP

DB_REFCLKINNSSC DB_REFCLKINPSSC

CLKREQ#

CLK14

USB_CLK48

SUSCLK

SMB_ALERT#

SMB_DATA

SMB_CLK

TMS

TDO TCK

AW13 AV12 AU13 AT12 AR13 AP12 AN13 AM12 AL13 AK12 AJ13 AH12 AG13 AF12 AE13 AC13 AB12 AA13 Y12 W13 V12 U13 T12 R13 P12 N13 M14 M12 AD12

N49 M50 K48

TDI

M48 N47

H30

H50 BA41 K50 U41 N43 N45 R41

N41 B30 F32 P50

G29 K30 F34 G33 K36 H36 F36 J31 H34 K28

J35 K14 E13 A13 F14 B14 D14 E15 H14

AU43 AU45 AL45 AL43 AE45 AE43 B28 H32 W41 J47

K32 G37 H38

+1.05VS

C38 1U_0402_6.3V6K

1

2

R125 10K_0402_5%

100_0402_1%

R73

1 2

PLT_RST#

SB_INT_FLASH_SEL

SCH_PCIE_W AKE# EC_SMI# EC_THERM#

GPIO0 EC_EAPD_R#_SCH

GPIO3

1 2

R76 10K_0402_5%

SPKR_SCH HDA_BITCLK_AUDIO_SCH HDA_SYNC_AUDIO_SCH HDA_RST_AUDIO#_SCH

HDA_SDOUT_AUDIO_SCH

C45

@

10P_0402_50V8J

1 2

R124 10K_0402_5%

R83

10K_0402_5%

C40 1U_0402_6.3V6K

1

2

C39 1U_0402_6.3V6K

12

+1.05VS

T12 TPC12 T13 TPC12 T14 TPC12 T15 TPC12

H_STP_CPU# <13>

PM_RSTRDY# <18> PLT_RST# < 14,17,18,19> PM_RSTWARN_R <18>

TPC24

T55

PBTN_OUT# <18> EC_LID_OUT# <18>

EC_SMI# <18> EC_THERM# <4,7,18> EC_SCI# <18>

T73 TPC24

BT_APM <20>

TPC24

T57

TPC24

T58

SLPIOV R# <4,22> PROCHOT# <4,25>

+3VS

R180 39_0402_5%

1 2

R78 39_0402_5%

1 2

R79 39_0402_5%

1 2

R80 39_0402_5%

1 2

R81 39_0402_5%

R82 10_0402_5%@

1 2

12

+3VS

R84

2.7K_0402_5%

12

T5 PAD

12

R85

2.7K_0402_5%

2

1

C41 10U_0603_6.3V6M

2

SCH_PCIE_W AKE#

R71 1K_0402_5%

EC_THERM#

R72 8.2K_0402_5%@

SPKR <16> HDA_BITCLK_AUDIO <16,17> HDA_SYNC_AUDIO <16,17> HDA_R ST_AUDIO# <16,17> HDA_SDIN0 <16> HDA_SDIN1 <17> HDA_SDOUT_AUDIO <16,17>

CLK_MC H_DREFCLK# <13> CLK_MCH_DREFCLK <13> MCH_SS CDREFCLK# <13> MCH_SS CDREFCLK <13>

CLK_14M_SCH <13>

SMB_DAT <13> SMB_CLK <13>

+3VS

1

+3VALW

1 2

+3VS

1 2

+3VS

12

@

R74 10K_0402_5%

1 2

R77 10K_0402_5%

HDA_BITCLK_AUDIO

HDA_SDOUT_AUDIO

1 2

+3VS

R131 1K_0402_1%

GPIO0H@

1 2

+3VS

R126 1K_0402_1%@

*3,2*3,25$0B9HQGRU5$0B7\SH55 &0&6DPVXQJ*E[;9 &0&+\QL[*E[;;'HIDXOW &0&1DQ\D*E[99 &0&0LFURQ*E[9;

*3,2,QWHUQDOSXOOGRZQN *3,2,QWHUQDO3XOOKLJKN

C671 22P_0402_50V8J

C672 22P_0402_50V8J

GPIO0

GPIO3

RF Solution

1 2

R127 1K_0402_1%

@

1 2

R75 1K_0402_1%

GPIO3L@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDEN TIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMA TION IT C ONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPA L ELEC TRONICS, INC.

3

2008/05/30 2011/05/30

Compal Secret Data

Deciphered Date

Title

Size Docu ment Number Re v

Custom

2

Date: Sheet

Compal Electronics, Inc.

Poulsbo(3/5)-HDA/PATA/USB

NYU00 LA-5301P

828Monday, Apr il 06, 2009

1

0.2

of

5

4

3

2

1

+1.05VS

T32

T30

T28

T26

T24

T22

T20

T18

T16

AK22

AK20

AK18

AK16

AH34

AH32

AH30

AH28

AH26

AH24

AH22

AH20

AH18

AH16

AF34

AF32

AF30

AF28

AF26

AF24

AF22

AF20

AF18

AF16

AD30

AD28

AD26

AD24

AD22

AD20

AD18

AB18

AB16

Y30

Y28

Y26

Y24

V22

V20

V18

AG37 AF38 AF36 AE37 AD36

AT34 AT32 AR37 AP38 AP36 AN37 AU37 AT38 AT36 AM36 AV38

AK36

AJ37 AH38 AH36 AK38

AL37

U4E

VCCLVDS_101 VCCLVDS_100 VCCLVDS_1 VCCLVDS_2 VCCLVDS_3

VCCPCIE_4 VCCPCIE_5 VCCPCIE_6 VCCPCIE_7 VCCPCIE_8 VCCPCIE_9 VCCPCIE_1 VCCPCIE_2 VCCPCIE_3 VCCPCIE_100 VCCPCIE_101

VCCSDVO_110 VCCSDVO_100 VCCSDVO_101 VCCSDVO_103 VCCSDVO_106 VCCSDVO_105

VCC_79

VCC_80

D D

+1.5VS

C53 1U_0402_6.3V6K

+1.5VS

1

2

C C

+1.5VS

1

2

C56 1U_0402_6.3V6K

1

C57 1U_0402_6.3V6K

2

Y22

T34

VCC_9

VCC_8

VCC_7

VCC_6

VCC_5

VCC_4

VCC_3

VCC_2

VCC_1

VCC_11

VCC_12

VCC_13

VCC_14

VCC_15

VCC_16

VCC_17

VCC_18

VCC_19

VCC_20

VCC_21

VCC_22

VCC_23

VCC_24

VCC_25

VCC_26

VCC_27

VCC_28

VCC_29

VCC_30

VCC_31

VCC_32

VCC_33

VCC_63

VCC_64

VCC_65

VCC_66

VCC_67

VCC_68

VCC_81

VCC_69

VCC_10

VCC_34

VCC

AD16

VCC_35

VCC_36

VCC_37

VCC_38

VCC_39

VCC_40

VCC_41

AM34

AM32

AM30

AM28

AM26

AM24

AM22

AM20

AM18

AM16

AK34

AK32

AK30

AB30

AB28

AB26

AB24

AB22

AB20

VCC_49

VCC_50

VCC_51

VCC_52

VCC_53

VCC_42

VCC_43

VCC_44

VCC_45

VCC_46

VCC_47

VCC_54

VCC_48

AK28

VCC_55

VCC_56

VCC_57

VCC_58

VCC_59

VCC_60

VCC_61

C46

0.1U_0402_16V7K

Y18

Y16

V34

V32

V30

V28

V16

AK26

AK24

VCC_62

VCC_71

VCC_72

VCC_73

VCC_74

VCC_75

VCC_82

VCC_120

VCC_121

RESERVED10

RESERVED9

VCC15USB_1 VCC15USB_2 VCC15USB_3 VCC15USB_4 VCC15USB_5 VCC15USB_6

RESERVED12 RESERVED11 RESERVED13

VCCAPCIEBG

VSSAPCIEBG

V26

V24

VCC_76

VCC_77

VCC_78

VCC15_1 VCC15_2 VCC15_3 VCC15_4 VCC15_5 VCC15_6 VCC15_7 VCC15_8

VCC15_9 VCC15_10 VCC15_11 VCC15_12 VCC15_13 VCC15_14 VCC15_15 VCC15_16 VCC15_17 VCC15_18

Y20

VCC_70

C47

0.1U_0402_16V7K

1

2

R33 R31 R29 R27 R25 R23 R21 R19 R17 R15 P34 P32 N33 N31 M38 M36 M34 M32

P38 P36

AD34 AD32 AB34 AB32 Y34 Y32

AB38 AA37 W37

AW41 AY42

C49 1U_0402_6.3V6K

1

2

C48

0.1U_0402_16V7K

+1.5VS

1

C54 1U_0402_6.3V6K

2

Place under Poulsbo

+1.5VS

1

2

C50

4.7U_0603_6.3V6K

Place under Poulsbo

1

2

T7 PAD

+3VS

R86 0_0402_5%

1 2

C663

10U_0603_6.3V6M C51 10U_0603_6.3V6M

1

2

C664 10U_0603_6.3V6M

1

+

C55 150U_B2_6.3VM_R35M

2

T6 PAD

1

C58

0.1U_0402_16V7K

2

1

+

C52 150U_B2_6.3VM_R35M

2

VCCSM_103

VCCSM_104

VCCSM_105

VCCSM_106

AW29

AW27

AW25

AW23

C61 1U_0402_6.3V6K

VCCSM_10

VCCSM_107

VCCSM_108

AW37

AW21

AW19

1

2

VCCSM_1

VCCSM_2

VCCSM_3

VCCSM_4

VCCSM_5

VCCSM_6

AV36

AV34

AV32

AV30

AV28

AV26

AW17

1

2

C62 10U_0603_6.3V6M

VCCSM_7

VCCSM_21

VCCSM_22

AV24

AV22

VCCSM_23

VCCSM_24

VCCSM_25

VCCSM_26

VCCSM_27

AT30

AT28

AT26

AV20

AV18

AV16

1

+

C63 150U_B2_6.3VM_R35M

2

VCCSM_28

VCCSM_29

VCCSM_30

VCCSM_31

VCCSM_32

VCCSM_33

VCCSM_34

VCCSM_35

VCCSM_36

VCCSM_37

VCCSM_38

VCCSM_39

VCCSM_40

VCCSM_41

AT24

AT22

AT20

AT18

AT16

AP34

AP32

AP30

AP28

AP26

AP24

AP22

AP20

C67

0.1U_0402_16V7K

VCCSM_100

VCCSM_101

VCCSM_102

VCCSM_43

AP16

AW35

AW33

B B

C59 1U_0402_6.3V6K

+1.8V

1

2

AW31

1

2

C60 1U_0402_6.3V6K

VCCP33USBSUS_2

RESERVED16

RESERVED17

VCCSM_42

RESERVED14

RESERVED15

Y38

N37

N35

AB36

AP18

AC37

T8

T9

PAD

Place under Poulsbo

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDEN TIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMA TION IT C ONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPA L ELEC TRONICS, INC.

3

VCC33_15

VCC33SUS_1

VCC33SUS_2

VCC33SUS_3

VCCP33USBSUS_1

VCCP33USBSUS_3

T38

R39

U37

M18

W39

AA39

1

2

C69

0.1U_0402_16V7K

2008/05/30 2011/05/30

VCC33_9

VCC33_10

VCC33_11

VCC33_12

VCC33_13

VCC33_14

M30

M28

M26

M24

M22

M20

C70

1U_0402_6.3V6K

1

2

C71

1U_0402_6.3V6K

Compal Secret Data

VCC33_6

N19

VCC33_3

VCC33_4

VCC33_5

VCC33_7

VCC33_8

N25

N23

N21

N17

N15

+RTCVCC

+3VS

1

2

C72 1U_0402_6.3V6K

0.1U_0402_16V7K

Deciphered Date

VCC33_1

VCC33_2

VCC33RTC

VCCHDA_1

VCCHDA_2

VCCAUSBPLL

VCCDHPLL

VCCAHPLL

VCCAUSBBGSUS

VCCADPLLA

VCCAPCIEPLL

VCCADPLLB

VCC5REF_1

K34

AE39

AN49

AG39

+VCCADPLL

VCC5REFSUS

POULSBO_FCBGA1249

AA41

+V5_5REFSUS_SCH

+V5_5REF_SCH

0.1U_0402_16V7K

1

C68

0.1U_0402_16V7K

2

1 2

R88 0_0402_5%

1

C74

0.1U_0402_16V7K

2

+5VALW+3VALW

12

D1 CH751H-40PT_SOD323-2

1

2

+1.5VS

Title

NYU00 LA-5301P

1

2

C66

0.1U_0402_16V7K

+V5_5REFSUS_SCH

D2 CH751H-40PT_SOD323-2

+V5_5REF_SCH

Compal Electronics, Inc.

Poulsbo(4/5)-PWR

C65

Size Docu ment Number Re v

Custom

Date: Sheet

21

1

R87 10_0402_5%

+5VS+3VS

12

R132 10_0402_5%

928Monday, April 06, 2009

of

0.2

VCC33_16

A45

N29

N27

M16

1

2

J11

K12

1

C64

2

1U_0402_6.3V6K

+VCCAUSBPLL

C75

BB10

BA11

AC39

+VCCAHPLL

C73

0.1U_0402_16V7K

R89 0_0402_5%

1 2

R90

1

0_0402_5%

2

VSSAUSBBGSUS

AE41

AC41

1

2

+1.5VS

+3VALW+3VALW

+1.5VS

5

U4F

BH30

VSS_1

BH28

VSS_2

BH26

VSS_3

BH24

VSS_4

BH22

VSS_5

BH20

VSS_6

BH18

VSS_7

BH16

D D

C C

B B

A A

VSS_8

BH14

VSS_9

BH12

VSS_10

BH2

VSS_11

BG9

VSS_12

BG7

VSS_13

BG5

VSS_14

BG3

VSS_15

BG1

VSS_16

BF50

VSS_17

BF48

VSS_18

BF46

VSS_19

BF44

VSS_20

BF42

VSS_21

BF40

VSS_22

BF38

VSS_23

BF36

VSS_24

BF34

VSS_25

BF32

VSS_26

BF30

VSS_27

BF28

VSS_28

BF26

VSS_29

BF24

VSS_30

BF22

VSS_31

BF20

VSS_32

BF18

VSS_33

BF16

VSS_34

BF14

VSS_35

BF12

VSS_36

BE9

VSS_37

BE7

VSS_38

BE5

VSS_39

BE3

VSS_40

BD48

VSS_41

BD46

VSS_42

BD44

VSS_43

BD42

VSS_44

BD40

VSS_45

BD38

VSS_46

BD36

VSS_47

BD34

VSS_48

BD32

VSS_49

BD30

VSS_50

BD28

VSS_51

BD26

VSS_52

BD24

VSS_53

BD22

VSS_54

BD20

VSS_55

BD18

VSS_56

BD16

VSS_57

BD14

VSS_58

BD12

VSS_59

BC49

VSS_60

BC9

VSS_61

BC7

VSS_62

BC5

VSS_63

BC3

VSS_64

BB46

VSS_65

BB44

VSS_66

BB42

VSS_67

BB40

VSS_68

BB38

VSS_69

BB36

VSS_70

BB34

VSS_71

BB32

VSS_72

BB30

VSS_73

BB28

VSS_74

BB26

VSS_75

BA9

VSS_83

BB12

VSS_82

BB14

VSS_81

BB16

VSS_80

BB18

VSS_79

BB20

VSS_78

AM44

VSS_420

AM42

VSS_421

AM40

VSS_422

AM38

VSS_423

AM14

VSS_424

AM10

VSS_425

AL49

VSS_426

AL47

VSS_427

AL41

VSS_521

AL39

VSS_520

AL35

VSS_523

AL33

VSS_519

AL31

VSS_518

AL29

VSS_517

AL27

VSS_516

AL25

VSS_515

AL23

VSS_514

AL21

VSS_416

AL19

VSS_417

AL17

VSS_418

AL15

VSS_419

AL11

VSS_414

AL9

VSS_415

AK46

VSS_513

AL3

VSS_512

POULSBO_FCBGA1249

VSS

5

VSS_76 VSS_77 VSS_84 VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97 VSS_98

VSS_99 VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143 VSS_144 VSS_145 VSS_146 VSS_147 VSS_148 VSS_149 VSS_150 VSS_151 VSS_152 VSS_153 VSS_154 VSS_155 VSS_156 VSS_384 VSS_385 VSS_386 VSS_387 VSS_388 VSS_389 VSS_390 VSS_391 VSS_392 VSS_393 VSS_394 VSS_395 VSS_396 VSS_397 VSS_398 VSS_399 VSS_400 VSS_401 VSS_402 VSS_522 VSS_405 VSS_406 VSS_407 VSS_408 VSS_409 VSS_410 VSS_411 VSS_412 VSS_413 VSS_510 VSS_511

BB24 BB22 BA7 BA5 BA3 AY46 AY44 AY40 AY38 AY36 AY34 AY32 AY30 AY28 AY26 AY24 AY22 AY20 AY18 AY16 AY14 AY12 AW49 AW47 AW39 AW15 AW11 AW9 AW7 AW5 AW3 AV46 AV44 AV42 AV40 AV14 AU41 AU39 AU35 AU33 AU31 AU29 AU27 AU25 AU23 AU21 AU19 AU17 AU15 AU11 AU9 AU7 AU5 AU3 AT46 AT44 AT42 AT40 AT14 AR49 AR47 AR41 AR39 AR35 AR33 AR31 AR29 AR27 AR25 AR23 AR21 AR19 AR17 AR15 AR11 AR9 AR7 AR5 AR3 AP46 AP44 AP42 AP40 AP14 AN47 AN41 AN39 AN35 AN33 AN31 AN29 AN27 AN25 AN23 AN21 AN19 AN17 AN15 AN11 AN9 AN7 AN5 AN3 AM46 AL7 AL5

4

AJ3

AH46

AH44

AH42

AH40

AH14

AG49

AG47

AG41

AG35

AG33

AG31

VSS_185

VSS_736

AG29

VSS_186

VSS_187

VSS_188

VSS_189

VSS_190

VSS_191

VSS_192

VSS_737

VSS_738

VSS_800

VSS_801

VSS_802J7VSS_803J5VSS_804J3VSS_805

J17

J13

P46

P44

W35 W33 W31 W29 W27 W25 W23 W21 W19 W17 W15 W11

AJ41 AJ47

AJ49 AK14 AK40 AK44

AJ11

AJ15

AJ17

AJ19

AJ21

AJ23

AJ25

AJ27

AJ29

AJ31

AJ33

AJ35

AJ39

U27 U25 G47 G41 G39 G35 G31 G27 G25 G23 C19 C17 C15 C13

BH50 BH48 BH46 BH44 BH42

U4G

VSS_293 VSS_294 VSS_295

VSS_180

VSS_181

VSS_182

VSS_183

VSS_296 VSS_297 VSS_298 VSS_299 VSS_300 VSS_301 VSS_302 VSS_303 VSS_304

W9

VSS_305

W7

VSS_306

W5

VSS_307

W3

VSS_308

V46

VSS_309

V44

VSS_310

V42

VSS_311 VSS_163 VSS_162 VSS_161 VSS_160 VSS_159 VSS_157

AJ5

VSS_179

AJ7

VSS_178

AJ9

VSS_177 VSS_176 VSS_175 VSS_174 VSS_173 VSS_172 VSS_171 VSS_170 VSS_169 VSS_168 VSS_167 VSS_166 VSS_165 VSS_164

L9

VSS_323

L7

VSS_324

L5

VSS_325

L3

VSS_326

K46

VSS_327

K44

VSS_328

J37

VSS_329

J33

VSS_330

J29

VSS_331

J25

VSS_332

J21

VSS_333 VSS_709 VSS_710 VSS_335 VSS_336 VSS_337 VSS_338 VSS_339 VSS_340 VSS_341 VSS_342 VSS_504 VSS_503 VSS_502 VSS_501

G3

VSS_505

E45

VSS_506

BJ1

VSS_1014 VSS_1015 VSS_1016 VSS_1017 VSS_1018 VSS_1019

VSS_701

VSS_1022

V38

BH36

VSS_184

VSS_702

VSS_703

VSS_704

VSS_705

VSS_706

VSS_707

VSS_708

V36

V14

P48

U39

U35

U33

U31

U29

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDEN TIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMA TION IT C ONTAINS

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPA L ELEC TRONICS, INC.

3

AG27

AG25

AG23

AG21

AG19

AG17

AG15

AG11

AG9

AG7

AG5

AG3

AF46

AF44

AF42

AF40

AF14

AE35

AE33

AE31

AE29

AE27

AE25

AE23

AE21

AE19

AE17

AE15

AE11

AE9

AE7

AE5

AE3

AD46

AD44

VSS_193

VSS_194

VSS_195

VSS_196

VSS_197

VSS_198

VSS_199

VSS_200

VSS_201

VSS_202

VSS_203

VSS_204

VSS_205

VSS_206

VSS_207

VSS_208

VSS_209

VSS_210

VSS_211

VSS_212

VSS_213

VSS_214

VSS_215

VSS_216

VSS_217

VSS_218

VSS_219

VSS_220

VSS_221

VSS_222

VSS_223

VSS_224

VSS_225

VSS_226

VSS_227

VSS

VSS_711

VSS_712

VSS_713

VSS_714

VSS_715

VSS_716

VSS_717U9VSS_718U7VSS_719U5VSS_720U3VSS_721

VSS_722

VSS_723

VSS_724

VSS_725

VSS_726

VSS_727

VSS_728

VSS_729

VSS_730

VSS_731

VSS_732

T14

R49

R47

R37

R35

VSS_733R7VSS_734R5VSS_735

R9

R3

R11

Compal Secret Data

VSS_806

VSS_807

T46

T44

T42

T40

U23

U21

U19

U17

U15

H46

H44

U11

G49

T36

2008/05/30 2011/05/30

3

VSS_751

VSS_850

VSS_851

VSS_852

VSS_853E9VSS_854

E7

E19

E17

E11

N11

Deciphered Date

VSS_750

N39

2

AD42

AD40

AD38

AD14

AC49

AC47

AC35

AC33

AC31

AC29

AC27

AC25

AC23

AC21

AC19

AC17

AC15

AC11

AC9

AC7

AC5

AC3

AB46

AB44

AB42

AB40

AB14

AA35

AA33

AA31

AA29

AA27

AA25

AA23

AA21

VSS_228

VSS_229

VSS_230

VSS_231

VSS_232

VSS_233

VSS_234

VSS_235

VSS_236

VSS_237

VSS_238

VSS_239

VSS_240

VSS_241

VSS_242

VSS_243

VSS_244

VSS_245

VSS_246

VSS_247

VSS_248

VSS_249

VSS_250

VSS_251

VSS_252

VSS_253

VSS_254

VSS_255

VSS_256

VSS_257

VSS_258

VSS_259

VSS_260

VSS_261

VSS_700

VSS_739

VSS_740

VSS_741

VSS_742

VSS_743

VSS_744

VSS_745

VSS_746

VSS_747

VSS_748

VSS_749

P24

P22

P20

P18

P16

P14

VSS_855E5VSS_856E3VSS_857E1VSS_858

VSS_859

VSS_860

VSS_861

VSS_862

VSS_863

VSS_864

VSS_865

VSS_866

VSS_867

VSS_868

VSS_869

VSS_870

VSS_871

VSS_872

VSS_873

VSS_874C9VSS_875C7VSS_876C5VSS_877C3VSS_878C1VSS_879

V40

P42

P40

P30

P28

P26

2

D50

D48

C45

C43

C41

C39

C37

C35

C33

C31

C29

C27

C25

C23

C21

C11

Title

Size Docu ment Number Re v

Custom

Date: Sheet

Compal Electronics, Inc.

Poulsbo(5/5)-GND

NYU00 LA-5301P

VSS_262

B50

VSS_1023

VSS_1003 VSS_1000 VSS_1001 VSS_1004 VSS_1005 VSS_1006 VSS_1007 VSS_1008 VSS_1009 VSS_1010 VSS_1011 VSS_1012 VSS_1013

VSS_880

VSS_883

B48

A47

1

VSS_263 VSS_264 VSS_265 VSS_266 VSS_267 VSS_268 VSS_269 VSS_270 VSS_271 VSS_272 VSS_273 VSS_274 VSS_275 VSS_276 VSS_277 VSS_278 VSS_292 VSS_291 VSS_290 VSS_289 VSS_288 VSS_287 VSS_286 VSS_285 VSS_284 VSS_283 VSS_282 VSS_281 VSS_280 VSS_279 VSS_312 VSS_313 VSS_314 VSS_315 VSS_316 VSS_317 VSS_318 VSS_319 VSS_320 VSS_321 VSS_343 VSS_344 VSS_345 VSS_346 VSS_347 VSS_348 VSS_349 VSS_158 VSS_404 VSS_403 VSS_383 VSS_378 VSS_379 VSS_380 VSS_381 VSS_382 VSS_508 VSS_507 VSS_882 VSS_881

VSS_1021

VSS_1024

BH38

BH32

1

BH34 AA19 AA17 AA15 AA11 AA9 AA7 AA5 AA3 Y46 Y44 Y42 Y40 Y36 Y14 W49 W47 N9 N7 N5 N3 M46 M44 M42 M40 L49 L47 L37 L35 L33 L31 L29 L27 L25 L23 L21 L19 L17 L15 L13 L11 G19 G17 G15 G13 G9 G7 G5 AK42 E21 E23 E27 E29 E31 E33 E35 E37 E39 E41 A49 B2 A15 A5 A3 BK48 BK46 BK4 BK2 BJ49 BJ11 BJ9 BJ7 BJ5 BJ3

VSS_1020

POULSBO_FCBGA1249

BH40

10 28Monday, April 06, 2009

0.2

of

5

DDR_A_BS#0 DDR_A_BS#1

DDR_A_MA12 DDR_A_MA11 DDR_A_MA10 DDR_A_MA9 DDR_A_MA8 DDR_A_MA7 DDR_A_MA6 DDR_A_MA5 DDR_A_MA4 DDR_A_MA3

D D

M_CLK_DDR#0<6,12> M_CLK_DDR0<6,12>

M_CKE0<6>

M_CS#0<6>

DDR_A_WE#<6,12>

DDR_A_RAS#<6,12>

DDR_A_CAS#<6,12>

M_ODT<12>

+1.8V

R91

12

R92 1K_0402_1%

+VRAM_VREFA

1K_0402_1%

1 2

1

C76

0.1U_0402_16V4Z

2

Close to U5

1

C95

0.1U_0402_16V4Z

2

Close to U11

C C

+VRAM_VREFA

B B

A A

DDR_A_MA2 DDR_A_MA1 DDR_A_MA0

M_CLK_DDR#0 M_CLK_DDR0

M_CKE0

M_CS#0

DDR_A_WE#

DDR_A_RAS#

DDR_A_CAS#

M_ODT

DDR_A_DQS0

DDR_A_DQS1

(SSTL-1.8) VREF = .5*VD DQ

DDR_A_BS#2 DDR_A_BS#2

DDR_A_MA13 DDR_A_MA13

DDR_A_BS#0 DDR_A_BS#1

DDR_A_MA12 DDR_A_MA11 DDR_A_MA10 DDR_A_MA9 DDR_A_MA8 DDR_A_MA7 DDR_A_MA6 DDR_A_MA5 DDR_A_MA4 DDR_A_MA3 DDR_A_MA2 DDR_A_MA1 DDR_A_MA0

M_CLK_DDR#1 M_CLK_DDR1

M_CKE0

M_CS#0

DDR_A_WE#

DDR_A_RAS#

DDR_A_CAS#

M_ODT

DDR_A_DQS6

DDR_A_DQS7

(SSTL-1.8) VREF = .5*VD DQ

DDR_A_BS#2

DDR_A_MA13

5

U5

L2

BA0

L3

BA1

R2

A12

P7

A11

M2

A10/AP

P3

A9

P8

A8

P2

A7

N7

A6

N3

A5

N8

A4

N2

A3

M7

A2

M3

A1

M8

A0

K8

CK

J8

CK

K2

CKE

L8

CS

K3

WE

K7

RAS

L7

CAS

F3

LDM

B3

UDM

K9

ODT

F7

LDQS

E8

LDQS

B7

UDQS

A8

UDQS

J2

VREF

A2

NC#A2

E2

NC#E2

L1

BA2

R3

NC#R3

R7

NC#R7

R8

NC#R8

K4T1G164QE-HCF7_FBGA84

1GB@

U11

L2

BA0

L3

BA1

R2

A12

P7

A11

M2

A10/AP

P3

A9

P8

A8

P2

A7

N7

A6

N3

A5

N8

A4

N2

A3

M7

A2

M3

A1

M8

A0

K8

CK

J8

CK

K2

CKE

L8

CS

K3

WE

K7

RAS

L7

CAS

F3

LDM

B3

UDM

K9

ODT

F7

LDQS

E8

LDQS

B7

UDQS

A8

UDQS

J2

VREF

A2

NC#A2

E2

NC#E2

L1

BA2

R3

NC#R3

R7

NC#R7

R8

NC#R8

K4T1G164QE-HCF7_FBGA84

1GB@

DQ15 DQ14 DQ13 DQ12 DQ11 DQ10

DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0

VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDDQ9

VDDQ10

VDD1 VDD2 VDD3 VDD4 VDD5

VDDL

VSSDL

VSSQ1 VSSQ2 VSSQ3 VSSQ4 VSSQ5 VSSQ6 VSSQ7 VSSQ8 VSSQ9

VSSQ10

VSS1 VSS2 VSS3 VSS4 VSS5

DQ15 DQ14 DQ13 DQ12 DQ11 DQ10

DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0

VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDDQ9

VDDQ10

VDD1 VDD2 VDD3 VDD4 VDD5

VDDL

VSSDL

VSSQ1 VSSQ2 VSSQ3 VSSQ4 VSSQ5 VSSQ6 VSSQ7 VSSQ8 VSSQ9

VSSQ10

VSS1 VSS2 VSS3 VSS4 VSS5

DDR_A_D11

B9

DDR_A_D8

B1

DDR_A_D13

D9

DDR_A_D14

D1

DDR_A_D9

D3

DDR_A_D12

D7

DDR_A_D15

C2

DDR_A_D10

C8

DDR_A_D5

F9

DDR_A_D6

F1

DDR_A_D4

H9

DDR_A_D3

H1

DDR_A_D7

H3

DDR_A_D0

H7

DDR_A_D2

G2

DDR_A_D1

G8

A9 C1 C3 C7 C9 E9 G1 G3 G7 G9

A1 E1 J9 M9 R1

J1 J7

A7 B2 B8 D2 D8 E7 F2 F8 H2 H8

A3 E3 J3 N1 P9

B9 B1 D9 D1 D3 D7 C2 C8 F9 F1 H9 H1 H3 H7 G2 G8

A9 C1 C3 C7 C9 E9 G1 G3 G7 G9

A1 E1 J9 M9 R1

J1 J7

A7 B2 B8 D2 D8 E7 F2 F8 H2 H8

A3 E3 J3 N1 P9

DDR_A_D61 DDR_A_D62 DDR_A_D57 DDR_A_D63 DDR_A_D58 DDR_A_D56 DDR_A_D59 DDR_A_D60 DDR_A_D55 DDR_A_D51 DDR_A_D50 DDR_A_D52 DDR_A_D48 DDR_A_D53 DDR_A_D49 DDR_A_D54

4

Group1

Group0

+1.8V

+VRAM_VREFA

0.1U_0402_16V4Z

Close to U8

Group7

Group6

3

DDR_A_BS#0 DDR_A_BS#1

DDR_A_MA12 DDR_A_MA11 DDR_A_MA10 DDR_A_MA9 DDR_A_MA8 DDR_A_MA7 DDR_A_MA6 DDR_A_MA5 DDR_A_MA4 DDR_A_MA3 DDR_A_MA2 DDR_A_MA1 DDR_A_MA0

M_CLK_DDR#0 M_CLK_DDR0

M_CKE0

M_CS#0

DDR_A_WE#

DDR_A_RAS#

DDR_A_CAS#

M_ODT

DDR_A_DQS2

DDR_A_DQS3

(SSTL-1.8) VREF = .5*VD DQ

1

C77

2

Security Classification

U8

L2

BA0

L3

BA1

R2

A12

P7

A11

M2

A10/AP

P3

A9

P8

A8

P2

A7

N7

A6

N3

A5

N8

A4

N2

A3

M7

A2

M3

A1

M8

A0

K8

CK

J8

CK

K2

CKE

L8

CS

K3

WE

K7

RAS

L7

CAS

F3

LDM

B3

UDM

K9

ODT

F7

LDQS

E8

LDQS

B7

UDQS

A8

UDQS

J2

VREF

A2

NC#A2

E2

NC#E2

L1

BA2

R3

NC#R3

R7

NC#R7

R8

NC#R8

K4T1G164QE-HCF7_FBGA84

1GB@

DDR_A_BS#[0..2]<6,12>

DDR_A_D[0..63]<6,12>

DDR_A_DQS[0..7]<6,12>

DDR_A_MA[0..13]<6,12>

VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDDQ9

VDDQ10

VSSDL

VSSQ1 VSSQ2 VSSQ3 VSSQ4 VSSQ5 VSSQ6 VSSQ7 VSSQ8 VSSQ9

VSSQ10

M_ODT

M_CLK_DDR0

M_CLK_DDR#0

DQ15 DQ14 DQ13 DQ12 DQ11 DQ10

DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0

VDD1 VDD2 VDD3 VDD4 VDD5

VDDL

VSS1 VSS2 VSS3 VSS4 VSS5

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDEN TIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMA TION IT C ONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPA L ELEC TRONICS, INC.

3

DDR_A_D26

B9

DDR_A_D31

B1

DDR_A_D24

D9

DDR_A_D27

D1

DDR_A_D25

D3

DDR_A_D28

D7

DDR_A_D30

C2

DDR_A_D29

C8

DDR_A_D20

F9

DDR_A_D23

F1

DDR_A_D17

H9

DDR_A_D21

H1

DDR_A_D19

H3

DDR_A_D16

H7

DDR_A_D22

G2

DDR_A_D18

G8

A9 C1 C3 C7 C9 E9 G1 G3 G7 G9

A1 E1 J9 M9 R1

J1 J7

A7 B2 B8 D2 D8 E7 F2 F8 H2 H8

A3 E3 J3 N1 P9

12

R93 10K_0402_5%

12

R94 100_0402_1%

2008/05/30 2011/05/30

Group3

Group2

M_CLK_DDR#1<6,12> M_CLK_DDR1<6,12>

+1.8V

+VRAM_VREFA

C78

0.1U_0402_16V4Z

Close to U6

0.01U_0402_16V7K

+1.8V

0.01U_0402_16V7K

Compal Secret Data

Deciphered Date

+1.8V

2

(SSTL-1.8) VREF = .5*VD DQ

1

2

0.1U_0402_16V4Z

1

C79

2

0.1U_0402_16V4Z

1

C87

2

0.1U_0402_16V4Z

1

C91

2

DDR_A_BS#0 DDR_A_BS#1

DDR_A_MA12 DDR_A_MA11 DDR_A_MA10 DDR_A_MA9 DDR_A_MA8 DDR_A_MA7 DDR_A_MA6 DDR_A_MA5 DDR_A_MA4 DDR_A_MA3 DDR_A_MA2 DDR_A_MA1 DDR_A_MA0

M_CLK_DDR#1 M_CLK_DDR1

M_CKE0

M_CS#0

DDR_A_WE#

DDR_A_RAS#

DDR_A_CAS#

M_ODT

DDR_A_DQS5

DDR_A_DQS4

DDR_A_BS#2

DDR_A_MA13

1

C80

2

1U_0402_6.3V6K

1

C88

2

1U_0402_6.3V6K

1

C92

2

1U_0402_6.3V6K

0.1U_0402_16V4Z

1

C82

C81

2

0.1U_0402_16V4Z

1

C90

C89

2

0.1U_0402_16V4Z

1

C94

C93

2

U6

L2

BA0

L3

BA1

R2

A12

P7

A11

M2

A10/AP

P3

A9

P8

A8

P2

A7

N7

A6

N3

A5

N8

A4

N2

A3

M7

A2

M3

A1

M8

A0

K8

CK

J8

CK

K2

CKE

L8

CS

K3

WE

K7

RAS

L7

CAS

F3

LDM

B3

UDM

K9

ODT

F7

LDQS

E8

LDQS

B7

UDQS

A8

UDQS

J2

VREF

A2

NC#A2

E2

NC#E2

L1

BA2

R3

NC#R3

R7

NC#R7

R8

NC#R8

K4T1G164QE-HCF7_FBGA84

1GB@

Title

Size Docu ment Number Re v

Custom

Date: Sheet

B9

DQ15

B1

DQ14

D9

DQ13

D1

DQ12

D3

DQ11

D7

DQ10

C2

DQ9

C8

DQ8

F9

DQ7

F1

DQ6

H9

DQ5

H1

DQ4

H3

DQ3

H7

DQ2

G2

DQ1

G8

DQ0

A9

VDDQ1

C1

VDDQ2

C3

VDDQ3

C7

VDDQ4

C9

VDDQ5

E9

VDDQ6

G1

VDDQ7

G3

VDDQ8

G7

VDDQ9

G9

VDDQ10

A1

VDD1

E1

VDD2

J9

VDD3

M9

VDD4

R1

VDD5

J1

VDDL

J7

VSSDL

A7

VSSQ1

B2

VSSQ2

B8

VSSQ3

D2

VSSQ4

D8

VSSQ5

E7

VSSQ6

F2

VSSQ7

F8

VSSQ8

H2

VSSQ9

H8

VSSQ10

A3

VSS1

E3

VSS2

J3

VSS3

N1

VSS4

P9

VSS5

+1.8V

C84

0.1U_0402_16V4Z

1

2

C83

0.01U_0402_16V7K

Compal Electronics, Inc.

DDRII-DEVICE DOWN(1/2)

NYU00 LA-5301P

1

DDR_A_D34 DDR_A_D38 DDR_A_D32 DDR_A_D39 DDR_A_D36 DDR_A_D35 DDR_A_D37 DDR_A_D33 DDR_A_D47 DDR_A_D40 DDR_A_D46 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D45 DDR_A_D44

1

2

C85 1U_0402_6.3V6K

1

+1.8V

C86

0.1U_0402_16V4Z

Group4

Group5

11 28Monday, April 06, 2009

0.2

of

5

DDR_A_BS#0 DDR_A_BS#1

DDR_A_MA12 DDR_A_MA11 DDR_A_MA10 DDR_A_MA9 DDR_A_MA8 DDR_A_MA7 DDR_A_MA6 DDR_A_MA5 DDR_A_MA4

D D

M_CLK_DDR#0<6,11> M_CLK_DDR0<6,11>

M_CKE1<6>

M_CS#1<6>

DDR_A_WE#<6,11>

DDR_A_RAS#<6,11>

DDR_A_CAS#<6,11>

M_ODT<11>

C C

+VRAM_VREFA

B B

M_CLK_DDR#1<6,11> M_CLK_DDR1<6,11>

A A

+VRAM_VREFA

1

C115

0.1U_0402_16V4Z

2

DDR_A_MA3 DDR_A_MA2 DDR_A_MA1 DDR_A_MA0

M_CLK_DDR#0 M_CLK_DDR0

M_CKE1

M_CS#1

DDR_A_WE#

DDR_A_RAS#

DDR_A_CAS#

M_ODT

DDR_A_DQS0

DDR_A_DQS1

(SSTL-1.8) VREF = .5*VD DQ

DDR_A_BS#2

DDR_A_MA13

DDR_A_BS#0 DDR_A_BS#1

DDR_A_MA12 DDR_A_MA11 DDR_A_MA10 DDR_A_MA9 DDR_A_MA8 DDR_A_MA7 DDR_A_MA6 DDR_A_MA5 DDR_A_MA4 DDR_A_MA3 DDR_A_MA2 DDR_A_MA1 DDR_A_MA0

M_CLK_DDR#1 M_CLK_DDR1

M_CKE1

M_CS#1

DDR_A_WE#

DDR_A_RAS#

DDR_A_CAS#

M_ODT

DDR_A_DQS6

DDR_A_DQS7

(SSTL-1.8) VREF = .5*VD DQ

DDR_A_BS#2

DDR_A_MA13

5

U12

L2

BA0

L3

BA1

R2

A12

P7

A11

M2

A10/AP

P3

A9

P8

A8

P2

A7

N7

A6

N3

A5

N8

A4

N2

A3

M7

A2

M3

A1

M8

A0

K8

CK

J8

CK

K2

CKE

L8

CS

K3

WE

K7

RAS

L7

CAS

F3

LDM

B3

UDM

K9

ODT

F7

LDQS

E8

LDQS

B7

UDQS

A8

UDQS

J2

VREF

A2

NC#A2

E2

NC#E2

L1

BA2

R3

NC#R3

R7

NC#R7

R8

NC#R8

K4T1G164QE-HCF7_FBGA84

1GB@

U18

L2

BA0

L3

BA1

R2

A12

P7

A11

M2

A10/AP

P3

A9

P8

A8

P2

A7

N7

A6

N3

A5

N8

A4

N2

A3

M7

A2

M3

A1

M8

A0

K8

CK

J8

CK

K2

CKE

L8

CS

K3

WE

K7

RAS

L7

CAS

F3

LDM

B3

UDM

K9

ODT

F7

LDQS

E8

LDQS

B7

UDQS

A8

UDQS

J2

VREF

A2

NC#A2

E2

NC#E2

L1

BA2

R3

NC#R3

R7

NC#R7

R8

NC#R8

K4T1G164QE-HCF7_FBGA84

1GB@

DQ15 DQ14 DQ13 DQ12 DQ11 DQ10

DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0

VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDDQ9

VDDQ10

VDD1 VDD2 VDD3 VDD4 VDD5

VDDL

VSSDL

VSSQ1 VSSQ2 VSSQ3 VSSQ4 VSSQ5 VSSQ6 VSSQ7 VSSQ8 VSSQ9

VSSQ10

VSS1 VSS2 VSS3 VSS4 VSS5

DQ15 DQ14 DQ13 DQ12 DQ11 DQ10

DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0

VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDDQ9

VDDQ10

VDD1 VDD2 VDD3 VDD4 VDD5

VDDL

VSSDL

VSSQ1 VSSQ2 VSSQ3 VSSQ4 VSSQ5 VSSQ6 VSSQ7 VSSQ8 VSSQ9

VSSQ10

VSS1 VSS2 VSS3 VSS4 VSS5

DDR_A_D8

B9

DDR_A_D11

B1

DDR_A_D14

D9

DDR_A_D13

D1

DDR_A_D12

D3

DDR_A_D9

D7

DDR_A_D10

C2

DDR_A_D15

C8

DDR_A_D6

F9

DDR_A_D5

F1

DDR_A_D3

H9

DDR_A_D4

H1

DDR_A_D0

H3

DDR_A_D7

H7

DDR_A_D1

G2

DDR_A_D2

G8

A9 C1 C3 C7 C9 E9 G1 G3 G7 G9

A1 E1 J9 M9 R1

J1 J7

A7 B2 B8 D2 D8 E7 F2 F8 H2 H8

A3 E3 J3 N1 P9

B9 B1 D9 D1 D3 D7 C2 C8 F9 F1 H9 H1 H3 H7 G2 G8

A9 C1 C3 C7 C9 E9 G1 G3 G7 G9

A1 E1 J9 M9 R1

J1 J7

A7 B2 B8 D2 D8 E7 F2 F8 H2 H8

A3 E3 J3 N1 P9

DDR_A_D62 DDR_A_D61 DDR_A_D63 DDR_A_D57 DDR_A_D56 DDR_A_D58 DDR_A_D60 DDR_A_D59 DDR_A_D51 DDR_A_D55 DDR_A_D52 DDR_A_D50 DDR_A_D53 DDR_A_D48 DDR_A_D54 DDR_A_D49

4

Group1

Group0

+1.8V

Group7

Group6

+VRAM_VREFA

3

DDR_A_BS#0 DDR_A_BS#1

DDR_A_MA12 DDR_A_MA11 DDR_A_MA10 DDR_A_MA9 DDR_A_MA8 DDR_A_MA7 DDR_A_MA6 DDR_A_MA5 DDR_A_MA4 DDR_A_MA3 DDR_A_MA2 DDR_A_MA1 DDR_A_MA0

M_CLK_DDR#0 M_CLK_DDR0

M_CKE1

M_CS#1

DDR_A_WE#

DDR_A_RAS#

DDR_A_CAS#

M_ODT

DDR_A_DQS2

DDR_A_DQS3

(SSTL-1.8) VREF = .5*VD DQ

DDR_A_BS#2 DDR_A_BS#2

DDR_A_MA13

Security Classification

U13

L2

BA0

L3

BA1

R2

A12

P7

A11

M2

A10/AP

P3

A9

P8

A8

P2

A7

N7

A6

N3

A5

N8

A4

N2

A3

M7

A2

M3

A1

M8

A0

K8

CK

J8

CK

K2

CKE

L8

CS

K3

WE

K7

RAS

L7

CAS

F3

LDM

B3

UDM

K9

ODT

F7

LDQS

E8

LDQS

B7

UDQS

A8

UDQS

J2

VREF

A2

NC#A2

E2

NC#E2

L1

BA2

R3

NC#R3

R7

NC#R7

R8

NC#R8

K4T1G164QE-HCF7_FBGA84

1GB@

DDR_A_BS#0 DDR_A_BS#1 DDR_A_BS#2

DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13

DDR_A_WE# DDR_A_RAS# DDR_A_CAS#

DQ15 DQ14 DQ13 DQ12 DQ11 DQ10

DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0

VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDDQ9

VDDQ10

VDD1 VDD2 VDD3 VDD4 VDD5

VDDL

VSSDL

VSSQ1 VSSQ2 VSSQ3 VSSQ4 VSSQ5 VSSQ6 VSSQ7 VSSQ8 VSSQ9

VSSQ10

VSS1 VSS2 VSS3 VSS4 VSS5

R97 121_0402_1% R98 121_0402_1% R99 121_0402_1%

R100 121_0402_1% R101 121_0402_1% R102 121_0402_1% R103 121_0402_1% R104 121_0402_1% R105 121_0402_1% R106 121_0402_1% R107 121_0402_1% R108 121_0402_1% R109 121_0402_1% R110 121_0402_1% R111 121_0402_1% R112 121_0402_1% R114 121_0402_1%

R119 121_0402_1% R120 121_0402_1% R121 121_0402_1%

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDEN TIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMA TION IT C ONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPA L ELEC TRONICS, INC.

3

DDR_A_D31

B9

DDR_A_D26

B1

DDR_A_D27

D9

DDR_A_D24

D1

DDR_A_D28

D3

DDR_A_D25

D7

DDR_A_D29

C2

DDR_A_D30

C8

DDR_A_D23

F9

DDR_A_D20

F1

DDR_A_D21

H9

DDR_A_D17

H1

DDR_A_D16

H3

DDR_A_D19

H7

DDR_A_D18

G2

DDR_A_D22

G8

A9 C1 C3 C7 C9 E9 G1 G3 G7 G9

A1 E1 J9 M9 R1

J1 J7

A7 B2 B8 D2 D8 E7 F2 F8 H2 H8

A3 E3 J3 N1 P9

12 12 12

12 12 12 12 12 12 12 12 12 12 12 12 12 12

12 12 12

2008/05/30 2011/05/30

Group3

Group2

+1.8V

+0.9VS

0.01U_0402_16V7K

+1.8V

0.01U_0402_16V7K

Compal Secret Data

Deciphered Date

+VRAM_VREFA

+1.8V

0.1U_0402_16V4Z

1

C101

2

0.1U_0402_16V4Z

1

C107

2

0.1U_0402_16V4Z

1

C111

2

1

2

1

2

1

2

DDR_A_BS#0 DDR_A_BS#1

DDR_A_MA12 DDR_A_MA11 DDR_A_MA10 DDR_A_MA9 DDR_A_MA8 DDR_A_MA7 DDR_A_MA6 DDR_A_MA5 DDR_A_MA4 DDR_A_MA3 DDR_A_MA2 DDR_A_MA1 DDR_A_MA0

M_CLK_DDR#1 M_CLK_DDR1

M_CKE1

M_CS#1

DDR_A_WE#

DDR_A_RAS#

DDR_A_CAS#

M_ODT

DDR_A_DQS5

DDR_A_DQS4

(SSTL-1.8) VREF = .5*VD DQ

DDR_A_MA13

0.1U_0402_16V4Z

1

C102

C103

2

1U_0402_6.3V6K

0.1U_0402_16V4Z

1

C109

C108

2

1U_0402_6.3V6K

0.1U_0402_16V4Z

1

C113

C112

2

1U_0402_6.3V6K

1

U14

L2

BA0

L3

BA1

R2

A12

P7

A11

M2

A10/AP

P3

A9

P8

A8

P2

A7

N7

A6

N3

A5

N8

A4

N2

A3

M7

A2

M3

A1

M8

A0

K8

CK

J8

CK

K2

CKE

L8

CS

K3

WE

K7

RAS

L7

CAS

F3

LDM

B3

UDM

K9

ODT

F7

LDQS

E8

LDQS

B7

UDQS

A8

UDQS

J2

VREF

A2

NC#A2

E2

NC#E2

L1

BA2

R3

NC#R3

R7

NC#R7

R8

NC#R8

K4T1G164QE-HCF7_FBGA84

1GB@

1

C104

2

1

C110

2

1

C114

2

DQ15 DQ14 DQ13 DQ12 DQ11 DQ10

DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0

VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDDQ9

VDDQ10

VDD1 VDD2 VDD3 VDD4 VDD5

VDDL

VSSDL

VSSQ1 VSSQ2 VSSQ3 VSSQ4 VSSQ5 VSSQ6 VSSQ7 VSSQ8 VSSQ9

VSSQ10

VSS1 VSS2 VSS3 VSS4 VSS5

+1.8V

0.1U_0402_16V4Z

1

C105

2

0.01U_0402_16V7K

DDR_A_BS#[0..2]<6,11>

DDR_A_D[0..63]<6,11>

DDR_A_DQS[0..7]<6,11>

DDR_A_MA[0..13]<6,11>

Title

Size Docu ment Number Re v

Date: Sheet

DDR_A_D38

B9

DDR_A_D34

B1

DDR_A_D39

D9

DDR_A_D32

D1

DDR_A_D35

D3

DDR_A_D36

D7

DDR_A_D33

C2

DDR_A_D37

C8

DDR_A_D40

F9

DDR_A_D47

F1

DDR_A_D41

H9

DDR_A_D46

H1

DDR_A_D43

H3

DDR_A_D42

H7

DDR_A_D44

G2

DDR_A_D45

G8

A9 C1 C3 C7 C9 E9 G1 G3 G7 G9

A1 E1 J9 M9 R1

J1 J7

A7 B2 B8 D2 D8 E7 F2 F8 H2 H8

A3 E3 J3 N1 P9

1

C106

2

1U_0402_6.3V6K

0.1U_0402_16V4Z

1

C99

2

12

R113 100_0402_1%

1

2

M_CLK_DDR1

M_CLK_DDR#1

Compal Electronics, Inc.

DDRII-DEVICE DOWN(2/2)

NYU0 0 LA-5301P

1

C100

Group4

Group5

+1.8V

12 28Monday, April 06, 2009

0.2

of

5

4

3

2

1

+3VS_CK505+3VS

1 2

R95 0_0603_5%

D D

C C

1 2

C134 22P_0402_50V8J

1 2

C135 22P_0402_50V8J

B B

CLK_14M_SCH<8>

R128 33_0402_5%

1 2

RF Solution

A A

1

2

+1.5VS_CK610

C130

0.1U_0402_16V4Z

CPU_BSEL2<4,6>

CLK_XTAL_IN

Y1

14.318MHZ_16PF_7A14300083

1 2

CLK_XTAL_OUT

C129

0.1U_0402_16V4Z

+3VS_+1.5VS_CK505

1

2

C131

0.1U_0402_16V4Z

R500 0_0402_5%

R133 10K_0402_5%

R134 10K_0402_5%

1

C674 22P_0402_50V8J

2

R470 0_0603_5%

C132

0.1U_0402_16V4Z

1

2

1 2

+1.5VS

12

+3VS_CK505

1

2

C133

0.1U_0402_16V4Z

CPU_BSEL2_R

CLK_REF

U19

5

VDDREF_3.3

8

VDDCORE_1.5

14

VDDCORE_1.5

15

VDDIO_1.5

22

VDDIO_1.5

23

VDDCORE_1.5

29

VDDCORE_1.5

30

VDDIO_1.5

41

VDDIO_1.5

42

VDDCORE_1.5

46

VDDIO_1.5

37

FSB_L

9

FSC_L

4

X1

3

X2

10

TEST_MODE

11

TEST_SEL

6

REF

7

GNDREF

18

GNDDOT

19

GNDLCD

25

GNDSRC

33

GNDSRC

40

GNDCPU

45

GNDCPU

49

THERMAL_PAD

ICS9UMS9610BKLF-T_MLF48_6X6

SCLK_3.3

SDATA_3.3

CPU_STOP#

CPUC0_LPR

CPUT0_LPR

CPUC1_LPR

CPUT1_LPR

CPUC2_LPR

CPUT2_LPR

*CR#0 *CR#1 *CR#2

SRCC2_LPR

SRCT2_LPR

SRCC1_LPR

SRCT1_LPR

SRCC0_LPR

SRCT0_LPR

LCD100C_LPR

LCD100T_LPR

DOT96C_LPR

DOT96T_LPR

CLKPWRGD/PD#

SMB_CLK

12

SMB_DAT

13

1

CLK_CPU_BCLK#

47

CLK_CPU_BCLK

48

CLK_MCH_BCLK#

43

CLK_MCH_BCLK

44

38

39

24 28

T68 TPC24

36

34

35

31

32

26

27

20

21

16

17

CLK_ENABLE#_R

2

Q4

2N7002T-7_SOT523

L5

FBMA-L11-160808-121LMT_0603

+1.5VS

T2 TPC24

T3 TPC24

T69 T PC24

T70 T PC24

1 2

R129 10K_0402_5%

1 2

R471 1K_0402_5%

2

3 1

+3VS_+1.5VS_CK505

1 2

C124

10U_0603_6.3V6M

SMB_CLK <8>

SMB_DAT <8>

H_STP_CPU# <8>

CLK_CPU_BCLK# <4>

CLK_CPU_BCLK <4>

CLK_MCH_BCLK# <6>

CLK_MCH_BCLK <6>

CLK_PCIE_WLAN# <14>

CLK_PCIE_WLAN <14>

CLK_PCIE_ICH# <7>

CLK_PCIE_ICH <7>

MCH_SS CDREFCLK# <8>

MCH_SS CDREFCLK <8>

CLK_MCH_DREFCLK# <8>

CLK_MCH_DREFCLK <8>

+3VS

CK_PW RGD <18>

1

C125

0.1U_0402_16V4Z

2

CLK_ENABLE# <25>

1

C126

0.1U_0402_16V4Z

2

1

C127

0.1U_0402_16V4Z

2

RF Solution

C128

0.1U_0402_16V4Z

1

2

12

C673 47P_0402_50V8J

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDEN TIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMA TION IT C ONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPA L ELEC TRONICS, INC.

3

2008/05/30 2011/05/30

Compal Secret Data

Deciphered Date

Title

Size Docu ment Number Re v

2

Date: Sheet

Compal Electronics, Inc.

Clock Generator CK610

NYU0 0 LA-5301P

13 28Monday, April 06, 2009

1

0.2

of

5

D D

4

3

+3VALW +3VS

2

1

To IO BOARD

C414 10U_0603_6.3V6M

T71TPC24

T48TPC24

VS

T75TPC24 T76TPC24

CLK_PCIE_WLAN# CLK_PCIE_WLAN

PCIE_WLANTX_IRX_C_N2 PCIE_WLANTX_IRX_C_P2

PCIE_ITX_C_WLANRX_N2 PCIE_ITX_C_WLANRX_P2

BT_COEX1 BT_COEX2 BT_COEX3 WL_OFF# PLT_RST# LED_WLAN# WLAN_PWR EC_T X EC_RX ON/OFF_EC# FSTCHG EC_ON IREF CHGVADJ

MAINPWON ADP_I

3G_PWR

EC_SMB_CK2 EC_SMB_DA2

C C

B B

CLK_PCIE_WLAN#<13>

CLK_PCIE_WLAN<13>

PCIE_WLANTX_IRX_C_N2<7>

PCIE_WLANTX_IRX_C_P2<7>

PCIE_ITX_C_WLANRX_N2<7>

PCIE_ITX_C_WLANRX_P2<7>

BT_COEX1<20> BT_COEX2<20> BT_COEX3<20>

WL_OFF#<18>

PLT_RST#<8,17,18,19> LED_WLAN#<20> WLAN_PWR<18>

EC_TX<18> EC_RX<18>

ON/OFF_EC#<18>

FSTCHG<18>

EC_ON<18>

IREF<18>

CHGVADJ<18>

MAINPWON<26>

ADP_I<18>

3G_PWR<18> 3G_RST#<18>

SIM_DET<18>

EC_SMB_CK2<4,18,20> EC_SMB_DA2<4,18,20>

1

2

JP23

1 3 5 7

9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79

HRS_D F30FB-80DS-0P4V(81)

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79

GND181GND2

2

4

6

8

10

12

14

16

18

20

22

24

26

28

30

32

34

36

38

40

42

44

46

48

50

52

54

56

58

60

62

64

66

68

70

72

74

76

78

80

82

USB20_N3 USB20_P3

3G_EN# LED_WWAN#

MINSD_CLK MINSD_DATA3 MINSD_DATA2 MINSD_DATA1 MINSD_DATA0 MINSD_CMD MINSD_CD# MINSD_WP MINSD_PWR#

ACIN ACOFF BATT_OVP BATT_TEMPA CPU_TMP_SENSE

USB20_P2 USB20_N2

USB_EN# LID_SW ITCH# EC_SMB_CK1 EC_SMB_DA1

1

10U_0603_6.3V6M

2

C415

USB20_N3 <8> USB20_P3 <8>

3G_EN# <18>

LED_WWAN# <20>

MINSD_CLK <7> MINSD_DATA3 <7> MINSD_DATA2 <7> MINSD_DATA1 <7> MINSD_DATA0 <7>

MINSD_CMD <7>

MINSD_CD# <7>

MINSD_WP <7>

MINSD_PWR# <7>

ACIN <18> ACOFF <18> BATT_OVP < 18> BATT_TEMPA <18> CPU_TMP_SENSE <25>

USB20_P2 <8>

USB20_N2 <8>

USB_EN# <15,18>

LID_SW ITCH# <18>

EC_SMB_CK1 <18,20> EC_SMB_DA1 <18,20>

+5VALW

+RTCVCC

3G

USB RIGHT

3

JP9

6

8

6

G2

5

7

5

G1

4

3

2

1

ACES_87213-0600G

2008/05/30 2011/05/30

Compal Secret Data

Deciphered Date

2

Title

Size Docu ment Number Re v

Custom

Date: Sheet

Compal Electronics, Inc.

LVDS/FUN_B/PWR_B/USB_B CONN

NYU00 LA-5301P

14 28Monday, Apr il 06, 2009

1

of

0.2

B+ B++

PL11 FBMA-L11-321611-121LMA30T_1206

A A

1 2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDEN TIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMA TION IT C ONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPA L ELEC TRONICS, INC.

A

B

C

D

E

USB/B Connector(Left)

D3

@

+LCDVDD

12

R188 470_0402_5%

1 1

2 2

3 3

Q7A

2N7002DWH_SOT363-6

GMCH_LVDDEN<7>

B+

+5VS

61

@

R603 0_0805_5%

R310 0_0805_5%

2

Q7B 2N7002DWH_SOT363-6

+3VS_LCD

INVT_PW M<7>

BKOFF#<18>

+BL

12

1

12

2

EDID_DAT_LCD<7>

LCD POWER CIRCUIT

+5VALW

12

R190 100K_0402_5%

+5VA_GATE_LCD

34

5

LCD Panel Connector

+LCDVDD_R

+3VS_LCD

EDID_CLK_LCD<7>

LVDSA0-<7>

LVDSA0+<7>

LVDSA1-<7>

LVDSA1+<7>

LVDSA2-<7>

LVDSA2+<7>

LVDSAC-<7> LVDSAC+<7> LVDS_EN

1 2

R200 10K_0402_5%

1 2

R193 100K_0402_5%

C666 1000P_0402_50V7K

2

C146 1000P_0402_50V7K

1

JP3

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

JAE_FI-G30S-VF25

+3VS

W=60mils

L6

Q8

S

AO3413_SOT23

G

2

D

1 3

W=60mils

C148

0.1U_0402_16V4Z

L7

FBMA-L11-160808-121LMT_0603

+3VS

37

G7

36

G6

35

G5

34

G4

33

G3

32

G2

31

G1

KC FBM-L11-201209-221LMAT_0805

+LCDVDD

1 2

1

C149

4.7U_0603_6.3V6K

2

1 2

1

C151

0.1U_0402_16V4Z

2

+LCDVDD_R

1

2

+3VS_LCD

1

C150

0.1U_0402_16V4Z

2

USB_EN#<14,18>

Add another one

R543 0_0603_5%

1 2

USB20_N0<8>

USB20_P0<8 >

USB20_N1<8>

USB20_P1<8 >

+5VALW_USB+5VALW

USB_EN#

PJSOT05CH_SOT23-3

1

D4

@

PJSOT05CH_SOT23-3

C678

0.1U_0402_16V4Z

1 2

150U_B2_6.3VM_R35M

C153

2

3

2

3

2A

U20

1

GND

2

VIN VIN3VOUT

4

EN

RT9715BGS_SO8

Close to JP5

+USB_VCCC

1

+

2

+USB_VCCC

8

VOUT

7

VOUT

6 5

FLG

1

2

C154

0.1U_0402_16V4Z

JP1

1

VCC

2

D-

3

D+

4

GND

TYCO_2009104-1

JP2

1

VCC

2

D-

3

D+

4

GND

TYCO_2009104-1

USB (LEFT)

1

C155 1000P_0402_50V7K

2

GND1

GND2

GND3

GND4

GND1

GND2

GND3

GND4

5

6

7

8

5

6

7

8

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDEN TIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMA TION IT C ONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPA L ELEC TRONICS, INC.

C

2008/05/30 2011/05/30

Compal Secret Data

Deciphered Date

Title

Size Docu ment Number Re v

Custom

D

Date: Sheet

Compal Electronics, Inc.

LCD/USB

NYU00 LA-5301P

E

15 28Monday, Apr il 06, 2009

0.2

of

A

+5VS

C208

4.7U_0805_10V4Z

0.1U_0402_16V4Z

1 2

+5VS

1 1

2 2

3 3

R228 10K_0402_5%

MIC MIC1_R

+3VS

SENSE A

4 4

SENSE B

Codec Regulator

C209

LDO_SD#

APL5151-475BC-TRG_SOT23-5

+MIC1_VREFO_L

12

R324

2.2K_0402_5%

1 2

C294 4.7U _0805_10V4Z

1 2

C295 4.7U _0805_10V4Z

C296

@

100P_0402_50V8J

1 2

R574 4.7K_0402_5%@

1 2

R575 4.7K_0402_5%@

ImpedanceSense Pin

39.2K

20K

10K

5.1K

39.2K

20K

10K

5.1K

A

U27

1

VIN

VOUT

2

GND

3

SHDN#

1

2

DMIC_DATA

DMIC_CLK

Codec Signals

PORT-A (PIN 32, 33)

PORT-B (PIN 21, 22)

PORT-C (PIN 23, 24)

PORT-D (PIN 48)

PORT-E (PIN 14, 15)

PORT-F (PIN 16, 17)

PORT-G (PIN 20)

PORT-H (PIN 47)

+5V_VDDA_HD

5

4

BP

LDO_BP

0.22U_0402_6.3V6K

+3VS

FBMA-L11-160808-800LMT_0603

EC_EAPD_R#<18>

MIC1_L

1

@

C297 100P_0402_50V8J

2

+5V_VDDA_HD

4.75v

@

C210

C212

4.7U_0805_10V4Z

12

L26

1 2

@

C219 100P_0402_50V8J

R502 0_0402_5%

HDA_RST_AUDIO#<8,17>

MONO_IN

R601 1M_0402_5%

MIC MIC_COM

1 2

R555 453K_0402_1%

1 2

+3VS_HD

R602 100K_0402_5%

B

10U_0805_10V4Z

1

2

DMIC_DATA<20>

DMIC_CLK<20>

12

C551 0.1U_0402_16V4Z

C231 100P_0402_50V8J@

20mil

1

C220

C221

2

0.1U_0402_16V4Z

MIC1_L MIC1_R

EC_EAPD_R#_HD

1 2

SENSE_A

1 2

C232 2.2U_0402_6.3V4Z

0.6V

COM_REF

12

1

2

B

+5VS_HDA

+3VS_HD

0.1U_0402_16V4Z

1

C222

2

DMIC_DATA

DMIC_CLK

CBP

9

1

U28

DVDD

PVDD139PVDD2

DVDD_IO

23

LINE1_L

24

LINE1_R

14

LINE2_L

15

LINE2_R

21

MIC1_L

22

MIC1_R

16

MIC2_L

17

MIC2_R

2

GPIO0/DMIC_D ATA

3

GPIO1/DMIC_C LK

4

PD#

11

RESET#

12

PCBEEP

13

SENSE A

18

SENSE B

36

CBP

35

CBN

31

CPVREF

43

PVSS2

42

PVSS1

7

DVSS

DGND AGND

DGND To AGND Bypass

EAPD/SPDIFO2

MIC1_VREFO_R

MIC1_VREFO_L

EXPOSE_PAD

ALC269Q-GR_QFN48_7X7

49

1 2

R243 0_0603_5%

1 2

R244 0_0603_5%

1 2

R245 0_0603_5%@

1 2

R597 0_0603_5%@

DGND AGND

+3VS_HD

12

U38

1

IN+

5

VCC+

2

GND

3

IN-

LMV331IDCKRG4_SC70-5

0.1U_0402_16V4Z

HP_MIC_SENSE_C0

OUT

C665

4

COM_OUT

2

B

E

+HD_AVDD

46

AVDD125AVDD2

SPK_OUT_L+

SPK_OUT_L-

SPK_OUT_R+

SPK_OUT_R-

HP_OUT_L HP_OUT_R

SYNC

BCLK

SDATA_OUT

SDATA_IN

SPDIFO

MONO_OUT

MIC2_VREFO

VREF

JDREF

CPVEE

AVSS1 AVSS2

100P_0402_50V8J

1

C224

@

2

38

0.1U_0402_16V4Z

SPKL+

40

SPKL-

41

SPKR+

45

SPKR-

44

HP_L

32

HP_R

33

10

HDA_BITCLK_AUDIO

6

5

AZ_SDIN0_HD_R

8

47

48

20

10mil

29

10mil

30 28

10mil

27

19

34

26 37

C225

1

2

1

2

CPVEE

C215

C217

C

W=40mil

10U_0805_10V4Z

W=40mil

10U_0805_10V4Z

0.1U_0402_16V4Z

1

C226

2

1 2

R237 33_0402_5%

T74 TPC24

AVREFCBN

JDREF

12

1

R238 20K_0402_1%

2

C235

2.2U_0 402_6.3V4Z

1

C216

0.1U_0402_16V4Z

2

1

C218

0.1U_0402_16V4Z

2

40mil

1

C227

2

10U_0805_10V4Z

+MIC1_VREFO_R +MIC1_VREFO_L

1

@

C233 10U_0603_6.3V6M

2

1 2

R321 0_0603_5%

FBMA-L11-160808-800LMT_0603

+5V_VDDA_HD

L27

12

R240 22_0402_5%

1

C234

0.1U_0402_16V4Z

2

+5VS

1 2

C236 10P_0402_50V8J

HDA_SYNC_AUDIO <8,17>

HDA_BITCLK_AUDIO <8,17>

HDA_SDOUT_AUDIO <8,17>

HDA_SDIN0 <8>

HeadPhone/MIC JACK

C667

0.1U_0402_16V4Z

1 2

R600 100K_0402_5%

MIC_SENSE

1 2

R241 20K_0402_1%

C

2

B

E

3 1

C

Q38 MMBT3904WH_ SOT323-3

3 1

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDEN TIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMA TION IT C ONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPA L ELEC TRONICS, INC.

Q39

MMBT3904WH_ SOT323-3

R239

39.2K_0402_1%

Issued Date

C

SENSE_AHP_SENSE

12

2008/05/30 2011/05/30

MIC MIC_1

HP_R

HP_L

HPR_R

1 2

R248 75_0402_1%

HPL_R

1 2

R249 75_0402_1%

Compal Secret Data

Deciphered Date

D

Beep Circuit

EC Beep

BEEP#<18>

SPKR<8>

Speaker Conn.

HP_MIC_SENSE_C0

1 2

L34 BLM15AG121SN1D_L0402_2P

1 2

L32 BLM15AG121SN1D_L0402_2P

1 2

L33 BLM15AG121SN1D_L0402_2P

@

C240 10P_0402_50V8J

D

1

2

@

C239 10P_0402_50V8J

@

D16 PJSOT05CH_SOT23-3

E

+3VS +5V_VDDA_HD

12

2 1

1

2

1

C238

0.1U_0402_16V4Z

R468 100K_0402_5%

C677

@

1000P_0402_50V7K

1 2

JACK-AGND

12

C

2

B

E

3 1

12

@

R231 10K_0402_5%

D14 PJSOT05CH_SOT23-3

3

SPK_L1 SPK_L2 SPK_R1 SPK_R2

3

D15 PJSOT05CH_SOT23-3

JP4

1 8 4 7 3 6 5 2

LINGY_CX -31930-Q

1

J1

1

JUMP_43X39

2

E

R225 10K_0402_5%

C211 1U_0402_6.3V6K

1 2

C214 1U_0402_6.3V6K

CH751H-40PT_SOD323-2

SPKL+

L28 0_0603_5%

1 2

SPKL-

L29 0_0603_5%

1 2

SPKR+

L30 0_0603_5%

1 2

SPKR-

L31 0_0603_5%

1 2

C237

0.1U_0402_16V4Z

HPR

HPL

1

2

3

1

Title

Size Docu ment Number Re v

Custom

NYU00 LA-5301P

Date: Sheet

R227 560_0402_5%

1 2

R229 560_0402_5%

D13

+MIC1_VREFO_R +MIC1_VREFO_L

+5V_VDDA_HD

12

2

3

1

@

D17 PJSOT05CH_SOT23-3

Compal Electronics, Inc.

HDA-ALC269Q-GR

R226 20K_0402_1%

C213 1U_0402_6.3V6K

MONO_IN

1 2

R230

2.4K_0402_5%

Q9 MMBT3904WH_S OT323-3

JP6

1

2

3

5

3

GND

4

6

4

GND

ACES_87213-0400G

1

@

J2

1

JUMP_43X39

2

16 28Monday, Apr il 06, 2009

of

0.2

5

4

3

2

1

+1.8VS_H DMI_PVDD

C157 0.1U_0402_16V7K C159 0.1U_0402_16V7K C158 0.1U_0402_16V7K C160 0.1U_0402_16V7K C161 0.1U_0402_16V7K C162 0.1U_0402_16V7K C163 0.1U_0402_16V7K C164 0.1U_0402_16V7K

1 2

R522 1K_0402_1%

@

C165 0.1U_0402_16V7K C166 0.1U_0402_16V7K

1 2 1 2

1 2

R507 1K_0402_1%

HDMI_DDC_DAT HDMI_DDC_CLK

HDMI_A1

12

R523 1K_0402_1%

SDVO_INT_0 SDVO_INT#_0

SDVO_RED_0 SDVO_RED#_0

SDVO_GREEN_0 SDVO_GREEN#_0

SDVO_BLUE_0 SDVO_BLUE#_0

SDVO_CLK_0 SDVO_CLK#_0

HDMI_EXT_RES

D D

SDVO_INT<7> SDVO_INT#<7>

SDVO_RED<7> SDVO_RED#<7>

SDVO_GREEN<7> SDVO_GREEN#<7>

SDVO_BLUE<7> SDVO_BLUE#<7>

SDVO_CLK<7> SDVO_CLK#<7>

PLT_RST#<8,14,18,19> SDVO_CTRLDATA<7> SDVO_CTRLCLK<7>

C C

+3VS_HDMI

+1.8VS_HDMI

U23

46

SDI+

47

SDI-

51

SDR+

52

SDR-

54

SDG+

55

SDG-

57

SDB+

58

SDB-

60

SDC+

61

SDC-

49

EXT_RES

1

RESET#

6

SDSDA

7

SDSCL

12

SDADDC

11

SCLDDC

14

SCLROM

13

SDAROM

8

A1

44

TEST

48

VCC2VCC9VCC38VCC43VCC

Red

Green

Blue

Clock

I2C fr om SDVO

I2C to DDC/ HDCP

I2C to Config. PROM

32

AVCC1.821AVCC1.827AVCC3.3

Serial Input Interface

SiI1392 Tx 64-Pin QFN

GND5GND10GND41GND45SGND53SGND

+3VS+3VS

R530 300_0402_1%

R532

1K_0402_1%

1

2

5.6K_0402_5%

12

R520

+SDVO_CLK

C586 1U_0402_6.3V6K

1

2

C587

0.1U_0402_16V4Z

B B

12

R531 300_0402_1%

R533 1K_0402_1%

12

C588

0.1U_0402_16V4Z

R521

5.6K_0402_5%

SDVO_CTRLDATA

SDVO_CTRLCLK

+SDVO_DAT

1

2

C589 1U_0402_6.3V6K

1

2

HDMI_PWR<18>

+1.8VS_HDMI+3VS_HD MI

31

PVCC117PVCC2

59

33

OTPVCC

AGND18AGND24AGND

+1.8VS_HDMI_SVCC

64

37

56

SVCC50SVCC

OVCC

HDAVCC

TX2+

TX2-

TX1+

TX1-

HDMI/DV I

TX0+

Interface

TX0-

TXC+

TXC-

HTPLG

EXT_SWING

HDABCLK

HDARST#

HDASDI

HDASYNC

SPDIF/HDASDO

LSCL

LSDA

LINT#

SPGND63EPAD

30

65

+5VS

2

+3VS_HDMI

62

SPVCC

HDMI_TX2+

29

HDMI_TX2-

28

HDMI_TX1+

26

HDMI_TX1-

25

HDMI_TX0+

23

HDMI_TX0-

22

HDMI_TXC+

20

HDMI_TXC-

19

42

EXT_SWIN G

16

39

35

HDA_SDIN1_R

36

40

34

DCEN

4

PREEMP

3

15

SII1392CNU_QFN64_9X9

12

R545 100K_0402_5%

HDMI_PWR_M

Q27

2N7002T-7_SOT523

3 1

R560 0_0402_5%

1 2

+1.8V_GATE_HDMIHDMI_PWR_M

1 2

R505 1K_0402_5%

1 2

R506 680_0402_5%

1 2

R509 33_0402_5%

1 2

C596

C646

12

2

1

1000P_0402_50V7K

2

1

1000P_0402_50V7K

R512 4.7K_0402_5%

R514 0_0402_5%

HDMI_HP_DET1HDMI_HP_DET

+3VS

G

+1.8VS

G

+1.8VS_HDMI

+3VS_HDMI

1

C595

0.1U_0402_16V4Z

2

S

D

Q26

1 3

AO3413_SOT23

1

C597

0.1U_0402_16V4Z

2

S

D

Q28

1 3

AO3413_SOT23

HDA_BITCLK_AUDIO <8,16>

HDA_R ST_AUDIO# <8,16>

HDA_SDIN1 <8>

HDA_SYNC_AUDIO <8,16>

HDA_SDOUT_AUDIO <8,16>

+3VS_HDMIS

+1.8V_HDMIS

HDMI_TX2+

HDMI_TX2-

HDMI_TX1+

HDMI_TX1-

HDMI_TX0+

HDMI_TX0-

HDMI_TXC+

HDMI_TXC-

R510

HDMI_TX0+

300_0402_1%

R513

HDMI_TX1+

300_0402_1%

R515

HDMI_TX2+

300_0402_1%

R516

HDMI_TXC+

300_0402_1%

HDA_BITCLK_AUDIO

Change P/N to TDK SM070001700

L39

1

2

ACM2012H-900-2P-T00_4P

L40

1

2

ACM2012H-900-2P-T00_4P

L41

1

2

ACM2012H-900-2P-T00_4P

L42

1

2

ACM2012H-900-2P-T00_4P

Locate these source termination R,C to SiI1392

1 2

R519 10_0402_5%

EMI Locate R,C to SiI1392 Pin39

HDMI_TX2+_C

4

HDMI_TX2-_C

3

HDMI_TX1+_C

4

HDMI_TX1-_C

3

HDMI_TX0+_C

4

HDMI_TX0-_C HDMI_TX2+_C

3

HDMI_TXC+_C

4

HDMI_TXC-_C

3

C554

HDMI_TX0-

0.1U_0402_16V7K

C555

HDMI_TX1-

0.1U_0402_16V7K

C556

HDMI_TX2-

0.1U_0402_16V7K

C557

HDMI_TXC-

0.1U_0402_16V7K

1 2

C558 22P_0402_50V8J

TPC24

+5VS_HDMI_DDC

HDMI_HP_DET1<18>

T24

HDMI_TX2-_C HDMI_TX1+_C

HDMI_TX1-_C HDMI_TX0+_C

HDMI_TX0-_C HDMI_TXC+_C

HDMI_TXC-_C

HDMI_CEC

HDMI_DDC_CLK HDMI_DDC_DAT

HDMI_HP_DET1

R517

1.8K_0402_5%

D24

+5VS +5VS_HDMI_DDC

NC

3

1

2

CH491DPT_SOT23-3

12

R604 10K_0402_5%

+5VS_HDMI_DDC

12

1

2

HDMI CONN.

JP5

1

D2+

2

D2_shield

3

D2-

4

D1+

5

D1_shield

6

D1-

7

D0+

8

D0_shield

9

D0-

10

CK+

11

CK_shield

12

CK-

13

CEC

14

Reserved

15

SCL

16

SDA

17

DDC/CEC_GND

18

+5V

19

HP_DET

TAITW_PDVBTD-19FLBS4NN4N

R518

1.8K_0402_5%

HDMI_DDC_CLK

HDMI_DDC_DAT

C553

0.1U_0402_16V4Z

23

GND

22

GND

21

GND

20

GND

+1.8V_HDMIS +1.8VS_HDMI

L43 FBMA-L11-160808-800LMT_0603

A A

L44

FBMA-L11-160808-800LMT_0603

+1.8V_HDMIS

C568 10U_0603_6.3V6M

10U_0603_6.3V6M

+1.8VS_H DMI_PVDD

5

0.1U_0402_16V4Z

12

1

C559

2

12

1

2

C569

0.1U_0402_16V4Z

C560

0.1U_0402_16V4Z

C570

0.1U_0402_16V4Z

1

2

C561

1

2

C562

0.1U_0402_16V4Z

1

2

1

2

C564

0.1U_0402_16V4Z

1

2

C563

0.1U_0402_16V4Z

C565

0.1U_0402_16V4Z

+1.8V_HDMIS

L46

FBMA-L11-160808-800LMT_0603

C575 10U_0603_6.3V6M

C566

0.1U_0402_16V4Z

1

2

C567

0.1U_0402_16V4Z

+1.8VS_HDMI_SVCC

12

1

2

C576

0.1U_0402_16V4Z

4

+3VS_HDMIS +3VS_H DMI

L45

1

FBMA-L11-160808-800LMT_0603

2

C577

0.1U_0402_16V4Z

1

2

C571 10U_0603_6.3V6M

C573

0.1U_0402_16V4Z

12

1

2

C572

0.1U_0402_16V4Z

1

2

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDEN TIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMA TION IT C ONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPA L ELEC TRONICS, INC.

2

Issued Date

1

C574

0.1U_0402_16V4Z

2

3

2008/05/30 2011/05/30

Compal Secret Data

Deciphered Date

Title

Size Docu ment Number Re v

Custom

2

Date: Sheet

Compal Electronics, Inc.

SDVO TO HDMI

NYU00 LA-5301P

1

17 28Monday, Apr il 06, 2009

0.2

of

A

+3VALW +3VALW_EC

1 2

R250 0_0603_5%

1 1

H_INIT#<4,6>

Q11A 2N7002DWH_SOT363-6

2 2

H_A20M#<4>

Q10A 2N7002DWH_SOT363-6

CLK_PCI_LPC

@

R458 10_0402_5%

@

C539 10P_0402_50V8J

3 3

4 4

+3VALW_EC +EC_AVCC

R253 10K_0402_5%

61

2

R259 10K_0402_5%

61

2

12

+5VALW

1 2

R273 4.7K_0402_5%

1 2

R274 4.7K_0402_5%

+3VS

1 2

R275 2.2K_0402_5%

1 2

R276 2.2K_0402_5%

A

L36 FBM-11-160808-601-T_0603

1 2

C243

0.1U_0402_16V4Z

+3VALW_EC

R254

12

EC_INIT#

5

+3VALW_EC

GATEA20

5

EC_SMI#<8 >

USB_EN#<14,15>

3G_RST#<14>

SIM_DET<14>

PLT_RST#<8,14,17,19>

EC_SMB_CK1

EC_SMB_DA1

EC_SMB_CK2

EC_SMB_DA2

47K_0402_5%

R255 47K_0402_5%

R260

12

47K_0402_5%

PM_SLPRDY# EC_RSMRST# PM_SLPMOD E EC_SMI# USB_EN# USB_EN#_R

PLT_RST#

PM_RSTWARN_R

1 2

34

Q11B 2N7002DWH_SOT363-6

1 2

34

Q10B 2N7002DWH_SOT363-6

PM_SLPRDY#<7> PM_SLPMODE<7>

PM_RSTWARN_R<8> 3G_EN# <14>

2

1

+3VALW_EC

R499 100K_0402_5%

1

C244

4.7U_0603_6.3V6K

2

12

2

C249

0.1U_0402_16V4Z

1

1 2

PM_1.8V_PWRGD<23>

R266 0_0402_5% R268 0_0402_5%

R584 0_0402_5%

R271 100_0402_1%

R270 0_0402_5%

ON/OFF_EC#<14>

LED#_AC<20> SLEEP_LED#<20>

LPC_FRAME#<7>

CLK_PCI_LPC<7>

PLT_RST#

VGATE<25>

EC_SMB_CK1<14,20> EC_SMB_DA1<14,20>

EC_SMB_CK2<4,14,20> EC_SMB_DA2<4,14,20>

EC_TX<14> EC_RX<14>

B

C245

0.1U_0402_16V4Z

SIRQ<7>

LPC_AD3<7> LPC_AD2<7> LPC_AD1<7> LPC_AD0<7>

EC_SCI#<8>

1 2 1 2

1 2

1

2

GATEA20

T59TPC24

SIRQ LPC_FRAME# LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0

CLK_PCI_LPC PLT_RST# EC_RST# EC_SCI#

T60TPC24

KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7 KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15 VGATE PM_1.8V_PWRGD

EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DA2

PM_SLPRDY_R# PM_SLPMODE_R#

PLT_RST#_R

T79TPC24

PM_RSTWARN EC_INIT# EC_T X EC_RX ON/OFF_EC#

XCLKI XCLKO

@

R272 20M_0603_5%

XCLKI XCLKO

1 2

32.768KHZ_12.5P_1TJE125DP1A000M

1 2

1

C253 15P_0402_50V8J

2

B

+3VALW_EC

C247

0.1U_0402_16V4Z

1

2

C246

0.1U_0402_16V4Z

X2

1

C248

4.7U_0603_6.3V6K

2

U35

M2

GA20/GPIO00

L2

KBRST#/GPIO01

M3

SERIRQ

K4

LFRAME#

N3

LAD3

M4

LAD2

K5

LAD1

N4

LPC & MISC

LAD0

N5

PCICLK

M5

PCIRST#/GPIO05

K13

ECRST#

N6

SCI#/GPIO0E

M6

CLKRUN#/GPIO1D

D9

KSI0/GPIO30

E12

KSI1/GPIO31

E13

KSI2/GPIO32

D12

KSI3/GPIO33

D13

KSI4/GPIO34

C12

KSI5/GPIO35

C13

KSI6/GPIO36

D10

KSI7/GPIO37

J13

KSO0/GPIO20

J12

KSO1/GPIO21

H12

KSO2/GPIO22

H13

KSO3/GPIO23

H10

KSO4/GPIO24

H9

KSO5/GPIO25

G9

KSO6/GPIO26

G10

KSO7/GPIO27

G13

KSO8/GPIO28

G12

KSO9/GPIO29

F13

KSO10/GPIO2A

F12

KSO11/GPIO2B

F10

KSO12/GPIO2C

F9

KSO13/GPIO2D

E10

KSO14/GPIO2E

E9

KSO15/GPIO2F

E8

KSO16/GPIO48

D8

KSO17/GPIO49

A8

SCL1/GPIO44

A7

SDA1/GPIO45

B8

SCL2/GPIO46

A6

SDA2/GPIO47

J5

PM_SLP_S3#/GPIO04

N9

PM_SLP_S5#/GPIO07

L13

EC_SMI#/GPIO0 8

K6

LID_SW# /GPIO0A

N7

SUSP#/GPIO0B

M7

PBTN_OUT#/GPIO0C

N8

EC_PME#/GP IO0D

K8

EC_THERM#/GPIO11

M11

FAN_SPEED1/FANFB1/GPIO14

N11

FANFB2/GPIO15

K10

EC_TX/GPIO16

K9

EC_RX/GPIO17

N12

ON_OFF/GPIO18

M13

PWR_LE D#/GPIO19

L12

NUMLED#/GPIO1A

J1

XCLKI

K1

XCLKO

KB926BFC0_LFBGA128

1

C254 15P_0402_50V8J

2

C

+3VALW_EC

KSO1

+EC_AVCC

B11

K12

M12

J6

J4

VCC

AVCC

INVT_PW M/PWM0/GPIO0F

BEEP#/PWM1/GPIO10

ACOFF/FANPWM2/GPIO13

PWM Output

BATT_TEMP/AD0/GPIO38

BATT_OVP/AD1/GPIO39

AD Input

SELIO2#/AD5/GP IO43

DAC_BRIG/D A0/GPIO3C

EN_DFAN1/DA1/GPIO3D

DA Output

TP_CLK/PSCLK3/GPIO4E

TP_DATA/PSDAT3/GPIO4F

SPI Device Interface

SPI Flash ROM

CIR_RLC_TX/GPIO41

FSTCHG/SEL IO#/GPIO50

BATT_CHGI_ LED#/GPIO52

CAPS_LED#/GPIO53

GPIO

BATT_LOW_LED#/GPIO54

SUSP_LED#/GPIO55

VR_ON/XCLK32K/GPIO57

EC_RSMRST#/GPXO03

EC_LID_OUT#/GPXO04

ICH_PWROK/GPXO07

GPO

GPIO

PM_SLP_S4#/GPXID1

GPI

GND

AGND

GND

J9

G2

J10

A11

N13

FANPWM1/GPIO12

ADP_I/AD2/GPIO3A

AD3/GPIO3B

AD4/GPIO42

IREF/DA2/GPIO3 E

DA3/GPIO3F

PSCLK1/GPIO4 A PSDAT1/GPIO4B PSCLK2/GPIO4 C

PSDAT2/GPIO4D

SDICS#/GPXOA00 SDICLK/GPXOA01

SDIDO/GPXOA02

SDIDI/GPXID0

SPIDI/RD#

SPIDO/WR#

SPICLK/GPIO58

CIR_RX/GPIO40

SYSON/GPIO56

AC_IN/GPIO59

EC_ON/GPXO05

EC_SWI#/GPXO06

BKOFF#/GPXO08

WL_OFF#/GPXO09

ENBKL/GPXID2

Int. K/B Matrix

SM Bus

J7

K7

VCC

PS2 Inte rface

J8

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDEN TIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMA TION IT C ONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPA L ELEC TRONICS, INC.

C

1 2

R497 47K_0402_5%

KSO2

1 2

R498 47K_0402_5%

M9

BEEP#

M8

PM_1.05_PWRGD

M10

ACOFF

N10

BATT_TEMPA

B13

BATT_OVP

A13

ADP_I_R

B12

PM_1.5V_PWRGD_R

A12

LS_INT#_R

E7

GSENSOR_INT_R

D7

B10

PM_EN_1.5_1.05_R

A9

IREF

A10

CHGVADJ

B9

GSENSOR_INT2_R

D6 E6 E5 D5

TP_CLK

A5

TP_DATA

B5

CK_PW RGD_R

B1 A1 C1

LID_SW ITCH#

C2

K2 J2

SPI_CLK

M1 N2

SPICS#

BT_PWR

B6

HDMI_HP_D ET_R

B7

FSTCHG

B4 A4

CAPSLED#_R

B3

BATT_CHG_LOW_LED#

A3 A2

SYSON

B2

VR_ON

H5

ACIN

N1

EC_RSMRST#_R

D4

EC_LID_OUT#_R

D1

EC_ON

D2 E2

ICH_POK

E4

BKOFF#

E1

WL_OFF#

F4

CAM_PWR

F2

GPXO10 GPXO11

GPXID3 GPXID4 GPXID5 GPXID6 GPXID7

V18R

2008/05/30 2011/05/30

3G_EN#

F1

PM_RSTRDY#

F5

ENBKL

G1

EC_EAPD_R#_EC EC_EAPD_R#

G5

EC_THERM#_R

H1

SUSP#

G4

PBTN_OUT#_R

H4

RADIO_OFF#_R RADIO_OFF#

H2

V18R

L1

1

2

Compal Secret Data

TP_CLK

TP_DATA

BATT_OVP

BATT_TEMPA

ACIN

T85 TPC24

BEEP# <16>

PM_1.05_PWRGD <23,25> AC OFF <14>

1 2 1 2 1 2 1 2

T86 TPC24

1 2

IREF <14>

CHGVADJ <14>

1 2

TP_CLK <20> TP_DATA <20>

1 2

LID_SW ITCH# <14>

R300 33_0402_5%

1 2

SYSON <23,24> VR_ON <23,25> ACIN <14>

1 2 1 2

C252

4.7U_0603_6.3V6K

Deciphered Date

D

1 2

R459 4.7K_0402_5%

1 2

R460 4.7K_0402_5%

C540 100P_0402_50V8J

C541 100P_0402_50V8J

C542 100P_0402_50V8J

R573 0_0402_5% R591 0_0402_5% R503 0_0402_5% R504 0_0402_5%

R257 0_0402_5%

R592 0_0402_5%

R483 0_0402_5%

12

R485 0_0402_5%

R538 0_0402_5%

R267 0_0402_5% R488 0_0402_5%

R494 0_0402_5% R495 0_0402_5%

R496 0_0402_5% R581 0_0402_5%

D

1 2

R265 10K_0402_5%

BATT_TEMPA <14> BATT_OVP <14>

ADP_I <14>

PM_1.5V_PWRGD <24>

LS_INT# <20> GSENSOR_INT <20>

PM_EN_1.5_1.05 <23>

T77 TPC24

CK_PWRGD

T83 TPC24

HDMI_HP_DET1

BATT_FULL_LED# CAPSLED#

T84 TPC24

1 2

EC_LID_OUT#

T78 TPC24

EC_THERM#

PBTN_OUT#

+5VS

KEYBOARD CONN.

KSI1 KSI7 KSI6 KSO9 KSI4 KSI5 KSO0 KSI2 KSI3 KSO5 KSO1 KSI0 KSO2 KSO4 KSO7 KSO8 KSO6 KSO3 KSO12 KSO13 KSO14 KSO11 KSO10

KSO15 CAPSLED#_P CAPSLED#

SP01000GE00 85201-26051 24P P1.0 ACES_85201-26051_24P

GSENSOR_INT2 <20>

WLAN_PWR <14> 3G_PWR <14>

CK_ PWRGD <13>

HDMI_PWR <17>

SPI_SO <21> SPI_SI <21>

SPI_CLK_R <21> INT_SPI_CS# <21>

BT_PWR <20> HDMI_HP_DET1 <17> FSTCHG <14>

BATT_FULL_LED# <20>

BATT_CHG_LOW_LED# <20>

EC_RSMRST# <7> EC_LID_OUT# <8> EC_ ON <14>

ICH_POK <7> BKOFF# <15>

WL_OFF# <14>

CAM_PWR <20>

PM_RSTRDY# <8> ENBKL <7> EC_EAPD_R# <16>

EC_THERM# <4,7,8> SUSP# <14,22> PBTN_OUT# <8> RADIO_OFF# <20>

Title

Size Docu ment Number Re v

Custom

NYU00 LA-5301P

Date: Sheet

E

JP10

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

ACES_85201-26051

27

G1

28

G2

For EMI

C599 100P_0402_50V8J

KSO15

1 2

C600 100P_0402_50V8J

KSO10

1 2

C601 100P_0402_50V8J

KSO11

1 2

C602 100P_0402_50V8J

KSO14

1 2

C603 100P_0402_50V8J

KSO13

1 2

C604 100P_0402_50V8J

KSO12

1 2

C605 100P_0402_50V8J

KSO3

1 2

C606 100P_0402_50V8J

KSO6

1 2

C607 100P_0402_50V8J

KSO8

1 2

C608 100P_0402_50V8J

KSO7

1 2

C609 100P_0402_50V8J

KSO4

1 2

C610 100P_0402_50V8J

KSO2

1 2

C611 100P_0402_50V8J

KSI0

1 2

C612 100P_0402_50V8J

KSO1

1 2

C613 100P_0402_50V8J

KSO5

1 2

C614 100P_0402_50V8J

KSI3

1 2

C615 100P_0402_50V8J

KSI2

1 2

C616 100P_0402_50V8J

KSO0

1 2

C617 100P_0402_50V8J

KSI5

1 2

C618 100P_0402_50V8J

KSI4

1 2

C619 100P_0402_50V8J

KSO9

1 2

C620 100P_0402_50V8J

KSI6

1 2

C621 100P_0402_50V8J

KSI7

1 2

C622 100P_0402_50V8J

KSI1

1 2

SPI_CLK_R

RF Solution

+3VS

12

R585 330_0603_5%

CAPSLED#_P

Compal Electronics, Inc.

ENE-KB926/KB Conn

18 28Monday, Apr il 06, 2009

E

1

C675 22P_0402_50V8J

2

of

0.2

A

1 1

PD_D7<8> PD_D8<8>

+1.8V_SATA

PD_D6<8> PD_D9<8> PD_D5<8>

PD_D10<8>

PD_D4<8> PD_D11<8> PD_D3<8> PD_D12<8>

PD_D2<8> PD_D13<8> PD_D1<8> PD_D14<8> PD_D0<8> PD_D15<8>

PD_DREQ<8> PD_IOW#<8> PD_IOR#<8> PD_IORDY<8> PD_DACK#<8>

1

2

C624

4.7U_0603_6.3V6K

@

+3VS_PATA

C631

+3VS_PATA

1

2

1

2

+1.8V_SATA

2 2

C623

4.7U_0603_6.3V6K

PD_D7 PD_D8 831_HRST# PD_D6 PD_D9 PD_D5

PD_D10

PD_D4 PD_D11 PD_D3 PD_D12 831_HOST PD_D2 PD_D13 PD_D1 PD_D14 PD_D0 PD_D15

PD_DREQ PD_IOW# PD_IOR# PD_IORDY PD_DACK#

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

B

U37

1

BUSY

2

DD7

3

DD8

4

HRST

5

DD6

6

DD9

7

DD5

8

CVDD1

9

VDD1 GND1 DD10 TEST DD4 DD11 DD3 DD12 HOST DD2 DD13 DD1 DD14 DD0 DD15 CVDD2 GND2 VDD2 V5 DMARQ DIOW DIOR IORDY DMACK

GL831-MSG_LQ FP64_7X7

INTRQ

VDD3

CVDD3

GND3

VDD4

GND4

VDD5

CVDD4

GND5

RTERM PLLVDD1 PLLVDD2

GND6 GND7

TXVDD

RXN

RXVDD

GND8

CVDD5

GND9 RESET# SPDSEL

DA1 DA0 DA2 CS0 CS1

TXP TXN

RXP

X2 X1

+3VS_PATA

33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48

831_RTERM

49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64

+1.8V_SATA

PLT_RST#

831_X2 831_X1

1 2

SATA_TXP SATA _TXN SATA_RXN SATA_RXP

PD_IRQ

PD_A1 PD_A0 PD_A2 PD_CS#1 PD_CS#3

PD_IRQ <8>

PD_A1 <8> PD_A0 <8>

PD_A2 <8> PD_CS#1 <8> PD_CS#3 <8>

+1.8V_SATAPLL

R550

5.1K_0402_1%

PLT_RST# < 8,14,17,18>

C

831_X2

831_X1

15P_0402_50V8J

C629

1M_0402_5%

1

2

R549

12

Y2 25MHZ_12PF_7A25000101

12

1

15P_0402_50V8J

2

C630

D

C625 0.01U_0402_16V7K C626 0.01U_0402_16V7K C627 0.01U_0402_16V7K C628 0.01U_0402_16V7K

SATA_TXP SATA _TXN

SATA_RXN SATA_RXP

+3VS +3VS_HDD

1 2 1 2

R565 0_0603_5%

1 2

SATA_TXPC SATA_TXNC

SATA_RXNC SATA_RXPC

E

JP20

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

ACES_87151-1607G

18

G18

17

G17

3 3

4 4

+3VS +3VS_PATA

R283 0_0603_5%

1 2

0.1U_0402_16V4Z

+1.8V_SATAPLL +1.8V_SATA

R554

@

0_0603_5%

1 2

C636

0.1U_0402_16V4Z

+1.8VS +1.8V_SATAPLL

L51

FBMA-L11-160808-800LMT_0603

1 2

C668

4.7U_0603_6.3V6K

A

C267

1

2

1

2

C637

0.1U_0402_16V4Z

C640

0.1U_0402_16V4Z

1

2

C266

0.1U_0402_16V4Z

1

2

1

2

1

2

C641

0.1U_0402_16V4Z

1

C265

0.1U_0402_16V4Z

2

C642

0.1U_0402_16V4Z

1

2

C638

0.1U_0402_16V4Z

1

2

C643

0.1U_0402_16V4Z

+3VS_PATA

1

C639

0.1U_0402_16V4Z

2

1 2

R552 0_0402_5%

1 2

R553 10K_0402_1%

B

831_HOST

PD_D7

R269 510K_0402_1%

12

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDEN TIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMA TION IT C ONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPA L ELEC TRONICS, INC.

Issued Date

C632 1U_0402_6.3V6K

2

C

2008/05/30 2011/05/30

Compal Secret Data

Deciphered Date

D

831_HRST#

1

+3VS_HDD

1

2

1

C652

0.1U_0402_16V4Z

2

E

19 28Monday, Apr il 06, 2009

C650

10U_0603_6.3V6M

Custom

Date: Sheet

1

2

C651

0.1U_0402_16V4Z

Title

Size Docu ment Number Re v

Compal Electronics, Inc.

PATA TO SATA

NYU00 LA-5301P

0.2

of

A

B

C

D

E

Touch/B Connector

+5VS

TP_CLK<18>

1

1 1

C255 1U_0402_6.3V6K

TP_DATA<18>

2

JP11

1

2

3

5

3

GND

4

6

4

GND

ACES_85201-04051

BlueTooth Connector

JP15

1

2

3

4

5

6

7

8

9

10

11

GND1

12

GND2

ACES_87213-1000G

New!-->

C269

0.1U_0402_16V4Z

Q18 SI1305DL-T1-E3_SC70-3

+BT_VCC_A

1 2

R285 0_0603_5%

BT_LED

+BT_VCC

LED & ALS Board

CAM_PWR<18>

BT_LED#

1

Q30

O

I

3

DDTC124EUA-7-F_SOT323-3

G

2

R577 0_0402_5% R578 0_0402_5% R579 0_0402_5%

C272

0.1U_0402_16V4Z

+5VS_GATE_BT

+BT_VCC

BT_LED

2

1

C270 1000P_0402_50V7K

BT_COEX1_R BT_COEX2_R BT_COEX3_R

+3VS

3

S

G

D

1

USB20_P4<8> USB20_N4<8>

+BT_VCC

2

1 2 1 2 1 2

BT_APM<8> RADIO_OFF#<18>

(MAX=200mA)

1

2

+5VS

12

R286 100K_0402_5%

2N7002T-7_SOT523

3 1

Q19

BT_COEX1<14> BT_COEX2<14> BT_COEX3<14> EC_SMB_DA2<4,14,18>

New!-->

2 2

C271

4.7U_0603_6.3V6K

3 3

BT_PWR<18>

GPS + CMOS Camera/MIC + LED Board Connector

JP19

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

JAE_FI-G30S-VF25

1

C676 22P_0402_50V8J

2

CMOS & MIC _6P

+5VS

12

R556 100K_0402_5%

2

+5VA_GATE_CAM

Q32

3 1

2N7002T-7_SOT523

SLEEP_LED#<18>

BATT_FULL_LED#<18>

BATT_CHG_LOW_LED#<18>

LED_WWAN#<14>

Q31 SI1305DL-T1-E3_SC70-3

2

G

2

1

C645 1000P_0402_50V7K

USB20_P5<8> USB20_N5<8>

DMIC_CLK<16> DMIC_DATA<16>

LED_WLAN#<14> LED#_AC<18>

EC_SMB_CK2<4,14,18>

LS_INT#<18>

+5VS

+5V_CAM

+3VALW +3VS

C644

0.1U_0402_16V4Z

3

S

D

1

R564 0_0402_5% R563 0_0402_5%

BT_LED#

EC_SMB_CK2 EC_SMB_DA2

12

@

R605 0_0603_5%

+5V_CAM

0.1U_0402_16V4Z

1 2 1 2

C279

DMIC_ CLK_C DMIC_DATA_C

+5V_CAM

1

2

1

2

C264 1U_0603_10V6K

37

G7

36

G6

35

G5

34

G4

33

G3

32

G2

31

G1

RF Solution

+3VALW

12

R606

4.7K_0402_5%

2

+3VALW

5

EC_SMB_CK1_G

12

R607

4.7K_0402_5%

EC_SMB_DA1_G

C299

0.1U_0402_16V4Z

+3VALW_GS

GSENSOR_INT<18> GSENSOR_INT2<18>

EC_SMB_CK1<14,18>

4 4

EC_SMB_DA1<14,18>

6 1

Q40A 2N7002DWH_SOT363-6

3 4

Q40B 2N7002DWH_SOT363-6

A

12

C55210U_0603_6.3V6M C2980.1U_0402_16V4Z

EC_SMB_DA1_G EC_SMB_CK1_G

12

+3VALW_GS

1 6

8 9

12 13 14

7

B

G-Sensor

+3VALW +3VALW_GS

1 2

R326 0_0603_5%

U36

DVDD_IO AVDD

INT1/DRDY INT2

SDO SDA/SDI/SDO SLC/SPC

CS

MMA7455LR1_LGA14

GND

IADDR0

GND

NC NC NC

2 4 5

3 10 11

T80 TPC24

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDEN TIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMA TION IT C ONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPA L ELEC TRONICS, INC.

C

2008/05/30 2011/05/30

Compal Secret Data

Deciphered Date

D

Title

Size Docu ment Number Re v

Custom

Date: Sheet

Compal Electronics, Inc.

TP/BT/GSEN/LIG/CAM/LED

NYU00 LA-5301P

E

20 28Monday, Apr il 06, 2009

of

0.2

A

1 1

B

C

D

E

2 2

3 3

4 4

System SPI Flash ROM (8Mb)

@

C549 10P_0402_50V8J

@

R479 10_0402_5%

SPI_CLK_R C SPI_CLK_R

12

SPI_SI<18>

SPI_CLK_R<18>

INT_SPI_CS#<18>

12

SPI_CLK_R

INT_SPI_CS#

+3VALW

C277

0.1U_0402_16V4Z

1

2

U31

5

SO

SI

6

SCLK

1

CS

7

HOLD

3

WP

8

VCC

GND

MX25L8005M2C -15G_SO8

SPI_SOSPI_SI

2

4

SPI_SO <18>

@

H_2P2

1

FD1

FD2

@

1

H5

@

H_2P9x2P1

1

@

H_2P2

1

FD4

FD3

@

1

H6

@

H_2P1

1

H4

@

H3

H_2P2

1

1 2

R595 0_0603_5%

1 2

R596 0_0603_5% @

H2

@

H1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDEN TIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMA TION IT C ONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPA L ELEC TRONICS, INC.

C

2008/05/30 2011/05/30

Compal Secret Data

Deciphered Date

Title

Size Docu ment Number Re v

Custom

D

Date: Sheet

Compal Electronics, Inc.

ROM/SCREW

NYU00 LA-5301P

E

21 28Monday, Apr il 06, 2009

0.2

of

A

B

C

D

E

F

G

H

I

J

4

1

C171

0.047U_0402_16V4Z

2

D

6

2 1

G

C653

0.01U_0402_16V7K

Q24

D

6

2 1

G

3

1

C654

0.01U_0402_16V7K

2

+1.05VS_C6

1 2 3

C285

1

10U_0805_10V4Z

2

+3VS

C289

1

10U_0805_10V4Z

2

C286

1

0.1U_0402_16V4Z

2

C290

1

0.1U_0402_16V4Z

2

+5VS +3VS

12

@

R315 470_0402_5%

61

SUSP SUSP

2

@

Q22A 2N7002DWH_SOT363-6

SUSP#<14,18>

12

34

5

SUSP

SUSP#

2

@

R316 470_0402_5%

@

Q22B 2N7002DWH_SOT363-6

I

SUSP

+5VALW

12

R313 10K_0402_5%

1

Q25

O

DDTC124EUA-7-F_SOT323-3

G

3

+1.8VS

12

2

3 1

@

R568 470_0402_5%

@

Q36 2N7002T-7_SOT523

+3VS

1 1

R172

10K_0402_5%

SLPIOVR#<4,8>

SLPIOVR#

+5VS

1 2

2

A

1

B

+1.05VS

5

U26

P

4

Y

R173 1K_0402_5%

G

74AHCT1G08GW_SOT353-5

3

Q13 SI7326DN-T1-GE3_PAK1212-8-5

5

1 2

2 2

+5VALW to +5VS Transfer

+5VALW

12

C

Q35

2

B

MMBT3904WH_ SOT323-3

E

3 1

R566 100K_0402_5%

3 3

SUSP#

R567

1 2

100K_0402_5%

+5VALW +5VS

+5VS_GATE

4 4

Q23

SI3445ADV-T1-E3_TSOP6

S

4 5

3

1

2

+3VALW to +3VS Transfer

+3VALW

SI3445ADV-T1-E3_TSOP6

S

4 5

5 5

+5VALW

12

R569 100K_0402_5%

12

R570 10K_0402_5%

+3VS_GATE

SUSP#_GATE

6 6

SUSP#

R572

1 2

100K_0402_5%

C

Q37

2

B

MMBT3904WH_S OT323-3

E

3 1

12

R571 220K_0402_5%

7 7

8 8

A

B

C

+1.8V to +1.8VS Transfer

Q34

+1.8V +1.8VS

+1.8VS_GATE

C655

0.1U_0402_16V4Z

D

AO3413_SOT23

S

G

2

1

2

D

13

1

C648 10U_0603_6.3V6M

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDEN TIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMA TION IT C ONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPA L ELEC TRONICS, INC.

E

C649

1

0.1U_0402_16V4Z

2

2008/05/30 2011/05/30

F

Compal Secret Data

Deciphered Date

G

PRODUCT SUMMARY

Vgs

-8

Title

Size Docu ment Number Re v

Custom

H

Date: Sheet

rDS(on)

0.042 @ VGS = .4.5 V

0.060 @ VGS = .2.5 V

0.080 @ VGS = .1.8 V

Compal Electronics, Inc.

DC/DC Circuit

NYU00 LA-5301P

ID (A)

+-5.6

+-4.7

+-2.9

0.2

of

I

22 28Monday, Apr il 06, 2009

J

A

B

C

D

B+

1 1

112

JUMP_43X79@

+1.8VP

2 2

3 3

PJ5

2

PJ10

+0.9VSP +0.9VS

4 4

+1.5VSP +1.5VS

+1.8VP

112

JUMP_43X79@

PJ6

2

112

JUMP_43X118@

PJ7

2

112

JUMP_43X79@

PJ1

2

112

JUMP_43X118@

1.8V_B+

2

12

PC75

PC68

4.7U_0805_25V6-K

2.2UH_PCMC063T-2R2MN_8A_20%

1

+

PC124 150U_B2_6.3VM_R35M

PL7

1 2

2

PR86

0_0402_5%

SYSON<18,24>

1 2

+3VALW

PM_1.05_PWRGD<18,25>

PR94

0_0402_5%

PM_EN_1.5_1.05<18>

+5VALW

1 2

PR97

422_0603_1%

1 2

1U_0603_10V6K

PC85

12

PC80

0.1U_0402_16V7K

@

12

PQ20

8

G2

7

S2

6

S2

5

S2

12

PC71

0.1U_0402_16V7K

@

100K_0402_1%

1 2

12

PR143

10

1

G1

D1

2

D1

3

D1

4

D1

S1/D2

FDMC7200_POW ER33-8-10

9

LX_1.8V

PR88

4.7_1206_5%@

+5VALWP

5.1_0603_5%

PC72

680P_0603_50V7K

PM_1.8V_PWRGD<18>

@

PR179

1 2

1U_0603_10V6K

VR_ON<18,25>

PU7

2

TON

3

VOUT

4

V5FILT

5

VFB

6

PGOOD

DL_1.8V

PC76

270K_0402_1%

1

EN_PSV

+1.05VS+1.05VSP

PR99

9.53K_0402_1%

1 2

12

PR100

20.5K_0402_1%

+1.8V

A

B

PR87

0_0603_1%

1 2

DH_1.8V

PR177

5.1K_0402_1%

1 2

100K_0402_1% PR178

1 2

PC69

0.1U_0603_25V7K

12

PU12

VBST

DRVH

LL

DRVL

PGND_D

CS

V5FILT

PGOOD

S5

S3

NC

22

21

20

19

18

16

14

13

11

10

V5IN

15

7

NC

GND_S

Thermal pad

17

25

VLDOIN

VTT

VTTGND

VTTSNS

GND

MODE

VTTREF

COMP

VDDQSNS

VDDQSET

23

24

1

2

3

4

5

6

8

9

TPS51116RGE_QFN24

+1.8VP

+5VALWP

+1.8VP

+5VALWP

+1.8VP

10U_0603_6.3V6M

0.033U_0402_16V7

PC91

BST_1.05V-1

DH_1.05V

LX_1.05V

1 2

PR98

5.76K _0402_1%

DL_1.05V

+5VALWP

PC78

1 2

0.1U_0603_25V7K

+5VALW

12

PC83

4.7U_0805_10V6K

10

PQ22

1

G1

D1

2

D1

3

D1

4

D1

S1/D2

FDMC7200_POW ER33-8-10

9

12

PR96

12

PC81

@

8

G2

7

S2

6

S2

5

S2

PL8

2.2UH_PCMC063T-2R2MN_8A_20%

1 2

4.7_1206_5%@

680P_0603_50V7K

1U_0603_10V6K

PR93

1 2

BST_1.05V

15

14

TP

VBST

DRVH

TRIP

V5DRV

DRVL

GND7PGND

TPS51117RGYR_QFN14_3. 5x3.5

8

LL

PR95

0_0603_1%

1 2

13

12

11

10

9

OCP:3A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZE D BY COMPA L ELECTRO NICS, INC. N EITHER TH IS SHEET N OR THE INF ORMATION IT C ONTAINS MAY BE USED BY OR DISC LOSED TO A NY THIRD P ARTY WITH OUT PRIOR WR ITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Compal Secret Data

Deciphered Date

C

12

2008/11/122007/11/12

PC93

PC92

1.05V_B+

PC77

4.7U_0805_25V6-K

12

PC84

4.7U_0805_25V6-K

1

2

+0.9VSP

12

PC125 10U_0603_6.3V6M

0.9Vref

PJ11

2

JUMP_43X79@

B+

112

+1.05VSP

1.05V/1.5A

+

PC79 220U_B2_2.5VM_R15M

Title

Size Docu ment Number Re v

Date: Sheet

Compal Electronics, Inc.

1.05V / 1.8V

D

0.1

of

23 28Monday, April 06, 2009

5

4

3

2

1

1.5V_B+

PR176

100K_0402_1%

PC87

0.1U_0402_16V7K

@

12

1 2

PR108

1 2

20.5K _0402_1%

PR103

20.5K _0402_1%

FDMC7200_POW ER33-8-10

PR109

270K_0402_1%

1 2

15

1

PU8

2

TON

3

VOUT

4

V5FILT

5

VFB

6

PGOOD

TP

EN_PSV

GND7PGND

8

PR102

0_0603_1%

BST_1.5V

1 2

14

VBST

13

DRVH

12

LL

11

TRIP

10

V5DRV

9

DRVL

TPS51117RGYR_QFN14_3. 5x3.5

BST_1.5V-1

DH_1.5V

LX_1.5V

1 2

PR111

5.1K_0402_1%

DL_1.5V

PC110

1 2

0.1U_0603_25V7K

+5VALW

12

PC89

4.7U_0805_10V6K

10

PQ33

1

G2

G1

D1

2

D1

3 4

S2

D1

S2 S2

D1

S1/D2

9

12

OCP:3A

PR107

0_0402_5%

1 2

PR101

422_0603_1%

1 2

1U_0603_10V6K

+3VALW

12

PC86

D D

PM_1.5V_PWRGD<18>

SYSON<18,23>

+5VALW

C C

12

PC90

4.7U_0805_25V6-K

8 7 6 5

PL6

2.2UH_PCMC063T-2R2MN_8A_20%

1 2

PR110

4.7_1206_5%@

PC109

680P_0603_50V7K

@

PJ12

2

JUMP_43X79@

12

PC108

4.7U_0805_25V6-K

1

+

PC111 150U_B2_6.3VM_R35M

2

B+

112

+1.5VSP

1.5VS/1A

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZE D BY COMPA L ELECTRO NICS, INC. N EITHER TH IS SHEET N OR THE INF ORMATION IT C ONTAINS MAY BE USED BY OR DISC LOSED TO A NY THIRD P ARTY WITH OUT PRIOR WR ITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

Compal Secret Data

Deciphered Date

2008/11/122007/11/12

2

Title

Size Docu ment Number Re v

Dat e: Sh eet

Compal Electronics, Inc.

1.5V / 0.9V

24 28Monday, April 06, 2009

1

0.1

of

5

4

3

2

1

+5VS

1 2

12

1.69K _0402_1%

12

1 2

+CPU_B+

PC101

0.1U_0603_25V7K

1 2

DH_CPU

LX_CPU

PC105 1000P_0402_50V7K

1 2

PR171

PR144

10_0402_1%

PC97 1U_0402_6.3V6K

DL_CPU

+CPU_B+

578

PC106 1000P_0402_50V7K

1 2

10_0402_1%

1 2

PC107 1000P_0402_50V7K

1 2

680P_0402_50V7K

PQ25 AO4466_SO8

3 6

241

PQ26 AO4466_SO8

3 6

241

MAX8796_CSP

PR172

10_0402_1%

1 2

PR174

PC119

12

1 2

12

PC98

1 2

0.01U_0402_25V6K

2.2UH_PCMC063T-2R2MN_8A_20%

12

PR159

4.7_1206_5%@

PC102 680P_0603_50V8J@

PR175 10_0402_1%

PR160

5.1K_0402_1%

1 2

PR169

10_0402_1%

12

PC99

4.7U_0805_25V6-K

1 2

PR163

1.65K_0402_1%

1 2

0.1U_0402_16V7K

VCCSENSE <5>

VSSSENSE <5>

HCB2012KF-121T50_0805

1 2

12

PC100

4.7U_0805_25V6-K

PL10

12

PC103

PL9

+CPU_COREP

12

PJ14

2

JUMP_43X118@

B+

680P_0402_50V7K

PC115

+CPU_CORE

112

D D

PC96

1U_0402_6.3V6K

CPU_VID0<5>

CPU_VID1<5>

CPU_VID2<5>

CPU_VID3<5>

CPU_VID4<5>

12

PR153

10K_0402_1%@

VR_ON<18,23>

C C

PR155

0_0402_5%

12

CPU_VID5<5>

CPU_VID6<5>

DPRSLPVR<7>

H_DPRSTP#<4,6>

PM_1.05_PWRGD<18,23>

+3VS

12

PR165

56_0402_5%@

PR168

0_0402_5%@

PROCHOT#<4,8>

CLK_ENABLE#<13>

1 2

PR170

0_0402_5%

PR166 2K_0402_1%@

1 2

PR145 0_0402_5%

PR146 0_0402_5%

PR147 0_0402_5%

PR148 0_0402_5%

PR150 0_0402_5%

PR151 0_0402_5%

PR154 0_0402_5%

PR156 0_0402_5%

PR157 0_0402_5%

PR158 0_0402_5%

PR161

61.9K_0402_1%

1 2

VGATE<18>

+5VS

B B

12.7K _0402_1%

+3VS

PR167

0_0402_5%

1 2

13K_0402_1%

12

PR162

1 2

PR164

10K_0402_1%

PR173

1 2

PU10

14

D0

15

D1

16

D2

17

D3

18

D4

19

D5

20

D6

11

SHDN

7

DPRSLPVR

6

DPRSLP

27

PGD_IN

29

TIME

30

ILIM

13

V3P3

1 2

10

PWRGD

28

VRHOT

12

CLKEN

1

PWR

8

THRM

PAD

MAX8796GTJ+_TQFN32_5X5

33

VDD

VCC

TON

PGND

CSP

CSN

CCV

GNDS

BST

DH

LX

DL

FB

23

31

9

BOOT_CPU

24

26

25

22

21

5

4

32

47P_0402_50V8J

3

2

121K_0402_1%

1 2

12

PC104

PR149

PR152

2.2_0603_1%

+5VALW

A A

100K_0603_1%_TH11-4H104FT

CPU_TM P_SENSE<14>

5

4

PH1

12

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZE D BY COMPA L ELECTRO NICS, INC. N EITHER TH IS SHEET N OR THE INF ORMATION IT C ONTAINS MAY BE USED BY OR DISC LOSED TO A NY THIRD P ARTY WITH OUT PRIOR WR ITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/11/12 2008/11/12

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Docu ment Number Re v

Custom

2

Date: Sheet

+CPU_CORE

Monday, April 06, 2009

0.1

of

25 28

1

5

4

3

2

1

ISL6237_B+

8 7 6 5

PC61

10U_1206_25V6M

1 2

4.7UH_PCMC063T-4R7MN_5.5A_20%

12

PR78

@

4.7_1206_5%

12

PC62

@

680P_0603_50V7K

12

PC59

2200P_0402_50V7K

+5VALWP

PL4

1

PR118

61.9K_0402_1%@

1 2

PR75

0_0402_5%

1 2

+3VALWP +3VALW

+5VALWP +5VALW

2

(4A,160mils ,Via NO.= 8)

JUMP_43X79@

2

JUMP_43X79@

+

PC122 150U_B2_6.3VM_R35M

2

PJ2

112

PJ3

112

12

4.7_1206_5%

12

680P_0603_50V7K

1 2

2

ISL6237_B+

PQ21

8

G2

7

S2

6

S2

5

S2

PR81

100K_0402_1%

PR79

1 2

200K_0402_5%

PR84

0_0402_5%

PQ30

TP0610K-T1-E3_SOT23-3

0_0805_5%

1 2

10

1

G1

D1

2

D1

3

D1

4

D1

S1/D2

FDMC7200_POW ER33-8-10

9

PR117

2.2_0603_1%

PC112

0.1U_0603_25V7K

1 2

PC64

0.22U_0603_25V7K

1 2

+VL

PR121

12

PR114

47K_0402_5%@

1 2

806K_0603_1%

1 2

12

PC118

PR76

PC66

0.1U_0603_25V7K

DH3

BST3A

12

LX3

DL3

FB3

+VL

2VREF_ISL6237

1 2

PC120 0.22U_0603_10V7K

PR113

@

0_0402_5%

1 2

1U_0603_10V6K

12

2VREF_ISL6237

PC117

0.047U_0402_16V7K

0.047U_0603_16V7K

@

PR80

33

26

24

25

23

30

32

1

8

20

4

14

27

0_0402_5%

PC114

1 2

PU11

TP

UGATE2

BOOT2

PHASE2

LGATE2

OUT2

REFIN2

REF

LDOREFIN

NC

EN_LDO

EN1

EN2

+VL

1 2

PC116

3

6

VIN

VCC

TON

NC

2

5

12

PR122 0_0402_5%

2VREF_ISL6237

12

PC65

1U_0603_10V6K

7

19

PVCC

LDO

15

UGATE1

17

BOOT1

16

PHASE1

18

LGATE1

22

PGND

10

OUT1

11

FB1

9

BYP

29

SKIP

28

POK2

13

POK1

12

ILIM1

31

ILIM2

GND

ISL6237IRZ-T_QFN32_5X5

21

4.7U_0805_6.3V6K

DH5

BST5A

LX5

DL5

FB5

ILM1

ILIM2

PC60

1U_0603_10V6K

1 2

PR115

PC113

2.2_0603_1%

0.1U_0603_25V7K

PR119 0_0402_5%@

PR82 0_0402_5%

1 2

12

1 2

12

PR116

150K_0402_1%

PR112

150K_0402_1%

10

PQ23

1

G1

D1

2

D1

3

D1

4

D1

S1/D2

9

12

G2 S2 S2 S2

FDMC7200_POW ER33-8-10

+VL

B+

PJ9

2

112

D D

+3VALWP

1

+

PC123

150U_B2_6.3VM_R35M

C C

B B

2

JUMP_43X79@

PL5

1 2

4.7UH_PCMC063T-4R7MN_5.5A_20%

PR77

0_0402_5%

1 2

PR83

10K_04 02_1%

1 2

@

VS

RLZ5.1B_LL34

12

PC121

10U_1206_25V6M

PD6

1 2

1 3

PC63

2200P_0402_50V7K

PR120

@

PC67

@

MAINPWON<14>

PD7

1 2

1SS355TE-17_SOD323-2

A A

Title

<Title>

Size Document Number Re v

Custom

5

4

3

2

Date: Sheet

1

of

26 28Monday, April 06, 2009

1

2

3

4

5

6

7

8

ITEM

)L[HG,VVXH5HDVRQIRUFKDQJH

REV

1.DC/DC switch Capacity voltage tolerance

1

2

A A

3

4

5

6

7

B B

8

9

10

2.B+ is over Q23, Q24, Q34 Gate Voltage and cause the leakage on +1.8VS & +3VS.

1.Change JP19 to I-PEX 30Pin.

1.Follow the LCD SPEC to add Pin 20 LVDS_EN

1.BT is USB 2.0 Full Speed. Change USB port to Port 4

1.C5, C8, C550 change to lower cost and lower ESR.

1.C52, C55, C63, C153 change to lower cost and lower ESR.

1.Add HP, HP/MIC Auto Detect circuit.

1.USB port change to on board.

1.SATA FPC connector change to TOP conduction.

1.Panel Backlight voltage change for efficient.

0.2

PAGE

CHANGE LIST

1.Change C653, C654, C655 to 50V tolerance

PAGE 22

2.Q23, Q24, Q34 Gate pull high voltage change to +5VALW

PAGE 20 1.Change JP19 to I-PEX 30Pin(I-PEX_20439-R30E-02).

PAGE 211.Del reserve DB port Conn. of EC

PAGE 15 PAGE 18

PAGE 14 PAGE 20

PAGE 05

PAGE 09

PAGE 16

1.Delete JP26.

2.Delete LPC DB port.

1.Add LVDS_EN on JP3 Pin20 and U35 B10

2.Add R200 100K pull high.

1.BT USB change to USB20 port 4.

2.3G USB change to USB20 port 7.

1.C5, C8, C550 change from 220U_B15G_70m ohm to 220U_B2_15m ohm

1.C52, C55, C63, C153 change from 150U_B15G_70m ohm to 150U_B2_35m ohm

1.Add U38 Comparator circuit.

090310

090311

090312

1.Change JP1 and add JP2 TYCO_2009104.

PAGE 15 090320

PAGE 15

2.Change JP20 from 87152 type to 87151type.

1.Add B+ for LED backlight supply.

090326

11

1.GL831 +1.8V pin input output separate for decrease the power consumption

0.2

PAGE 19

1.U37 Pin8, 24, 35(CVDD1, 2, 3) use internal 3.3V to 1.8V regulator

2.Other 1.8V pins use system +1.8VS power.

090326

1.Change Interface to EC SMBUS1, change to +3VALW power

12

C C

13

14

D D

1.G-Sensor application need always power.

1

2

0.2

3

PAGE 20

2.Add level shift for SMBUS I/F (+5VALW to +3VALW.)

3.Change G-Sensor from MMA7660 to MMA7455

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZE D BY COMPA L ELECTRO NICS, INC. N EITHER TH IS SHEET N OR THE INF ORMATION IT C ONTAINS MAY BE USED BY OR DISC LOSED TO A NY THIRD P ARTY WITH OUT PRIOR WR ITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

2008/05/15 2009/05/15

5

Compal Secret Data

Deciphered Date

6

Compal Electronics, Inc.

Title

P27_Change List

Size Docu ment Number Re v

LA-5301P 0.2

Custom

Date: Sheet

7

090326

090327

of

27 28Monday, April 06, 2009

8

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PR OPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECT RONICS, INC. NEITH ER THIS SHEET NOR THE INF ORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOU T PRIO R WRIT TEN CO NSENT OF COMPAL ELEC TRONICS, INC.

2005/06/01 2006/06/01

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Re v

Date: Sheet

Power PIR

LA-3481P

of

28 28Monday, April 06, 2009

0.3