Nokia 6630 Service Manual rm 1 09_system

Nokia Customer Care

9 — System Module

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Table of Contents

Baseband description...................................................................................................................................................................9–7

System module block diagram............................................................................................................................................9–7

Baseband functional description........................................................................................................................................9–7

Absolute maximum ratings..................................................................................................................................................9–9

Modes of operation.................................................................................................................................................................9–9

Power distribution................................................................................................................................................................9–12

Clocking scheme.....................................................................................................................................................................9–14

Bluetooth..................................................................................................................................................................................9–15

USB..............................................................................................................................................................................................9–15

SIM interface............................................................................................................................................................................9–15

RS MMC interface....................................................................................................................................................................9–16

Battery interface....................................................................................................................................................................9–17

Camera interface....................................................................................................................................................................9–18

User interface..........................................................................................................................................................................9–19

Display interface...............................................................................................................................................................9–19

Keyboard.............................................................................................................................................................................9–20

Display and keyboard backlight..................................................................................................................................9–20

ALS interface......................................................................................................................................................................9–20

ASICs...........................................................................................................................................................................................9–21

RAP3G ASIC.........................................................................................................................................................................9–21

Retu EM ASIC......................................................................................................................................................................9–21

Tahvo EM ASIC...................................................................................................................................................................9–22

Device memories...................................................................................................................................................................9–22

RAP3G memories NOR flash and SDRAM...................................................................................................................9–22

Combo memory (Helen 3).............................................................................................................................................9–22

Audio concept...............................................................................................................................................................................9–22

Audio HW architecture.........................................................................................................................................................9–22

Internal microphone.............................................................................................................................................................9–23

External microphone............................................................................................................................................................9–24

Internal earpiece....................................................................................................................................................................9–24

Internal speaker.....................................................................................................................................................................9–25

External earpiece...................................................................................................................................................................9–25

Vibra circuitry..........................................................................................................................................................................9–26

Pop-portTM connector.........................................................................................................................................................9–26

Baseband technical specifications.........................................................................................................................................9–28

External interfaces.................................................................................................................................................................9–28

ACI interface electrical characteristics.............................................................................................................................9–28

VOUT electrical characteristics...........................................................................................................................................9–29

USB IF electrical characteristics.........................................................................................................................................9–29

FBUS interface electrical characteristics.........................................................................................................................9–30

Headset hook detection interface (XMICN) electrical characteristics....................................................................9–30

Audio signal electrical characteristics.............................................................................................................................9–30

SIM IF connections.................................................................................................................................................................9–31

RS MMC interface connections...........................................................................................................................................9–31

Charger connector and charging interface connections & electrical characteristics.......................................9–32

Battery connector and interface connections & electrical characteristics...........................................................9–33

Internal interfaces.................................................................................................................................................................9–33

UI module connector and IF connections......................................................................................................................9–34

Keyboard interface electrical characteristics................................................................................................................9–35

Display connector and interface connections...............................................................................................................9–36

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Camera interface connections and electrical characteristics...................................................................................9–37

Back-up battery interface connections and electrical characteristics..................................................................9–39

RF description...............................................................................................................................................................................9–40

Introduction to receiver functionality.............................................................................................................................9–40

WCDMA receiver......................................................................................................................................................................9–40

GSM receiver............................................................................................................................................................................9–40

Introduction to transmitter functionality......................................................................................................................9–41

WCDMA transmitter...............................................................................................................................................................9–41

GSM transmitter......................................................................................................................................................................9–43

Frequency synthesizers........................................................................................................................................................9–46

Regulators................................................................................................................................................................................9–47

Frequency mappings..................................................................................................................................................................9–49

EGSM900 frequencies............................................................................................................................................................9–49

GSM1800 frequencies...........................................................................................................................................................9–50

GSM1900 frequencies...........................................................................................................................................................9–51

WCDMA Rx frequencies.........................................................................................................................................................9–52

WCDMA Tx frequencies.........................................................................................................................................................9–53

List of Tables

Table 7 Keymatrix.........................................................................................................................................................................9–20

Table 8 ALS resistor values.........................................................................................................................................................9–21

Table 9 Audio connector pin assignments...........................................................................................................................9–27

Table 10 Charging interface connections..............................................................................................................................9–32

Table 11 Charging IF electrical characteristics....................................................................................................................9–32

Table 12 Battery interface connections.................................................................................................................................9–33

Table 13 Battery IF electrical characteristics........................................................................................................................9–33

Table 14 User interface connections......................................................................................................................................9–34

Table 15 Display interface connections.................................................................................................................................9–36

Table 16 Camera interface connections................................................................................................................................9–37

Table 17 Camera CCP IF electrical characteristics...............................................................................................................9–38

Table 18 Camera supply voltage characteristics.................................................................................................................9–39

Table 19 Camera control IF electrical characteristics........................................................................................................9–39

Table 20 Back-Up battery connections..................................................................................................................................9–39

Table 21 Back-Up battery electrical characteristics...........................................................................................................9–40

List of Figures

Figure 90 System level block diagram......................................................................................................................................9–7

Figure 91 Functional block diagram.........................................................................................................................................9–8

Figure 92 Helen3 high level block diagram............................................................................................................................9–8

Figure 93 State diagram.............................................................................................................................................................9–11

Figure 94 Power distribution diagram..................................................................................................................................9–12

Figure 95 System start-up timing............................................................................................................................................9–14

Figure 96 Clocking scheme........................................................................................................................................................9–15

Figure 97 SIM interface...............................................................................................................................................................9–16

Figure 98 Reduced size MMC.....................................................................................................................................................9–16

Figure 99 MMC interface.............................................................................................................................................................9–17

Figure 100 Battery pin order.....................................................................................................................................................9–17

Figure 101 Block diagram of Mirage-X camera module...................................................................................................9–18

Figure 102 General diagram of the LCD module.................................................................................................................9–19

Figure 103 ALS HW implementation.......................................................................................................................................9–21

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Figure 104 Audio block diagram..............................................................................................................................................9–23

Figure 105 Internal microphone circuitry.............................................................................................................................9–24

Figure 106 External microphone circuitry (Pop-Port connects to the right side)....................................................9–24

Figure 107 Internal earpiece circuitry....................................................................................................................................9–25

Figure 108 Internal speaker circuitry.....................................................................................................................................9–25

Figure 109 External earpiece circuitry (Pop-Port connected on the right)................................................................9–26

Figure 110 Vibra circuitry...........................................................................................................................................................9–26

Figure 111 External audio connector.....................................................................................................................................9–27

Figure 112 Charger connector..................................................................................................................................................9–32

Figure 113 Battery connector...................................................................................................................................................9–33

Figure 114 UI connector.............................................................................................................................................................9–34

Figure 115 Display connector...................................................................................................................................................9–36

Figure 116 WCDMA transmitter................................................................................................................................................9–42

Figure 117 Block diagram of DCDC converter and WCDMA PA........................................................................................9–43

Figure 118 GSM transmitter.......................................................................................................................................................9–44

Figure 119 GSM/EDGE power control topology and control signals.............................................................................9–45

Figure 120 Power control signal usage in GSM (GMSK) and EDGE (8PSK) transmission. Timings are not shown

accurately........................................................................................................................................................................................9–45

Figure 121 Phase locked loop in N7500 and N7501 (PLL)...............................................................................................9–47

Figure 122 RF supply connections from the BB mixed mode ASIC................................................................................9–48

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Baseband description

System module block diagram

The device consists of two different main modules: transceiver (1ax) and UI (1ay). The transceiver board consists of baseband and RF components

The UI board consists of key domes and keypad backlights. Connection between the UI and the transceiver board is established via a board-to-board spring connector.

Note: In this description, user interface HW covers display, camera, keyboard, keyboard backlight and

ALS.

Figure 90 System level block diagram

Baseband functional description

Digital baseband consists of ISA based modem and SYMBIAN based application sections. Modem functionality is in RAP3G and Helen2/3 acts as a platform for SYMBIAN applications.

Modem section consists of RAP3G ASIC with NOR FLASH and SDRAM memory as the core. RAP3G supports cellular protocols of WCDMA (3GPP R-4) and GSM (minimum EDGE glass 10, GPRS phase2). Modem SDRAM memory have 64Mbits of memory and NOR flash have 64Mbits of memory. RAP3G operates with the system clock of 38.4 MHz, which comes from the VCTCXO.

Application section includes Helen3 ASIC with DDR/NAND combo memory as the core. Stacked DDR/NAND application memory has 256Mbits of DDR memory and 256Mbits of flash memory. Helen3 uses 19.2MHz clock, which comes from the RAP3G divided by two from the 38.4 MHz system clock.

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Figure 91 Functional block diagram

Helen3 processor (OMAP1710) is called also as an application ASIC in RM-1 because it is processing application SW and handles the UI SW. It consists of OMAP3.3 and peripheral subsystems like camera-, display- and keyboard driver blocks.

Figure 92 Helen3 high level block diagram

OMAP3.3 consists of ARM926 (MPU subsystem), TMS320C55x (DSP subsystem), DMA and OMAP3.3s internal peripherals.

Helen3s MPU subsystem is based on an ARM926EJ. MPU is able to perform most of the application operations on the chip.

System DMA: This component is mainly used to help the MPU and DSP perform data memory transfer-specific tasks, leaving more available MIPS for both processors.

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The DSP subsystem is based on a TMS320C55x™ DSP core, which is responsible for intensive data computing tasks like real-time audio and video handling on application side. E.g. voice recording.

Internal memory subsystem: This subsystem is composed of a single port SRAM. Secure modules: OMAP1610 contains a set of several components, including ROM, a single port SRAM, and eFUSE

cells. These components enable the system to support secure applications. Memory interfaces: The memory interfaces define the system memory access organization of OMAP1610. USB & modem interface: These two modules enable the platform to support a universal serial link and a

dedicated modem interface, enabling a high data transfer rate between the modem and the application chip. System components: System components are group of modules responsible for managing system interactions

such as interrupt, clock control and idle. Peripheral subsystem: The peripheral subsystem defines all the components used to interface OMAP1610 with

specific external devices such as camera, keyboard, display etc.

Absolute maximum ratings

Signal Min Nom Max Unit Notes

Battery voltage (idle) -0.3 +4.5 V Battery voltage maximum value is

specified during charging is active

Battery voltage (Call) +4.3 V Battery voltage maximum value is

specified during charging is active

Charger input voltage -0.3 +16V V

Back-Up supply voltage 0 2.5 2.7 V Maximum capacity of the backup

power supply assumed to be 200 µAh.

Modes of operation

Mode Description

NO_SUPPLY (dead) mode means that the main battery is not present or its voltage is too low (below

RETU master reset threshold) and that the back-up battery voltage is too low.

BACK_UP The main battery is not present or its voltage is too low but back-up battery voltage is

adequate and the 32kHz oscillator is running (RTC is on).

PWR_OFF In this mode (warm), the main battery is present and its voltage is over RETU master reset

threshold. All regulators are disabled, PurX is on low state, the RTC is on and the oscillator is on. PWR_OFF (cold) mode is almost the same as PWR_OFF (warm), but the RTC and the oscillator are off.

RESET RESET mode is a synonym for start-up sequence. In this mode certain regulators are

enabled and after they and RFClk have stabilized, the system reset (PurX) is released and PWR_ON mode entered. RESET mode uses 32kHz clock to count the REST mode delay (typically 16ms).

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Mode Description

SLEEP SLEEP mode is entered only from PWR_ON mode with the aid of SW when the system’s

activity is low. There are in principle three different sleep modes:

• Helen3 sleep

• RAP3G sleep

• Helen3 and RAP3G sleep (deep sleep) In SLEEP mode RETU’s regulators VIO, VDRAM, VSIM1, VSIM2, VAUX and Vana are in low

quiescent current mode (output voltages still present but regulators will not give as much current out). Other regulators including VR1 supplying system clock oscillator are disabled.

In SLEEP mode, TAHVO VCORE SMPS regulator is in low quiescent current mode (if sleep mode is not internally disabled). Linear regulator VOUT state depends on the accessory connected to the system connector (Pop-Port), if there is any.

FLASHING FLASHING mode is for SW downloading. FLASHING mode is not really a RETU or TAHVO

state but rather a system state. From RETU and TAHVO point of view, it is like PWR_ON. The state is entered from PWR_ON. It is possible to use external voltage (VPP) during flashing to speed up the process (provided that the memory components support the feature).

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Figure 93 State diagram

Voltage limits

Parameter Description Value

VMSTR Master reset threshold (RETU) 2.2V (typ.)

Threshold for charging, rising

VMSTR+

VMSTR-

VCOFF+ Hardware cutoff (rising) 2.9V (typ.)

VCOFF- Hardware cutoff (falling) 2.6V (typ.)

SWCOFF SW cutoff limit ~3.2V

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(TAHVO) 2.1V (typ.)

Threshold for charging, falling (TAHVO) 1.9V (typ.)

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The master reset threshold controls the internal reset of Retu / (Tahvo). If battery voltage is above VMSTR, UEME’s charging control logic is alive. Also, RTC is active and supplied from the main battery. Above VMSTR UEME allows the system to be powered on although this may not succeed due to voltage drops during start up. SW can also consider battery voltage too low for operation and power down the system.

Power key

The system boots up when power key is pressed (adequate battery voltage, VBAT, present). Power down can be initiated by pressing the power key again (the system is powered down with the aid of

SW). Power on key is connected to Retu ASIC via PWRONX signal.

Power distribution

Figure 94 Power distribution diagram

Power supply components:

• RETU

• TAHVO

• Helen VCORE SMPS

• BT

• LDO

• camera LDO

• backlight SMPS All the above are powered by the main battery voltage. Battery voltage is also used on the RF side for power amplifiers (GSM PA & WCDMA PA) and for RF ASICs Hinku

(Rx) & Vinku(Tx).

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Discrete power supplies are used to generate 2.8V for BT, 1.5V for the camera module, 1.3V/1.5V for Helen3 and 18V for backlight LEDs.

The device supports both 1.8V/3V SIM cards which are powered by RETU / VSIM1. RETUs VSIM2 is used to power RS MMC 1.8V only. USB accessories which needs power from the device are powered by TAHVO / VOUT.

Because LED driver in TAHVO is not used, the external SMPS is used instead. External LED SMPS is still controlled by TAHVO and powered by battery voltage.

System power-up

After inserting the main battery, regulators started by HW are enabled. SW checks, if there is some reason to keep the power on. If not, the system is set to power off state by watchdog. Power up can be caused by the following reasons:

• Power key is pressed

• Charger is connected

• RTC alarm occurs

• MBUS wake-up After that:

• Retu activates sleep clock and VANA, VDRAM, VIO and VR1 regulators.

• Voltage appearing at Retu’s RSTX pin is used for enabling Tahvo ASIC.

• Tahvo enables VCORE regulator and its internal RC-oscillator (600kHz).

• VCTCXO regulator is set ON and RF clock (main system clock) is started to produce.

• Retu will release PURX ~ 16ms after power up is enabled (the RF clock is then stable enough).

• Synchronizing clock (2.4MHz) for Tahvo is started to be produced. After PURX is released and two rising edges of 2.4MHz synchronous clock have been detected in SMPSClk input Tahvo is starting to use that instead of 600kHz internal RC-oscillator.

• HW start-up procedure has been finalized and the system is up and running. Now it is possible for SW to switch ON other needed regulators.

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Figure 95 System start-up timing

Clocking scheme

In BB5.0, two main clocks are provided to the system: 38.4MHz RF clock produced by VCTCXO in RF section and

32.768kHz sleep clock produced by RETU with an external crystal. RF clock is generated only when VCTCXO is powered on by RETU regulator. Regulator itself is activated by SleepX

signals from both RAP3G and Helen3. When both CPUs are on sleep, RF clock is stopped. RF clock is used by RAP3G that then provides (divided) 19.2MHz SysClk further to Helen3. Both RAPG and Helen3

have internal PLLs which then create clock signals for other peripheral devices/interfaces like RS MMC, SIM, CCP, I2C and memories.

32k Sleep Clock is always powered on after startup. Sleep clock is used by RAP3G and Helen3 for low-power operation.

SMPS Clk is 2.4MHz clock line from RAP3G to Tahvo used for switch mode regulator synchronizing in active mode. In deep sleep mode, when VCTCXO is off, this signal is set to '0'-state.

BT Clk is 38.4MHz signal from Hinku ASIC to BT module. CLK600 is 600KHz signal from Tahvo to APE VCORE SMPS. The clock source is internal RC oscillator in Tahvo (during

the RM-1 power-up sequence) or RAP3G SMPS Clk divided by 4 after the power-up sequence.

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Figure 96 Clocking scheme

Bluetooth

Bluetooth provides a fully digital link for communication between a master unit and one or more slave units. The system provides a radio link that offers a high degree of flexibility to support various applications and product scenarios. Data and control interface for a low power RF module is provided. Data rate is regulated between the master and the slave.

The device Bluetooth is based on CSR's BC3 BT ASIC. The UART1 interface handles the transfer of control and data information between Helen3 and the BT system

(BC3). The PCM interface is used for audio data transfer between RAP3G and the BT system (BC3).

USB

USB (Universal Serial Bus) provides a wired connectivity between host PC and peripheral devices. USB is a differential serial bus for USB devices. USB controller (RAP3G) supports USB specification revision 2.0

with full speed USB (12Mbps). The device is connected to the USB host through the Pop-PortTM connector. The USB bus is hot plugged capable, which means that USB devices may be plugged in/out at any time.

SIM interface

The device has one SIM (Subscriber Identification Module) interface and the SIM card location is under the battery. SIM interface consists of internal interface between RAP3G and Retu and an external interface between Retu and SIM contacts. SIM interface functionality is located in RAP3G while Retu takes care of power up/down, card detection, ATR counting and level shifting. For Retu external SIM IF connections, see SIM interface

connections (Page 9–31).

The SIM IF is shown in the following figure:

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Figure 97 SIM interface

Retu handles SIM card detection and the detection method is based on the BSI line. Due to location of the SIM card removal of the battery causes quick power down of the SIM IF. The Retu SIM1 interface supports both the

1.8V and 3.0V SIM cards. SIM interface voltage is first 1.8V when the SIM card is inserted and if the card does not response to the ATR (Answer To Reset) 3V interface voltage is used. The data communication between the card and the phone is asynchronous half duplex and the clock supplied to cards is 1-5MHz, which is 3.2MHz by default (in GSM system). The data baud rate is SIM card clock frequency divided by 372 (by default), 64, 32 or 16.

RS MMC interface

The reduced size (24mm x 18mm x 1.4mm) multimedia card slot is located under the battery. The device supports RS MMC hot insertion so it is possible to remove/insert the card when the phone is powered on.

Figure 98 Reduced size MMC

RS MMC card is connected to the Helen3 processor MMC/SDIO2 (1.8V) interface. MMC interface is shown in the following figure:

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Figure 99 MMC interface

The basic multimedia card concept is based on the following communication signals CLK, CMD and DAT. With each cycle of the CLK signal one bit transfer on the DAT and CMD line is done. The maximum CLK frequency is 20MHz (specified in multimedia card specification). Maximum used CLK frequency at the time is 16MHz. CMD is a bi-directional command channel used for card initialization and data transfer commands. CMD signal has two operational modes open-drain and push-pull mode. Open-drain mode is used for card initialization and pushpull mode for fast command transfer. CMD commands are sent by the host and CMD responses are sent by the card. DAT is a bi-directional data channel, which operates at push-pull mode.

The detection of RS MMC card removal/insertion is done via RS MMC cover switch. Removing RS MMC while writing to RS MMC may corrupt data in RS MMC. RS MMC cover switch gives an interrupt to the SW while the cover is opened or closed. After RS MMC cover lid opening (RS MMC SW signal is connected to GND via cover switch) the SW power down the RS MMC card and switches off the RS MMC power supply (VSIM2). When the RS MMC cover lid is closed (RS MMC SW signal is internally connected in Helen3 to 1.8V) the card should be identified if card exists.

Battery interface

The battery interface supports NMP Lynx battery interface for the BL-5C battery. This interface consists of three connectors: VBAT, BSI and GND. BSI line is used to recognize battery capacity by a battery internal pull down resistor.

Figure 100 Battery pin order

Battery temperature is estimated by measuring separate battery temperature NTC via BTEMP line, which is located on the transceiver PWB, in a place where phone temperature is most stabile.

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