Nevion FSR-HD User Manual

FSR-HD

HD-SDI Frame Synchronizer with Audio De-Embedding

User manual

Rev. G

Nevion

Nordre Kullerød 1
3241 Sandefjord
Norway
Tel: [phone]

nevion.com

FRS-HD Rev. G

Nevion Europe
P.O. Box 1020

3204 Sandefjord, Norway
Support phone 1: [phone]
Support phone 2: [phone]

Nevion USA

1600 Emerson Avenue

Oxnard, CA 93033, USA

Toll free North America: [phone]

Outside North America: +1 (805) 247-

8560

E-mail: [e-mail]

See http://www.nevion.com/support/ for service hours for customer support globally.

Rev.

Repl.

Date

Sign

Change description

G

F

2015-01-21

AJM

Changed text in Chapter 2.
Updated logo.

F 5 2012-12-04

JD

Changed HD sensitivity

5 4 2012-08-10

TB/JD

Added information on audio min/max delay.
Updated template

4 3 2008-12-15

NBS

Rewritten Chapter 3.5.1.
Changed text in Chapters 1, 3 and 4.
Corrected Chapter 3.7.1.

3 2 2008-11-12

SHH

Added information about termination of loop­thru on rev.1 backplanes.
Added drawing and description of termination
on rev.2 backplane

2 1 2008-10-21

NBS

Corrected information about FACTORY reset.

1 0 2008-06-11

SHH /

AS

Changed name on manual from FRS-HD­DMUX to FRS-HD.
Change in functionality description:
Page 15: the remark that push button settings
are reset at power down was removed as this
setting is stored by the microcontroller.

0 - 2008-03-17

SHH

Initial release.

Nevion Support

Revision history

Current revision of this document is the uppermost in the table below.

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FRS-HD Rev. G

Contents

1 Product overview ............................................................................................. 4

1.1 Product versions ..................................................................................................... 4

2 Specifications .................................................................................................. 5

3 Description ...................................................................................................... 7

3.1 Data path ................................................................................................................ 7

3.2 Video blocks overview ............................................................................................ 7

3.3 Optical/ Electrical input selection ............................................................................ 8

3.4 De-glitcher .............................................................................................................. 8

3.5 Frame synchronizer ................................................................................................ 8

3.5.1 Frame sync mode ................................................................................................ 8

3.5.2 Frame delay mode .............................................................................................13

3.6 Video generator .....................................................................................................13

3.7 Video processing block ..........................................................................................14

3.7.1 Gain and offset ...................................................................................................14

3.7.2 Video payload legalizer ......................................................................................14

3.8 EDH processing block ...........................................................................................14

3.9 Video output selection ...........................................................................................14

3.10 Audio blocks overview .........................................................................................14

3.11 Audio de-embedder .............................................................................................15

3.12 Audio delay .........................................................................................................15

3.13 Audio cross point matrix ......................................................................................15

3.14 Audio generator ...................................................................................................15

3.15 Audio processing block ........................................................................................16

3.16 Audio embedder ..................................................................................................16

3.17 Analog audio output.............................................................................................16

4 Configuration ................................................................................................. 17

4.1 Manual mode ........................................................................................................17

4.1.1 DIP switch functions ...........................................................................................17

4.1.2 Rotary switch and push buttons ..........................................................................19

4.1.3 Slide switches .....................................................................................................19

4.2 GYDA mode ..........................................................................................................20

4.2.1 Information page ................................................................................................20

4.2.2 Configuration page .............................................................................................21

5 Connections .................................................................................................. 23

6 Operation ...................................................................................................... 24

6.1 Front panel LED indicators ....................................................................................24

6.2 GPI alarms ................................................................................................ ............24

6.3 GPI/ AES/ Data connections 8pin modular jack .....................................................24

6.4 RS422 commands .................................................................................................25

6.4.1 FLP4.0 required commands ...............................................................................25

6.4.2 Normal control blocks .........................................................................................26

6.4.3 Commands intended for debug/lab use only .......................................................30

General environmental requirements for Nevion equipment ............................ 31

Product Warranty ............................................................................................. 32

Appendix A Materials declaration and recycling information ............................ 33

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FRS-HD Rev. G

FRS-HD-SDI

SD/HD frame sync with internal audio handling and GPI I/O
control, 4 SDI outputs

FRS-HD-DMUX

SD/HD frame sync, analogue stereo audio out, AES out (or RS­422 data out, replaces AES), 4 SDI outputs

FRS-HD-SDI-R

SD/HD frame sync with high sensitivity 9/125um single mode
optical input, internal audio handling and GPI I/O control, 4 SDI
outputs

FRS-HD-DMUX-R

SD/HD frame sync with high sensitivity 9/125um single mode
optical input, analogue stereo audio out, AES out (or RS-422
data out, replaces AES), 4 SDI outputs

1 Product overview

Figure 1: Simplified block diagram of the FRS-HD-DMUX card

The Flashlink FRS-HD-DMUX synchronizes a HD-SDI or a SD-SDI input to a reference.
The reference can be a traditional black & burst signal or tri-level sync. The HD-SDI/SD­SDI output can be adjusted relative to the sync signal. The FRS-HD-DMUX also has a
de-glitcher to give error-free synchronous switching.

FRS-HD-DMUX can be used as a frame delay. The adjustable delay is then relative to
the input SDI signal.

The audio embedded on the SDI is de-embedded and can be delayed relative to the
video. Each audio stereo pair can be swapped through a matrix before they are
embedded back to the SDI. It is also possible to disable the embedder function and keep
the SDI stream unaltered.

The user parameters of the card can either be changed by switches on the board, or by
the control interface GYDA.

1.1 Product versions

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FRS-HD Rev. G

Data rate optical:

270 – 1485 Mbps

Sensitivity

- HD-SDI (1485 Mbps):

Better than -20dBm

- SD-SDI (270 Mbps):

Better than -22dBm

Detector overload
threshold:

Min. -3dBm
Detector damage threshold:

>+1dBm

Optical wavelength:

1200-1620nm

Transmission circuit fiber:

9/125um Single Mode

Connector return loss:

>40dB w/ SM fiber

Connector:

SC/UPC

Connectors

75 Ohm BNC

Equalization

Automatic;

- >300m @270Mbps w/Belden 8281, with BER < 10E-12

- >100m @1485Mbps w/Belden 1694A, with BER < 10E-12

Input Return loss

>15dB, 5MHz -1.5GHz

Jitter tolerance

SD limit:

- 10Hz-1kHz: >1 UI

- 10kHz – 5MHz: >0.2 UI

HD limit:

- 10Hz-100kHz: >1 UI

- 100kHz–10MHz: >0.2 UI

Connector

2x 75 Ohm BNC

Format

Black & Burst, Tri-level

Input Return loss
Termination

>35dB @ < 10MHz,
30dB @ < 30MHz
Selectable internal or external 75 Ohm termination(FRS-SDI­DMUX-C1 rev.2 or later only)
75R termination on one of the sync inputs necessary on FRS­SDI-DMUX-C1 rev.1

Number of outputs

4

Connectors

75 Ohm BNC

Output Return loss

>15dB, 5MHz -1.5GHz

Output signal level

800mV +/- 10%

Output signal rise / fall time
20% - 80%

- SD limit: [0.4ns – 1.5ns]; <0.5ns rise/fall var.

- HD limit: < 270ps, <100ps rise/fall var.

Amplitude overshoot

<10%

Output timing jitter

- SD: <0.2 UI

- HD: <1 UI

Output alignment jitter

- SD: <0.15 UI

- HD: <0.15 UI

2 Specifications

Optical SDI input

Electrical SDI input

Electrical Sync input

Electrical SDI outputs

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FRS-HD Rev. G

Number of outputs

1 stereo pair

Connectors

2 x WECO audio connectors

Impedance

< 66R

Dynamic range

>100dB(A)

Crosstalk

< -60dB 20Hz-20kHz

THD+N

-70dB

Frequency response

20Hz-20kHz +/- 0.5dB

Maximum output level

24dBu +/- 1dB

Common mode DC immunity

0 – 48V

Level adjustment range

0 – 24dBu with 1db step

Two tone intermodulation

< -80dB

Number of outputs

1

Connectors

TP45

Return loss

110R +/-20% 0.1MHz – 6.144MHz

Output jitter

<0.0025UI peak

SD, 270 Mbps

SMPTE 259M, SMPTE 272M-AC

HD, 1485 Mbps

SMPTE 292M, SMPTE 274M, SMPTE 291M, SMPTE 296M,
SMPTE 299M

Video switch point definition
and sync

SMPTE RP168 (tri-level), SMPTE 170m, ITU-R. BT.470
AES

AES3-1996

Optical

SMPTE 297M, SMPTE 292M

EDH

Compliant to SMPTE-RP165

Video Payload Identification

SMPTE 352M-2002

Power consumption

< 5W

- 4.5W/5V, 0.9W/15V, 0.0W/-15V with optics

- 3.5W/5V without optics

Analog Audio output

AES output

Supported standards

Other

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FRS-HD Rev. G

De-glitcher

Frame sync
control logic

Video/

Audio

Frame

buffer

Video

Generator

Video

processing

Audio

embedder

Reclocker

And

De-serializer

To audio

de

-

embedder

Optical

receiver

Cable

equalizer

From audio

processing

EDH

processing

Serializer

and

reclocker

2x2
output
switch

10bit

10bit

3 Description

3.1 Data path

HD/SD-SDI input is selected from either optical or electrical input and equalized, re­clocked and de-serialized and transferred to a processing unit called an FPGA. In the
FPGA the signal is first sent through a de-glitcher that cleans up errors that might appear
on lines, for instance due to switching. After the video is de-glitched, it is sent along two
paths; it is given to a frame-store buffer, and it is given to the audio de-embedder.

The 16 audio channels coming from the de-embedder are bundled in pairs and sent to
an audio store buffer. The audio is fetched from the audio store buffer according to a
user specified delay and sent to an Audio Cross Point. The audio out of the Audio Cross
Point can be any pair of audio channels de-embedded from the incoming video stream,
an internal 1 kHz sine or an internal “black sound”. “Black sound” is in function mute, but
it produces a waveform pattern on the AES output which is different from mute. From the
cross point outputs each channel pair enters an Audio Processing Block, where the
paired channels may be shuffled. After the audio processing block the audio enters the
Audio Embedder.

The video (with audio still inserted) is fetched from the frame buffer with the user
specified delay and sent to a Video processing block followed by an EDH processing
block. After the EDH block the video and audio is embedded according to the user
settings and the video is sent from the FPGA to a serializer that re-clocks the data and
output the SDI to a buffered output switch.

The buffered output switch is a 2x2 cross point with input 1 being the equalized and re­clocked input (non-processed) and input 2 being the output of the video processing. The
two outputs are sent to two paired (non-inverting and inverting) outputs.

There are also outputs for one stereo pair of analog audio and one AES. These outputs
are taken out from the Audio cross point and can be any stereo pair of audio channels
embedded on the incoming video stream, the internal 1 kHz sine generator or the internal
“black sound” generator.

3.2 Video blocks overview

Figure 2: Video function blocks

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FRS-HD Rev. G

3.3 Optical/ Electrical input selection

The FRS-HD-DMUX has both an optical (option, see Chapter 1.1) and an electrical input.
The input can be chosen either by an automatic selection with priorities and rule of
switching or by manual selection. This feature is only available through GYDA.

Automatic selection mode

In GYDA the video in mode choice is set to auto. Three input choices can be made for
three priorities; optical, electrical or mute. This priority sets the order in which the card
will look for a valid input.

It is also possible to set a rule for when the input should be switched to the next priority.
The rules are:

 lol = loss of lock
 los = loss of signal
 EDH = Errors are found in the video

Hold time and lock time can also be set for signals. This is described in Chapter 3.5.1.

3.4 De-glitcher

The de-glitcher corrects timing errors within a line. The de-glitcher has a 2048 samples

buffer. When the first signal is present, we call it the “initial phase signal”, data is taken

from the centre of this buffer. If the timing reference of the video signal changes, when
for instance a new source being switched into the signal path, the timing errors occurring
by this change will be corrected if the new timing reference is within +/-1024 samples of
the “initial phase signal”. This also goes for all consecutive timing references.

If a signal occurs that is more than +/-1024 samples off relative to the “initial phase

signal”, the output will repeat the last frame, refill the 2048 samples buffer and take out

data from the centre of the buffer. This new signal is now considered the “initial phase
signal”.

Hence, it produces an error free video output without frame wrapping when the video
input comes from a router with synchronous input video signals that all lies within +/­1024 samples of each other.

3.5 Frame synchronizer

The frame synchronizer consists of a frame store buffer and some control logic. The
frame store buffer can store up to 8 full HD frames. Data is fetched from this buffer
according to the user settings by force of the control logic. The control logic sets the
frame synchronizer into different modes dependent on the presence of a sync input.

3.5.1 Frame sync mode

If a sync input (B&B or Tri-level) is present, the frame synchronizer will output a signal
that has a delay relative to this signal. Two parameters can be set; "Phase delay" and
"Video delay".

Figure 3: Gyda view of the video delay settings

Let us first focus on the phase delay, which also may be called “output phase delay”.
This parameter can be positive or negative, and determines the relationship between the

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FRS-HD Rev. G

1

outgoing video and the sync signal. The parameter really determines a delay on an
internal sync signal, isync1. The output is synchronous with isync, see Figure 4.

Figure 4: Positive phase delay

Figure 4 show how the sync signal and the isync signal would look on an oscilloscope, if
converted to analogue signals. The delay of isync can be given in frames, lines, and
samples. The delay can be negative, see Figure 5.

Figure 5: Negative phase delay

The phase delay can thus be written in several ways, a large positive delay will equal a
small negative delay, because there is wrap-around on a frame basis. It follows that it is
not useful to specify a phase delay larger than 1 frame. Strictly speaking the range could
have been limited to -1/2 frame to 1/2 frame. For convenience, the delay range is allowed
to be from -1 frame + 1100 samples to 1 frame – 1100 samples.

In order for FRS-HD-DMUX to honor the phase delay setting, it should ideally delay the
incoming video between 0 to 1 frames. Because the processing delay through the card
is 2 lines minimum, the actual window is between 2 lines and 1 frame + 2 lines. Hence,
with the parameter (minimum) video delay set to 2 lines (the least number possible for
the parameter); the output video will be between 2 lines and 1 frame + 2 lines delayed,
with respect to the incoming video. A common occurrence in practical use is to
synchronize an incoming video with a sync, but to let the outgoing video lead some
samples or lines to the sync. This can easily be accomplished. Say that we want the
outgoing video to occur 50 samples before the sync. We will then set the phase delay to

-50 samples, and the video delay parameter to 2 lines. For convenience, let us assume

Note that isync is not a physical entity, but a term used in this context to explain the delay process and the use of the

configurable parameters related to this process.

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FRS-HD Rev. G

that the incoming video is iso-synchronous, but that it lags 20 lines after the sync. We
will then have the situation shown in Figure 6.

Note that the numbers in circles in the next figures are visualizing the video frames.

Figure 6: Example of delayed outgoing video

To match larger processing delays, one will want to first delay the incoming video, and
then synchronize the video. This is equivalent to introducing a delay line for the incoming
video, and then synchronize the output of the delay line with sync. In effect, one moves
the delay-window start; this is equivalent with setting of the video delay to a larger value.

Let us assume that the video delay is set to 2 frames, 200 lines. In that case the outgoing
video will be between 2 frames + 200 lines and 3 frames + 200 lines delayed with respect
to the incoming video. For convenience, let us assume that the incoming video is iso­synchronous, but that it lags 25 lines after the sync. Let us also assume that the phase
delay is set to -60 samples. We will then have the situation shown in Figure 7.

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