Nevion DWC-HD, DWC-HD-R, DWC-HD-DMUX-R, DWC-HD-DMUX User Manual

DWC-HD

HD-SDI to SD-SDI Down-converter

(with optional Audio De-embedding)

User manual

Rev. 5

DWC-HD Rev. 5

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Nevion Support

Nevion Europe

P.O. Box 1020

3204 Sandefjord, Norway

Support phone 1: [phone]

Support phone 2: [phone]

Nevion USA

1600 Emerson Avenue

Oxnard, CA 93033, USA

Toll free North America: [phone]

Outside North America: [phone]

E-mail: [e-mail]

See http://www.nevion.com/support/ for service hours for customer support globally.

Revision history

Current revision of this document is the uppermost in the table below.

Rev.

Repl.

Date

Sign

Change description

5 4 2011-01-03

AA

New template.

4 3 2008-12-15

NBS

Added more information about minimum delay.

3 2 2008-11-24

NBS

Corrected number of SDI outputs in Chapter 1;

Corrected table in Chapter 5;

Added specification of minimum delay in Chapter 2.

2 1 2008-07-09

NBS

Added Block diagram in Chapter 1.

1 0 2008-06-18

NBS

Removed monitoring versions.

0 - 2008-06-12

TB

First version for public release.

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Contents

1 Product overview ..................................................................................................... 4

1.1 Product versions .............................................................................................................. 4

2 Specifications .......................................................................................................... 6

3 Description ............................................................................................................... 9

3.1 Data path ......................................................................................................................... 9

3.2 Video blocks overview ................................................................................................... 10

3.3 Optical/ Electrical input selection ................................................................................... 10

3.4 De-glitcher ..................................................................................................................... 10

3.5 Scaling block ................................................................................................................. 11

3.6 Frame synchronizer ....................................................................................................... 11

3.7 Video generator ............................................................................................................. 13

3.8 Video processing block .................................................................................................. 14

3.9 EDH processing block ................................................................................................... 14

3.10 Video output selection ................................................................................................. 14

3.11 Video DAC ................................................................................................................... 14

3.12 Audio overview ............................................................................................................ 15

3.13 Audio de-embedder ..................................................................................................... 16

3.14 Audio delay .................................................................................................................. 16

3.15 Audio cross point matrix .............................................................................................. 16

3.16 Audio fallback options .................................................................................................. 16

3.17 Audio generator ........................................................................................................... 16

3.18 Audio processing block ................................................................................................ 16

3.19 Audio embedder .......................................................................................................... 17

3.20 Analog audio output ..................................................................................................... 17

4 Configuration ......................................................................................................... 18

4.1 DIP switch functions ...................................................................................................... 18

4.2 FACTORY reset function ............................................................................................... 19

4.3 GYDA mode .................................................................................................................. 20

5 Connections ........................................................................................................... 22

6 Operation ............................................................................................................... 23

6.1 Front panel LED indicators ............................................................................................ 23

6.2 RS422 commands ......................................................................................................... 23

General environmental requirements for Nevion equipment..................................... 31

Product Warranty ...................................................................................................... 32

Appendix A Materials declaration and recycling information..................................... 33

EC Declaration of Conformity ................................................................................... 34

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1 Product overview

The Flashlink DWC-HD-DMUX converts an HD-SDI input signal to an SD-SDI output signal
with user selectable aspect ratio.

Two digital outputs and a set of configurable analog video outputs are provided, all of which
can be set to output the SD signal or the re-clocked original HD signal.

For SD input the card will act as an SD frame synchronizer with an adjustable delay relative
to the sync signal. This frame synchronizer functionality is also present when down­converting. The card is prepared to accept black & burst or a tri-level signal from the frame.

The DWC-HD-DMUX also has a de-glitcher to give error-free synchronous switching.

The audio embedded in the HD-SDI or SD-SDI stream is de-embedded and can be delayed
relative to video. Each audio channel can be swapped in an audio matrix before they are re­embedded in the SD-SDI data output stream. For SD-SDI inputs it is possible to turn
embedding completely off and leave the SDI stream unaltered.

A selection of user parameters of the card can be controlled by switches on the board.
Complete control of all parameters is available by use of the Flashlink RS422 Control
Protocol Version 4, which is supported by the Gyda system controller from software release

2.13.

Figure 1: DWC-HD-DMUX-R block diagram

1.1 Product versions

DWC-HD

HD down-converter. With 2XSDI out, SD/HD analog out, internal

audio handling, and frame synchronizer functionality.

DWC-HD-R

HD down-converter. With high sensitivity 9/125µm single mode

optical input, 2XSDI out, SD/HD analog out, internal audio handling,
and frame synchronizer functionality.

DWC-HD-DMUX

HD down-converter. With 2XSDI out, SD/HD analog out, internal

audio handling, analog stereo out, AES (or RS-422 data) out, and
frame synchronizer functionality.

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DWC-HD-DMUX-R HD down-

converter. With high sensitivity 9/125µm single mode

optical input, 2XSDI out, SD/HD analog out, internal audio handling,
analog stereo out, AES (or RS-

422 data) out, and frame

synchronizer functionality.

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2 Specifications

Optical SDI input

Data rate optical:

270 – 1485 Mbps

Sensitivity

- HD-SDI (1485 Mbps):

Better than -22dBm

- SD-SDI (270 Mbps):

Better than -22dBm

Detector overload threshold:

Min. -3dBm

Detector damage threshold:

>+1dBm

Optical wavelength:

1200-1620nm
Transmission circuit fiber:

9/125um Single Mode

Connector return loss:

>40dB w/ SM fiber

Connector:

SC/UPC

Electrical SDI input

Connectors

75 Ohm BNC

Equalization

Automatic:

- >300m @270Mbps w/Belden 8281, BER < 10E-12

- >100m @1485Mbps w/Belden 1694A, BER < 10E-12

Input Return loss

>15dB, 5MHz -1.5GHz

Jitter tolerance

- SD limit:

- 10Hz-1kHz: >1 UI

- 10kHz – 5MHz: >0.2 UI

- HD limit:

- 10Hz-100kHz: >1 UI

-

100kHz–10MHz: >0.2 UI

Electrical Sync input

Connector

75 Ohm BNC

Format

Black & Burst, Tri-level

Input Return loss

<-35dB @ < 10MHz,
30dB @ < 30MHz

Electrical SDI outputs

Number of outputs

2

Connectors

75 Ohm BNC

Output Return loss

>15dB, 5MHz -1.5GHz

Output signal level

800mV +/- 10%

Output signal rise /
fall time, 20% - 80%

- SD limit: [0.4ns – 1.5ns]; <0.5ns rise/fall var.

- HD limit: < 270ps, <100ps rise/fall var.

Amplitude overshoot

<10%

Output timing jitter

- SD: <0.2 UI

-

HD: <1 UI

Output alignment jitter

- SD: <0.15 UI

- HD: <0.15 UI

Analog Video output, NTSC/PAL

Number of outputs

1 Component RGB/ YUV or 3 CVBS

Connector

3 x 75R BNC

DC offset

< 0±15mV

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White level, NTSC

100±1 IRE

Sync level, NTSC

40±1 IRE

Return loss

> 35dB @ 10MHz, >40dB @ 5MHz

White level, PAL

100±1 IRE

Sync level, PAL

40±1 IRE

Diff gain

<0.5%

Diff phase

<1deg

AM noise

< -60dB

PM noise

< -60dB

S/N

< -60dB

2T K-factor
(2T pulse distortion)

< 0.5%
Luma non-linearity

< 2%

Output resolution

10 bits

Analog Video output, HD

Number of outputs

1 component RGB/ YPbPr

Connector

3 x 75R BNC

DC offset

< 0±15mV

White level

100±1 IRE

Return loss

> 30dB @ 30MHz

Output resolution

10 bits

Analog Audio output

Number of outputs

1 stereo pair

Connectors

2 x WECO audio connectors

Impedance

< 66R

Dynamic range

>100dB(A)

Crosstalk

< -60dB 20Hz-20kHz

THD+N

-70dB

Frequency response

20Hz-20kHz +/- 0.5dB

Output level

24dBu +/- 1dB

Common mode DC
immunity

0 – 48V
Level adjustment range

0 – 24dBu with 1db step

Two tone intermodulation

< -80dB

Output resolution

24 bits

AES output

Number of outputs

1

Connectors

WECO audio connector

Return loss

110R +/-20% 0.1MHz – 6.144MHz

Output jitter

<0.0025UI peak

Supported standards

SD, 270 Mbps

SMPTE 259M, SMPTE 272M-AC

HD, 1485 Mbps

SMPTE 292M, SMPTE 274M, SMPTE 291M, SMPTE 296M,
SMPTE 299M

Analog video

SMPTE 170M, SMPTE 274M, ITU-R. BT.470,
ITU-R. BT.709 Part 2

Centre of picture definition

SMPTE RP187, ITU-R. BT.470

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Aspect ratio preservation

SMPTE RP199-1999, SMPTE RP221

Color space conversion

HD: ITU-R. BT.709

SD: ITU-R. BT.601

See also ITU-R. BT.1361 for more information

Video switch point
definition and sync

SMPTE RP168 (tri-level), SMPTE 170M, ITU-R. BT.470
AES

AES3-1996

Optical

SMPTE 297M, SMPTE 292M

EDH

Compliant to SMPTE RP165

Video Payload
Identification

SMPTE 352M-2002

Minimum video signal delay through processing

Input standards

Minimum delay [Field+Lines]

Full frame

Cropped edge

Letterbox (NTSC)

Letterbox (PAL)

Regular input standards:

1920/1080i50

0+10

0+41

0+44

1920/1080i59.94

0+10

0+41

0+44

1280/720p50

0+10

0+41

0+44

1280/720p59.94

0+10

0+41

0+44

Progressive input with low frame rate:

1920/1080p25

1+10

1+41

1+44

1920/108p29.97

1+10

1+41

1+44

1280/720p25

1+10

1+41

1+44

1280/720p29.97

1+10

1+41

1+44

Input standards for telecine converters:

Minimum delay [Frame+Lines]

1920/1080p23.97

1+10

1+41

1+44

1280/720p23.97

1+10

1+41

1+44

Other

Power consumption

5V – 5.3W (4.9W without optical receiver)

15V – 2.55W

-15V – 0.7W

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3 Description

3.1 Data path

The HD/SD-SDI input selected from the optical or electrical input is equalized, re-clocked and
de-serialized and transferred to a processing unit (FPGA). In the FPGA the signal is sent
through a de-glitcher that cleans up erroneous video lines, for instance due to switching.
After the de-glitcher the video is sent to the Audio de-embedders, where audio is split from
the video.

3.1.1 Audio data path

The 16 audio channels coming out of the de-embedder are bundled in pairs and sent to an
audio store buffer. After a user specified delay the audio is fetched from the audio store
buffer and sent to an Audio Cross Point. The 10 audio outputs from the Audio Cross Point
can be any pair of audio channels de-embedded from the incoming video stream, a
generated 1 kHz sine, or a generated black sound (a legal audio stream with silence only).
As part of the audio cross point, missing output pairs can be replaced with generated fallback
signals. From the cross point outputs each stereo pair enters an Audio Processing Block
where channels can be processed or rearranged within each channel pair. Finally, eight
stereo pairs are routed to the Audio Embedder and the two remaining pairs are sent to the
audio DAC and the AES out, respectively.

3.1.2 When down-converting HD video

The video is routed to a Scaling block and the resulting SD video is passed to a Frame
synchronizer block. If video is missing, an internal video generator can be switched in as a
fallback source. The video then passes through a Video processing block with an integrated
Legalizer, before entering an EDH processing block where the user can select to insert

updated EDH flags. Although audio is re-embedded before the video processing block, the
video processing and EDH processing blocks will not manipulate the audio data.

After passing the EDH block, the video stream with embedded audio is sent in parallel out of
the FPGA and into a serializer that re-clocks the data and sends the SDI to a buffered output
switch.

The buffered output switch can be viewed as 3 simple switches, each selecting between the
equalized and re-clocked output (Through mode) and the down-converted output (Processed
mode). The output of the first two switches are sent to two paired (inverting and non­inverting) digital outputs, whereas output of the third switch is sent to the onboard video
DAC.

3.1.3 When frame synchronizing SD video

The video data path when operating as an SD frame synchronizer is conceptually the same
as when down-converting, except that the Scaling block is not needed, placing the Frame
synchronizer block directly after the de-glitcher.

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3.2 Video blocks overview

Figure 2: Video function blocks when down-converting HD to SD

3.3 Optical/ Electrical input selection

The DWC-HD-DMUX has both an optical and an electrical input. The active input can be
chosen either by an automatic selection based on a prioritized list of inputs and a selected
rule of switching or by manual selection. When in Gyda over-ride mode (control by DIP
switches), the card will use the priorities and rule saved from the last Gyda session.

Automatic selection mode

Mode under Video in in Gyda must be set to auto. Three input choices can be made for three
priorities; optical, electrical or mute. The priority is the order in which the board will look for a
valid input.

It is also possible to set a rule for when the input should be switched to the next priority. The
rules are:

- lol (loss of lock)

- los (loss of signal)

- EDH (Errors are found in the video frame)

Hold time determines how long a signal has to be missing/unlockable/contain errors to be
considered lost, while Lock time determines how long a higher prioritized signal has to be
present/locked/error free before it again can be considered to be present and stable. This is
described in more detail in chapter 3.6.1, most mainly in the two “If video input disappears”
sections.

3.4 De-glitcher

The de-glitcher corrects timing errors within a line of video.

The de-glitcher has a buffer of 13.6 µs for HD and 50 µs for SD. When the first signal is
present, we call it the “initial phase signal”, data is taken from the centre of this buffer. If the
timing reference of the video signal changes, for instance when a new source is being
switched into the signal path, the timing errors occurring by this change will be corrected if
the new timing reference is within ±6.8 µs (for HD, ±25 µs for SD) of the “initial phase signal”.
This also goes for all consecutive timing references.

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If a signal occurs that is more than ±6.8 µs (for HD, ±25 µs for SD) off relative to the “initial
phase signal”, the output will repeat the last frame, refill the buffer and take out data from the
centre of the buffer. This new signal is now considered the “initial phase signal”.

Hence, it produces an error free video output without frame wrapping when the video input
comes from a router with synchronous input video signals that all lies within ±6.8 µs (for HD,
±25 µs for SD) of each other.

3.5 Scaling block

The Scaling block is the heart of the down-converter. The frame rate of the HD input dictates
the video standard that the Scaling block will produce: If the input is 50Hz-based, e.g.
1080/25p, the output will be 576/50i, and if the input is 60Hz-based (with or without
pulldown), e.g. 720/59.94p or 1080/24p, the output will be 486/29.97i.

The following assumes that the aspect ratio of the incoming HD is 16:9, and that the pictures
are such that objects are shown geometrically correct on a 16:9 monitor. The user must then
set the crop and aspect ratio of the output and the illustration below shows the options
available. The figure assumes a 4:3 monitor that ignores the WideScreen Signaling bits
(WSS bits can be inserted automatically according to the selected aspect ratio, or they can
be turned off or replaced by a user selected value. See chapter 3.11 for details.) Had the
monitor in the example processed WSS bits, the full-frame picture in the lower left would’ve
been internally converted and shown letterboxed to preserve picture geometry. The cropped
edge 4:3 and letterboxed 16:9 options should normally only be used for 4:3 monitor.

Figure 3: Picture cropping and geometry options

3.6 Frame synchronizer

The frame synchronizer consists of a frame store buffer and some control logic. The frame
store buffer can store up to 8 SD frames. When the input is an HD source to be converted to
SD, the frame synchronizer is placed after the Scaling block. When the input is SD, the frame