V850/SC1, V850/SC2, and V850/SC3 are trademarks of NEC Corporation.
Windows is either a registered trademark or a trademark of Microsoft Corporation in the United States
and/or other countries.
PC/AT is a trademark of International Business Machines Corporation.
Ethernet is a trademark of Xerox Corporation.
•
The information in this document is current as of May, 2002. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data
books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products
and/or types are available in every country. Please check with an NEC sales representative for
availability and additional information.
•
No part of this document may be copied or reproduced in any form or by any means without prior
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•
NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
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liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC or others.
•
Descriptions of circuits, software and other related information in this document are provided for illustrative
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circuits, software and information in the design of customer's equipment shall be done under the full
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parties arising from the use of these circuits, software and information.
•
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agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
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redundancy, fire-containment, and anti-failure features.
•
NEC semiconductor products are classified into the following three quality grades:
"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products
developed based on a customer-designated "quality assurance program" for a specific application. The
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Customers must check the quality grade of each semiconductor product before using it in a particular
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support systems and medical equipment for life support, etc.
The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
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(Note)
(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.
(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for
NEC (as defined above).
M8E 00. 4
User’s Manual U15776EJ1V0UM
3
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, pIease contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
•
Device availability
•
Ordering information
•
Product release schedule
•
Availability of related technical literature
•
Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
•
Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California
Tel: 408-588-6000
800-366-9782
Fax: 408-588-6130
800-729-9288
NEC do Brasil S.A.
Electron Devices Division
Guarulhos-SP, Brasil
Tel: 11-6462-6810
Fax: 11-6462-6829
1.5Contents in Carton ....................................................................................................................................... 13
1.6Connection Between IE-703002-MC and IE-703089-MC-EM1.................................................................... 15
CHAPTER 2 NAMES AND FUNCTIONS OF COMPONENTS ...............................................................19
2.1Component Names and Functions of IE-703089-MC-EM1 ........................................................................ 20
4.1VDD and PORTVDD of Target System............................................................................................................ 28
4.2I/O Signal ....................................................................................................................................................... 29
4.3VPP Signal ......................................................................................................................................................29
4.4NMI Signal Mask Function ........................................................................................................................... 29
CHAPTER 5 DIFFERENCES BETWEEN TARGET DEVICE AND TARGET INTERFACE CIRCUIT.... 30
1-2Contents in Carton.............................................................................................................................................13
4-1Schematic Diagram of Power Supply Acquisition..............................................................................................28
4-2I/O Signal Flow Path..........................................................................................................................................29
5-1Equivalent Circuit of Emulation Circuit...............................................................................................................31
2-3JP1 Setting in IE-703002-MC............................................................................................................................25
2-4JP3 and JP4 Setting in IE-703002-MC.............................................................................................................. 25
Caution Emulation cannot be performed by inputting a clock from the target system.
The specifications of OSC1 are as follows.
V850/SCx
I/O
chip
X1
1 MΩ
GND
1
X2
GND
7
7
8
1
2
10 pF20 MHz
User’s Manual U15776EJ1V0UM
10 pF
23
2.2.2 Subclock setting
CHAPTER 2 NAMES AND FUNCTIONS OF COMPONENTS
Table 2-2. Subclock Setting
IE-703089-MC-EM1 SettingEmulator Usage
Note 2
Environment
When using emulator as
Clock Supply Method
Internal clock
Note 1
OSC2
standalone unit
When using emulator with
target system
Internal clock
Note 1
17
(Oscillator mounted)
Notes 1. A clock input by an oscillator cannot be used for the internal clock.
2. To use a subclock frequency other than 32.768 kHz, remove the resonator on OSC2 and mountan
oscillator.
The specifications of OSC2 are as follows.
V850/SCx
I/O chip
XT2XT1
GND
1
27 pF32.768 kHz727 pF
GND
JP6
7
8
(3-4 shorted: Fixed)
1
2
Caution Emulation cannot be performed by inputting a clock from the target system.
24
User’s Manual U15776EJ1V0UM
CHAPTER 2 NAMES AND FUNCTIONS OF COMPONENTS
2.3Illegal Access Detection ROM Setting
If using the IE-703002-MC for an in-circuit emulator for the V850/SCx by connecting the IE-703089-MC-EM1, set
JP1 of the IE-703002-MC as follows.
Table 2-3. JP1 Setting in IE-703002-MC
JP1Description
Note
Open
Illegal access detection ROM (mounted on IE-703089-MC-EM1) for V850/SCx is
used.
Note When JP1 is set to open, keep the removed jumper contact attached to one
JP1
pin as shown in the drawing on the right.
Jumper
contact
2.4CPU Operation Voltage Range Switching Setting
If using the IE-703002-MC for an in-circuit emulator for the V850/SCx by connecting the IE-703089-MC-EM1, set
JP3 and JP4 of the IE-703002-MC as follows.
Table 2-4. JP3 and JP4 Setting in IE-703002-MC
JP3, JP4Description
JP3
JP4
1
2
(Shorted)
1
2
3
(Open)
The operation voltage range of the IE-703002-MC is 3.0 to 5.5 V.
The power supply for PORTVDD is generated on the IE-703089-MC-EM1.
User’s Manual U15776EJ1V0UM
25
CHAPTER 2 NAMES AND FUNCTIONS OF COMPONENTS
2.5Address Output Setting of Separate Bus
When using the separate bus function while debugging using the IE-703089-MC-EM1, switching to the separate
bus output function is not possible by setting the memory address output register (MAM) by software.
Use DIP switch SW5 to output the address of the separate bus function while debugging using the IE-703089-MC-
EM1.
The switches of SW5 and their corresponding ports are shown in Table 2-5.
Figure 2-2. SW5
163425
ON
OFF
Table 2-5. SW5 Setting
SwitchSettingSelection of Alternate-Function Pin
ONP113 to P110 (port mode)1
OFFA4 to A1 output to P113 to P110 (memory address output function of separate bus)
ONP103 to P100 (port mode)2
OFFA8 to A5 output to P103 to P100 (memory address output function of separate bus)
ONP107 to P104 (port mode)3
OFFA12 to A9 output to P107 to P104 (memory address output function of separate bus)
ONP34 (port mode)4
OFFA13 output to P34 (memory address output function of separate bus)
ONP35 (port mode)5
OFFA14 output to P35 (memory address output function of separate bus)
ONP33 (port mode)6
OFFA15 output to P33 (memory address output function of separate bus)
26
User’s Manual U15776EJ1V0UM
CHAPTER 3 FACTORY SETTINGS
ItemDescriptionRemark
OSC1
OSC2
JP1 to JP4
GND
GND
V850/SCx
I/O chip
X1X2
1 MΩ
1
10 pF20 MHz
V850/SCx
I/O chip
XT2XT1
1
27 pF32.768 kHz727 pF
123
(2-3 shorted)
10 pF
Pins 1 and 2: For mounting capacitor (10 pF)
Pins 6 and 7: For mounting capacitor (10 pF)
Pins 3 to 5: Crystal oscillator (20 MHz)
Pin 4: Open
20 MHz clock supplied for main clock
GND
7
Pins 1 and 2: For mounting capacitor (27 pF)
Pins 6 and 7: For mounting capacitor (27 pF)
Pins 3 to 5: Crystal oscillator (32.768 MHz)
Pin 4: Open
32.768 MHz clock supplied for subclock
GND
Pins 2 and 3: Short
Pin 1: Open
Use these jumpers with the factory settings.
JP5, JP6
SW1 to SW4
SW5
7
8
1
2
(3-4 shorted)
Pins 1 and 2: Open
Pins 3 and 4: Shorted
Pins 5 and 6: Open
Pins 7 and 8: Open
Use these jumpers with the factory settings.
1
3
3-6 side
Use these switches with the factory settings.
4
ON
OFF
6
(3-6 side)
163425
All bits ON (port mode)
User’s Manual U15776EJ1V0UM
27
CHAPTER 4 CAUTIONS
4.1V
and PORTVDD of Target System
DD
(1) VDD in the target system is used to sense the level for target system power supply ON/OFF.
• When VDD is lower than 3.5 V, it is judged that the target system is not connected, and mapping of the
target memory cannot be performed with a debugger (FCAN cannot be used).
• When VDD is 3.5 V or higher, it is judged that the target system is connected, and mapping of the target
memory can be performed with a debugger (FCAN can be used).
(2) PORTV
(n = 0 to 2) in the target system is not supplied directly to the emulator chip; it is connected to the
DDn
target voltage emulation circuit.
• When PORTV
• When PORTV
is lower than 3.3 V, VCC (5 V) in the internal emulator is supplied to the emulator chip.
DDn
is 3.3 V or higher, a voltage of the same potential as PORTV
DDn
in the target system is
DDn
generated and supplied to the emulator chip.
Figure 4-1. Schematic Diagram of Power Supply Acquisition
IE-703089-MC-EM1IE-703002-MC
ON/OFF?
Target system
DD0
V
PORTV
DDn
(n = 0 to 2)
Target voltage
emulation
VCC (5 V)
Relay
V850/SC3
I/O chip
Relay n
(n = 0 to 2)
VCC (5 V)
Target voltage emulation n
(n = 0 to 2)
Evaluation
chip
28
User’s Manual U15776EJ1V0UM
CHAPTER 4 CAUTIONS
(3) The V
(4) The following conditions must be satisfied when other than V
1. When FCAN is used, PORTV
signal from the target system is left open in the IE-703089-MC-EM1.
DD1
= V
DD0
DD1
≤ PORTV
DD1
(restricted by the power supply voltage conditions of the in-
DD2
= ADCVDD = PORTV
= PORTV
DD1
DD2
.
circuit emulator)
2. When ADC is used, V
= ADCVDD = 4.5 to 5.5 V
DD0
4.2I/O Signal
The input signal (NMI signal) from the target system, the I/O signals for ports 4, 5, 6, and 11, and the I/O signal for
port 9 are all delayed (tPD = 0.25 ns (typ.)) because they pass through Q switches QS3125, QS3384, and QS3244,
respectively, before being input to the emulator chip.
The DC characteristics also change. The input voltage becomes VIH = 2.0 V (MIN.), VIL = 0.8 V (MAX.), and the
input current becomes IIN = ±0.5 µA (MAX.).
Figure 4-2. I/O Signal Flow Path
IE-703089-MC-EM1
NMI signal
Target
system
Port signal
NMI pinQS3125
Port pin
QS3384/
QS3244
Emulator chip
4.3VPP Signal
The VPP signal from the target system is left open in the emulator.
4.4NMI Signal Mask Function
When using the P00/NMI pin in the port mode, do not mask the NMI signal.
User’s Manual U15776EJ1V0UM
29
CHAPTER 5 DIFFERENCES BETWEEN TARGET DEVICE AND TARGET INTERFACE CIRCUIT
Differences between the signal lines of the target device and the signal lines of the IE-703089-MC-EM1 target
interface circuit are described in this chapter.
The target device is a CMOS circuit, whereas the target interface circuit of the IE-703089-MC-EM1 is configured
with an emulation circuit such as a gate array TTL or CMOS-IC.
When debugging the IE system connected to the target system, the IE system emulates as if the real target device
is operating on the target system.
Small differences occur however, because the IE system is emulating actual operation.
(1) Signals input/output to/from the emulation gate array
• P47 to P40
• P57 to P50
• P67 to P60
• P97 to P90
• P117 to P110
• P133 to P130
(2) Other signals
• P07 to P00
• P17 to P10
• P27 to P20
• P37 to P30
• P77 to P70
• P83 to P80
• P107 to P100
• P127 to P120
• P147 to P140
• P157 to P150
• P176 to P170
• V
DD0
• PORTVDD0
, PORTV
, PORTV
DD1
DD2
, ADCV
DD
• CLKOUT
• RESET
• VDD1
• MODE/VPP
• CPUREG
• X1, X2, XT1, XT2
• GND0, GND1, GND2, PORTGND0, PORTGND1, ADCGND
Figure 5-1 shows the signals in (1) and (2) above in the circuit for the IE system.
30
User’s Manual U15776EJ1V0UM
CHAPTER 5 DIFFERENCES BETWEEN TARGET DEVICE AND TARGET INTERFACE CIRCUIT
Figure 5-1. Equivalent Circuit of Emulation Circuit (1/2)
IE system sideProbe side
P00,
P36 to P34
P07 to P01,
P17 to P10,
P27 to P20,
P37 to P30,
P77 to P70,
P83 to P80,
P127 to P120,
P147 to P140,
P157 to P150,
P176 to P170
P107 to P100
QS3125
QS3257
PORTV
DD0
IN/OUT
IN/OUT
IN/OUT
µ
PD70F3089Y
emulation
CPU
P47 to P40,
P57 to P50
P67 to P60
P96 to P90
P113 to P110
QS3244
VHC244
QS3244
QS3384
QS3257
QS3244
VHC125
PORTV
VHC125
PORTV
VHC125
PORTV
VHC125
PORTV
VHC125
PD703091
µ
DD0
DD0
DD1
DD1
OUT
IN
OUT
IN
OUT
IN
OUT
IN
OUT
OR3T125
(FPGA)
P117 to P114
P133 to P130
PORTV
DD2
VHC125
User’s Manual U15776EJ1V0UM
IN
OUT
IN
31
CHAPTER 5 DIFFERENCES BETWEEN TARGET DEVICE AND TARGET INTERFACE CIRCUIT
Figure 5-1. Equivalent Circuit of Emulation Circuit (2/2)
V
PORTV
3.5 V
CC
100 Ω
V
DD0
100 F
µ
1 MΩ
PC339
µ
Relay
V
3.3 V
CC
100 Ω
DD0
100 F
µ
1 MΩ
PC393
µ
V
DD
IE system sideProbe side
LED
PD70F3089Y
µ
emulation CPU
LED
PORTV
DD1
PORTV
DD2
ADCV
CLKOUT, RESET
DD1
DD2
DD
Internal power
supply circuit
LED
PD70F3089Y
µ
emulation CPU
LED
PD70F3089Y
µ
emulation CPU
PD703091
µ
Relay
PC741
µ
V
3.3 V
CC
100 Ω
PC339
µ
100 F
µ
1 MΩ
PORTV
PORTV
3.3 V
Relay
V
CC
100 Ω
DD
100 F
µ
1 MΩ
RELEY
PC393
µ
ADCV
emulation CPU
V
DD1
, MODE, CPUREG,
X1, X2, XT1, XT2
GND0, GND1, GND2,
PORTGND0, PORTGND1,
ADCGND
32
Open
User’s Manual U15776EJ1V0UM
APPENDIX PACKAGE DRAWINGS
IE-703002-MC + IE-703089-MC-EM1 (Unit: mm)
571
103166
302
9027
IE-703002-MC
58.8
IE-703089-MC-EM1
Top view
Pin 1 direction
Side view
50
Bottom view
180
User’s Manual U15776EJ1V0UM
33.0
Top view
33.0
33
[MEMO]
34
User’s Manual U15776EJ1V0UM
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