Page 1
User’s Manual
TM
V850/SB1
, V850/SB2
32-Bit Single-Chip Microcontroller
Hardware
PD703031A
µµµµ
PD703031AY
µµµµ
PD703032A
µµµµ
PD703032AY
µµµµ
PD703033A
µµµµ
PD703033AY
µµµµ
PD70F3032A
µµµµ
PD703030B
µµµµ
PD703030BY
µµµµ
PD703031B
µµµµ
PD703031BY
µµµµ
PD703032B
µµµµ
PD703032BY
µµµµ
PD703033B
µµµµ
PD703034A
µµµµ
PD703034AY
µµµµ
PD703035A
µµµµ
PD703035AY
µµµµ
PD703037A
µµµµ
PD703037AY
µµµµ
PD70F3035A
µµµµ
TM
PD703034B
µµµµ
PD703034BY
µµµµ
PD703035B
µµµµ
PD703035BY
µµµµ
PD703036H
µµµµ
PD703036HY
µµµµ
PD703037H
µµµµ
PD70F3032AY
µµµµ
PD70F3033A
µµµµ
PD70F3033AY
µµµµ
Document No. U13850EJ6V0UD00 (6th edition)
Date Published February 2003 N CP(K)
Printed in Japan
PD703033BY
µµµµ
PD70F3030B
µµµµ
PD70F3030BY
µµµµ
PD70F3032B
µµµµ
PD70F3032BY
µµµµ
PD70F3033B
µµµµ
PD70F3033BY
µµµµ
1999, 2000, 2003
PD70F3035AY
µµµµ
PD70F3037A
µµµµ
PD70F3037AY
µµµµ
PD703037HY
µµµµ
PD70F3035B
µµµµ
PD70F3035BY
µµµµ
PD70F3036H
µµµµ
PD70F3036HY
µµµµ
PD70F3037H
µµµµ
PD70F3037HY
µµµµ
Page 2
[MEMO]
2
User’s Manual U13850EJ6V0UD
Page 3
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
DD
pin should be connected to V
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
or GND with a resistor, if it is considered to have a possibility of
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
Purchase of NEC I2C components conveys a license under the Philips I2C Patent Rights to use these
components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined
by Philips.
V850 Series, V850/SA1, V850/SB1, V850/SB2, IEBus, and Inter Equipment Bus are trademarks of NEC
Electronics Corporation.
Windows is either a registered trademark or a trademark of Microsoft Corporation in the United States and/or
other countries.
User’s Manual U13850EJ6V0UD
3
Page 4
These commodities, technology or software, must be exported in accordance
with the export administration regulations of the exporting country.
Diversion contrary to the law of that country is prohibited.
•
The information in this document is current as of December, 2002. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC Electronics data
sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not
all products and/or types are available in every country. Please check with an NEC Electronics sales
representative for availability and additional information.
No part of this document may be copied or reproduced in any form or by any means without the prior
•
written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may
appear in this document.
•
NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from the use of NEC Electronics products listed in this document
or any other liability arising from the use of such products. No license, express, implied or otherwise, is
granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.
Descriptions of circuits, software and other related information in this document are provided for illustrative
•
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of a customer's equipment shall be done under the full
responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by
customers or third parties arising from the use of these circuits, software and information.
•
While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products,
customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To
minimize risks of damage to property or injury (including death) to persons arising from defects in NEC
Electronics products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment and anti-failure features.
•
NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and
"Specific".
The "Specific" quality grade applies only to NEC Electronics products developed based on a customerdesignated "quality assurance program" for a specific application. The recommended applications of an NEC
Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of
each NEC Electronics product before using it in a particular application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots.
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support).
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC
Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications
not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to
determine NEC Electronics' willingness to support a given application.
(Note)
(1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its
majority-owned subsidiaries.
(2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics
(as defined above).
M8 E 02 . 11-1
4
User’s Manual U13850EJ6V0UD
Page 5
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
Electronics product in your application, pIease contact the NEC Electronics office in your country to
obtain a list of authorized representatives and distributors. They will verify:
•
Device availability
•
Ordering information
•
Product release schedule
•
Availability of related technical literature
•
Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
•
Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
NEC Electronics America, Inc. (U.S.)
Santa Clara, California
Tel: 408-588-6000
800-366-9782
Fax: 408-588-6130
800-729-9288
NEC Electronics (Europe) GmbH
Duesseldorf, Germany
Tel: 0211-65 03 01
Fax: 0211-65 03 327
• Sucursal en España
Madrid, Spain
Tel: 091-504 27 87
Fax: 091-504 28 60
• Succursale Française
Vélizy-Villacoublay, France
Tel: 01-30-67 58 00
Fax: 01-30-67 58 99
• Filiale Italiana
Milano, Italy
Tel: 02-66 75 41
Fax: 02-66 75 42 99
• Branch The Netherlands
Eindhoven, The Netherlands
Tel: 040-244 58 45
Fax: 040-244 45 80
• Tyskland Filial
Taeby, Sweden
Tel: 08-63 80 820
Fax: 08-63 80 388
• United Kingdom Branch
Milton Keynes, UK
Tel: 01908-691-133
Fax: 01908-670-290
NEC Electronics Hong Kong Ltd.
Hong Kong
Tel: 2886-9318
Fax: 2886-9022/9044
NEC Electronics Hong Kong Ltd.
Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411
NEC Electronics Shanghai, Ltd.
Shanghai, P.R. China
Tel: 021-6841-1138
Fax: 021-6841-1137
NEC Electronics Taiwan Ltd.
Taipei, Taiwan
Tel: 02-2719-2377
Fax: 02-2719-5951
NEC Electronics Singapore Pte. Ltd.
Novena Square, Singapore
Tel: 6253-8311
Fax: 6250-3583
User’s Manual U13850EJ6V0UD
J02.11
5
Page 6
Major Revisions in This Edition (1/3)
Page Description
Throughout • Addition of the following products.
PD703030B, 703030BY, 703031B, 703031BY, 703032B, 703032BY, 703033B, 703033BY, 703034B,
µ
703034BY, 703035B, 703035BY, 703036H, 703036HY, 703037H, 703037HY, 70F3030B, 70F3030BY,
70F3032B, 70F3032BY, 70F3033B, 70F3033BY, 70F3035B, 70F3035BY, 70F3036H, 70F3036HY,
70F3037H, 70F3037HY
• Deletion of the following products.
PD703030A, 703030AY, 703036A, 703036AY
µ
p. 63 Addition of description on minimum instruction execution time in
p. 63 Addition of description on instruction set in
p. 73 Addition of description in
p. 80 Modification of description and addition of
Operating Mode
p. 87 Addition of description in
p. 92 Modification of P23 I/O circuit type and description on P33 in
Supplies and Connection of Unused Pins
p. 96 Addition of description on minimum instruction execution time in
p. 100 Modification of description and addition of
p. 110 Addition of
pp. 119, 124, 125 Modification of
p. 126 Addition of description in
p. 126 Modification of
p. 126 Modification of
p. 127 Addition of
p. 129 Addition of
p. 158 Addition of
p. 162 Addition of
p. 165 Addition of
p. 165 Addition of
p. 176 Addition of
p. 178 Addition of
p. 179 Addition of
p. 184 Addition of description in
p. 185 Modification of description in
setup
p. 186 Modification of description in
pp. 190, 191 Addition and deletion of description in
p. 192 Modification of description in
p. 194 Addition of description in
p. 194 Modification of description in
3.4.5 (2) (a) V850/SB1 (
Note
[Description example]
Caution 2
Remarks
Note
Remark
Caution 2
Caution
Remark
Remark
5.8.1 Interrupt request valid timing after EI instruction
5.9 Interrupt Control Register Bit Manipulation Instructions During DMA Transfer
Table 2-1 Pin I/O Buffer Power Supplies
2.3 (9) (b) (i) LBEN
µµµµ
PD703031B, 703031BY), V850/SB2 (
and addition of registers in
3.4.9 Specific registers
in
in
3.4.9 Specific registers
in
3.4.9 (2) (b) Reset conditions (PRERR = 1)
and
Caution
in
in
in
in
in
4.2.2 (1) System control register (SYC)
5.3.3 Priorities of maskable interrupts
in
5.3.4 Interrupt control register (xxICn)
5.3.5 In-service priority register (ISPR)
5.3.6 ID flag
5.6.2 (2) To generate exception in service program
Cautions
6.4.4 (1) Settings and operating states
in
6.3.1 (1) Processor clock control register (PCC)
6.3.1 (1) (b) Example of subclock operation →
6.3.1 (2) Power save control register (PSC)
Table 6-1 Operating Statuses in HALT Mode
Table 6-2 Operating Statuses in IDLE Mode
Table 6-3 Operating Statuses in Software STOP Mode
1.5.1
in
Notes
in
Note
3.4.8 Peripheral I/O registers
3.4.9 Specific registers
Table 2-3 Operating States of Pins in Each
2.4 Pin I/O Circuit Types, I/O Buffer Power
3.2.2 (2) Program status word (PSW)
1.5.1
3.1
µµµµ
PD703034B, 703034BY
)
main clock operation
6
User’s Manual U13850EJ6V0UD
Page 7
Major Revisions in This Edition (2/3)
Pages Description
p. 197 Addition of
p. 198 Addition of
p. 206 Addition of description in
p. 207 Addition of description in
p. 213 Modification of description in
p. 214 Addition of
p. 214 Addition of
p. 215 Modification of description in
p. 217 Modification of description in
p. 219 Modification of description in
p. 221 Modification of description in
Rising Edge Specified)
p. 222 Modification of description in
p. 227 Modification of description in
p. 231 Modification of description in
p. 231 Modification of description in
p. 234 Addition of
p. 242 Change of
p. 246 Addition of description to
p. 248 Addition of description to
p. 253 Addition of registers and
p. 254 Addition of registers and
p. 255 Addition of description and
p. 256 Addition of
p. 257 Addition of description in
p. 263 Addition of
p. 268 Addition of description in
p. 280 Modification of
p. 288 Addition of
p. 334 Addition of
p. 402 Addition of description to
(ASIM0, ASIM1)
p. 405 Addition of description to
(BRGMCn0, BRGMCn1)
p. 406 Addition of description to
p. 407 Addition of description to
Mode)
p. 410 Addition of description to
Serial Interface Mode)
6.6 (1) While an instruction is being executed on internal ROM
6.6 (2) While an instruction is being executed on external ROM
Caution
Caution
in
7.1.4 (1) 16-bit timer mode control registers 0, 1 (TMC0, TMC1)
in
7.1.4 (2) Capture/compare control registers 0, 1 (CRC0, CRC1)
Figure 7-5 (a) 16-bit timer mode control registers 0, 1 (TMC0, TMC1)
Figure 7-6 Configuration of PPG Output
Figure 7-7 PPG Output Operation Timing
Figure 7-8 (a) 16-bit timer mode control registers 0, 1 (TMC0, TMC1)
Figure 7-11 (a) 16-bit timer mode control registers 0, 1 (TMC0, TMC1)
Figure 7-14 (a) 16-bit timer mode control registers 0, 1 (TMC0, TMC1)
Figure 7-17 Timing of Pulse Width Measurement by Restarting (with
Figure 7-18 (a) 16-bit timer mode control registers 0, 1 (TMC0, TMC1)
Caution
in
7.2.6 (2) One-shot pulse output with external trigger
7.2.7 (6) (a) One-shot pulse output by software
7.2.7 (6) (b) One-shot pulse output with external trigger
7.3.1 Outline
Figure 7-32 Timing of Interval Timer Operation (3/3)
Remarks
Remarks
Caution
Note
in
Figure 7-34 Square Wave Output Operation Timing
in
Figure 7-35 Timing of PWM Output
in
Figure 8-1 Block Diagram of Watch Timer
in
Table 8-2 Configuration of Watch Timer
Caution
in
8.3 Watch Timer Control Register
8.3 (2) Watch timer high-speed clock selection register (WTNHC)
8.3 (3) Watch timer clock selection register (WTNCS)
in
Caution
9.3 (2) Watchdog timer clock selection register (WDCS)
10.2 (2) 3-wire serial I/O mode (fixed to MSB first)
Caution
Caution
10.4 I
in
10.3.2 (1) IIC control registers 0, 1 (IICC0, IICC1)
in
10.3.2 (3) IIC clock selection registers 0, 1 (IICCL0, IICCL1)
2
C Bus (B and H Versions)
Cautions
Cautions
Cautions
Cautions
Cautions
in
10.5.2 (1) Asynchronous serial interface mode registers 0, 1
in
10.5.2 (4) Baud rate generator mode control registers n0, n1
in
Figure 10-45 ASIMn Setting (Operation Stop Mode)
in
Figure 10-46 ASIMn Setting (Asynchronous Serial Interface
in
Figure 10-49 BRGMCn0 and BRGMCn1 Settings (Asynchronous
User’s Manual U13850EJ6V0UD
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Page 8
Major Revisions in This Edition (3/3)
Pages Description
p. 437 Addition of
p. 447 Addition of
p. 452 Addition of
p. 455 Addition of
p. 460 Addition of
p. 462 Addition of
p. 463 Addition of
p. 466 Addition of
p. 468 Addition of
p. 471 Addition of description in
p. 473 Addition of
p. 474 Addition of description in
p. 501 Addition of
p. 504 Addition of
p. 511, 512 Addition of description in
p. 515 Addition of
p. 517 Addition of description in
p. 517 Addition of description in
p. 524 Addition of
p. 526 Addition of
100GC-8EU)
p. 527 Addition of
8EU)
p. 528 Addition of
3BA)
p. 529 Addition of
3BA)
p. 549 Modification of description in
p. 560 Addition of register to
p. 582 Addition of
p. 583 Addition of
p. 600 Addition of
p. 635 Addition of
p. 637 Addition of
p. 642 Addition of
p. 658 Modification of
p. 664 Addition of
Caution
11.7 How to Read A/D Converter Characteristics Table
12.3 Configuration
12.4 (2) (a) V850/SB1 (
Caution
12.5 Operation
12.6 Cautions
13.2 Features
13.3 (2) Output latch
13.7 (3)
Caution
Caution
14.4 Port Function Operation
18.1.1 (2) V850/SB1 (
Table 18-1 Table for Wiring of V850/SB1 and V850/SB2 Flash Writing Adapter (FA-100GC-
Figure 18-2 Wiring Example of V850/SB1 and V850/SB2 Flash Writing Adapter (FA-100GF-
Table 18-2 Table for Wiring of V850/SB1 and V850/SB2 Flash Writing Adapter (FA-100GF-
Remark
19.3.2 (14) IEBus high-speed clock selection register (IEHCLK)
CHAPTER 20 ELECTRICAL SPECIFICATIONS
CHAPTER 21 PACKAGE DRAWINGS
CHAPTER 22 RECOMMENDED SOLDERING CONDITIONS
APPENDIX A NOTES ON TARGET SYSTEM DESIGN
APPENDIX E REVISION HISTORY
in
11.3 (2) Analog input channel specification register (ADS)
µµµµ
PD703031B, 703031BY), V850/SB2 (
in
12.4 (5) DMA channel control registers 0 to 5 (DCHC0 to DCHC5)
13.5 Usage
Table 14-1 Pin I/O Buffer Power Supplies
in
14.2.8 (1) Function of P9 pins
in
14.2.9 (1) Function of P10 pins
Table 14-12 Setting When Port Pin is Used as Alternate Function
16.1 Outline
Figure 16-1 Regulator
µµµµ
PD70F3030B, 70F3030BY), V850/SB2 (
Figure 18-1 Wiring Example of V850/SB1 and V850/SB2 Flash Writing Adapter (FA-
Table 19-5 Acknowledge Signal Output Condition of Control Field
Table 19-7 Internal Registers of IEBus Controller
in
19.3.2 (13) IEBus clock selection register (IECLK)
APPENDIX D INDEX
µµµµ
PD703034B, 703034BY)
µµµµ
PD70F3036H, 70F3036HY)
The mark shows major revised points.
8
User’s Manual U13850EJ6V0UD
Page 9
INTRODUCTION
Readers This manual is intended for users who wish to understand the functions of the V850/SB1 and
V850/SB2 and design application systems using the V850/SB1 or V850/SB2.
Purpose This manual is intended to give users to an understanding of the hardware functions described in the
Organization below.
Organization The V850/SB1, V850/SB2 User’s Manual is divided into two parts: hardware (this manual) and
TM
architecture (V850 Series
Architecture User’s Manual).
Hardware Architecture
•
Pin function
•
CPU function
•
On-chip peripheral function
•
Flash memory programming
•
IEBus controller (V850/SB2 only)
•
Electrical specifications
•
Data type
•
Register set
•
Instruction format and instruction set
•
Interrupt and exception
•
Pipeline operation
How to Read This Manual It is assumed that the reader of this manual has general knowledge in the fields of
electrical engineering, logic circuits, and microcontrollers.
To find out the details of a register whose name is known:
→ Refer to APPENDIX B REGISTER INDEX.
To find out the details of a function, etc., whose name is known:
→ Refer to APPENDIX D INDEX.
To understand the details of a instruction function:
→ Refer to V850 Series Architecture User’s Manual available separately.
To know the electrical specifications of the V850/SB1 and V850/SB2:
→ Refer to CHAPTER 20 ELECTRICAL SPECIFICATIONS.
How to read register formats:
→ Names of bits whose numbers are enclosed in a square are defined in the device file under
reserved words.
To understand the overall functions of the V850/SB1 and V850/SB2:
→ Read this manual in accordance with the CONTENTS.
User’s Manual U13850EJ6V0UD
9
Page 10
Conventions Data significance: Higher digits on the left and lower digits on the right
Active low: xxx (overscore over pin or signal name)
Memory map address: Higher addresses at the top and lower addresses at the bottom
Note: Footnote for items marked with Note in the text
Caution: Information requiring particular attention
Remark: Supplementary information
Number representation: Binary … xxxx or xxxxB
Decimal … xxxx
Hexadecimal … xxxxH
Prefixes indicating power of 2 (address space, memory capacity):
10
K (kilo): 2
M (mega): 220 … 1024
G (giga): 230 … 1024
… 1024
2
3
10
User’s Manual U13850EJ6V0UD
Page 11
Related Documents The related documents indicated in this publication may include preliminary versions.
However, preliminary versions are not marked as such.
Related documents for V850/SB1 and V850/SB2
Document Name Document No.
V850 Series Architecture User’s Manual U10243E
V850/SB1, V850/SB2 Hardware User’s Manual This manual
Related documents for development tool (user’s manual)
Document Name Document No.
CA850 Ver. 2.40 or Later C Compiler Package
ID850 Ver. 2.40 Integrated Debugger Operation (Windows™ Based) U15181E
SM850 Ver. 2.40 System Simulator Operation (Windows Based) U15182E
SM850 Ver. 2.00 or Later System Simulator External Part User Open Interface Specifications U14873E
RX850 Ver. 3.13 or Later Real-time OS
RX850 Pro Ver. 3.13 Real-time OS
RD850 Ver. 3.01 Task Debugger U13737E
RD850 Pro Ver. 3.01 Task Debugger U13916E
AZ850 Ver. 3.0 System Performance Analyzer U14410E
PG-FP3 Flash Memory Programmer U13502E
PG-FP4 Flash Memory Programmer U15260E
Operation U15024E
C Language U15025E
Project Manager U15026E
Assembly Language U15027E
Basic U13430E
Installation U13410E
Technical U13431E
Basic U13773E
Installation U13774E
Technical U13772E
User’s Manual U13850EJ6V0UD
11
Page 12
CONTENTS
CHAPTER 1 INTRODUCTION.................................................................................................................29
1.1 General.......................................................................................................................................29
1.2 V850/SB1 (A Versions) .............................................................................................................33
1.2.1 Features (V850/SB1 (A versions)) ..............................................................................................33
1.2.2 Application fields (V850/SB1 (A versions)) .................................................................................34
1.2.3 Ordering information (V850/SB1 (A versions))............................................................................35
1.2.4 Pin configuration (top view) (V850/SB1 (A versions)) .................................................................36
1.2.5 Function blocks (V850/SB1 (A versions)) ...................................................................................39
1.3 V850/SB1 (B Versions) .............................................................................................................43
1.3.1 Features (V850/SB1 (B versions)) ..............................................................................................43
1.3.2 Application fields (V850/SB1 (B versions)) .................................................................................44
1.3.3 Ordering information (V850/SB1 (B versions))............................................................................45
1.3.4 Pin configuration (top view) (V850/SB1 (B versions)) .................................................................46
1.3.5 Function blocks (V850/SB1 (B versions)) ...................................................................................49
1.4 V850/SB2 (A Versions) .............................................................................................................53
1.4.1 Features (V850/SB2 (A versions)) ..............................................................................................53
1.4.2 Application fields (V850/SB2 (A versions)) .................................................................................54
1.4.3 Ordering information (V850/SB2 (A versions))............................................................................55
1.4.4 Pin configuration (top view) (V850/SB2 (A versions)) .................................................................56
1.4.5 Function blocks (V850/SB2 (A versions)) ...................................................................................59
1.5 V850/SB2 (B and H Versions) ..................................................................................................63
1.5.1 Features (V850/SB2 (B and H versions))....................................................................................63
1.5.2 Application fields (V850/SB2 (B and H versions)) ....................................................................... 64
1.5.3 Ordering information (V850/SB2 (B and H versions)) .................................................................65
1.5.4 Pin configuration (top view) (V850/SB2 (B and H versions)).......................................................66
1.5.5 Function blocks (V850/SB2 (B and H versions)) ......................................................................... 69
CHAPTER 2 PIN FUNCTIONS ...............................................................................................................73
2.1 List of Pin Functions ................................................................................................................73
2.2 Pin States...................................................................................................................................80
2.3 Description of Pin Functions...................................................................................................81
2.4 Pin I/O Circuit Types, I/O Buffer Power Supplies and Connection of Unused Pins...........92
2.5 Pin I/O Circuits..........................................................................................................................94
CHAPTER 3 CPU FUNCTIONS..............................................................................................................96
3.1 Features.....................................................................................................................................96
3.2 CPU Register Set ......................................................................................................................97
3.2.1 Program register set.................................................................................................................... 98
3.2.2 System register set .....................................................................................................................99
3.3 Operation Modes ....................................................................................................................102
3.4 Address Space........................................................................................................................103
3.4.1 CPU address space ..................................................................................................................103
12
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3.4.2 Image ........................................................................................................................................104
3.4.3 Wrap-around of CPU address space ........................................................................................ 105
3.4.4 Memory map .............................................................................................................................106
3.4.5 Area .......................................................................................................................................... 107
3.4.6 External expansion mode ......................................................................................................... 114
3.4.7 Recommended use of address space ...................................................................................... 117
3.4.8 Peripheral I/O registers .............................................................................................................119
3.4.9 Specific registers....................................................................................................................... 126
CHAPTER 4 BUS CONTROL FUNCTION ..........................................................................................128
4.1 Features...................................................................................................................................128
4.2 Bus Control Pins and Control Register................................................................................128
4.2.1 Bus control pins ........................................................................................................................ 128
4.2.2 Control register ......................................................................................................................... 129
4.3 Bus Access .............................................................................................................................129
4.3.1 Number of access clocks .......................................................................................................... 129
4.3.2 Bus width .................................................................................................................................. 130
4.4 Memory Block Function.........................................................................................................131
4.5 Wait Function..........................................................................................................................132
4.5.1 Programmable wait function...................................................................................................... 132
4.5.2 External wait function................................................................................................................ 133
4.5.3 Relationship between programmable wait and external wait .................................................... 133
4.6 Idle State Insertion Function................................................................................................. 134
4.7 Bus Hold Function..................................................................................................................135
4.7.1 Outline of function ..................................................................................................................... 135
4.7.2 Bus hold procedure................................................................................................................... 136
4.7.3 Operation in power save mode .................................................................................................136
4.8 Bus Timing..............................................................................................................................137
4.9 Bus Priority .............................................................................................................................144
4.10 Memory Boundary Operation Conditions ............................................................................145
4.10.1 Program space.......................................................................................................................... 145
4.10.2 Data space................................................................................................................................ 145
CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION .................................................146
5.1 Outline .....................................................................................................................................146
5.1.1 Features.................................................................................................................................... 146
5.2 Non-Maskable Interrupt .........................................................................................................149
5.2.1 Operation ..................................................................................................................................150
5.2.2 Restore ..................................................................................................................................... 152
5.2.3 NP flag ......................................................................................................................................153
5.2.4 Noise eliminator of NMI pin....................................................................................................... 153
5.2.5 Edge detection function of NMI pin ...........................................................................................154
5.3 Maskable Interrupts................................................................................................................155
5.3.1 Operation ..................................................................................................................................155
5.3.2 Restore ..................................................................................................................................... 157
5.3.3 Priorities of maskable interrupts................................................................................................ 158
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5.3.4 Interrupt control register (xxICn) ...............................................................................................162
5.3.5 In-service priority register (ISPR) ..............................................................................................165
5.3.6 ID flag ........................................................................................................................................ 165
5.3.7 Watchdog timer mode register (WDTM).................................................................................... 166
5.3.8 Noise elimination.......................................................................................................................166
5.3.9 Edge detection function............................................................................................................. 168
5.4 Software Exceptions ..............................................................................................................169
5.4.1 Operation ..................................................................................................................................169
5.4.2 Restore...................................................................................................................................... 170
5.4.3 EP flag.......................................................................................................................................171
5.5 Exception Trap........................................................................................................................171
5.5.1 Illegal opcode definition............................................................................................................. 171
5.5.2 Operation ..................................................................................................................................171
5.5.3 Restore...................................................................................................................................... 173
5.6 Priority Control........................................................................................................................174
5.6.1 Priorities of interrupts and exceptions .......................................................................................174
5.6.2 Multiple interrupt servicing ........................................................................................................174
5.7 Interrupt Latency Time...........................................................................................................177
5.8 Periods in Which Interrupt Is Not Acknowledged ...............................................................177
5.8.1 Interrupt request valid timing after EI instruction.......................................................................178
5.9 Interrupt Control Register Bit Manipulation Instructions During DMA Transfer..............179
5.10 Key Interrupt Function ...........................................................................................................180
CHAPTER 6 CLOCK GENERATION FUNCTION...............................................................................182
6.1 Outline......................................................................................................................................182
6.2 Configuration ..........................................................................................................................183
6.3 Clock Output Function...........................................................................................................183
6.3.1 Control registers ........................................................................................................................184
6.4 Power Save Functions ...........................................................................................................188
6.4.1 Outline.......................................................................................................................................188
6.4.2 HALT mode ...............................................................................................................................189
6.4.3 IDLE mode ................................................................................................................................192
6.4.4 Software STOP mode ...............................................................................................................194
6.5 Oscillation Stabilization Time................................................................................................196
6.6 Notes on Power Save Function.............................................................................................197
CHAPTER 7 TIMER/COUNTER FUNCTION........................................................................................200
7.1 16-Bit Timer (TM0, TM1) .........................................................................................................200
7.1.1 Outline.......................................................................................................................................200
7.1.2 Function ....................................................................................................................................200
7.1.3 Configuration .............................................................................................................................202
7.1.4 Timer 0, 1 control registers .......................................................................................................205
7.2 16-Bit Timer Operation...........................................................................................................211
7.2.1 Operation as interval timer (16 bits) ..........................................................................................211
7.2.2 PPG output operation................................................................................................................213
7.2.3 Pulse width measurement ......................................................................................................... 215
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7.2.4 Operation as external event counter......................................................................................... 222
7.2.5 Operation to output square wave.............................................................................................. 223
7.2.6 Operation to output one-shot pulse........................................................................................... 225
7.2.7 Cautions.................................................................................................................................... 230
7.3 8-Bit Timer (TM2 to TM7)........................................................................................................234
7.3.1 Outline....................................................................................................................................... 234
7.3.2 Functions .................................................................................................................................. 234
7.3.3 Configuration............................................................................................................................. 235
7.3.4 Timer n control register .............................................................................................................236
7.4 8-Bit Timer Operation............................................................................................................. 242
7.4.1 Operation as interval timer (8-bit operation) ............................................................................. 242
7.4.2 Operation as external event counter......................................................................................... 245
7.4.3 Operation as square wave output (8-bit resolution) ..................................................................246
7.4.4 Operation as 8-bit PWM output................................................................................................. 247
7.4.5 Operation as interval timer (16 bits).......................................................................................... 250
7.4.6 Cautions.................................................................................................................................... 252
CHAPTER 8 WATCH TIMER................................................................................................................ 253
8.1 Function ..................................................................................................................................253
8.2 Configuration..........................................................................................................................254
8.3 Watch Timer Control Registers............................................................................................. 255
8.4 Operation.................................................................................................................................258
8.4.1 Operation as watch timer ..........................................................................................................258
8.4.2 Operation as interval timer........................................................................................................ 258
8.4.3 Cautions.................................................................................................................................... 259
CHAPTER 9 WATCHDOG TIMER .......................................................................................................260
9.1 Functions ................................................................................................................................260
9.2 Configuration..........................................................................................................................262
9.3 Watchdog Timer Control Register........................................................................................ 262
9.4 Operation.................................................................................................................................265
9.4.1 Operation as watchdog timer ....................................................................................................265
9.4.2 Operation as interval timer........................................................................................................ 266
9.5 Standby Function Control Register...................................................................................... 267
CHAPTER 10 SERIAL INTERFACE FUNCTION................................................................................ 268
10.1 Overview .................................................................................................................................. 268
10.2 3-Wire Serial I/O (CSI0 to CSI3) .............................................................................................268
10.2.1 Configuration............................................................................................................................. 269
10.2.2 CSIn control registers ...............................................................................................................270
10.2.3 Operations ................................................................................................................................272
10.3 I2C Bus (A Versions) ...............................................................................................................275
10.3.1 Configuration............................................................................................................................. 278
10.3.2 I2C control registers................................................................................................................... 280
10.3.3 I2C bus mode functions ............................................................................................................. 291
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10.3.4 I2C bus definitions and control methods .................................................................................... 292
10.3.5 I2C interrupt requests (INTIICn).................................................................................................299
10.3.6 Interrupt request (INTIICn) generation timing and wait control .................................................317
10.3.7 Address match detection method..............................................................................................318
10.3.8 Error detection........................................................................................................................... 318
10.3.9 Extension code..........................................................................................................................318
10.3.10 Arbitration..................................................................................................................................319
10.3.11 Wakeup function .......................................................................................................................320
10.3.12 Communication reservation.......................................................................................................321
10.3.13 Cautions ....................................................................................................................................324
10.3.14 Communication operations........................................................................................................325
10.3.15 Timing of data communication ..................................................................................................327
10.4 I2C Bus (B and H Versions) ....................................................................................................334
10.4.1 Configuration.............................................................................................................................337
10.4.2 I2C control register.....................................................................................................................339
10.4.3 I2C bus mode functions .............................................................................................................352
10.4.4 I2C bus definitions and control methods .................................................................................... 353
10.4.5 I2C interrupt requests (INTIICn).................................................................................................360
10.4.6 Interrupt request (INTIICn) generation timing and wait control .................................................378
10.4.7 Address match detection method..............................................................................................379
10.4.8 Error detection........................................................................................................................... 379
10.4.9 Extension code..........................................................................................................................379
10.4.10 Arbitration..................................................................................................................................380
10.4.11 Wakeup function .......................................................................................................................382
10.4.12 Communication reservation.......................................................................................................383
10.4.13 Cautions ....................................................................................................................................388
10.4.14 Communication operations........................................................................................................389
10.4.15 Timing of data communication ..................................................................................................392
10.5 Asynchronous Serial Interface (UART0, UART1) ................................................................399
10.5.1 Configuration.............................................................................................................................399
10.5.2 UARTn control registers............................................................................................................401
10.5.3 Operations.................................................................................................................................406
10.5.4 Standby function .......................................................................................................................418
10.6 3-Wire Variable-Length Serial I/O (CSI4)...............................................................................419
10.6.1 Configuration.............................................................................................................................419
10.6.2 CSI4 control registers................................................................................................................422
10.6.3 Operations.................................................................................................................................426
CHAPTER 11 A/D CONVERTER..........................................................................................................431
11.1 Function...................................................................................................................................431
11.2 Configuration ..........................................................................................................................433
11.3 Control Registers....................................................................................................................435
11.4 Operation.................................................................................................................................438
11.4.1 Basic operation .........................................................................................................................438
11.4.2 Input voltage and conversion result ..........................................................................................440
11.4.3 A/D converter operation mode ..................................................................................................441
11.5 Low Power Consumption Mode ............................................................................................443
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11.6 Cautions ..................................................................................................................................443
11.7 How to Read A/D Converter Characteristics Table .............................................................447
CHAPTER 12 DMA FUNCTIONS ......................................................................................................... 451
12.1 Functions ................................................................................................................................ 451
12.2 Transfer Completion Interrupt Request ...............................................................................451
12.3 Configuration .......................................................................................................................... 452
12.4 Control Registers ...................................................................................................................453
12.5 Operation................................................................................................................................. 462
12.6 Cautions ..................................................................................................................................463
CHAPTER 13 REAL-TIME OUTPUT FUNCTION (RTO) ...................................................................466
13.1 Function .................................................................................................................................. 466
13.2 Features................................................................................................................................... 466
13.3 Configuration .......................................................................................................................... 467
13.4 RTO Control Registers...........................................................................................................469
13.5 Usage .......................................................................................................................................471
13.6 Operation................................................................................................................................. 472
13.7 Cautions ..................................................................................................................................473
CHAPTER 14 PORT FUNCTION..........................................................................................................474
14.1 Port Configuration..................................................................................................................474
14.2 Port Pin Function....................................................................................................................474
14.2.1 Port 0 ........................................................................................................................................474
14.2.2 Port 1 ........................................................................................................................................479
14.2.3 Port 2 ........................................................................................................................................483
14.2.4 Port 3 ........................................................................................................................................488
14.2.5 Ports 4 and 5............................................................................................................................. 492
14.2.6 Port 6 ........................................................................................................................................495
14.2.7 Ports 7 and 8............................................................................................................................. 498
14.2.8 Port 9 ........................................................................................................................................500
14.2.9 Port 10 ......................................................................................................................................503
14.2.10 Port 11 ..................................................................................................................................... 507
14.3 Setting When Port Pin Is Used as Alternate Function ........................................................511
14.4 Port Function Operation ........................................................................................................515
14.4.1 Write operation to I/O port......................................................................................................... 515
14.4.2 Read operation from I/O port .................................................................................................... 515
CHAPTER 15 RESET FUNCTION........................................................................................................516
15.1 General ....................................................................................................................................516
15.2 Pin Operations ........................................................................................................................ 516
CHAPTER 16 REGULATOR .................................................................................................................517
16.1 Outline .....................................................................................................................................517
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16.2 Operation.................................................................................................................................517
CHAPTER 17 ROM CORRECTION FUNCTION .................................................................................518
17.1 General.....................................................................................................................................518
17.2 ROM Correction Peripheral I/O Registers ............................................................................519
CHAPTER 18 FLASH MEMORY ..........................................................................................................523
18.1 Features...................................................................................................................................523
18.1.1 Erase unit .................................................................................................................................. 524
18.1.2 Write/read time..........................................................................................................................524
18.2 Writing with Flash Programmer ............................................................................................525
18.3 Programming Environment ...................................................................................................530
18.4 Communication Mode ............................................................................................................530
18.5 Pin Connection .......................................................................................................................533
18.5.1 VPP pin.......................................................................................................................................533
18.5.2 Serial interface pin ....................................................................................................................533
18.5.3 RESET pin.................................................................................................................................536
18.5.4 Port pins (including NMI)...........................................................................................................536
18.5.5 Other signal pins .......................................................................................................................536
18.5.6 Power supply............................................................................................................................. 536
18.6 Programming Method.............................................................................................................537
18.6.1 Flash memory control................................................................................................................ 537
18.6.2 Flash memory programming mode ...........................................................................................538
18.6.3 Selection of communication mode ............................................................................................539
18.6.4 Communication command.........................................................................................................539
18.6.5 Resources used ........................................................................................................................540
CHAPTER 19 IEBus CONTROLLER (V850/SB2) ..............................................................................541
19.1 IEBus Controller Function .....................................................................................................541
19.1.1 Communication protocol of IEBus.............................................................................................541
19.1.2 Determination of bus mastership (arbitration) ........................................................................... 542
19.1.3 Communication mode ...............................................................................................................542
19.1.4 Communication address............................................................................................................543
19.1.5 Broadcasting communication .................................................................................................... 543
19.1.6 Transfer format of IEBus ...........................................................................................................544
19.1.7 Transfer data.............................................................................................................................554
19.1.8 Bit format...................................................................................................................................557
19.2 IEBus Controller Configuration.............................................................................................558
19.3 Internal Registers of IEBus Controller..................................................................................560
19.3.1 Internal register list....................................................................................................................560
19.3.2 Internal registers .......................................................................................................................561
19.4 Interrupt Operations of IEBus Controller .............................................................................584
19.4.1 Interrupt control block................................................................................................................584
19.4.2 Interrupt source list....................................................................................................................585
19.4.3 Communication error source processing list ............................................................................. 586
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19.5 Interrupt Generation Timing and Main CPU Processing ....................................................588
19.5.1 Master transmission.................................................................................................................. 588
19.5.2 Master reception ....................................................................................................................... 590
19.5.3 Slave transmission.................................................................................................................... 592
19.5.4 Slave reception .........................................................................................................................594
19.5.5 Interval of occurrence of interrupt for IEBus control.................................................................. 596
CHAPTER 20 ELECTRICAL SPECIFICATIONS .................................................................................600
CHAPTER 21 PACKAGE DRAWINGS ................................................................................................635
CHAPTER 22 RECOMMENDED SOLDERING CONDITIONS ...........................................................637
APPENDIX A NOTES ON TARGET SYSTEM DESIGN ...................................................................642
APPENDIX B REGISTER INDEX .........................................................................................................644
APPENDIX C INSTRUCTION SET LIST .............................................................................................651
APPENDIX D INDEX.............................................................................................................................. 658
APPENDIX E REVISION HISTORY...................................................................................................... 664
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Figure No. Title Page
3-1 CPU Register Set ...........................................................................................................................................97
3-2 CPU Address Space.....................................................................................................................................103
3-3 Image on Address Space .............................................................................................................................104
3-4 Program Space............................................................................................................................................. 105
3-5 Data Space...................................................................................................................................................105
3-6 Memory Map................................................................................................................................................. 106
3-7 Internal ROM Area (128 KB).........................................................................................................................107
3-8 Internal ROM/Flash Memory Area (256 KB).................................................................................................107
3-9 Internal ROM/Flash Memory Area (384 KB).................................................................................................108
3-10 Internal ROM/Flash Memory Area (512 KB).................................................................................................108
3-11 Internal RAM Area (8 KB) .............................................................................................................................110
3-12 Internal RAM Area (12 KB) ...........................................................................................................................110
3-13 Internal RAM Area (16 KB) ...........................................................................................................................111
3-14 Internal RAM Area (24 KB) ...........................................................................................................................111
3-15 On-Chip Peripheral I/O Area.........................................................................................................................112
3-16 External Memory Area (When Expanded to 64 K, 256 K, or 1 MB)..............................................................113
3-17 External Memory Area (When Expanded to 4 MB).......................................................................................114
3-18 Application of Wrap-Around..........................................................................................................................117
3-19 Recommended Memory Map (Flash Memory Version) ................................................................................118
4-1 Byte Access (8 Bits)......................................................................................................................................130
4-2 Halfword Access (16 Bits).............................................................................................................................130
4-3 Word Access (32 Bits) ..................................................................................................................................130
4-4 Memory Block ...............................................................................................................................................131
4-5 Wait Control ..................................................................................................................................................133
4-6 Example of Inserting Wait States..................................................................................................................133
4-7 Bus Hold Procedure......................................................................................................................................136
4-8 Memory Read ...............................................................................................................................................137
4-9 Memory Write ...............................................................................................................................................141
4-10 Bus Hold Timing ........................................................................................................................................... 143
5-1 Non-Maskable Interrupt Servicing ................................................................................................................150
5-2 Acknowledging Non-Maskable Interrupt Request.........................................................................................151
5-3 RETI Instruction Processing .........................................................................................................................152
5-4 Maskable Interrupt Servicing ........................................................................................................................156
5-5 RETI Instruction Processing .........................................................................................................................157
5-6 Example of Multiple Interrupt Servicing ........................................................................................................159
5-7 Example of Servicing Interrupt Requests Generated Simultaneously ..........................................................161
5-8 Software Exception Processing....................................................................................................................169
5-9 RETI Instruction Processing .........................................................................................................................170
5-10 Illegal Opcode...............................................................................................................................................171
5-11 Exception Trap Processing...........................................................................................................................172
5-12 RETI Instruction Processing .........................................................................................................................173
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5-13 Pipeline Operation at Interrupt Request Acknowledgment........................................................................... 177
5-14 Pipeline Flow and Interrupt Request Signal Generation Timing................................................................... 179
5-15 Key Return Block Diagram ........................................................................................................................... 181
6-1 Clock Generator ...........................................................................................................................................183
6-2 Oscillation Stabilization Time .......................................................................................................................196
7-1 Block Diagram of TM0 and TM1................................................................................................................... 201
7-2 Control Register Settings When TMn Operates as Interval Timer ...............................................................211
7-3 Configuration of Interval Timer .....................................................................................................................212
7-4 Timing of Interval Timer Operation............................................................................................................... 212
7-5 Control Register Settings in PPG Output Operation..................................................................................... 213
7-6 Configuration of PPG Output........................................................................................................................ 214
7-7 PPG Output Operation Timing...................................................................................................................... 214
7-8 Control Register Settings for Pulse Width Measurement with Free-Running Counter
and One Capture Register............................................................................................................................ 215
7-9 Configuration for Pulse Width Measurement with Free-Running Counter.................................................... 216
7-10 Timing of Pulse Width Measurement with Free-Running Counter and One Capture Register
(with Both Edges Specified) .........................................................................................................................216
7-11 Control Register Settings for Measurement of Two Pulse Widths with Free-Running Counter....................217
7-12 CRn1 Capture Operation with Rising Edge Specified ..................................................................................218
7-13 Timing of Pulse Width Measurement with Free-Running Counter (with Both Edges Specified) ..................218
7-14 Control Register Settings for Pulse Width Measurement with Free-Running Counter
and Two Capture Registers.......................................................................................................................... 219
7-15 Timing of Pulse Width Measurement with Free-Running Counter and Two Capture Registers
(with Rising Edge Specified).........................................................................................................................220
7-16 Control Register Settings for Pulse Width Measurement by Restarting....................................................... 221
7-17 Timing of Pulse Width Measurement by Restarting (with Rising Edge Specified) .......................................221
7-18 Control Register Settings in External Event Counter Mode..........................................................................222
7-19 Configuration of External Event Counter...................................................................................................... 223
7-20 Timing of External Event Counter Operation (with Rising Edge Specified).................................................. 223
7-21 Control Register Settings in Square Wave Output Mode .............................................................................224
7-22 Timing of Square Wave Output Operation ................................................................................................... 225
7-23 Control Register Settings for One-Shot Pulse Output with Software Trigger ...............................................226
7-24 Timing of One-Shot Pulse Output Operation with Software Trigger............................................................. 227
7-25 Control Register Settings for One-Shot Pulse Output with External Trigger ................................................228
7-26 Timing of One-Shot Pulse Output Operation with External Trigger (with Rising Edge Specified)................ 229
7-27 Start Timing of 16-Bit Timer Register n ........................................................................................................230
7-28 Timing After Changing Compare Register During Timer Count Operation...................................................230
7-29 Data Hold Timing of Capture Register..........................................................................................................231
7-30 Operation Timing of OVFn Bit ...................................................................................................................... 232
7-31 Block Diagram of TM2 to TM7...................................................................................................................... 235
7-32 Timing of Interval Timer Operation............................................................................................................... 242
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7-33 Timing of External Event Counter Operation (with Rising Edge Specified)..................................................245
7-34 Square Wave Output Operation Timing........................................................................................................246
7-35 Timing of PWM Output .................................................................................................................................248
7-36 Timing of Operation Based on CRn0 Transitions .........................................................................................249
7-37 Cascade Connection Mode with 16-Bit Resolution.......................................................................................251
7-38 Start Timing of Timer n .................................................................................................................................252
7-39 Timing After Compare Register Changes During Timer Count Operation....................................................252
8-1 Block Diagram of Watch Timer .....................................................................................................................253
8-2 Operation Timing of Watch Timer/Interval Timer..........................................................................................259
8-3 Watch Timer Interrupt Request (INTWTN) Generation (Interrupt Period = 0.5 s).........................................259
9-1 Block Diagram of Watchdog Timer ...............................................................................................................260
10-1 Block Diagram of 3-Wire Serial I/O...............................................................................................................269
10-2 CSIMn Setting (Operation Stop Mode) .........................................................................................................272
10-3 CSIMn Setting (3-Wire Serial I/O Mode).......................................................................................................273
10-4 Timing of 3-Wire Serial I/O Mode .................................................................................................................274
10-5 Block Diagram of I2C.....................................................................................................................................276
10-6 Serial Bus Configuration Example Using I2C Bus ......................................................................................... 277
10-7 Pin Configuration Diagram............................................................................................................................292
10-8 I2C Bus’s Serial Data Transfer Timing ..........................................................................................................292
10-9 Start Condition..............................................................................................................................................293
10-10 Address.........................................................................................................................................................293
10-11 Transfer Direction Specification....................................................................................................................294
10-12 ACK Signal ...................................................................................................................................................295
10-13 Stop Condition ..............................................................................................................................................296
10-14 Wait Signal....................................................................................................................................................297
10-15 Arbitration Timing Example...........................................................................................................................319
10-16 Communication Reservation Timing.............................................................................................................322
10-17 Timing for Acknowledging Communication Reservations.............................................................................322
10-18 Communication Reservation Flowchart ........................................................................................................323
10-19 Master Operation Flowchart .........................................................................................................................325
10-20 Slave Operation Flowchart ...........................................................................................................................326
10-21 Example of Master to Slave Communication
(When 9-Clock Wait Is Selected for Both Master and Slave) .......................................................................328
10-22 Example of Slave to Master Communication
(When 9-Clock Wait Is Selected for Both Master and Slave) .......................................................................331
10-23 Block Diagram of I2C.....................................................................................................................................335
10-24 Serial Bus Configuration Example Using I2C Bus ......................................................................................... 336
10-25 Pin Configuration Diagram............................................................................................................................353
10-26 I2C Bus’s Serial Data Transfer Timing ..........................................................................................................353
10-27 Start Conditions ............................................................................................................................................354
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10-28 Address ........................................................................................................................................................354
10-29 Transfer Direction Specification ................................................................................................................... 355
10-30 ACK Signal ...................................................................................................................................................356
10-31 Stop Condition .............................................................................................................................................. 357
10-32 Wait Signal ...................................................................................................................................................358
10-33 Arbitration Timing Example ..........................................................................................................................381
10-34 Communication Reservation Timing............................................................................................................. 384
10-35 Timing for Accepting Communication Reservations.....................................................................................384
10-36 Communication Reservation Flowchart........................................................................................................385
10-37 Timing at Which STTn = 1 Cannot Be Set.................................................................................................... 386
10-38 Master Communication Start or Stop Flowchart........................................................................................... 387
10-39 Master Operation Flowchart (1)....................................................................................................................389
10-40 Master Operation Flowchart (2)....................................................................................................................390
10-41 Slave Operation Flowchart ...........................................................................................................................391
10-42 Example of Master to Slave Communication
(When 9-Clock Wait Is Selected for Both Master and Slave) ....................................................................... 393
10-43 Example of Slave to Master Communication
(When 9-Clock Wait Is Selected for Both Master and Slave) ....................................................................... 396
10-44 Block Diagram of UARTn .............................................................................................................................400
10-45 ASIMn Setting (Operation Stop Mode) ......................................................................................................... 406
10-46 ASIMn Setting (Asynchronous Serial Interface Mode) .................................................................................407
10-47 ASISn Setting (Asynchronous Serial Interface Mode).................................................................................. 408
10-48 BRGCn Setting (Asynchronous Serial Interface Mode)................................................................................ 409
10-49 BRGMCn0 and BRGMCn1 Settings (Asynchronous Serial Interface Mode)................................................ 410
10-50 Error Tolerance (When k = 16), Including Sampling Errors.......................................................................... 412
10-51 Format of Transmit/Receive Data in Asynchronous Serial Interface............................................................ 413
10-52 Timing of Asynchronous Serial Interface Transmit Completion Interrupt .....................................................415
10-53 Timing of Asynchronous Serial Interface Receive Completion Interrupt ......................................................416
10-54 Receive Error Timing....................................................................................................................................417
10-55 Block Diagram of CSI4 .................................................................................................................................420
10-56 When Transfer Bit Length Other Than 16 Bits Is Set ...................................................................................421
10-57 CSIM4 Setting (Operation Stop Mode)......................................................................................................... 426
10-58 CSIM4 Setting (3-Wire Variable-Length Serial I/O Mode) ............................................................................427
10-59 CSIB4 Setting (3-Wire Variable-Length Serial I/O Mode)............................................................................. 428
10-60 Timing of 3-Wire Variable-Length Serial I/O Mode....................................................................................... 429
10-61 Timing of 3-Wire Variable-Length Serial I/O Mode (When CSIB4 = 08H) .................................................... 430
11-1 Block Diagram of A/D Converter ..................................................................................................................432
11-2 Basic Operation of A/D Converter ................................................................................................................ 439
11-3 Relationship Between Analog Input Voltage and A/D Conversion Result.................................................... 440
11-4 A/D Conversion by Hardware Start (with Falling Edge Specified)................................................................ 441
11-5 A/D Conversion by Software Start................................................................................................................ 442
11-6 Handling of Analog Input Pin........................................................................................................................444
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11-7 A/D Conversion End Interrupt Generation Timing ........................................................................................445
11-8 Handling of AVDD Pin ....................................................................................................................................446
11-9 Overall Error .................................................................................................................................................447
11-10 Quantization Error.........................................................................................................................................448
11-11 Zero-Scale Error ...........................................................................................................................................448
11-12 Full-Scale Error.............................................................................................................................................449
11-13 Differential Linearity Error .............................................................................................................................449
11-14 Integral Linearity Error ..................................................................................................................................450
11-15 Sampling Time..............................................................................................................................................450
12-1 Block Diagram of DMA .................................................................................................................................452
12-2 Correspondence Between DRAn Setting Value and Internal RAM (8 KB) ...................................................455
12-3 Correspondence Between DRAn Setting Value and Internal RAM (12 KB) .................................................456
12-4 Correspondence Between DRAn Setting Value and Internal RAM (16 KB) .................................................457
12-5 Correspondence Between DRAn Setting Value and Internal RAM (24 KB) .................................................458
12-6 DMA Transfer Operation Timing...................................................................................................................462
12-7 Processing When Transfer Requests DMA0 to DMA5 Are Generated Simultaneously ...............................463
12-8 When Interrupt Servicing Occurs Twice During DMA Operation ..................................................................464
13-1 Block Diagram of RTO..................................................................................................................................467
13-2 Configuration of Real-Time Output Buffer Registers ....................................................................................468
13-3 Example of Operation Timing of RTO (When EXTR = 0, BYTE = 0)............................................................472
14-1 Block Diagram of P00 to P07........................................................................................................................478
14-2 Block Diagram of P10 to P12, P14, and P15................................................................................................481
14-3 Block Diagram of P13...................................................................................................................................482
14-4 Block Diagram of P20 to P22, P24, and P25................................................................................................486
14-5 Block Diagram of P23, P26, and P27 ...........................................................................................................487
14-6 Block Diagram of P30 to P32 and P35 to P37..............................................................................................490
14-7 Block Diagram of P33 and P34.....................................................................................................................491
14-8 Block Diagram of P40 to P47 and P50 to P57..............................................................................................494
14-9 Block Diagram P60 to P65............................................................................................................................497
14-10 Block Diagram of P70 to P77 and P80 to P83..............................................................................................499
14-11 Block Diagram of P90 to P96........................................................................................................................502
14-12 Block Diagram of P100 to P107....................................................................................................................506
14-13 Block Diagram of P110 to P113....................................................................................................................510
15-1 System Reset Timing....................................................................................................................................516
16-1 Regulator ......................................................................................................................................................517
17-1 Block Diagram of ROM Correction................................................................................................................518
17-2 ROM Correction Operation and Program Flow.............................................................................................522
24
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LIST OF FIGURES (6/6)
Figure No. Title Page
18-1 Wiring Example of V850/SB1 and V850/SB2 Flash Writing Adapter (FA-100GC-8EU)............................... 526
18-2 Wiring Example of V850/SB1 and V850/SB2 Flash Writing Adapter (FA-100GF-3BA) ...............................528
18-3 Environment Required for Writing Programs to Flash Memory.................................................................... 530
18-4 Communication with Dedicated Flash Programmer (UART0) ...................................................................... 530
18-5 Communication with Dedicated Flash Programmer (CSI0).......................................................................... 531
18-6 Communication with Dedicated Flash Programmer (CSI0 + HS) ................................................................. 531
18-7 VPP Pin Connection Example........................................................................................................................ 533
18-8 Conflict of Signals (Serial Interface Input Pin)..............................................................................................534
18-9 Malfunction of Other Device ......................................................................................................................... 535
18-10 Conflict of Signals (RESET Pin) ................................................................................................................... 536
18-11 Procedure for Manipulating Flash Memory................................................................................................... 537
18-12 Flash Memory Programming Mode ..............................................................................................................538
18-13 Communication Command ........................................................................................................................... 539
19-1 IEBus Transfer Signal Format ...................................................................................................................... 544
19-2 Master Address Field....................................................................................................................................545
19-3 Slave Address Field .....................................................................................................................................546
19-4 Control Field ................................................................................................................................................. 548
19-5 Telegraph Length Field ................................................................................................................................550
19-6 Data Field ..................................................................................................................................................... 551
19-7 Bit Configuration of Slave Status.................................................................................................................. 555
19-8 Configuration of Lock Address .....................................................................................................................556
19-9 Bit Format of IEBus ......................................................................................................................................557
19-10 IEBus Controller Block Diagram ................................................................................................................... 558
19-11 Interrupt Generation Timing (for (1), (3), and (4))......................................................................................... 567
19-12 Interrupt Generation Timing (for (2) and (5)) ................................................................................................ 568
19-13 Timing of INTIE2 Interrupt Generation in Locked State (for (4) and (5)) ......................................................568
19-14 Timing of INTIE2 Interrupt Generation in Locked State (for (3))................................................................... 569
19-15 Example of Broadcasting Communication Flag Operation...........................................................................573
19-16 Configuration of Interrupt Control Block .......................................................................................................584
19-17 Master Transmission ....................................................................................................................................588
19-18 Master Reception .........................................................................................................................................590
19-19 Slave Transmission ......................................................................................................................................592
19-20 Slave Reception ...........................................................................................................................................594
19-21 Master Transmission (Interval of Interrupt Occurrence) ............................................................................... 596
19-22 Master Reception (Interval of Interrupt Occurrence) ....................................................................................597
19-23 Slave Transmission (Interval of Interrupt Occurrence) ................................................................................. 598
19-24 Slave Reception (Interval of Interrupt Occurrence) ......................................................................................599
A-1 100-Pin Plastic LQFP (Fine Pitch) (14 × 14) ................................................................................................642
A-2 100-Pin Plastic QFP (14 × 20)...................................................................................................................... 643
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Page 26
LIST OF TABLES (1/3)
Table No. Title Page
1-1 Product Lineup of V850/SB1 ..........................................................................................................................30
1-2 Product Lineup of V850/SB2 ..........................................................................................................................31
2-1 Pin I/O Buffer Power Supplies ........................................................................................................................73
2-2 Differences in Pins Between V850/SB1 and V850/SB2 .................................................................................73
2-3 Operating States of Pins in Each Operating Mode .........................................................................................80
3-1 Program Registers.......................................................................................................................................... 98
3-2 System Register Numbers..............................................................................................................................99
3-3 Interrupt/Exception Table..............................................................................................................................109
4-1 Bus Control Pins ...........................................................................................................................................128
4-2 Number of Access Clocks.............................................................................................................................129
4-3 Bus Priority ...................................................................................................................................................144
5-1 Interrupt Source List .....................................................................................................................................147
5-2 Interrupt Control Register (xxICn).................................................................................................................164
5-3 Priorities of Interrupts and Exceptions..........................................................................................................174
5-4 Description of Key Return Detection Pin ......................................................................................................180
6-1 Operating Statuses in HALT Mode ...............................................................................................................190
6-2 Operating Statuses in IDLE Mode ................................................................................................................192
6-3 Operating Statuses in Software STOP Mode ...............................................................................................194
7-1 Configuration of Timers 0 and 1 ...................................................................................................................202
7-2 Valid Edge of TIn0 Pin and Capture Trigger of CRn0...................................................................................203
7-3 Valid Edge of TIn1 Pin and Capture Trigger of CRn0...................................................................................203
7-4 TIn0 Pin Valid Edge and CRn1 Capture Trigger...........................................................................................204
7-5 Configuration of Timers 2 to 7 ......................................................................................................................235
8-1 Interval Time of Interval Timer......................................................................................................................254
8-2 Configuration of Watch Timer .......................................................................................................................254
8-3 Interval Time of Interval Timer......................................................................................................................258
9-1 Inadvertent Program Loop Detection Time of Watchdog Timer....................................................................261
9-2 Interval Time of Interval Timer......................................................................................................................261
9-3 Configuration of Watchdog Timer .................................................................................................................262
9-4 Inadvertent Program Loop Detection Time of Watchdog Timer....................................................................265
9-5 Interval Time of Interval Timer......................................................................................................................266
10-1 Configuration of CSIn ...................................................................................................................................269
10-2 Configuration of I2Cn.....................................................................................................................................278
10-3 Selection Clock Setting.................................................................................................................................290
26
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LIST OF TABLES (2/3)
Table No. Title Page
10-4 INTIICn Generation Timing and Wait Control............................................................................................... 317
10-5 Extension Code Bit Definitions ..................................................................................................................... 319
10-6 Status During Arbitration and Interrupt Request Generation Timing............................................................ 320
10-7 Wait Periods ................................................................................................................................................. 321
10-8 Configuration of I2Cn.....................................................................................................................................337
10-9 Selection Clock Setting ................................................................................................................................351
10-10 INTIICn Generation Timing and Wait Control............................................................................................... 378
10-11 Extension Code Bit Definitions .....................................................................................................................380
10-12 Status During Arbitration and Interrupt Request Generation Timing ............................................................ 381
10-13 Wait Periods .................................................................................................................................................383
10-14 Wait Time .....................................................................................................................................................386
10-15 Configuration of UARTn ...............................................................................................................................399
10-16 Relationship Between Main Clock and Baud Rate ....................................................................................... 411
10-17 Receive Error Causes ..................................................................................................................................417
10-18 Configuration of CSI4 ...................................................................................................................................419
11-1 Configuration of A/D Converter ....................................................................................................................433
12-1 Internal RAM Area Usable in DMA............................................................................................................... 454
13-1 Configuration of RTO....................................................................................................................................467
13-2 Operation When Real-Time Output Buffer Registers Are Manipulated........................................................ 468
13-3 Operation Mode and Output Trigger of Real-Time Output Port.................................................................... 470
14-1 Pin I/O Buffer Power Supplies...................................................................................................................... 474
14-2 Port 0 Alternate Function Pins...................................................................................................................... 475
14-3 Port 1 Alternate Function Pins...................................................................................................................... 479
14-4 Port 2 Alternate Function Pins...................................................................................................................... 483
14-5 Port 3 Alternate Function Pins...................................................................................................................... 488
14-6 Alternate Function Pins of Ports 4 and 5......................................................................................................492
14-7 Port 6 Alternate Function Pins...................................................................................................................... 495
14-8 Alternate Function Pins of Ports 7 and 8......................................................................................................498
14-9 Port 9 Alternate Function Pins...................................................................................................................... 500
14-10 Port 10 Alternate Function Pins....................................................................................................................503
14-11 Port 11 Alternate Function Pins....................................................................................................................507
14-12 Setting When Port Pin Is Used as Alternate Function .................................................................................. 511
18-1 Table for Wiring of V850/SB1 and V850/SB2 Flash Writing Adapter (FA-100GC-8EU)...............................527
18-2 Table for Wiring of V850/SB1 and V850/SB2 Flash Writing Adapter (FA-100GF-3BA) ............................... 529
18-3 Signal Generation of Dedicated Flash Programmer (PG-FP3).....................................................................532
18-4 Pins Used in Serial Interfaces ......................................................................................................................533
18-5 List of Communication Modes ...................................................................................................................... 539
18-6 Flash Memory Control Command.................................................................................................................540
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LIST OF TABLES (3/3)
Table No. Title Page
18-7 Response Command....................................................................................................................................540
19-1 Transfer Rate and Maximum Number of Transfer Bytes in Communication Mode 1....................................542
19-2 Contents of Control Bits................................................................................................................................547
19-3 Control Field for Locked Slave Unit ..............................................................................................................548
19-4 Control Field for Unlocked Slave Unit...........................................................................................................548
19-5 Acknowledge Signal Output Condition of Control Field................................................................................549
19-6 Contents of Telegraph Length Bit.................................................................................................................550
19-7 Internal Registers of IEBus Controller .......................................................................................................... 560
19-8 Reset Conditions of Flags in ISR Register ...................................................................................................575
19-9 Interrupt Source List .....................................................................................................................................585
19-10 Communication Error Source Processing List ..............................................................................................586
22-1 Surface Mounting Type Soldering Conditions ..............................................................................................637
C-1 Symbols in Operand Description..................................................................................................................651
C-2 Symbols Used for Opcode............................................................................................................................652
C-3 Symbols Used for Operation Description......................................................................................................652
C-4 Symbols Used for Flag Operation.................................................................................................................653
C-5 Condition Codes ...........................................................................................................................................653
28
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CHAPTER 1 INTRODUCTION
The V850/SB1 and V850/SB2 are products in the NEC Electronics V850 Series of single-chip microcontrollers
designed for low power operation.
1.1 General
The V850/SB1 and V850/SB2 are 32-bit single-chip microcontrollers that include the V850 Series CPU core, and
peripheral functions such as ROM/RAM, a timer/counter, a serial interface, an A/D converter, a timer, and DMA
controller.
Based on the V850/SA1™, the V850/SB1 and V850/SB2 feature various additions, including 3 to 5 V I/O interface
support, and ROM correction. For V850/SB2, based on the V850/SB1™, the peripheral functions of automobile LAN
(IEBus™ (Inter Equipment Bus™)) are added. In addition to high real-time response characteristics and 1-clock-pitch
basic instructions, the V850/SB1 and V850/SB2 have multiply, saturation operation, and bit manipulation instructions
realized with a hardware multiplier for digital servo control. Moreover, as a real-time control system, the V850/SB1
and V850/SB2 enable the realization of extremely high cost-performance for applications that require low power
consumption, such as audio equipment, car audio systems, and VCRs.
Table 1-1 shows the outlines of the V850/SB1 and V850/SB2 product lineup.
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CHAPTER 1 INTRODUCTION
Table 1-1. Product Lineup of V850/SB1
Product Name ROM
Commercial Name Part Number
V850/SB1
PD703031A No
µ
PD703031AY Yes
µ
PD703033A Mask ROM
µ
PD70F3033A
µ
PD703033AY Mask ROM
µ
PD70F3033AY
µ
PD703032A Mask ROM
µ
PD70F3032A
µ
PD703032AY Mask ROM
µ
PD70F3032AY
µ
PD703031B No
µ
PD703031BY Yes
µ
PD703033B Mask ROM
µ
PD70F3033B
µ
PD703033BY Mask ROM
µ
PD70F3033BY
µ
PD703030B Mask ROM
µ
PD70F3030B
µ
PD703030BY Mask ROM
µ
PD70F3030BY
µ
PD703032B Mask ROM
µ
PD70F3032B
µ
PD703032BY Mask ROM
µ
PD70F3032BY
µ
On-Chip
2
I
C
No
Yes
No
Yes
No
Yes
No
Yes
No
Yes
RAM Size Package On-Chip
Type Size
Mask ROM 128 KB 12 KB 100-pin QFP (14 × 20)/
100-pin LQFP (14 × 14)
256 KB 16 KB 100-pin QFP (14 × 20)/
Flash memory
Flash memory
512 KB 24 KB 100-pin QFP (14 × 20)
Flash memory
Flash memory
Mask ROM 128 KB 8 KB 100-pin QFP (14 × 20)/
256 KB 16 KB 100-pin QFP (14 × 20)/
Flash memory
Flash memory
384 KB 24 KB 100-pin QFP (14 × 20)/
Flash memory
Flash memory
512 KB 24 KB 100-pin QFP (14 × 20)
Flash memory
Flash memory
100-pin LQFP (14 × 14)
100-pin LQFP (14 × 14)
100-pin LQFP (14 × 14)
100-pin LQFP (14 × 14)
IEBus
No
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CHAPTER 1 INTRODUCTION
Table 1-2. Product Lineup of V850/SB2
Product Name ROM
Commercial Name Part Number
V850/SB2
PD703034A No
µ
PD703034AY Yes
µ
PD703035A Mask ROM
µ
PD70F3035A
µ
PD703035AY Mask ROM
µ
PD70F3035AY
µ
PD703037A Mask ROM
µ
PD70F3037A
µ
PD703037AY Mask ROM
µ
PD70F3037AY
µ
PD703034B No
µ
PD703034BY Yes
µ
PD703035B Mask ROM
µ
PD70F3035B
µ
PD703035BY Mask ROM
µ
PD70F3035BY
µ
PD703036H Mask ROM
µ
PD70F3036H
µ
PD703036HY Mask ROM
µ
PD70F3036HY
µ
PD703037H Mask ROM
µ
PD70F3037H
µ
PD703037HY Mask ROM
µ
PD70F3037HY
µ
On-Chip
2
I
C
No
Yes
No
Yes
No
Yes
No
Yes
No
Yes
RAM Size Package On-Chip
Type Size
Mask ROM 128 KB 12 KB 100-pin QFP (14 × 20)/
100-pin LQFP (14 × 14)
256 KB 16 KB 100-pin QFP (14 × 20)/
Flash memory
Flash memory
512 KB 24 KB 100-pin QFP (14 × 20)
Flash memory
Flash memory
Mask ROM 128 KB 8 KB 100-pin QFP (14 × 20)/
256 KB 16 KB 100-pin QFP (14 × 20)/
Flash memory
Flash memory
384 KB 24 KB 100-pin QFP (14 × 20)/
Flash memory
Flash memory
512 KB 24 KB 100-pin QFP (14 × 20)
Flash memory
Flash memory
100-pin LQFP (14 × 14)
100-pin LQFP (14 × 14)
100-pin LQFP (14 × 14)
100-pin LQFP (14 × 14)
IEBus
Yes
The part numbers of the V850/SB1 and V850/SB2 are described as follows in this manual.
• A versions
A versions of the V850/SB1:µPD703031A, 703031AY, 703032A, 703032AY, 703033A, 703033AY,
70F3032A, 70F3032AY, 70F3033A, 70F3033AY
A versions of the V850/SB2:µPD703034A, 703034AY, 703035A, 703035AY, 703037A, 703037AY,
70F3035A, 70F3035AY, 70F3037A, 70F3037AY
• B versions, H versions
B versions of the V850/SB1:
PD703030B, 703030BY, 703031B, 703031BY, 703032B, 703032BY,
µ
703033B, 703033BY, 70F3030B, 70F3030BY, 70F3032B, 70F3032BY,
70F3033B, 70F3033BY
B and H versions of the V850/SB2:µPD703034B, 703034BY, 703035B, 703035BY, 703036H, 703036HY,
703037H, 703037HY, 70F3035B, 70F3035BY, 70F3036H, 70F3036HY,
70F3037H, 70F3037HY
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CHAPTER 1 INTRODUCTION
• Flash memory versions
Flash memory versions of the V850/SB1:
PD70F3030B, 70F3030BY, 70F3032A, 70F3032AY, 70F3032B,
µ
70F3032BY, 70F3033A, 70F3033AY, 70F3033B, 70F3033BY
Flash memory versions of the V850/SB2:µPD70F3035A, 70F3035AY, 70F3035B, 70F3035BY, 70F3036H,
70F3036HY, 70F3037A, 70F3037AY, 70F3037H, 70F3037HY
• Mask ROM versions
Mask ROM versions of the V850/SB1:µPD703030B, 703030BY, 703031A, 703031AY, 703031B, 703031BY,
703032A, 703032AY, 703032B, 703032BY, 703033A, 703033AY,
703033B, 703033BY
Mask ROM versions of the V850/SB2:µPD703034A, 703034AY, 703034B, 703034BY, 703035A, 703035AY,
703035B, 703035BY, 703036H, 703036HY, 703037A, 703037AY,
703037H, 703037HY
• Y versions (with on-chip I2C)
Y versions of the V850/SB1 (with on-chip I2C):µPD703030BY, 703031AY, 703031BY, 703032AY, 703032BY,
703033AY, 703033BY, 70F3030BY, 70F3032AY, 70F3032BY,
70F3033AY, 70F3033BY
Y versions of the V850/SB2 (with on-chip I2C):µPD703034AY, 703034BY, 703035AY, 703035BY, 703036HY,
703037AY, 703037HY, 70F3035AY, 70F3035BY, 70F3036HY,
70F3037AY, 70F3037BY
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CHAPTER 1 INTRODUCTION
1.2 V850/SB1 (A Versions)
1.2.1 Features (V850/SB1 (A versions))
{ Number of instructions: 74
{ Minimum instruction execution time
50 ns (operating at 20 MHz, external power supply 5 V, regulator output 3.3 V)
{ General-purpose registers 32 bits × 32 registers
{ Instruction set Signed multiplication (16 × 16 → 32): 100 ns (operating at 20 MHz)
(able to execute instructions in parallel continuously without creating any register
hazards).
Saturation operations (overflow and underflow detection functions are included)
32-bit shift instruction: 1 clock
Bit manipulation instructions
Load/store instructions with long/short format
{ Memory space 16 MB of linear address space (for programs and data)
External expandability: expandable to 4 MB
Memory block allocation function: 2 MB per block
Programmable wait function
Idle state insertion function
{ External bus interface 16-bit data bus (address/data multiplex)
Address bus: separate output enabled
3 V to 5 V interface enabled
Bus hold function
External wait function
{ Internal memory
{ Interrupts and exceptions Non-maskable interrupts: 2 sources
{ I/O lines Total: 83 (12 input ports and 71 I/O ports)
{ Timer/counter 16-bit timer: 2 channels (PWM output)
{ Watch timer When operating under subclock or main clock: 1 channel
{ Watchdog timer 1 channel
PD703031A, 703031AY (mask ROM: 128 KB/RAM: 12 KB)
µ
PD703033A, 703033AY (mask ROM: 256 KB/RAM: 16 KB)
µ
PD703032A, 703032AY (mask ROM: 512 KB/RAM: 24 KB)
µ
PD70F3033A, 70F3033AY (flash memory: 256 KB/RAM: 16 KB)
µ
PD70F3032A, 70F3032AY (flash memory: 512 KB/RAM: 24 KB)
µ
Maskable interrupts: 37 sources (µPD703031A, 703032A, 703033A, 70F3032A,
70F3033A)
38 sources (µPD703031AY, 703032AY, 703033AY,
70F3032AY, 70F3033AY)
Software exceptions: 32 sources
Exception trap: 1 source
3 V to 5 V interface enabled
8-bit timer: 6 channels (4 PWM outputs, cascade connection enabled)
Operation using the subclock or main clock is also possible in the IDLE mode.
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CHAPTER 1 INTRODUCTION
{ Serial interface (SIO) Asynchronous serial interface (UART)
Clocked serial interface (CSI)
I2C bus interface (I2C) (only for µPD703031AY, 703032AY, 703033AY, 70F3032AY,
and 70F3033AY)
8-/16-bit variable-length serial interface
CSI/UART: 2 channels
CSI/I2C: 2 channels
CSI (8-/16-bit valuable): 1 channel
Dedicated baud rate generator: 3 channels
{ A/D converter 10-bit resolution: 12 channels
{ DMA controller Internal RAM ←→ on-chip peripheral I/O: 6 channels
{ Real-time output port (RTP) 8 bits × 1 channel or 4 bits × 2 channels
{ ROM correction Modifiable 4 points
{ Regulator 4.0 V to 5.5 V input → internal 3.3 V
{ Key return function 4 to 8 selecting enabled, falling edge fixed
{ Clock generator During main clock or subclock operation
5-level CPU clock (including sub operations)
{ Power-saving functions HALT/IDLE/STOP modes
{ Package 100-pin plastic LQFP (fine pitch, 14 × 14)
100-pin plastic QFP (14 × 20)
{ CMOS structure All static circuits
1.2.2 Application fields (V850/SB1 (A versions))
AV equipment
Example: Audio, car audio equipment, VCR, and TV.
34
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CHAPTER 1 INTRODUCTION
1.2.3 Ordering information (V850/SB1 (A versions))
Part Number Package Internal ROM
PD703031AGC-xxx-8EU
µ
PD703031AGF-xxx-3BA
µ
PD703031AYGC-xxx-8EU
µ
PD703031AYGF-xxx-3BA
µ
PD703033AGC-xxx-8EU
µ
PD703033AGF-xxx-3BA
µ
PD703033AYGC-xxx-8EU
µ
PD703033AYGF-xxx-3BA
µ
PD703032AGF-xxx-3BA
µ
PD703032AYGF-xxx-3BA
µ
PD70F3033AGC-8EU
µ
PD70F3033AGF-3BA
µ
PD70F3033AYGC-8EU
µ
PD70F3033AYGF-3BA
µ
PD70F3032AGF-3BA
µ
PD70F3032AYGF-3BA
µ
100-pin plastic LQFP (fine pitch) (14 × 14)
100-pin plastic QFP (14 × 20)
100-pin plastic LQFP (fine pitch) (14 × 14)
100-pin plastic QFP (14 × 20)
100-pin plastic LQFP (fine pitch) (14 × 14)
100-pin plastic QFP (14 × 20)
100-pin plastic LQFP (fine pitch) (14 × 14)
100-pin plastic QFP (14 × 20)
100-pin plastic QFP (14 × 20)
100-pin plastic QFP (14 × 20)
100-pin plastic LQFP (fine pitch) (14 × 14)
100-pin plastic QFP (14 × 20)
100-pin plastic LQFP (fine pitch) (14 × 14)
100-pin plastic QFP (14 × 20)
100-pin plastic QFP (14 × 20)
100-pin plastic QFP (14 × 20)
Mask ROM (128 KB)
Mask ROM (128 KB)
Mask ROM (128 KB)
Mask ROM (128 KB)
Mask ROM (256 KB)
Mask ROM (256 KB)
Mask ROM (256 KB)
Mask ROM (256 KB)
Mask ROM (512 KB)
Mask ROM (512 KB)
Flash memory (256 KB)
Flash memory (256 KB)
Flash memory (256 KB)
Flash memory (256 KB)
Flash memory (512 KB)
Flash memory (512 KB)
Remarks 1. ××× indicates ROM code suffix.
2. ROMless devices are not provided.
User’s Manual U13850EJ6V0UD
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CHAPTER 1 INTRODUCTION
N
t
2
N
t
2
A
A
A
N
t
2
1.2.4 Pin configuration (top view) (V850/SB1 (A versions))
100-pin plastic LQFP (fine pitch) (14 × 14)
PD703031AGC-xxx-8EU •µPD70F3033AGC-8EU
•
µ
• µPD703031AYGC-xxx-8EU •µPD70F3033AYGC-8EU
• µPD703033AGC-xxx-8EU
• µPD703033AYGC-xxx-8EU
e
e
o
o
e
o
P21/SO2
P22/SCK2/SCL1
Note 2
P23/RXD1/SI3
P24/TXD1/SO3
P25/ASCK1/SCK3
EV
EV
P26/TI2/TO2
P27/TI3/TO3
P30/TI00
P31/TI01
P32/TI10/SI4
P33/TI11/SO4
P34/TO0/A13/SCK4
P35/TO1/A14
P36/TI4/TO4/A15
P37/TI5/TO5
Note 1
IC/V
PP
P100/RTP0/KR0/A5
P101/RTP1/KR1/A6
P102/RTP2/KR2/A7
P103/RTP3/KR3/A8
P104/RTP4/KR4/A9
P105/RTP5/KR5/A10
P106/RTP6/KR6/A11
P20/SI2/SDA1
P14/SO1/TXD0
P13/SI1/RXD0
P15/SCK1/ASCK0
9998979695949392919089888786858483828180797877
100
1
2
3
4
DD
SS
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
27
2829303132333435363738394041424344454647484950
26
P07/INTP6
P11/SO0
P10/SI0/SDA0
P12/SCK0/SCL0
P06/INTP5/RTPTRG
P05/INTP4/ADTRG
P04/INTP3
P03/INTP2
P02/INTP1
P01/INTP0
P00/NMI
P83/ANI11
P82/ANI10
P81/ANI9
P80/ANI8
P77/ANI7
P76/ANI6
P75/ANI5
P74/ANI4
P73/ANI3
P72/ANI2
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
P71/ANI1
P70/ANI0
V
REF
V
SS
V
DD
P65/A21
P64/A20
P63/A19
P62/A18
P61/A17
P60/A16
P57/AD15
P56/AD14
P55/AD13
P54/AD12
P53/AD11
P52/AD10
P51/AD9
P50/AD8
BV
SS
BV
DD
P47/AD7
P46/AD6
P45/AD5
P44/AD4
SS
DD
X2
X1
V
XT1
XT2
REGC
RESET
P112/A3
P113/A4
P111/A2
P110/WAIT/A1
V
CLKOUT
P90/LBEN/WRL
P91/UBEN
P92/R/W/WRH
P93/DSTB/RD
P94/ASTB
P95/HLDAK
P96/HLDRQ
P40/AD0
P41/AD1
P42/AD2
P43/AD3
P107/RTP7/KR7/A12
Notes 1. IC (
PD703031A, 703031AY, 703033A, 703033AY): Connect directly to VSS.
µ
VPP (µPD70F3033A, 70F3033AY): Connect to VSS in normal operation mode.
2. SCL0, SCL1, SDA0, and SDA1 are available only in the µPD703031AY, 703033AY, and 70F3033AY.
36
User’s Manual U13850EJ6V0UD
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CHAPTER 1 INTRODUCTION
L
100-pin plastic QFP (14 × 20)
• µPD703031AGF-xxx-3BA • µPD703033AGF-xxx-3BA • µPD70F3033AGF-3BA
• µPD703031AYGF-xxx-3BA • µPD703033AYGF-xxx-3BA • µPD70F3033AYGF-3BA
• µPD703032AGF-xxx-3BA • µPD70F3032AGF-3BA
• µPD703032AYGF-xxx-3BA • µPD70F3032AYGF-3BA
Note 2
Note 2
P13/SI1/RXD0
P11/SO0
P10/SI0/SDA0
P07/INTP6
P06/INTP5/RTPTRG
P05/INTP4/ADTRG
P04/INTP3
P03/INTP2
P02/INTP1
P01/INTP0
P00/NMI
P83/ANI11
P82/ANI10
P81/ANI9
P80/ANI8
P77/ANI7
P76/ANI6
P75/ANI5
P74/ANI4
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
P73/ANI3
P72/ANI2P15/SCK1/ASCK0
P71/ANI1
P70/ANI0
REF
AV
AV
SS
DD
AV
P65/A21
P64/A20
P63/A19
P62/A18
P61/A17
P60/A16
P57/AD15
P56/AD14
P55/AD13
P54/AD12
P53/AD11
P52/AD10
P51/AD9
P50/AD8
SS
BV
DD
BV
P47/AD7
P46/AD6
P45/AD5
P44/AD4
P43/AD3
P42/AD2
P41/AD1
P14/SO1/TXD0
P20/SI2/SDA1
P22/SCK2/SCL1
Note 2
P21/SO2
Note 2
P23/RXD1/SI3
P24/TXD1/SO3
P25/ASCK1/SCK3
EV
EV
P26/TI2/TO2
P27/TI3/TO3
P30/TI00
P31/TI01
P32/TI10/SI4
P33/TI11/SO4
P34/TO0/A13/SCK4
P35/TO1/A14
P36/TI4/TO4/A15
P37/TI5/TO5
Note 1
PP
IC/V
P100/RTP0/KR0/A5
P101/RTP1/KR1/A6
P102/RTP2/KR2/A7
P103/RTP3/KR3/A8
P104/RTP4/KR4/A9
P105/RTP5/KR5/A10
P106/RTP6/KR6/A11
P107/RTP7/KR7/A12
P110/WAIT/A1
P12/SCK0/SCL0
99989796959493929190898887868584838281
10031
1
2
3
4
5
6
7
DD
SS
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
32333435363738394041424344454647484950
SS
DD
X2
X1
V
V
CLKOUT
P90/LBEN/WR
P91/UBEN
P92/R/W/WRH
P93/DSTB/RD
P94/ASTB
P95/HLDAK
P40/AD0
P96/HLDRQ
Notes 1. IC (
XT1
XT2
REGC
RESET
P111/A2
P112/A3
P113/A4
PD703031A, 703031AY, 703032A, 703032AY, 703033A, 703033AY):
µ
Connect directly to VSS.
VPP (µPD70F3032A, 70F3032AY, 70F3033A, 70F3033AY):
Connect to VSS in normal operation mode.
2. SCL0, SCL1, SDA0, and SDA1 are available only in the µPD703031AY, 703032AY, 703033AY,
70F3032AY, and 70F3033AY.
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CHAPTER 1 INTRODUCTION
Pin names (V850/SB1 (A versions))
A1 to A21: Address bus P70 to P77: Port 7
AD0 to AD15: Address/data bus P80 to P83: Port 8
ADTRG: A/D trigger input P90 to P96: Port 9
ANI0 to ANI11: Analog input P100 to P107: Port 10
ASCK0, ASCK1: Asynchronous serial clock P110 to P113: Port 11
ASTB: Address strobe RD: Read
: Analog V
AVDD
AV
: Analog reference voltage RESET: Reset
REF
AVSS: Analog V
DD
SS
REGC: Regulator control
RTP0 to RTP7: Real-time output port
BVDD: Power supply for bus interface RTPTRG: RTP trigger
BVSS: Ground for bus interface R/W: Read/write status
CLKOUT: Clock output RXD0, RXD1: Receive data
DSTB: Data strobe SCK0 to SCK4: Serial clock
EVDD: Power supply for port SCL0, SCL1: Serial clock
EVSS: Ground for port SDA0, SDA1: Serial data
HLDAK: Hold acknowledge SI0 to SI4: Serial input
HLDRQ: Hold request SO0 to SO4: Serial output
IC: Internally connected TI00, TI01, TI10,
INTP0 to INTP6: Interrupt request from peripherals TI11, TI2 to TI5: Timer input
KR0 to KR7
:
Key return TO0 to TO5: Timer output
LBEN: Lower byte enable TXD0,TXD1: Transmit data
NMI: Non-maskable interrupt request UBEN: Upper byte enable
P00 to P07: Port 0 VDD: Power supply
P10 to P15: Port 1 VPP: Programming power supply
P20 to P27: Port 2 VSS: Ground
P30 to P37: Port 3 WAIT: Wait
P40 to P47: Port 4 WRH: Write strobe high level data
P50 to P57: Port 5 WRL: Write strobe low level data
P60 to P65: Port 6 X1, X2: Crystal for main clock
XT1, XT2: Crystal for subclock
38
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CHAPTER 1 INTRODUCTION
N
3
A
)
Note 3
(
)
)
)
)
)
)
)
)
Note 3
Note 3
Note 5
Note 6
1.2.5 Function blocks (V850/SB1 (A versions))
(1) Internal block diagram
ROM
Note
1
RAM
Note
2
P110 to P113
P100 to P107
INTP0 to INTP6
TI00,TI01,
TI10,TI11
TO0,TO1
TI2/TO2
TI3/TO3
TI4/TO4
TI5/TO5
SO0
SI0/SDA0
SCK0/SCL0
SO2
SI2/SDA1
SCK2/SCL1
SO1/TXD0
SI1/RXD0
SCK1/ASCK0
SO3/TXD1
SI3/RXD1
SCK3/ASCK1
SO4
SCK4
KR0 to KR7
NMI
ote
SI4
INTC
Timer/counter
16-bit timer:
TM0, TM1
8-bit timer:
TM2 to TM7
SIO
CSI0/I2C0
Note 4
CSI2/I2C1
Note 4
CSI1/UART0
CSI3/UART1
Variable
length CSI4
Key return
DMAC: 6 ch
PC
32-bit barrel
shifter
System
register
General-purpose
registers
32 bits × 32
Ports
P70 to P77
P80 to P83
P90 to P96
P60 to P65
CPU
ROM
correction
Multiplier
16 ×16→32
ALU
RTP
P40 to P47
P20 to P27
P30 to P37
P50 to P57
P10 to P15
P00 to P07
RTP0 to RTP7
3.3 V
RTPTRG
Instruction
queue
BCU
A/D
converter
SS
DD
REF
AV
AV
AV
Regulator
ANI0 to ANI11
HLDRQ (P96
HLDAK
STB (P94
DSTB/RD (P93
R/W /W RH (P92
UBEN (P91
LBEN/WRL (P90
WAIT (P110
A1 to A12
(P100 to P107,
P110 to P113
A13 to A15 (P34 to P36)
A16 to A21 (P60 to P65)
AD0 to AD15
(P40 to P47, P50 to P57)
CLKOUT
X1
X2
CG
XT1
XT2
RESET
ADTRG
V
DD
P95
SS
V
BV
BV
EV
EV
V
IC
DD
SS
DD
SS
PP
Notes 1.
Watch timer
Watchdog
timer
PD703031A, 703031AY: 128 KB (mask ROM)
µ
PD703033A, 703033AY: 256 KB (mask ROM)
µ
PD703032A, 703032AY: 512 KB (mask ROM)
µ
PD70F3033A, 70F3033AY: 256 KB (flash memory)
µ
PD70F3032A, 70F3032AY: 512 KB (flash memory)
µ
REGC
2.µPD703031A, 703031AY: 12 KB
PD703033A, 703033AY, 70F3033A, 70F3033AY: 16 KB
µ
PD703032A, 703032AY, 70F3032A, 70F3032AY: 24 KB
µ
3. SDA0, SDA1, SCL0, and SCL1 pins are available only in the µPD703031AY, 703032AY, 703033AY,
70F3032AY, and 70F3033AY.
4. I2C function is available only in the µPD703031AY, 703032AY, 703033AY, 70F3032AY, and
70F3033AY.
5.µPD70F3032A, 70F3032AY, 70F3033A, 70F3033AY
6.µPD703031A, 703031AY, 703032A, 703032AY, 703033A, 703033AY
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39
Page 40
(2) Internal units
(a) CPU
The CPU uses five-stage pipeline control to enable single-clock execution of address calculations,
arithmetic logic operations, data transfers, and almost all other instruction processing.
Other dedicated on-chip hardware, such as the multiplier (16 bits × 16 bits → 32 bits) and the barrel
shifter (32 bits) help accelerate processing of complex instructions.
(b) Bus control unit (BCU)
The BCU starts a required external bus cycle based on the physical address obtained by the CPU.
When an instruction is fetched from external memory space and the CPU does not send a bus cycle
start request, the BCU generates a prefetch address and prefetches the instruction code. The
prefetched instruction code is stored in an instruction queue.
(c) ROM
This consists of a mask ROM or flash memory mapped to the address space starting at 00000000H.
The ROM capacity varies depending on the product. The ROM capacity of each product is shown
below.
CHAPTER 1 INTRODUCTION
PD703031A, 703031AY: 128 KB (mask ROM)
µ
PD703033A, 703033AY: 256 KB (mask ROM)
µ
PD70F3033A, 70F3033AY: 256 KB (flash memory)
µ
PD703032A, 703032AY: 512 KB (mask ROM)
µ
PD70F3032A, 70F3032AY: 512 KB (flash memory)
µ
ROM can be accessed by the CPU in one clock cycle during instruction fetch.
(d) RAM
The RAM capacity and mapping addresses vary depending on the product. The RAM capacity of each
product is shown below.
PD703031A, 703031AY: 12 KB (mapping starts at FFFFC000H)
µ
PD703033A, 703033AY, 70F3033A, 70F3033AY: 16 KB (mapping starts at FFFFB000H)
µ
PD703032A, 703032AY, 70F3032A, 70F3032AY: 24 KB (mapping starts at FFFF9000H)
µ
RAM can be accessed by the CPU in one clock cycle during data access.
(e) Interrupt controller (INTC)
This controller handles hardware interrupt requests (NMI, INTP0 to INTP6) from on-chip peripheral
hardware and external hardware. Eight levels of interrupt priorities can be specified for these interrupt
requests, and multiplexed servicing control can be performed for interrupt sources.
40
(f) Clock generator (CG)
The clock generator includes two types of oscillators; each for main clock (fXX) and for subclock (fXT),
generates five types of clocks (fXX, fXX/2, fXX/4, fXX/8, and fXT), and supplies one of them as the operating
clock for the CPU (f
CPU
).
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CHAPTER 1 INTRODUCTION
(g) Timer/counter
A two-channel 16-bit timer/event counter, a four-channel 8-bit timer/event counter, and a two-channel 8-
bit interval timer are equipped, enabling measurement of pulse intervals and frequency as well as
programmable pulse output.
The two-channel 8-bit timer/event counter can be connected via a cascade to enable use as a 16-bit
timer.
The two-channel 8-bit interval timer can be connected via a cascade to enable to be used as a 16-bit
timer.
(h) Watch timer
This timer counts the reference time period (0.5 seconds) for counting the clock (the 32.768 kHz
subclock or the main clock). At the same time, the watch timer can be used as an interval timer for the
main clock.
(i) Watchdog timer
A watchdog timer is equipped to detect inadvertent program loops, system abnormalities, etc.
It can also be used as an interval timer.
When used as a watchdog timer, it generates a non-maskable interrupt request (INTWDT) after an
overflow occurs. When used as an interval timer, it generates a maskable interrupt request (INTWDTM)
after an overflow occurs.
(j) Serial interface (SIO)
The V850/SB1 includes three kinds of serial interfaces: asynchronous serial interfaces (UART0,
UART1), clocked serial interfaces (CSI0 to CSI3), and an 8-/16-bit variable-length serial interface (CSI4).
2
These plus the I
C bus interfaces (I2C0, I2C1) comprise five channels. Two of these channels are
switchable between the UART and CSI and another two switchable between CSI and I2C.
For UART0 and UART1, data is transferred via the TXD0, TXD1, RXD0, and RXD1 pins.
For CSI0 to CSI3, data is transferred via the SO0 to SO3, SI0 to SI3, and SCK0 to SCK3 pins.
For CSI4, data is transferred via the SO4, SI4, and SCK4 pins.
For I2C0 and I2C1, data is transferred via the SDA0, SDA1, SCL0, and SCL1 pins.
I2C0 and I2C1 are equipped only in the µPD703031AY, 703032AY, 703033AY, 70F3032AY, and
70F3033AY.
For UART and CSI4, a dedicated baud rate generator is equipped.
(k) A/D converter
This high-speed, high-resolution 10-bit A/D converter includes 12 analog input pins. Conversion uses
the successive approximation method.
(l) DMA controller
A six-channel DMA controller is equipped. This controller transfers data between the internal RAM and
on-chip peripheral I/O devices in response to interrupt requests sent by on-chip peripheral I/O.
(m) Real-time output port (RTP)
The RTP is a real-time output function that transfers preset 8-bit data to an output latch when an external
trigger signal occurs or when there is a match signal in a timer compare register. It can also be used for
4-bit × 2 channels.
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CHAPTER 1 INTRODUCTION
(n) Ports
As shown below, the following ports have general-purpose port functions and control pin functions.
Port I/O Port Function Control Function
Port 0 8-bit I/O NMI, external interrupt, A/D converter trigger, RTP trigger
Port 1 6-bit I/O Serial interface
Port 2 8-bit I/O Serial interface, timer I/O
Port 3 8-bit I/O Timer I/O, external address bus, serial interface
Port 4 8-bit I/O External address/data bus
Port 5 8-bit I/O
Port 6 6-bit I/O External address bus
Port 7 8-bit input A/D converter analog input
Port 8 4-bit input
Port 9 7-bit I/O External bus interface control signal I/O
Port 10 8-bit I/O Real-time output port, external address bus, key return input
Port 11 4-bit I/O
General-
purpose port
Wait control, external address bus
42
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CHAPTER 1 INTRODUCTION
1.3 V850/SB1 (B Versions)
1.3.1 Features (V850/SB1 (B versions))
{ Number of instructions: 74
{ Minimum instruction execution time
50 ns (@ 20 MHz operation, external power supply 5 V, regulator output 3.3 V
operation)
{ General-purpose registers 32 bits × 32 registers
{ Instruction set Signed multiplication (16 × 16 → 32): 100 ns (@ 20 MHz operation)
(able to execute instructions in parallel continuously without creating any register
hazards).
Saturation operations (overflow and underflow detection functions are included)
32-bit shift instruction: 1 clock
Bit manipulation instructions
Load/store instructions with long/short format
{ Memory space 16 MB of linear address space (for programs and data)
External expandability: expandable to 4 MB
Memory block allocation function: 2 MB per block
Programmable wait function
Idle state insertion function
{ External bus interface 16-bit data bus (address/data multiplex)
Address bus: separate output enabled
3 V to 5 V interface enabled
Bus hold function
External wait function
{ Internal memory
{ Interrupts and exceptions Non-maskable interrupts: 2 sources
{ I/O lines Total: 83 (12 input ports and 71 I/O ports)
{ Timer/counter 16-bit timer: 2 channels (PWM output)
{ Watch timer When operating under subclock or main clock: 1 channel
{ Watchdog timer 1 channel
PD703031B, 703031BY (mask ROM: 128 KB/RAM: 8 KB)
µ
PD703033B, 703033BY (mask ROM: 256 KB/RAM: 16 KB)
µ
PD703030B, 703030BY (mask ROM: 384 KB/RAM: 24 KB)
µ
PD703032B, 703032BY (mask ROM: 512 KB/RAM: 24 KB)
µ
PD70F3033B, 70F3033BY (flash memory: 256 KB/RAM: 16 KB)
µ
PD70F3030B, 70F3030BY (flash memory: 384 KB/RAM: 24 KB)
µ
PD70F3032B, 70F3032BY (flash memory: 512 KB/RAM: 24 KB)
µ
Maskable interrupts: 37 sources (µPD703030B, 703031B, 703032B, 703033B,
70F3030B, 70F3032B, 70F3033B)
38 sources (µPD703030BY, 703031BY, 703032BY,
703033BY, 70F3030BY, 70F3032BY, 70F3033BY)
Software exceptions: 32 sources
Exception trap: 1 source
3 V to 5 V interface enabled
8-bit timer: 6 channels (4 PWM outputs, cascade connection enabled)
Operation using the subclock or main clock is also possible in the IDLE mode.
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CHAPTER 1 INTRODUCTION
{ Serial interface (SIO) Asynchronous serial interface (UART)
Clocked serial interface (CSI)
I2C bus interface (I2C) (only for µPD703030BY, 703031BY, 703032BY, 703033BY,
70F3030BY, 70F3032BY, and 70F3033BY)
8-/16-bit variable-length serial interface
CSI/UART: 2 channels
CSI/I2C: 2 channels
CSI (8-/16-bit valuable): 1 channel
Dedicated baud rate generator: 3 channels
{ A/D converter 10-bit resolution: 12 channels
{ DMA controller Internal RAM ←→ on-chip peripheral I/O: 6 channels
{ Real-time output port (RTP) 8 bits × 1 channel or 4 bits × 2 channels
{ ROM correction Modifiable 4 points
{ Regulator 4.0 V to 5.5 V input → internal 3.3 V
{ Key return function 4 to 8 selecting enabled, falling edge fixed
{ Clock generator During main clock or subclock operation
5-level CPU clock (including sub operations)
{ Power-saving functions HALT/IDLE/STOP modes
{ Package 100-pin plastic LQFP (fine pitch, 14 × 14)
100-pin plastic QFP (14 × 20)
{ CMOS structure All static circuits
1.3.2 Application fields (V850/SB1 (B versions))
AV equipment
Example: Audio, car audio equipment, VCR, and TV.
44
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CHAPTER 1 INTRODUCTION
1.3.3 Ordering information (V850/SB1 (B versions))
Part Number Package Internal ROM
PD703031BGC-xxx-8EU
µ
PD703031BGF-xxx-3BA
µ
PD703031BYGC-xxx-8EU
µ
PD703031BYGF-xxx-3BA
µ
PD703033BGC-xxx-8EU
µ
PD703033BGF-xxx-3BA
µ
PD703033BYGC-xxx-8EU
µ
PD703033BYGF-xxx-3BA
µ
PD703030BGC-xxx-8EU
µ
PD703030BGF-xxx-3BA
µ
PD703030BYGC-xxx-8EU
µ
PD703030BYGF-xxx-3BA
µ
PD703032BGF-xxx-3BA
µ
PD703032BYGF-xxx-3BA
µ
PD70F3033BGC-8EU
µ
PD70F3033BGF-3BA
µ
PD70F3033BYGC-8EU
µ
PD70F3033BYGF-3BA
µ
PD70F3030BGC-8EU
µ
PD70F3030BGF-3BA
µ
PD70F3030BYGC-8EU
µ
PD70F3030BYGF-3BA
µ
PD70F3032BGF-3BA
µ
PD70F3032BYGF-3BA
µ
100-pin plastic LQFP (fine pitch) (14 × 14)
100-pin plastic QFP (14 × 20)
100-pin plastic LQFP (fine pitch) (14 × 14)
100-pin plastic QFP (14 × 20)
100-pin plastic LQFP (fine pitch) (14 × 14)
100-pin plastic QFP (14 × 20)
100-pin plastic LQFP (fine pitch) (14 × 14)
100-pin plastic QFP (14 × 20)
100-pin plastic LQFP (fine pitch) (14 × 14)
100-pin plastic QFP (14 × 20)
100-pin plastic LQFP (fine pitch) (14 × 14)
100-pin plastic QFP (14 × 20)
100-pin plastic QFP (14 × 20)
100-pin plastic QFP (14 × 20)
100-pin plastic LQFP (fine pitch) (14 × 14)
100-pin plastic QFP (14 × 20)
100-pin plastic LQFP (fine pitch) (14 × 14)
100-pin plastic QFP (14 × 20)
100-pin plastic LQFP (fine pitch) (14 × 14)
100-pin plastic QFP (14 × 20)
100-pin plastic LQFP (fine pitch) (14 × 14)
100-pin plastic QFP (14 × 20)
100-pin plastic QFP (14 × 20)
100-pin plastic QFP (14 × 20)
Mask ROM (128 KB)
Mask ROM (128 KB)
Mask ROM (128 KB)
Mask ROM (128 KB)
Mask ROM (256 KB)
Mask ROM (256 KB)
Mask ROM (256 KB)
Mask ROM (256 KB)
Mask ROM (384 KB)
Mask ROM (384 KB)
Mask ROM (384 KB)
Mask ROM (384 KB)
Mask ROM (512 KB)
Mask ROM (512 KB)
Flash memory (256 KB)
Flash memory (256 KB)
Flash memory (256 KB)
Flash memory (256 KB)
Flash memory (384 KB)
Flash memory (384 KB)
Flash memory (384 KB)
Flash memory (384 KB)
Flash memory (512 KB)
Flash memory (512 KB)
Remarks 1. ××× indicates ROM code suffix.
2. ROMless devices are not provided.
User’s Manual U13850EJ6V0UD
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CHAPTER 1 INTRODUCTION
N
t
2
N
t
2
A
A
A
N
t
2
1.3.4 Pin configuration (top view) (V850/SB1 (B versions))
100-pin plastic LQFP (fine pitch) (14 × 14)
PD703030BGC-xxx-8EU •µPD703033BGC-xxx-8EU •µPD70F3033BGC-8EU
•
µ
• µPD703030BYGC-xxx-8EU •µPD703033BYGC-xxx-8EU •µPD70F3033BYGC-8EU
• µPD703031BGC-xxx-8EU •µPD70F3030BGC-8EU
• µPD703031BYGC-xxx-8EU •µPD70F3030BYGC-8EU
e
e
o
o
e
o
P21/SO2
P22/SCK2/SCL1
Note 2
P23/RXD1/SI3
P24/TXD1/SO3
P25/ASCK1/SCK3
EV
EV
P26/TI2/TO2
P27/TI3/TO3
P30/TI00
P31/TI01
P32/TI10/SI4
P33/TI11/SO4
P34/TO0/A13/SCK4
P35/TO1/A14
P36/TI4/TO4/A15
P37/TI5/TO5
Note 1
IC/V
PP
P100/RTP0/KR0/A5
P101/RTP1/KR1/A6
P102/RTP2/KR2/A7
P103/RTP3/KR3/A8
P104/RTP4/KR4/A9
P105/RTP5/KR5/A10
P106/RTP6/KR6/A11
P20/SI2/SDA1
P15/SCK1/ASCK0
P14/SO1/TXD0
P13/SI1/RXD0
9998979695949392919089888786858483828180797877
100
1
2
3
4
DD
SS
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
27
2829303132333435363738394041424344454647484950
26
P07/INTP6
P05/INTP4/ADTRG
P04/INTP3
P03/INTP2
P02/INTP1
P01/INTP0
P00/NMI
P83/ANI11
P82/ANI10
P81/ANI9
P80/ANI8
P77/ANI7
P76/ANI6
P75/ANI5
P74/ANI4
P73/ANI3
P11/SO0
P10/SI0/SDA0
P12/SCK0/SCL0
P06/INTP5/RTPTRG
P72/ANI2
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
P71/ANI1
P70/ANI0
V
REF
V
SS
V
DD
P65/A21
P64/A20
P63/A19
P62/A18
P61/A17
P60/A16
P57/AD15
P56/AD14
P55/AD13
P54/AD12
P53/AD11
P52/AD10
P51/AD9
P50/AD8
BV
SS
BV
DD
P47/AD7
P46/AD6
P45/AD5
P44/AD4
SS
DD
X2
X1
V
XT1
XT2
REGC
RESET
P112/A3
P113/A4
P111/A2
P110/WAIT/A1
V
CLKOUT
P90/LBEN/WRL
P91/UBEN
P92/R/W/WRH
P93/DSTB/RD
P94/ASTB
P95/HLDAK
P96/HLDRQ
P40/AD0
P41/AD1
P42/AD2
P43/AD3
P107/RTP7/KR7/A12
Notes 1. IC (
PD703030B, 703030BY, 703031B, 703031BY, 703033B, 703033BY): Connect directly to VSS.
µ
VPP (µPD70F3030B, 70F3030BY, 70F3033B, 70F3033BY): Connect to VSS in normal operation mode.
2. SCL0, SCL1, SDA0, and SDA1 are available only in the 703030BY, µPD703031BY, 703033BY,
46
70F3030BY, and 70F3033BY.
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CHAPTER 1 INTRODUCTION
L
100-pin plastic QFP (14 × 20)
• µPD703030BGF-xxx-3BA • µPD703032BGF-xxx-3BA • µPD70F3030BYGF-3BA
• µPD703030BYGF-xxx-3BA • µPD703032BYGF-xxx-3BA • µPD70F3032BGF-3BA
• µPD703031BGF-xxx-3BA • µPD703033BGF-xxx-3BA • µPD70F3032BYGF-3BA
• µPD703031BYGF-xxx-3BA • µPD703033BYGF-xxx-3BA • µPD70F3033BGF-3BA
• µPD70F3030BGF-3BA • µPD70F3033BYGF-3BA
Note 2
Note 2
P13/SI1/RXD0
P11/SO0
P10/SI0/SDA0
P07/INTP6
P06/INTP5/RTPTRG
P05/INTP4/ADTRG
P04/INTP3
P03/INTP2
P02/INTP1
P01/INTP0
P00/NMI
P83/ANI11
P82/ANI10
P81/ANI9
P80/ANI8
P77/ANI7
P76/ANI6
P75/ANI5
P74/ANI4
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
P73/ANI3
P72/ANI2P15/SCK1/ASCK0
P71/ANI1
P70/ANI0
REF
AV
AV
SS
DD
AV
P65/A21
P64/A20
P63/A19
P62/A18
P61/A17
P60/A16
P57/AD15
P56/AD14
P55/AD13
P54/AD12
P53/AD11
P52/AD10
P51/AD9
P50/AD8
SS
BV
DD
BV
P47/AD7
P46/AD6
P45/AD5
P44/AD4
P43/AD3
P42/AD2
P41/AD1
P14/SO1/TXD0
P20/SI2/SDA1
P22/SCK2/SCL1
Note 2
P21/SO2
Note 2
P23/RXD1/SI3
P24/TXD1/SO3
P25/ASCK1/SCK3
EV
EV
P26/TI2/TO2
P27/TI3/TO3
P30/TI00
P31/TI01
P32/TI10/SI4
P33/TI11/SO4
P34/TO0/A13/SCK4
P35/TO1/A14
P36/TI4/TO4/A15
P37/TI5/TO5
Note 1
PP
IC/V
P100/RTP0/KR0/A5
P101/RTP1/KR1/A6
P102/RTP2/KR2/A7
P103/RTP3/KR3/A8
P104/RTP4/KR4/A9
P105/RTP5/KR5/A10
P106/RTP6/KR6/A11
P107/RTP7/KR7/A12
P110/WAIT/A1
P12/SCK0/SCL0
99989796959493929190898887868584838281
10031
1
2
3
4
5
6
7
DD
SS
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
32333435363738394041424344454647484950
SS
DD
X2
X1
V
V
CLKOUT
P90/LBEN/WR
P91/UBEN
P92/R/W/WRH
P93/DSTB/RD
P94/ASTB
P95/HLDAK
P40/AD0
P96/HLDRQ
Notes 1. IC (
XT1
XT2
REGC
RESET
P111/A2
P112/A3
P113/A4
PD703030B, 703030BY, 703031B, 703031BY, 703032B, 703032BY, 703033B, 703033BY):
µ
Connect directly to VSS.
VPP (µPD70F3030B, 70F3030BY, 70F3032B, 70F3032BY, 70F3033B, 70F3033BY):
Connect to VSS in normal operation mode.
2. SCL0, SCL1, SDA0, and SDA1 are available only in the µPD703030BY, 703031BY, 703032BY,
703033BY, 70F3030BY, 70F3032BY, and 70F3033BY.
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CHAPTER 1 INTRODUCTION
Pin names (V850/SB1 (B versions))
A1 to A21: Address bus P70 to P77: Port 7
AD0 to AD15: Address/data bus P80 to P83: Port 8
ADTRG: A/D trigger input P90 to P96: Port 9
ANI0 to ANI11: Analog input P100 to P107: Port 10
ASCK0, ASCK1: Asynchronous serial clock P110 to P113: Port 11
ASTB: Address strobe RD: Read
: Analog V
AVDD
AV
: Analog reference voltage RESET: Reset
REF
AVSS: Analog V
DD
SS
REGC: Regulator control
RTP0 to RTP7: Real-time output port
BVDD: Power supply for bus interface RTPTRG: RTP trigger
BVSS: Ground for bus interface R/W: Read/write status
CLKOUT: Clock output RXD0, RXD1: Receive data
DSTB: Data strobe SCK0 to SCK4: Serial clock
EVDD: Power supply for port SCL0, SCL1: Serial clock
EVSS: Ground for port SDA0, SDA1: Serial data
HLDAK: Hold acknowledge SI0 to SI4: Serial input
HLDRQ: Hold request SO0 to SO4: Serial output
IC: Internally connected TI00, TI01, TI10,
INTP0 to INTP6: Interrupt request from peripherals TI11, TI2 to TI5: Timer input
KR0 to KR7
:
Key return TO0 to TO5: Timer output
LBEN: Lower byte enable TXD0,TXD1: Transmit data
NMI: Non-maskable interrupt request UBEN: Upper byte enable
P00 to P07: Port 0 VDD: Power supply
P10 to P15: Port 1 VPP: Programming power supply
P20 to P27: Port 2 VSS: Ground
P30 to P37: Port 3 WAIT: Wait
P40 to P47: Port 4 WRH: Write strobe high level data
P50 to P57: Port 5 WRL: Write strobe low level data
P60 to P65: Port 6 X1, X2: Crystal for main clock
XT1, XT2: Crystal for subclock
48
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CHAPTER 1 INTRODUCTION
N
3
A
)
Note 3
(
)
)
)
)
)
)
)
)
Note 3
Note 3
Note 5
Note 6
1.3.5 Function blocks (V850/SB1 (B versions))
(1) Internal block diagram
ROM
Note
1
RAM
Note
2
P110 to P113
P100 to P107
INTP0 to INTP6
TI00,TI01,
TI10,TI11
TO0,TO1
TI2/TO2
TI3/TO3
TI4/TO4
TI5/TO5
SO0
SI0/SDA0
SCK0/SCL0
SO2
SI2/SDA1
SCK2/SCL1
SO1/TXD0
SI1/RXD0
SCK1/ASCK0
SO3/TXD1
SI3/RXD1
SCK3/ASCK1
SO4
SCK4
KR0 to KR7
NMI
ote
SI4
INTC
Timer/counter
16-bit timer:
TM0, TM1
8-bit timer:
TM2 to TM7
SIO
CSI0/I2C0
Note 4
CSI2/I2C1
Note 4
CSI1/UART0
CSI3/UART1
Variable
length CSI4
Key return
DMAC: 6 ch
PC
32-bit barrel
shifter
System
register
General-purpose
registers
32 bits × 32
Ports
P70 to P77
P80 to P83
P90 to P96
P60 to P65
CPU
ROM
correction
Multiplier
16 ×16→32
ALU
RTP
P40 to P47
P20 to P27
P30 to P37
P50 to P57
P10 to P15
P00 to P07
RTP0 to RTP7
3.3 V
RTPTRG
Instruction
queue
BCU
A/D
converter
SS
DD
REF
AV
AV
AV
Regulator
ANI0 to ANI11
HLDRQ (P96
HLDAK
STB (P94
DSTB/RD (P93
R/W /W RH (P92
UBEN (P91
LBEN/WRL (P90
WAIT (P110
A1 to A12
(P100 to P107,
P110 to P113
A13 to A15 (P34 to P36)
A16 to A21 (P60 to P65)
AD0 to AD15
(P40 to P47, P50 to P57)
CLKOUT
X1
X2
CG
XT1
XT2
RESET
ADTRG
V
DD
P95
Watch timer
Watchdog
timer
Notes 1.
PD703031B, 703031BY: 128 KB (mask ROM)
µ
PD703033B, 703033BY: 256 KB (mask ROM)
µ
PD703030B, 703030BY: 384 K (mask ROM)
µ
PD703032B, 703032BY: 512 K (mask ROM)
µ
PD70F3033B, 70F3033BY: 256 K (flash memory)
µ
PD70F3030B, 70F3030BY: 384 K (flash memory)
µ
PD70F3032B, 70F3032BY: 512 K (flash memory)
µ
PD703031B, 703031BY: 8 KB
2.
µ
PD703033B, 703033BY, 70F3033B, 70F3033BY: 16 KB
µ
PD703030B, 703030BY, 703032B, 703032BY,: 24 KB
µ
70F3030B, 70F3030BY, 70F3032B, 70F3032BY
3. SDA0, SDA1, SCL0, and SCL1 pins are available only in the
703033BY, 70F3032BY, 70F3030BY, and 70F3033BY
2
C function is available only in the µPD703030BY, 703031BY, 703032BY, 703033BY, 70F3030BY,
4. I
70F3032BY, and 70F3033BY
PD70F3030B, 70F3030BY, 70F3032B, 70F3032BY, 70F3033B, 70F3033BY
µ
5.
PD703030B, 703030BY, 703031B, 703031BY, 703032B, 703032BY, 703033B, 703033BY
6.
µ
SS
V
BV
REGC
PD703030BY, 703031BY, 703032BY,
µ
BV
EV
EV
V
IC
DD
SS
DD
SS
PP
User’s Manual U13850EJ6V0UD
49
Page 50
(2) Internal units
(a) CPU
The CPU uses five-stage pipeline control to enable single-clock execution of address calculations,
arithmetic logic operations, data transfers, and almost all other instruction processing.
Other dedicated on-chip hardware, such as the multiplier (16 bits × 16 bits → 32 bits) and the barrel
shifter (32 bits) help accelerate processing of complex instructions.
(b) Bus control unit (BCU)
The BCU starts a required external bus cycle based on the physical address obtained by the CPU.
When an instruction is fetched from external memory space and the CPU does not send a bus cycle
start request, the BCU generates a prefetch address and prefetches the instruction code. The
prefetched instruction code is stored in an instruction queue.
(c) ROM
This consists of a mask ROM or flash memory mapped to the address space starting at 00000000H.
The ROM capacity varies depending on the product. The ROM capacity of each product is shown
below.
CHAPTER 1 INTRODUCTION
PD703031B, 703031BY: 128 KB (mask ROM)
µ
PD703033B, 703033BY: 256 KB (mask ROM)
µ
PD70F3033B, 70F3033BY: 256 KB (flash memory)
µ
PD703030B, 703030BY: 384 KB (mask ROM)
µ
PD70F3030B, 70F3030BY: 384 KB (flash memory)
µ
PD703032B, 703032BY: 512 KB (mask ROM)
µ
PD70F3032B, 70F3032BY: 512 KB (flash memory)
µ
ROM can be accessed by the CPU in one clock cycle during instruction fetch.
(d) RAM
The RAM capacity and mapping addresses vary depending on the product. The RAM capacity of each
product is shown below.
PD703031B, 703031BY: 8 KB (mapping starts at FFFFD000H)
µ
PD703033B, 703033BY, 70F3033B, 70F3033BY: 16 KB (mapping starts at FFFFB000H)
µ
PD703030B, 703030BY, 70F3030B, 70F3030BY,
µ
703032B, 703032BY, 70F3032B, 70F3032BY: 24 KB (mapping starts at FFFF9000H)
RAM can be accessed by the CPU in one clock cycle during data access.
50
(e) Interrupt controller (INTC)
This controller handles hardware interrupt requests (NMI, INTP0 to INTP6) from on-chip peripheral
hardware and external hardware. Eight levels of interrupt priorities can be specified for these interrupt
requests, and multiplexed servicing control can be performed for interrupt sources.
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CHAPTER 1 INTRODUCTION
(f) Clock generator (CG)
The clock generator includes two types of oscillators; each for main clock (fXX
) and for subclock (fXT),
generates five types of clocks (fXX, fXX/2, fXX/4, fXX/8, and fXT), and supplies one of them as the operating
clock for the CPU (f
CPU
).
(g) Timer/counter
A two-channel 16-bit timer/event counter, a four-channel 8-bit timer/event counter, and a two-channel 8-
bit interval timer are equipped, enabling measurement of pulse intervals and frequency as well as
programmable pulse output.
The two-channel 8-bit timer/event counter can be connected via a cascade to enable use as a 16-bit
timer.
The two-channel 8-bit interval timer can be connected via a cascade to enable to be used as a 16-bit
timer.
(h) Watch timer
This timer counts the reference time period (0.5 seconds) for counting the clock (the 32.768 kHz
subclock or the main clock). At the same time, the watch timer can be used as an interval timer for the
main clock.
(i) Watchdog timer
A watchdog timer is equipped to detect inadvertent program loops, system abnormalities, etc.
It can also be used as an interval timer.
When used as a watchdog timer, it generates a non-maskable interrupt request (INTWDT) after an
overflow occurs. When used as an interval timer, it generates a maskable interrupt request (INTWDTM)
after an overflow occurs.
(j) Serial interface (SIO)
The V850/SB1 includes three kinds of serial interfaces: asynchronous serial interfaces (UART0,
UART1), clocked serial interfaces (CSI0 to CSI3), and an 8-/16-bit variable-length serial interface (CSI4).
These plus the I2C bus interfaces (I2C0, I2C1) comprise five channels. Two of these channels are
switchable between the UART and CSI and another two switchable between CSI and I2C.
For UART0 and UART1, data is transferred via the TXD0, TXD1, RXD0, and RXD1 pins.
For CSI0 to CSI3, data is transferred via the SO0 to SO3, SI0 to SI3, and SCK0 to SCK3 pins.
For CSI4, data is transferred via the SO4, SI4, and SCK4 pins.
For I2C0 and I2C1, data is transferred via the SDA0, SDA1, SCL0, and SCL1 pins.
I2C0 and I2C1 are equipped only in the µPD703030BY, 703031BY, 703032BY, 703033BY, 70F3030BY,
70F3032BY, and 70F3033BY.
For UART and CSI4, a dedicated baud rate generator is equipped.
(k) A/D converter
This high-speed, high-resolution 10-bit A/D converter includes 12 analog input pins. Conversion uses
the successive approximation method.
(l) DMA controller
A six-channel DMA controller is equipped. This controller transfers data between the internal RAM and
on-chip peripheral I/O devices in response to interrupt requests sent by on-chip peripheral I/O.
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CHAPTER 1 INTRODUCTION
(m) Real-time output port (RTP)
The RTP is a real-time output function that transfers preset 8-bit data to an output latch when an external
trigger signal occurs or when there is a match signal in a timer compare register. It can also be used for
4-bit × 2 channels.
(n) Ports
As shown below, the following ports have general-purpose port functions and control pin functions.
Port I/O Port Function Control Function
Port 0 8-bit I/O NMI, external interrupt, A/D converter trigger, RTP trigger
Port 1 6-bit I/O Serial interface
Port 2 8-bit I/O Serial interface, timer I/O
Port 3 8-bit I/O Timer I/O, external address bus, serial interface
Port 4 8-bit I/O External address/data bus
Port 5 8-bit I/O
Port 6 6-bit I/O External address bus
Port 7 8-bit input A/D converter analog input
Port 8 4-bit input
Port 9 7-bit I/O External bus interface control signal I/O
Port 10 8-bit I/O Real-time output port, external address bus, key return input
Port 11 4-bit I/O
General-
purpose port
Wait control, external address bus
52
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CHAPTER 1 INTRODUCTION
1.4 V850/SB2 (A Versions)
1.4.1 Features (V850/SB2 (A versions))
{ Number of instructions: 74
{ Minimum instruction execution time
79 ns (operating at 12.58 MHz, external power supply 5 V, regulator output 3.0 V)
{ General-purpose registers 32 bits × 32 registers
{ Instruction set Signed multiplication (16 × 16 → 32): 158 ns (operating at 12.58 MHz)
(able to execute instructions in parallel continuously without creating any register
hazards).
Saturation operations (overflow and underflow detection functions are included)
32-bit shift instruction: 1 clock
Bit manipulation instructions
Load/store instructions with long/short format
{ Memory space 16 MB of linear address space (for programs and data)
External expandability: expandable to 4 MB
Memory block allocation function: 2 MB per block
Programmable wait function
Idle state insertion function
{ External bus interface 16-bit data bus (address/data multiplex)
Address bus: separate output enabled
3 V to 5 V interface enabled
Bus hold function
External wait function
{ Internal memory
{ Interrupts and exceptions Non-maskable interrupts: 2 sources
{ I/O lines Total: 83 (12 input ports and 71 I/O ports)
{ Timer/counter 16-bit timer: 2 channels (PWM output)
{ Watch timer When operating under subclock or main clock: 1 channel
{ Watchdog timer 1 channel
{ Serial interface (SIO) Asynchronous serial interface (UART)
PD703034A, 703034AY (mask ROM: 128 KB/RAM: 12 KB)
µ
PD703035A, 703035AY (mask ROM: 256 KB/RAM: 16 KB)
µ
PD703037A, 703037AY (mask ROM: 512 KB/RAM: 24 KB)
µ
PD70F3035A, 70F3035AY (flash memory: 256 KB/RAM: 16 KB)
µ
PD70F3037A, 70F3037AY (flash memory: 512 KB/RAM: 24 KB)
µ
Maskable interrupts: 39 sources (µPD703034A, 703035A, 703037A,
70F3035A, 70F3037A)
40 sources (µPD703034AY, 703035AY, 703037AY,
70F3035AY, 70F3037AY)
Software exceptions: 32 sources
Exception trap: 1 source
3 V to 5 V interface enabled
8-bit timer: 6 channels (four PWM outputs, cascade connection enabled)
Operation using the subclock or main clock is also possible in the IDLE mode.
Clocked serial interface (CSI)
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CHAPTER 1 INTRODUCTION
I2C bus interface (I2C)
(only for µPD703034AY, 703035AY, 703037AY, 70F3035AY, and 70F3037AY)
8-/16-bit variable-length serial interface
CSI/UART: 2 channels
CSI/I2C: 2 channels
CSI (8-/16-bit valuable): 1 channel
Dedicated baud rate generator: 3 channels
{ A/D converter 10-bit resolution: 12 channels
{ DMA controller Internal RAM ←→ on-chip peripheral I/O: 6 channels
{ Real-time output port (RTP) 8 bits × 1 channel or 4 bits × 2 channels
{ ROM correction Modifiable 4 points
{ Regulator 4.0 V to 5.5 V input → internal 3.0 V
{ Key return function 4 to 8 selecting enabled, falling edge fixed
{ Clock generator During main clock or subclock operation
5-level CPU clock (including sub operations)
{ Power-saving functions HALT/IDLE/STOP modes
{ IEBus controller 1 ch
{ Package 100-pin plastic LQFP (fine pitch, 14 × 14)
100-pin plastic QFP (14 × 20)
{ CMOS structure All static circuits
1.4.2 Application fields (V850/SB2 (A versions))
AV equipment
Example: Audio, car audio equipment, VCR, and TV.
54
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CHAPTER 1 INTRODUCTION
1.4.3 Ordering information (V850/SB2 (A versions))
Part Number Package Internal ROM
PD703034AGC-xxx-8EU 100-pin plastic LQFP (fine pitch) (14 × 14) Mask ROM (128 KB)
µ
PD703034AGF-xxx-3BA 100-pin plastic QFP (14 × 20) Mask ROM (128 KB)
µ
PD703034AYGC-xxx-8EU 100-pin plastic LQFP (fine pitch) (14 × 14) Mask ROM (128 KB)
µ
PD703034AYGF-xxx-3BA 100-pin plastic QFP (14 × 20) Mask ROM (128 KB)
µ
PD703035AGC-xxx-8EU 100-pin plastic LQFP (fine pitch) (14 × 14) Mask ROM (256 KB)
µ
PD703035AGF-xxx-3BA 100-pin plastic QFP (14 × 20) Mask ROM (256 KB)
µ
PD703035AYGC-xxx-8EU 100-pin plastic LQFP (fine pitch) (14 × 14) Mask ROM (256 KB)
µ
PD703035AYGF-xxx-3BA 100-pin plastic QFP (14 × 20) Mask ROM (256 KB)
µ
PD703037AGF-xxx-3BA 100-pin plastic QFP (14 × 20) Mask ROM (512 KB)
µ
PD703037AYGF-xxx-3BA 100-pin plastic QFP (14 × 20) Mask ROM (512 KB)
µ
PD70F3035AGC-8EU 100-pin plastic LQFP (fine pitch) (14 × 14) Flash memory (256 KB)
µ
PD70F3035AGF-3BA 100-pin plastic QFP (14 × 20) Flash memory (256 KB)
µ
PD70F3035AYGF-8EU 100-pin plastic LQFP (fine pitch) (14 × 14) Flash memory (256 KB)
µ
PD70F3035AYGF-3BA 100-pin plastic QFP (14 × 20) Flash memory (256 KB)
µ
PD70F3037AGF-3BA 100-pin plastic QFP (14 × 20) Flash memory (512 KB)
µ
PD70F3037AYGF-3BA 100-pin plastic QFP (14 × 20) Flash memory (512 KB)
µ
Remarks 1. ××× indicates ROM code suffix.
2. ROMless devices are not provided.
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CHAPTER 1 INTRODUCTION
N
t
2
N
t
2
X
X
A
A
A
N
t
2
1.4.4 Pin configuration (top view) (V850/SB2 (A versions))
100-pin plastic LQFP (fine pitch) (14 × 14)
PD703034AGC-xxx-8EU •µPD70F3035AGC-8EU
•
µ
•µPD703034AYGC-xxx-8EU •µPD70F3035AYGC-8EU
•µPD703035AGC-xxx-8EU
•µPD703035AYGC-xxx-8EU
e
e
o
o
e
o
P21/SO2
P22/SCK2/SCL1
Note 2
P23/RXD1/SI3
P24/TXD1/SO3
P25/ASCK1/SCK3
EV
EV
P26/TI2/TO2
P27/TI3/TO3
P30/TI00
P31/TI01
P32/TI10/SI4
P33/TI11/SO4
P34/TO0/A13/SCK4
P35/TO1/A14
P36/TI4/TO4/A15
P37/TI5/TO5
Note 1
IC/V
PP
P100/RTP0/KR0/A5
P101/RTP1/KR1/A6
P102/RTP2/KR2/A7
P103/RTP3/KR3/A8
P104/RTP4/KR4/A9/IER
P105/RTP5/KR5/A10/IET
P106/RTP6/KR6/A11
P20/SI2/SDA1
P14/SO1/TXD0
P13/SI1/RXD0
P15/SCK1/ASCK0
9998979695949392919089888786858483828180797877
100
1
2
3
4
DD
SS
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
27
2829303132333435363738394041424344454647484950
26
P07/INTP6
P11/SO0
P10/SI0/SDA0
P12/SCK0/SCL0
P06/INTP5/RTPTRG
P05/INTP4/ADTRG
P04/INTP3
P03/INTP2
P02/INTP1
P01/INTP0
P00/NMI
P83/ANI11
P82/ANI10
P81/ANI9
P80/ANI8
P77/ANI7
P76/ANI6
P75/ANI5
P74/ANI4
P73/ANI3
P72/ANI2
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
P71/ANI1
P70/ANI0
V
REF
V
SS
V
DD
P65/A21
P64/A20
P63/A19
P62/A18
P61/A17
P60/A16
P57/AD15
P56/AD14
P55/AD13
P54/AD12
P53/AD11
P52/AD10
P51/AD9
P50/AD8
BV
SS
BV
DD
P47/AD7
P46/AD6
P45/AD5
P44/AD4
SS
DD
X2
X1
V
XT1
XT2
REGC
RESET
P112/A3
P113/A4
P111/A2
P110/WAIT/A1
V
CLKOUT
P90/LBEN/WRL
P91/UBEN
P92/R/W/WRH
P93/DSTB/RD
P94/ASTB
P95/HLDAK
P96/HLDRQ
P40/AD0
P41/AD1
P42/AD2
P43/AD3
P107/RTP7/KR7/A12
Notes 1. IC (
PD703034A, 703034AY, 703035A, 703035AY): Connect directly to VSS.
µ
VPP (µPD70F3035A, 70F3035AY): Connect to VSS in normal operation mode.
2. SCL0, SCL1, SDA0, and SDA1 are available only in the µPD703034AY, 703035AY, and 70F3035AY.
56
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CHAPTER 1 INTRODUCTION
L
100-pin plastic QFP (14 × 20)
•µPD703034AGF-xxx-3BA • µPD703037AGF-xxx-3BA • µPD70F3037AGF-3BA
•µPD703034AYGF-xxx-3BA • µPD703037AYGF-xxx-3BA • µPD70F3037AYGF-3BA
•µPD703035AGF-xxx-3BA • µPD70F3035AGF-3BA
•µPD703035AYGF-xxx-3BA • µPD70F3035AYGF-3BA
Note 2
Note 2
P13/SI1/RXD0
P11/SO0
P10/SI0/SDA0
P07/INTP6
P06/INTP5/RTPTRG
P05/INTP4/ADTRG
P04/INTP3
P03/INTP2
P02/INTP1
P01/INTP0
P00/NMI
P83/ANI11
P82/ANI10
P81/ANI9
P80/ANI8
P77/ANI7
P76/ANI6
P75/ANI5
P74/ANI4
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
P73/ANI3
P72/ANI2P15/SCK1/ASCK0
P71/ANI1
P70/ANI0
REF
AV
AV
SS
DD
AV
P65/A21
P64/A20
P63/A19
P62/A18
P61/A17
P60/A16
P57/AD15
P56/AD14
P55/AD13
P54/AD12
P53/AD11
P52/AD10
P51/AD9
P50/AD8
SS
BV
DD
BV
P47/AD7
P46/AD6
P45/AD5
P44/AD4
P43/AD3
P42/AD2
P41/AD1
P14/SO1/TXD0
P20/SI2/SDA1
P22/SCK2/SCL1
Note 2
P21/SO2
Note 2
P23/RXD1/SI3
P24/TXD1/SO3
P25/ASCK1/SCK3
EV
EV
P26/TI2/TO2
P27/TI3/TO3
P30/TI00
P31/TI01
P32/TI10/SI4
P33/TI11/SO4
P34/TO0/A13/SCK4
P35/TO1/A14
P36/TI4/TO4/A15
P37/TI5/TO5
Note 1
PP
IC/V
P100/RTP0/KR0/A5
P101/RTP1/KR1/A6
P102/RTP2/KR2/A7
P103/RTP3/KR3/A8
P104/RTP4/KR4/A9/IERX
P105/RTP5/KR5/A10/IETX
P106/RTP6/KR6/A11
P107/RTP7/KR7/A12
P110/WAIT/A1
P12/SCK0/SCL0
99989796959493929190898887868584838281
10031
1
2
3
4
5
6
7
DD
SS
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
32333435363738394041424344454647484950
SS
DD
X2
X1
V
V
CLKOUT
P90/LBEN/WR
P91/UBEN
P92/R/W/WRH
P93/DSTB/RD
P94/ASTB
P95/HLDAK
P40/AD0
P96/HLDRQ
Notes 1. IC (
XT1
XT2
REGC
RESET
P111/A2
P112/A3
P113/A4
PD703034A, 703034AY, 703035A, 703035AY, 703037A, 703037AY): Connect directly to VSS.
µ
VPP (µPD70F3035A, 70F3035AY, 70F3037A, 70F3037AY):
Connect to VSS in normal operation mode.
2. SCL0, SCL1, SDA0, and SDA1 are available only in the µPD703034AY, 703035AY, 703037AY,
70F3035AY, and 70F3037AY.
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CHAPTER 1 INTRODUCTION
Pin names (V850/SB2)
A1 to A21: Address bus P70 to P77: Port 7
AD0 to AD15: Address/data bus P80 to P83: Port 8
ADTRG: A/D trigger input P90 to P96: Port 9
ANI0 to ANI11: Analog input P100 to P107: Port 10
ASCK0, ASCK1: Asynchronous serial clock P110 to P113: Port 11
ASTB: Address strobe RD: Read
: Analog V
AVDD
AV
: Analog reference voltage RESET: Reset
REF
AVSS: Analog V
DD
SS
REGC: Regulator control
RTP0 to RTP7: Real-time output port
BVDD: Power supply for bus interface RTPTRG: RTP trigger
BVSS: Ground for bus interface R/W: Read/write status
CLKOUT: Clock output RXD0, RXD1: Receive data
DSTB: Data strobe SCK0 to SCK4: Serial clock
EVDD: Power supply for port SCL0, SCL1: Serial clock
EVSS: Ground for port SDA0, SDA1: Serial data
HLDAK: Hold acknowledge SI0 to SI4: Serial input
HLDRQ: Hold request SO0 to SO4: Serial output
IC: Internally connected TI00, TI01, TI10,
IERX: IEBus receive data TI11, TI2 to TI5: Timer input
IETX: IEBus transmit data TO0 to TO5: Timer output
INTP0 to INTP6: Interrupt request from peripherals TXD0,TXD1: Transmit data
KR0 to KR7
:
Key return UBEN: Upper byte enable
LBEN: Lower byte enable VDD: Power supply
NMI: Non-maskable interrupt request VPP: Programming power supply
P00 to P07: Port 0 VSS: Ground
P10 to P15: Port 1 WAIT: Wait
P20 to P27: Port 2 WRH: Write strobe high level data
P30 to P37: Port 3 WRL: Write strobe low level data
P40 to P47: Port 4 X1, X2: Crystal for main clock
P50 to P57: Port 5 XT1, XT2: Crystal for subclock
P60 to P65: Port 6
58
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CHAPTER 1 INTRODUCTION
Note 3
A
)
D
Note 3
(
)
)
)
)
)
)
)
Note 3
Note 3
Note 6
Note 6
1.4.5 Function blocks (V850/SB2 (A versions))
(1) Internal block diagram
ROM
Note
1
RAM
Note
2
P110 to P113
P100 to P107
INTP0 to INTP 6
TI00,TI01,
TI10,TI11
TO0,TO1
TI2/TO2
TI3/TO3
TI4/TO4
TI5/TO5
SO0
SI0/SDA0
SCK0/SCL0
SO2
SI2/SDA1
SCK2/SCL1
SO1/TXD0
SI1/RXD0
SCK1/ASCK0
SO3/TXD1
SI3/RXD1
SCK3/ASCK1
SO4
SCK4
KR0 to KR7
NMI
SI4
INTC
Timer/counter
16-bit timer:
TM0, TM1
8-bit timer:
TM2 to TM7
SIO
CSI0/I2C0
Note 4
CSI2/I2C1
Note 4
CSI1/UART0
CSI3/UART1
Variable
length C SI4
Key return
DMAC: 6 ch
PC
32-bit barrel
shifter
System
register
General-purpose
registers
32 bits × 32
Ports
P80 to P83
P90 to P96
P70 to P77
CPU
ROM
correction
Multiplier
16 ×16→32
ALU
RTP
P40 to P47
P20 to P27
P30 to P37
P60 to P65
P50 to P57
P10 to P15
P00 to P07
RTP0 to RTP7
3.0 V
RTPTRG
Instruction
queue
BCU
A/D
converter
SS
D
REF
AV
AV
AV
Regulator
ANI0 to ANI11
HLDRQ (P96
HLDAK
STB (P94
DSTB/RD (P93
R/W /WRH (P92
UBEN (P91
LBEN/WRL (P90
WAIT (P110
A1 to A12
(P100 to P107,
P110 to P113)
A13 to A15 (P34 to P36)
A16 to A21 (P60 to P65)
AD0 to AD15
(P40 to P47, P50 to P57)
CLKOUT
X1
X2
CG
XT1
XT2
RESET
ADTRG
V
DD
P95
Watch timer
Watchdog
timer
IETX
IERX
Notes 1.
µ
µ
µ
µ
µ
2.
µ
µ
µ
µ
IEBus
PD703034A, 703034AY: 128 KB (mask ROM)
PD703035A, 703035AY: 256 KB (mask ROM)
PD703037A, 703037AY: 512 KB (mask ROM)
PD70F3035A, 70F3035AY: 256 KB (flash memory)
PD70F3037A, 70F3037AY: 512 KB (flash memory)
PD703034A, 703034AY: 12 KB
PD703035A, 703035AY, 70F3035A, 70F3035AY: 16 KB
PD703036A, 703036AY: 20 KB
PD703037A, 703037AY, 70F3037A, 70F3037AY: 24 KB
3. SDA0, SDA1, SCL0, and SCL1 pins are available only in the
70F3035AY, and 70F3037AY
2
C function is available only in the µPD703034AY, 703035AY, 703037AY, 70F3035AY, and
4. I
70F3037AY
PD70F3035A, 70F3035AY, 70F3037A, 70F3037AY
µ
5.
PD703034A, 703034AY, 703035A, 703035AY, 703037A, 703037AY
6.
µ
V
SS
BV
REGC
PD703034AY, 703035AY, 703037AY,
µ
BV
EV
EV
V
IC
DD
SS
DD
SS
PP
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Page 60
(2) Internal units
(a) CPU
The CPU uses five-stage pipeline control to enable single-clock execution of address calculations,
arithmetic logic operations, data transfers, and almost all other instruction processing.
Other dedicated on-chip hardware, such as the multiplier (16 bits × 16 bits → 32 bits) and the barrel
shifter (32 bits) help accelerate processing of complex instructions.
(b) Bus control unit (BCU)
The BCU starts a required external bus cycle based on the physical address obtained by the CPU.
When an instruction is fetched from external memory space and the CPU does not send a bus cycle
start request, the BCU generates a prefetch address and prefetches the instruction code. The
prefetched instruction code is stored in an instruction queue.
(c) ROM
This consists of a mask ROM or flash memory mapped to the address space starting at 00000000H.
The ROM capacity varies depending on the product. The ROM capacity of each product is shown
below.
CHAPTER 1 INTRODUCTION
PD703034A, 703034AY: 128 KB (mask ROM)
µ
PD703035A, 703035AY: 256 KB (mask ROM)
µ
PD70F3035A, 70F3035AY: 256 KB (flash memory)
µ
PD703037A, 703037AY: 512 KB (mask ROM)
µ
PD70F3037A, 70F3037AY: 512 KB (flash memory)
µ
ROM can be accessed by the CPU in one clock cycle during instruction fetch.
(d) RAM
The RAM capacity and mapping addresses vary depending on the product. The RAM capacity of each
product is shown below.
PD703034A, 703034AY: 12 KB (mapping starts at FFFFC000H)
µ
PD703035A, 703035AY, 70F3035A, 70F3035AY: 16 KB (mapping starts at FFFFB000H)
µ
PD703037A, 703037AY, 70F3037A, 70F3037AY: 24 KB (mapping starts at FFFF9000H)
µ
RAM can be accessed by the CPU in one clock cycle during data access.
(e) Interrupt controller (INTC)
This controller handles hardware interrupt requests (NMI, INTP0 to INTP6) from on-chip peripheral
hardware and external hardware. Eight levels of interrupt priorities can be specified for these interrupt
requests, and multiplexed servicing control can be performed for interrupt sources.
60
(f) Clock generator (CG)
The clock generator includes two types of oscillators; each for main clock (fXX) and for subclock (fXT),
generates five types of clocks (fXX, fXX/2, fXX/4, fXX/8, and fXT), and supplies one of them as the operating
clock for the CPU (f
CPU
).
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CHAPTER 1 INTRODUCTION
(g) Timer/counter
A two-channel 16-bit timer/event counter, a four-channel 8-bit timer/event counter, and a two-channel 8-
bit interval timer are equipped, enabling measurement of pulse intervals and frequency as well as
programmable pulse output.
The two-channel 8-bit timer/event counter can be connected via a cascade to enable use as a 16-bit
timer.
The two-channel 8-bit interval timer can be connected via a cascade to enable to be used as a 16-bit
timer.
(h) Watch timer
This timer counts the reference time period (0.5 seconds) for counting the clock (the 32.768 kHz
subclock or the main clock). At the same time, the watch timer can be used as an interval timer for the
main clock.
(i) Watchdog timer
A watchdog timer is equipped to detect inadvertent program loops, system abnormalities, etc.
It can also be used as an interval timer.
When used as a watchdog timer, it generates a non-maskable interrupt request (INTWDT) after an
overflow occurs. When used as an interval timer, it generates a maskable interrupt request (INTWDTM)
after an overflow occurs.
(j) Serial interface (SIO)
The V850/SB2 includes three kinds of serial interfaces: asynchronous serial interfaces (UART0,
UART1), clocked serial interfaces (CSI0 to CSI3), and an 8-/16-bit variable-length serial interface (CSI4).
2
These plus the I
C bus interfaces (I2C0, I2C1) comprise five channels. Two of these channels are
switchable between the UART and CSI and another two switchable between CSI and I2C.
For UART0 and UART1, data is transferred via the TXD0, TXD1, RXD0, and RXD1 pins.
For CSI0 to CSI3, data is transferred via the SO0 to SO3, SI0 to SI3, and SCK0 to SCK3 pins.
For CSI4, data is transferred via the SO4, SI4, and SCK4 pins.
For I2C0 and I2C1, data is transferred via the SDA0, SDA1, SCL0, and SCL1 pins.
I2C0 and I2C1 are equipped only in the µPD703034AY, 703035AY, 703037AY, 70F3035AY, and
70F3037AY.
For UART and CSI4, a dedicated baud rate generator is equipped.
(k) A/D converter
This high-speed, high-resolution 10-bit A/D converter includes 12 analog input pins. Conversion uses
the successive approximation method.
(l) DMA controller
A six-channel DMA controller is equipped. This controller transfers data between the internal RAM and
on-chip peripheral I/O devices in response to interrupt requests sent by on-chip peripheral I/O.
(m) Real-time output port (RTP)
The RTP is a real-time output function that transfers preset 8-bit data to an output latch when an external
trigger signal occurs or when there is a match signal in a timer compare register. It can also be used for
4-bit × 2 channels.
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CHAPTER 1 INTRODUCTION
(n) Ports
As shown below, the following ports have general-purpose port functions and control pin functions.
Port I/O Port Function Control Function
Port 0 8-bit I/O NMI, external interrupt, A/D converter trigger, RTP trigger
Port 1 6-bit I/O Serial interface
Port 2 8-bit I/O Serial interface, timer I/O
Port 3 8-bit I/O Timer I/O, external address bus, serial interface
Port 4 8-bit I/O External address/data bus
Port 5 8-bit I/O
Port 6 6-bit I/O External address bus
Port 7 8-bit input A/D converter analog input
Port 8 4-bit input
Port 9 7-bit I/O External bus interface control signal I/O
Port 10 8-bit I/O Real-time output port, external address bus, key return input, IEBus
Port 11 4-bit I/O
General-
purpose port
data I/O
Wait control, external address bus
(o) IEBus controller
The IEBus controller is a small-scale digital data transfer system aiming at data transfer among units.
The IEBus controller is incorporated only in the V850/SB2.
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CHAPTER 1 INTRODUCTION
1.5 V850/SB2 (B and H Versions)
1.5.1 Features (V850/SB2 (B and H versions))
{ Number of instructions: 74
{ Minimum instruction execution time
B versions: 79 ns (@ 12.58 MHz operation, external power supply 5 V, regulator
output 3.0 V operation)
H versions: 53 ns (@ 18.87 MHz operation, external power supply 5 V, regulator
output 3.3 V operation)
{ General-purpose registers 32 bits × 32 registers
{ Instruction set Signed multiplication (16 × 16 → 32): (able to execute instructions in parallel
continuously without creating any register hazards).
B versions: 158 ns (@ 12.58 MHz operation)
H versions: 106 ns (@ 18.87 MHz operation)
Saturation operations (overflow and underflow detection functions are included)
32-bit shift instruction: 1 clock
Bit manipulation instructions
Load/store instructions with long/short format
{ Memory space 16 MB of linear address space (for programs and data)
External expandability: expandable to 4 MB
Memory block allocation function: 2 MB per block
Programmable wait function
Idle state insertion function
{ External bus interface 16-bit data bus (address/data multiplex)
Address bus: separate output enabled
3 V to 5 V interface enabled
Bus hold function
External wait function
{ Internal memory
{ Interrupts and exceptions Non-maskable interrupts: 2 sources
{ I/O lines Total: 83 (12 input ports and 71 I/O ports)
{ Timer/counter 16-bit timer: 2 channels (PWM output)
PD703034B, 703034BY (mask ROM: 128 KB/RAM: 8 KB)
µ
PD703035B, 703035BY (mask ROM: 256 KB/RAM: 16 KB)
µ
PD703036H, 703036HY (mask ROM: 384 KB/RAM: 24 KB)
µ
PD703037H, 703037HY (mask ROM: 512 KB/RAM: 24 KB)
µ
PD70F3035B, 70F3035BY (flash memory: 256 KB/RAM: 16 KB)
µ
PD70F3036H, 70F3036HY (flash memory: 384 KB/RAM: 24 KB)
µ
PD70F3037H, 70F3037HY (flash memory: 512 KB/RAM: 24 KB)
µ
Maskable interrupts: 39 sources (µPD703034B, 703035B, 703036H,
703037H, 70F3035B, 70F3036H, 70F3037H)
40 sources (µPD703034BY, 703035BY, 703036HY,
703037HY, 70F3035BY, 70F3036HY,
70F3037HY)
Software exceptions: 32 sources
Exception trap: 1 source
3 V to 5 V interface enabled
8-bit timer: 6 channels (four PWM outputs, cascade connection enabled)
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CHAPTER 1 INTRODUCTION
{ Watch timer When operating under subclock or main clock: 1 channel
Operation using the subclock or main clock is also possible in the IDLE mode.
{ Watchdog timer 1 channel
{ Serial interface (SIO) Asynchronous serial interface (UART)
Clocked serial interface (CSI)
I2C bus interface (I2C)
(only for µPD703034BY, 703035BY, 703036HY, 703037HY, 70F3035BY, 70F3036HY,
and 70F3037HY)
8-/16-bit variable-length serial interface
CSI/UART: 2 channels
CSI/I2C: 2 channels
CSI (8-/16-bit valuable): 1 channel
Dedicated baud rate generator: 3 channels
{ A/D converter 10-bit resolution: 12 channels
{ DMA controller Internal RAM ←→ on-chip peripheral I/O: 6 channels
{ Real-time output port (RTP) 8 bits × 1 channel or 4 bits × 2 channels
{ ROM correction Modifiable 4 points
{ Regulator 4.0 V to 5.5 V input → internal 3.0 V
{ Key return function 4 to 8 selecting enabled, falling edge fixed
{ Clock generator During main clock or subclock operation
5-level CPU clock (including sub operations)
{ Power-saving functions HALT/IDLE/STOP modes
{ IEBus controller 1 ch
{ Package 100-pin plastic LQFP (fine pitch, 14 × 14)
100-pin plastic QFP (14 × 20)
{ CMOS structure All static circuits
1.5.2 Application fields (V850/SB2 (B and H versions))
AV equipment
Example: Audio, car audio equipment, VCR, and TV.
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CHAPTER 1 INTRODUCTION
1.5.3 Ordering information (V850/SB2 (B and H versions))
Part Number Package Internal ROM
PD703034BGC-xxx-8EU 100-pin plastic LQFP (fine pitch) (14 × 14) Mask ROM (128 KB)
µ
PD703034BGF-xxx-3BA 100-pin plastic QFP (14 × 20) Mask ROM (128 KB)
µ
PD703034BYGC-xxx-8EU 100-pin plastic LQFP (fine pitch) (14 × 14) Mask ROM (128 KB)
µ
PD703034BYGF-xxx-3BA 100-pin plastic QFP (14 × 20) Mask ROM (128 KB)
µ
PD703035BGC-xxx-8EU 100-pin plastic LQFP (fine pitch) (14 × 14) Mask ROM (256 KB)
µ
PD703035BGF-xxx-3BA 100-pin plastic QFP (14 × 20) Mask ROM (256 KB)
µ
PD703035BYGC-xxx-8EU 100-pin plastic LQFP (fine pitch) (14 × 14) Mask ROM (256 KB)
µ
PD703035BYGF-xxx-3BA 100-pin plastic QFP (14 × 20) Mask ROM (256 KB)
µ
PD703036HGC-xxx-8EU 100-pin plastic LQFP (fine pitch) (14 × 14) Mask ROM (384 KB)
µ
PD703036HGF-xxx-3BA 100-pin plastic QFP (14 × 20) Mask ROM (384 KB)
µ
PD703036HYGC-xxx-8EU 100-pin plastic LQFP (fine pitch) (14 × 14) Mask ROM (384 KB)
µ
PD703036HYGF-xxx-3BA 100-pin plastic QFP (14 × 20) Mask ROM (384 KB)
µ
PD703037HGF-xxx-3BA 100-pin plastic QFP (14 × 20) Mask ROM (512 KB)
µ
PD703037HYGF-xxx-3BA 100-pin plastic QFP (14 × 20) Mask ROM (512 KB)
µ
PD70F3035BGC-8EU 100-pin plastic LQFP (fine pitch) (14 × 14) Flash memory (256 KB)
µ
PD70F3035BGF-3BA 100-pin plastic QFP (14 × 20) Flash memory (256 KB)
µ
PD70F3035BYGF-8EU 100-pin plastic LQFP (fine pitch) (14 × 14) Flash memory (256 KB)
µ
PD70F3035BYGF-3BA 100-pin plastic QFP (14 × 20) Flash memory (256 KB)
µ
PD70F3036HGC-8EU 100-pin plastic LQFP (fine pitch) (14 × 14) Flash memory (384 KB)
µ
PD70F3036HGF-3BA 100-pin plastic QFP (14 × 20) Flash memory (384 KB)
µ
PD70F3036HYGC-8EU 100-pin plastic LQFP (fine pitch) (14 × 14) Flash memory (384 KB)
µ
PD70F3036HYGF-3BA 100-pin plastic QFP (14 × 20) Flash memory (384 KB)
µ
PD70F3037HGF-3BA 100-pin plastic QFP (14 × 20) Flash memory (512 KB)
µ
PD70F3037HYGF-3BA 100-pin plastic QFP (14 × 20) Flash memory (512 KB)
µ
Note In planning
Remarks 1. ××× indicates ROM code suffix.
2. ROMless devices are not provided.
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CHAPTER 1 INTRODUCTION
N
t
2
N
t
2
X
X
A
A
A
N
t
2
1.5.4 Pin configuration (top view) (V850/SB2 (B and H versions))
100-pin plastic LQFP (fine pitch) (14 × 14)
PD703034BGC-xxx-8EU •µPD703036HGC-xxx-8EU •µPD70F3036HGC-8EU
•
µ
•µPD703034BYGC-xxx-8EU •µPD703036HYGC-xxx-8EU •µPD70F3036HYGC-8EU
•µPD703035BGC-xxx-8EU •µPD70F3035BGC-8EU
•µPD703035BYGC-xxx-8EU •µPD70F3035BYGC-8EU
e
e
o
o
e
o
P21/SO2
P22/SCK2/SCL1
Note 2
P23/RXD1/SI3
P24/TXD1/SO3
P25/ASCK1/SCK3
EV
EV
P26/TI2/TO2
P27/TI3/TO3
P30/TI00
P31/TI01
P32/TI10/SI4
P33/TI11/SO4
P34/TO0/A13/SCK4
P35/TO1/A14
P36/TI4/TO4/A15
P37/TI5/TO5
Note 1
IC/V
PP
P100/RTP0/KR0/A5
P101/RTP1/KR1/A6
P102/RTP2/KR2/A7
P103/RTP3/KR3/A8
P104/RTP4/KR4/A9/IER
P105/RTP5/KR5/A10/IET
P106/RTP6/KR6/A11
P20/SI2/SDA1
P14/SO1/TXD0
P13/SI1/RXD0
P15/SCK1/ASCK0
9998979695949392919089888786858483828180797877
100
1
2
3
4
DD
SS
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
27
2829303132333435363738394041424344454647484950
26
P07/INTP6
P11/SO0
P10/SI0/SDA0
P12/SCK0/SCL0
P06/INTP5/RTPTRG
P05/INTP4/ADTRG
P04/INTP3
P03/INTP2
P02/INTP1
P01/INTP0
P00/NMI
P83/ANI11
P82/ANI10
P81/ANI9
P80/ANI8
P77/ANI7
P76/ANI6
P75/ANI5
P74/ANI4
P73/ANI3
P72/ANI2
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
P71/ANI1
P70/ANI0
V
REF
V
SS
V
DD
P65/A21
P64/A20
P63/A19
P62/A18
P61/A17
P60/A16
P57/AD15
P56/AD14
P55/AD13
P54/AD12
P53/AD11
P52/AD10
P51/AD9
P50/AD8
BV
SS
BV
DD
P47/AD7
P46/AD6
P45/AD5
P44/AD4
SS
DD
X2
X1
V
XT1
XT2
REGC
RESET
P112/A3
P113/A4
P111/A2
P110/WAIT/A1
V
CLKOUT
P90/LBEN/WRL
P91/UBEN
P92/R/W/WRH
P93/DSTB/RD
P94/ASTB
P95/HLDAK
P96/HLDRQ
P40/AD0
P41/AD1
P42/AD2
P43/AD3
P107/RTP7/KR7/A12
Notes 1. IC (
PD703034B, 703034BY, 703035B, 703035BY, 703036H, 703036HY): Connect directly to VSS.
µ
VPP (µPD70F3035B, 70F3035BY, 70F3036H, 70F3036HY): Connect to VSS in normal operation mode.
2. SCL0, SCL1, SDA0, and SDA1 are available only in the µPD703034BY, 703035BY, 703036HY,
70F3035BY, and 70F3036HY.
66
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CHAPTER 1 INTRODUCTION
L
100-pin plastic QFP (14 × 20)
•µPD703034BGF-xxx-3BA • µPD703036HGF-xxx-3BA • µPD70F3035BYGF-3BA
•µPD703034BYGF-xxx-3BA • µPD703036HYGF-xxx-3BA • µPD70F3036HGF-xxx-3BA
•µPD703035BGF-xxx-3BA • µPD703037HGF-xxx-3BA • µPD70F3036HYGF-xxx-3BA
•µPD703035BYGF-xxx-3BA • µPD703037HYGF-xxx-3BA • µPD70F3037HGF-3BA
• µPD70F3035BGF-3BA • µPD70F3037HYGF-3BA
Note 2
Note 2
P13/SI1/RXD0
P11/SO0
P10/SI0/SDA0
P07/INTP6
P06/INTP5/RTPTRG
P05/INTP4/ADTRG
P04/INTP3
P03/INTP2
P02/INTP1
P01/INTP0
P00/NMI
P83/ANI11
P82/ANI10
P81/ANI9
P80/ANI8
P77/ANI7
P76/ANI6
P75/ANI5
P74/ANI4
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
P73/ANI3
P72/ANI2P15/SCK1/ASCK0
P71/ANI1
P70/ANI0
REF
AV
AV
SS
DD
AV
P65/A21
P64/A20
P63/A19
P62/A18
P61/A17
P60/A16
P57/AD15
P56/AD14
P55/AD13
P54/AD12
P53/AD11
P52/AD10
P51/AD9
P50/AD8
SS
BV
DD
BV
P47/AD7
P46/AD6
P45/AD5
P44/AD4
P43/AD3
P42/AD2
P41/AD1
P14/SO1/TXD0
P20/SI2/SDA1
P22/SCK2/SCL1
Note 2
P21/SO2
Note 2
P23/RXD1/SI3
P24/TXD1/SO3
P25/ASCK1/SCK3
EV
EV
P26/TI2/TO2
P27/TI3/TO3
P30/TI00
P31/TI01
P32/TI10/SI4
P33/TI11/SO4
P34/TO0/A13/SCK4
P35/TO1/A14
P36/TI4/TO4/A15
P37/TI5/TO5
Note 1
PP
IC/V
P100/RTP0/KR0/A5
P101/RTP1/KR1/A6
P102/RTP2/KR2/A7
P103/RTP3/KR3/A8
P104/RTP4/KR4/A9/IERX
P105/RTP5/KR5/A10/IETX
P106/RTP6/KR6/A11
P107/RTP7/KR7/A12
P110/WAIT/A1
P12/SCK0/SCL0
99989796959493929190898887868584838281
10031
1
2
3
4
5
6
7
DD
SS
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
32333435363738394041424344454647484950
SS
DD
X2
X1
V
V
CLKOUT
P90/LBEN/WR
P91/UBEN
P92/R/W/WRH
P93/DSTB/RD
P94/ASTB
P95/HLDAK
P40/AD0
P96/HLDRQ
Notes 1. IC (
XT1
XT2
REGC
RESET
P111/A2
P112/A3
P113/A4
PD703034B, 703034BY, 703035B, 703035BY, 703036H, 703036HY, 703037H, 703037HY):
µ
Connect directly to VSS.
VPP (µPD70F3035B, 70F3035BY, 70F3036H, 70F3036HY, 70F3037H, 70F3037HY):
Connect to VSS in normal operation mode.
2. SCL0, SCL1, SDA0, and SDA1 are available only in the µPD703034BY, 703035BY, 703036HY,
703037HY, 70F3035BY, 70F3036HY, and 70F3037HY.
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CHAPTER 1 INTRODUCTION
Pin names (V850/SB2 (B and H versions))
A1 to A21: Address bus P70 to P77: Port 7
AD0 to AD15: Address/data bus P80 to P83: Port 8
ADTRG: A/D trigger input P90 to P96: Port 9
ANI0 to ANI11: Analog input P100 to P107: Port 10
ASCK0, ASCK1: Asynchronous serial clock P110 to P113: Port 11
ASTB: Address strobe RD: Read
: Analog V
AVDD
AV
: Analog reference voltage RESET: Reset
REF
AVSS: Analog V
DD
SS
REGC: Regulator control
RTP0 to RTP7: Real-time output port
BVDD: Power supply for bus interface RTPTRG: RTP trigger
BVSS: Ground for bus interface R/W: Read/write status
CLKOUT: Clock output RXD0, RXD1: Receive data
DSTB: Data strobe SCK0 to SCK4: Serial clock
EVDD: Power supply for port SCL0, SCL1: Serial clock
EVSS: Ground for port SDA0, SDA1: Serial data
HLDAK: Hold acknowledge SI0 to SI4: Serial input
HLDRQ: Hold request SO0 to SO4: Serial output
IC: Internally connected TI00, TI01, TI10,
IERX: IEBus receive data TI11, TI2 to TI5: Timer input
IETX: IEBus transmit data TO0 to TO5: Timer output
INTP0 to INTP6: Interrupt request from peripherals TXD0,TXD1: Transmit data
KR0 to KR7
:
Key return UBEN: Upper byte enable
LBEN: Lower byte enable VDD: Power supply
NMI: Non-maskable interrupt request VPP: Programming power supply
P00 to P07: Port 0 VSS: Ground
P10 to P15: Port 1 WAIT: Wait
P20 to P27: Port 2 WRH: Write strobe high level data
P30 to P37: Port 3 WRL: Write strobe low level data
P40 to P47: Port 4 X1, X2: Crystal for main clock
P50 to P57: Port 5 XT1, XT2: Crystal for subclock
P60 to P65: Port 6
68
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CHAPTER 1 INTRODUCTION
Note 3
A
)
D
Note 3
(
)
)
)
)
)
)
)
Note 3
Note 3
Note 6
Note 7
1.5.5 Function blocks (V850/SB2 (B and H versions))
(1) Internal block diagram
ROM
Note
1
RAM
Note
2
P110 to P113
General-purpose
P80 to P83
P90 to P96
P100 to P107
32-bit barrel
32 bits × 32
P70 to P77
INTP0 to INTP 6
TI00,TI01,
TI10,TI11
TO0,TO1
TI2/TO2
TI3/TO3
TI4/TO4
TI5/TO5
SO0
SI0/SDA0
SCK0/SCL0
SO2
SI2/SDA1
SCK2/SCL1
SO1/TXD0
SI1/RXD0
SCK1/ASCK0
SO3/TXD1
SI3/RXD1
SCK3/ASCK1
SO4
SCK4
KR0 to KR7
NMI
SI4
INTC
Timer/counter
16-bit timer:
TM0, TM1
8-bit timer:
TM2 to TM7
SIO
CSI0/I2C0
Note 4
CSI2/I2C1
Note 4
CSI1/UART0
CSI3/UART1
Variable
length C SI4
Key return
DMAC: 6 ch
PC
shifter
System
register
registers
Ports
P60 to P65
CPU
ROM
correction
Multiplier
16 ×16→32
ALU
RTP
P40 to P47
P20 to P27
P30 to P37
P50 to P57
P10 to P15
P00 to P07
RTP0 to RTP7
Note 5
RTPTRG
Instruction
queue
BCU
A/D
converter
SS
D
REF
AV
AV
AV
Regulator
ANI0 to ANI11
HLDRQ (P96
HLDAK
STB (P94
DSTB/RD (P93
R/W /WRH (P92
UBEN (P91
LBEN/WRL (P90
WAIT (P110
A1 to A12
(P100 to P107,
P110 to P113)
A13 to A15 (P34 to P36)
A16 to A21 (P60 to P65)
AD0 to AD15
(P40 to P47, P50 to P57)
CLKOUT
X1
X2
CG
XT1
XT2
RESET
ADTRG
V
DD
P95
V
BV
BV
EV
EV
V
IC
SS
DD
SS
DD
SS
PP
IETX
IERX
Notes 1.
Watch timer
Watchdog
timer
IEBus
PD703034B, 703034BY: 128 K (mask ROM)
µ
PD703035B, 703035BY: 256 K (mask ROM)
µ
PD703036H, 703036HY: 384 K (mask ROM)
µ
PD703037H, 703037HY: 512 K (mask ROM)
µ
PD70F3035B, 70F3035BY: 256 K (flash memory)
µ
PD70F3036H, 70F3036HY: 384 K (flash memory)
µ
PD70F3037H, 70F3037HY: 512 K (flash memory)
µ
REGC
2.µPD703034B, 703034BY 8 KB
PD703035B, 703035BY, 70F3035B, 70F3035BY: 16 KB
µ
PD703036H, 703036HY, 703037H, 703037HY,: 24 KB
µ
70F3036H, 70F3036HY, 70F3037H, 70F3037HY
3. SDA0, SDA1, SCL0, SCL1 pins are available only in the µPD703034BY, 703035BY, 703036HY,
703037HY, 70F3035BY, 70F3036HY, and 70F3037HY
4. I2C functions is available only in the µPD703034BY, 703035BY, 703036HY, 703037HY, 70F3035BY,
70F3036HY, and 70F3037HY
5. B versions: 3.0 V, H versions: 3.3 V
6.µPD70F3035B, 70F3035BY, 70F3036H, 70F3036HY, 70F3037H, 70F3037HY
7.µPD703034B, 703034BY, 703035B, 703035BY, 703036H, 703036HY, 703037H, 703037HY
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(2) Internal units
(a) CPU
The CPU uses five-stage pipeline control to enable single-clock execution of address calculations,
arithmetic logic operations, data transfers, and almost all other instruction processing.
Other dedicated on-chip hardware, such as the multiplier (16 bits × 16 bits → 32 bits) and the barrel
shifter (32 bits) help accelerate processing of complex instructions.
(b) Bus control unit (BCU)
The BCU starts a required external bus cycle based on the physical address obtained by the CPU.
When an instruction is fetched from external memory space and the CPU does not send a bus cycle
start request, the BCU generates a prefetch address and prefetches the instruction code. The
prefetched instruction code is stored in an instruction queue.
(c) ROM
This consists of a mask ROM or flash memory mapped to the address space starting at 00000000H.
The ROM capacity varies depending on the product. The ROM capacity of each product is shown
below.
CHAPTER 1 INTRODUCTION
PD703034B, 703034BY: 128 KB (mask ROM)
µ
PD703035B, 703035BY: 256 KB (mask ROM)
µ
PD70F3035B, 70F3035BY: 256 KB (flash memory)
µ
PD703036H, 703036HY: 384 KB (mask ROM)
µ
PD70F3036H, 70F3036HY: 384 KB (flash memory)
µ
PD703037H, 703037HY: 512 KB (mask ROM)
µ
PD70F3037H, 70F3037HY: 512 KB (flash memory)
µ
ROM can be accessed by the CPU in one clock cycle during instruction fetch.
(d) RAM
The RAM capacity and mapping addresses vary depending on the product. The RAM capacity of each
product is shown below.
PD703034B, 703034BY: 8 KB (mapping starts at FFFFD000H)
µ
PD703035B, 703035BY, 70F3035B, 70F3035BY: 16 KB (mapping starts at FFFFB000H)
µ
PD703036H, 703036HY, 70F3036H, 70F3036HY,
µ
703037H, 703037HY, 70F3037H, 70F3037HY: 24 KB (mapping starts at FFFF9000H)
RAM can be accessed by the CPU in one clock cycle during data access.
70
(e) Interrupt controller (INTC)
This controller handles hardware interrupt requests (NMI, INTP0 to INTP6) from on-chip peripheral
hardware and external hardware. Eight levels of interrupt priorities can be specified for these interrupt
requests, and multiplexed servicing control can be performed for interrupt sources.
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CHAPTER 1 INTRODUCTION
(f) Clock generator (CG)
The clock generator includes two types of oscillators; each for main clock (fXX
) and for subclock (fXT),
generates five types of clocks (fXX, fXX/2, fXX/4, fXX/8, and fXT), and supplies one of them as the operating
clock for the CPU (f
CPU
).
(g) Timer/counter
A two-channel 16-bit timer/event counter, a four-channel 8-bit timer/event counter, and a two-channel 8-
bit interval timer are equipped, enabling measurement of pulse intervals and frequency as well as
programmable pulse output.
The two-channel 8-bit timer/event counter can be connected via a cascade to enable use as a 16-bit
timer.
The two-channel 8-bit interval timer can be connected via a cascade to enable to be used as a 16-bit
timer.
(h) Watch timer
This timer counts the reference time period (0.5 seconds) for counting the clock (the 32.768 kHz
subclock or the main clock). At the same time, the watch timer can be used as an interval timer for the
main clock.
(i) Watchdog timer
A watchdog timer is equipped to detect inadvertent program loops, system abnormalities, etc.
It can also be used as an interval timer.
When used as a watchdog timer, it generates a non-maskable interrupt request (INTWDT) after an
overflow occurs. When used as an interval timer, it generates a maskable interrupt request (INTWDTM)
after an overflow occurs.
(j) Serial interface (SIO)
The V850/SB2 includes three kinds of serial interfaces: asynchronous serial interfaces (UART0,
UART1), clocked serial interfaces (CSI0 to CSI3), and an 8-/16-bit variable-length serial interface (CSI4).
These plus the I2C bus interfaces (I2C0, I2C1) comprise five channels. Two of these channels are
switchable between the UART and CSI and another two switchable between CSI and I2C.
For UART0 and UART1, data is transferred via the TXD0, TXD1, RXD0, and RXD1 pins.
For CSI0 to CSI3, data is transferred via the SO0 to SO3, SI0 to SI3, and SCK0 to SCK3 pins.
For CSI4, data is transferred via the SO4, SI4, and SCK4 pins.
For I2C0 and I2C1, data is transferred via the SDA0, SDA1, SCL0, and SCL1 pins.
I2C0 and I2C1 are equipped only in the µPD703034BY, 703035BY, 703036HY, 703037HY, 70F3035BY,
70F3036HY, and 70F3037HY.
For UART and CSI4, a dedicated baud rate generator is equipped.
(k) A/D converter
This high-speed, high-resolution 10-bit A/D converter includes 12 analog input pins. Conversion uses
the successive approximation method.
(l) DMA controller
A six-channel DMA controller is equipped. This controller transfers data between the internal RAM and
on-chip peripheral I/O devices in response to interrupt requests sent by on-chip peripheral I/O.
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CHAPTER 1 INTRODUCTION
(m) Real-time output port (RTP)
The RTP is a real-time output function that transfers preset 8-bit data to an output latch when an external
trigger signal occurs or when there is a match signal in a timer compare register. It can also be used for
4-bit × 2 channels.
(n) Ports
As shown below, the following ports have general-purpose port functions and control pin functions.
Port I/O Port Function Control Function
Port 0 8-bit I/O NMI, external interrupt, A/D converter trigger, RTP trigger
Port 1 6-bit I/O Serial interface
Port 2 8-bit I/O Serial interface, timer I/O
Port 3 8-bit I/O Timer I/O, external address bus, serial interface
Port 4 8-bit I/O External address/data bus
Port 5 8-bit I/O
Port 6 6-bit I/O External address bus
Port 7 8-bit input A/D converter analog input
Port 8 4-bit input
Port 9 7-bit I/O External bus interface control signal I/O
Port 10 8-bit I/O Real-time output port, external address bus, key return input, IEBus
Port 11 4-bit I/O
General-
purpose port
data I/O
Wait control, external address bus
(o) IEBus controller
The IEBus controller is a small-scale digital data transfer system aiming at data transfer among units.
The IEBus controller is incorporated only in the V850/SB2.
72
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CHAPTER 2 PIN FUNCTIONS
2.1 List of Pin Functions
The names and functions of the pins of the V850/SB1 and V850/SB2 are described below divided into port pins
and non-port pins.
There are three types of power supplies for the pin I/O buffers: AVDD, BVDD, and EVDD. The relationship between
these power supplies and the pins is described below.
Table 2-1. Pin I/O Buffer Power Supplies
Power Supply Corresponding Pins Usable Voltage Range
AV
BV
EV
DD
DD
DD
Port 7, port 8 When using A/D converter: 4.5 V ≤ AVDD ≤ 5.5 V
When not using A/D converter: 3.5 V ≤ AV
≤ 5.5 V
DD
Port 4, port 5, port 6, port 9, CLKOUT 3.0 V ≤ BVDD ≤ 5.5 V
Port 0, port 1, port 2, port 3, port 10, port 11, RESET 3.0 V ≤ EVDD ≤ 5.5 V
Caution The electrical specifications in the case of 3.0 V to up to 4.0 V are different
from those for 4.0 to 5.5 V.
Differences in pins between the V850/SB1 and V850/SB2 are shown below.
Table 2-2. Differences in Pins Between V850/SB1 and V850/SB2
V850/SB1 V850/SB2Pin
PD703031A,
µ
PD703032A,
µ
PD703033A,
µ
PD703030B,
µ
PD703031B,
µ
PD703032B,
µ
PD703033B
µ
IC Available None Available None Available None Available None
V
PP
None Available None Available None Available None Available
SDA0,
SDA1
SCL0,
SCL1
IERX None Available
IETX None Available
PD70F3032A,
µ
PD70F3033A,
µ
PD70F3030B,
µ
PD70F3032B,
µ
PD70F3033B
µ
PD703031AY,
µ
PD703032AY,
µ
PD703033AY,
µ
PD703030BY,
µ
PD703031BY,
µ
PD703032BY,
µ
PD703033BY
µ
PD70F3032AY,
µ
PD70F3033AY,
µ
PD70F3030BY,
µ
PD70F3032BY,
µ
PD70F3033BY
µ
PD703034A,
µ
PD703035A,
µ
PD703037A,
µ
PD703034B,
µ
PD703035B,
µ
PD703036H,
µ
PD703037H
µ
PD70F3035A,
µ
PD70F3037A,
µ
PD70F3035B,
µ
PD70F3036H,
µ
PD70F3037H
µ
PD703034AY,
µ
PD703035AY,
µ
PD703037AY,
µ
PD703034BY,
µ
PD703035BY,
µ
PD703036HY,
µ
PD703037HY
µ
PD70F3035AY,
µ
PD70F3037AY,
µ
PD70F3035BY,
µ
PD70F3036HY,
µ
PD70F3037HY
µ
None Available None Available
None Available None Available
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(1) Port pins
Pin Name I/O PULL Function Alternate Function
(1/3)
P00 NMI
P01 INTP0
P02 INTP1
P03 INTP2
P04 INTP3
P05 INTP4/ADTRG
P06 INTP5/RTPTRG
P07
P10 SI0/SDA0
P11 SO0
P12 SCK0/SCL0
P13 SI1/RXD0
P14 SO1/TXD0
P15
P20 SI2/SDA1
P21 SO2
P22 SCK2/SCL1
P23 SI3/RXD1
P24 SO3/TXD1
P25 SCK3/ASCK1
P26 TI2/TO2
P27
I/O Yes Port 0
8-bit I/O port
Input/output mode can be specified in 1-bit units.
INTP6
I/O Yes Port 1
6-bit I/O port
Input/output mode can be specified in 1-bit units.
SCK1/ASCK0
I/O Yes Port 2
8-bit I/O port
Input/output mode can be specified in 1-bit units.
TI3/TO3
Remark PULL: On-chip pull-up resistor
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Pin Name I/O PULL Function Alternate Function
(2/3)
P30 TI00
P31 TI01
P32 TI10/SI4
P33 TI11/SO4
P34 TO0/A13/SCK4
P35 TO1/A14
P36 TI4/TO4/A15
P37
P40 AD0
P41 AD1
P42 AD2
P43 AD3
P44 AD4
P45 AD5
P46 AD6
P47
P50 AD8
P51 AD9
P52 AD10
P53 AD11
P54 AD12
P55 AD13
P56 AD14
P57
P60 A16
P61 A17
P62 A18
P63 A19
P64 A20
P65
I/O Yes Port 3
8-bit I/O port
Input/output mode can be specified in 1-bit units.
TI5/TO5
I/O No Port 4
8-bit I/O port
Input/output mode can be specified in 1-bit units.
AD7
I/O No Port 5
8-bit I/O port
Input/output mode can be specified in 1-bit units.
AD15
I/O No Port 6
6-bit I/O port
Input/output mode can be specified in 1-bit units.
A21
Remark PULL: On-chip pull-up resistor
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Pin Name I/O PULL Function Alternate Function
(3/3)
P70 ANI0
P71 ANI1
P72 ANI2
P73 ANI3
P74 ANI4
P75 ANI5
P76 ANI6
P77
P80 ANI8
P81 ANI9
P82 ANI10
P83
P90 LBEN/WRL
P91 UBEN
P92 R/W/WRH
P93 DSTB/RD
P94 ASTB
P95 HLDAK
P96
P100 RTP0/A5/KR0
P101 RTP1/A6/KR1
P102 RTP2/A7/KR2
P103 RTP3/A8/KR3
P104 RTP4/A9/KR4/IERX
P105 RTP5/A10/KR5/IETX
P106 RTP6/A11/KR6
P107
P110 A1/WAIT
P111 A2
P112 A3
P113
Input No Port 7
8-bit input port
ANI7
Input No Port 8
4-bit input port
ANI11
I/O No Port 9
7-bit I/O port
Input/output mode can be specified in 1-bit units.
HLDRQ
I/O Yes Port 10
8-bit I/O port
Input/output mode can be specified in 1-bit units.
RTP7/A12/KR7
I/O Yes Port 11
4-bit I/O port
Input/output mode can be specified in 1-bit units.
A4
Remark PULL: On-chip pull-up resistor
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(2) Non-port pins
Pin Name I/O PULL Function Alternate Function
(1/3)
A1 P110/WAIT
Output Yes Lower address bus used for external memory expansion
A2 to A4 P111 to P113
A5 to A8 P100/RTP0/KR0 to
P103/RTP3/KR3
A9 P104/RTP4/KR4/IERX
A10 P105/RTP5/KR5/IETX
A11, A12 P106/RTP6/KR6 to
P107/RTP7/KR7
A13 P34/TO0/SCK4
A14 P35/TO1
A15
P36/TI4/TO4
A16 to A21 Output No Higher address bus used for external memory expansion P60 to P65
AD0 to AD7 P40 to P47
AD8 to AD15
I/O No 16-bit multiplexed address/data bus used for external memory
expansion
P50 to P57
ADTRG Input Yes A/D converter external trigger input P05/INTP4
ANI0 to ANI7 Input No P70 to P77
ANI8 to ANI11 Input No
ASCK0 P15/SCK1
Input Yes Serial clock input for UART0 and UART1
ASCK1
Analog input to A/D converter
P80 to P83
P25/SCK3
ASTB Output No External address strobe signal output P94
AV
AV
AV
BV
BV
DD
REF
SS
DD
SS
−−Positive power supply for A/D converter and alternate-function port −
Input − Reference voltage input for A/D converter −
−−Ground potential for A/D converter and alternate-function port −
−−Positive power supply for bus interface and alternate-function port −
−−Ground potential for bus interface and alternate-function port −
CLKOUT Output − Internal system clock output −
DSTB Output No External data strobe signal output P93/RD
EV
DD
−−Power supply for I/O port and alternate-function pin (except for
−
bus interface)
EV
SS
−−Ground potential for I/O port and alternate-function pin (except
−
for bus interface)
HLDAK Output No Bus hold acknowledge output P95
HLDRQ Input No Bus hold request input P96
IERX Input IEBus data input (V850/SB2 only) P104/RTP4/KR4/A9
IETX Output
INTP0 to INTP3 External interrupt request input (analog noise elimination) P01 to P04
Input Yes
Yes
IEBus data output (V850/SB2 only) P105/RTP5/KR5/A10
INTP4 P05/ADTRG
INTP5
External interrupt request input (digital noise elimination)
P06/RTPTRG
Remark PULL: On-chip pull-up resistor
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Pin Name I/O PULL Function Alternate Function
(2/3)
INTP6 External interrupt request input (digital noise elimination for
Input Yes
P07
remote control)
KR0 to KR3 P100/A5/RTP0 to
Key return input
P103/A8/RTP3
KR4 P104/A9/RTP4/IERX
KR5 P105/A10/RTP5/IETX
KR6, KR7
P106/A11/RTP6 to
P107/A12/RTP7
LBEN Output No External data bus’s lower byte enable signal output P90/WRL
IC −−Internally connected (mask ROM versions only) −
NMI Input Yes Non-maskable interrupt request input (analog noise elimination) P00
RD Output No Read strobe signal output P93/DSTB
REGC −−Capacitor connection for regulator output stabilization −
RESET Input − System reset input −
RTP0 to RTP3 P100/A5/KR0 to
Output Yes Real-time output port
P103/A8/KR3
RTP4 P104/A9/KR4/IERX
RTP5 P105/A10/KR5/IETX
RTP6, RTP7
P106/A11/KR6,
P107/A12/KR7
RTPTRG Input Yes RTP external trigger input P06/INTP5
R/W Output No External read/write status output P92/WRH
RXD0 P13/SI1
RXD1
SCK0 P12/SCL0
Input Yes Serial receive data input for UART0 and UART1
I/O Yes
Serial clock I/O (3-wire type) for CSI0 to CSI3
P23/SI3
SCK1 P15/ASCK0
SCK2 P22/SCL1
SCK3
SCK4
SCL0 P12/SCK0
I/O Yes Serial clock I/O for I
SCL1
SDA0 P10/SI0
I/O Yes Serial transmit/receive data I/O for I
SDA1
SI0 P10/SDA0
Input Yes
Serial clock I/O for variable-length CSI4 (3-wire type) P34/TO0/A13
2
2
chip I
C) only)
(Y versions (products with on-chip I
C0 and I2C1 (Y versions (products with on-
2
C0 and I2C1
2
C) only)
Serial receive data input (3-wire type) for CSI0 to CSI3
P25/ASCK1
P22/SCK2
P20/SI2
SI1 P13/RXD0
SI2 P20/SDA1
SI3
SI4
Serial receive data input (3-wire type) for variable-length CSI4 P32/TI10
P23/RXD1
SO0 Output Yes Serial transmit data output (3-wire type) for CSI0 to CSI3 P11
Remark PULL: On-chip pull-up resistor
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Pin Name I/O PULL Function Alternate Function
(3/3)
SO1 P14/TXD0
Output Yes
Serial transmit data output (3-wire type) for CSI0 to CSI3
SO2 P21
SO3
SO4
TI00 Shared as external capture trigger input and external count
Input Yes
Serial transmit data output for variable-length CSI4 (3-wire type) P33/TI11
P24/TXD1
P30
clock input for TM0
TI01 External capture trigger input for TM0 P31
TI10 Shared as external capture trigger input and external count
P32/SI4
clock input for TM1
TI11 External capture trigger input for TM1 P33/SO4
TI2 External count clock input for TM2 P26/TO2
TI3
TI4 External count clock input for TM4 P36/TO4/A15
Input Yes
TI5
TO0, TO1 Pulse signal output for TM0, TM1 P34/A13/SCK4/P35/
Output Yes
External count clock input for TM3 P27/TO3
External count clock input for TM5 P37/TO5
A14
TO2 Pulse signal output for TM2 P26/TI2
TO3 Pulse signal output for TM3 P27/TI3
TO4 Pulse signal output for TM4 P36/TI4/A15
TO5
TXD0 P14/SO1
Output Yes Serial transmit data output for UART0 and UART1
TXD1
Pulse signal output for TM5 P37/TI5
P24/SO3
UBEN Output No Higher byte enable signal output for external data bus P91
V
DD
V
PP
−−Positive power supply pin −
−−High-voltage apply pin for program write/verify (flash memory
−
versions only)
V
SS
−−GND potential −
WAIT Input Yes Control signal input for inserting wait in bus cycle P110/A1
WRH Higher byte write strobe signal output for external data bus P92/R/W
WRL
X1 Input −
X2 −
XT1 Input −
XT2 −
Output No
Lower byte write strobe signal output for external data bus P90/LBEN
No Resonator connection for main clock
−
No Resonator connection for subclock
−
Remark PULL: On-chip pull-up resistor
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2.2 Pin States
The operating states of various pins are described below with reference to their operating modes.
Table 2-3. Operating States of Pins in Each Operating Mode
Operating State
Pin
Reset
Note 1
HALT Mode/
Idle State
IDLE Mode/
STOP Mode
Bus Hold Bus Cycle
Note 2
Inactive
AD0 to AD15 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
A1 to A15 Hi-Z Held Held Held Held
A16 to A21 Hi-Z Held Hi-Z Hi-Z Held
LBEN, UBEN Hi-Z Held Hi-Z Hi-Z Held
Note 3
Note 3
Note 3
R/W Hi-Z H Hi-Z Hi-Z H
DSTB, WRL, WRH, RD Hi-Z H Hi-Z Hi-Z H
ASTB Hi-Z H Hi-Z Hi-Z H
HLDRQ — Operating — Operating Operating
HLDAK Hi-Z Operating Hi-Z L Operating
WAIT —————
CLKOUT Hi-Z Operating
Note 4
L Operating
Note 4
Operating
Note 4
Notes 1. Pins (except the CLKOUT pin) are used as port pins (input mode) after reset.
2. The bus cycle inactivation timing occurs when the internal memory area is specified by the program
counter (PC) in the external expansion mode.
3. • When the external memory area has not been accessed even once after reset is released and the
external expansion mode is set: Undefined
• When the bus cycle is inactivated after access to the external memory area, or when the external
memory area has not been accessed even once after the external expansion mode is released and
set again: The state of the external bus cycle when the external memory area accessed last is held.
4. Low level (L) when in clock output inhibit mode
Remark Hi-Z: High impedance
Held: State is held during preset external bus cycle
L: Low-level output
H: High-level output
−: Input without sampling sampled (not acknowledged)
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2.3 Description of Pin Functions
(1) P00 to P07 (Port 0) ··· 3-state I/O
P00 to P07 constitute an 8-bit I/O port that can be set to input or output in 1-bit units.
P00 to P07 can also function as an NMI input, external interrupt request inputs, external trigger for the A/D
converter, and external trigger for the real-time output port. The valid edges of the NMI and INTP0 to INTP6 pins
are specified by the EGP0 and EGN0 registers.
(a) Port function
P00 to P07 can be set to input or output in 1-bit units using the port 0 mode register (PM0).
(b) Alternate functions
(i) NMI (Non-maskable interrupt request) ··· input
This is a non-maskable interrupt request signal input pin.
(ii) INTP0 to INTP6 (Interrupt request from peripherals) ··· input
These are external interrupt request input pins.
(iii) ADTRG (A/D trigger input) ··· input
This is the A/D converter’s external trigger input pin. This pin is controlled by A/D converter mode
register 1 (ADM1).
(iv) RTPTRG (Real-time output port trigger input) ··· input
This is the real-time output port’s external trigger input pin. This pin is controlled by the real-time output
port control register (RTPC).
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(2) P10 to P15 (Port 1) ··· 3-state I/O
P10 to P15 constitute a 6-bit I/O port that can be set to input or output in 1-bit units.
P10 to P15 can also function as input or output pins for the serial interface.
P10 to P12, P14, and P15 can be selected as normal output or N-ch open-drain output.
(a) Port function
P10 to P15 can be set to input or output in 1-bit units using the port 1 mode register (PM1).
(b) Alternate functions
(i) SI0, SI1 (Serial input 0, 1) ··· input
These are the serial receive data input pins of CSI0 and CSI1.
(ii) SO0, SO1 (Serial output 0, 1) ··· output
These are the serial transmit data output pins of CSI0 and CSI1.
(iii) SCK0, SCK1 (Serial clock 0, 1) ··· 3-state I/O
These are the serial clock I/O pins for CSI0 and CSI1.
(iv) SDA0 (Serial data 0) ··· I/O
2
This is the serial transmit/receive data I/O pin of I
C0 (Y versions (products with on-chip I2C) only).
(v) SCL0 (Serial clock 0) ··· I/O
This is the serial clock I/O pin for I2C0 (Y versions (products with on-chip I2C) only).
(vi) RXD0 (Receive data 0) ··· input
This is the serial receive data input pin of UART0.
(vii) TXD0 (Transmit data 0) ··· output
This is the serial transmit data output pin of UART0.
(viii) ASCK0 (Asynchronous serial clock 0) ··· input
This is the serial baud rate clock input pin of UART0.
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(3) P20 to P27 (Port 2) ··· 3-state I/O
P20 to P27 constitute an 8-bit I/O port that can be set to input or output in 1-bit units.
P20 to P27 can also function as input or output pins for the serial interface, and input or output pins for the
timer/counter.
P20 to P22, P24, and P25 can be selected as normal output or N-ch open-drain output.
(a) Port function
P20 to P27 can be set to input or output in 1-bit units using the port 2 mode register (PM2).
(b) Alternate functions
(i) SI2, SI3 (Serial input 2, 3) ··· input
These are the serial receive data input pins of CSI2 and CSI3.
(ii) SO2, SO3 (Serial output 2, 3) ··· output
These are the serial transmit data output pins of CSI2 and CSI3.
(iii) SCK2, SCK3 (Serial clock 2, 3) ··· 3-state I/O
These are the serial clock I/O pins of CSI2 and CSI3.
(iv) SDA1 (Serial data 1) ... I/O
2
This is the serial transmit/receive data I/O pin of I
C1 (Y versions (products with on-chip I2C) only).
(v) SCL1 (Serial clock) ... I/O
This is the serial clock I/O pin of I2C1 (Y versions (products with I2C) only).
(vi) RXD1 (Receive data 1) ... input
This is the serial receive data input pin of UART1.
(vii) TXD1 (Transmit data 1) ... output
This is the serial transmit data output pin of UART1.
(viii) ASCK1 (Asynchronous serial clock 1) ... input
This is the serial baud rate clock input pin of UART1.
(ix) TI2, TI3 (Timer input 2, 3) ... input
These are the external count clock input pins of timer 2 and timer 3.
(x) TO2, TO3 (Timer output 2, 3) ... output
These are the pulse signal output pins of timer 2 and timer 3.
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(4) P30 to P37 (Port 3) ··· 3-state I/O
P30 to P37 constitute an 8-bit I/O port that can be set to input or output in 1-bit units.
P30 to P37 can also function as input or output pins for the timer/counter, an address bus (A13 to A15) when
memory is expanded externally, and serial interface I/O.
P33 and P34 can be selected as normal output or N-ch open-drain output.
(a) Port function
P30 to P37 can be set to input or output in 1-bit units using the port 3 mode register (PM3).
(b) Alternate functions
(i) TI00, TI01, TI10, TI11, TI4, TI5 (Timer input 00, 01, 10, 11, 4, 5) ··· input
These are the external count clock input pins of timer 0, timer 1, timer 4, and timer 5.
(ii) TO0, TO1, TO4, TO5 (Timer output 0, 1, 4, 5) ··· output
These are the pulse signal output pins of timer 0, timer 1, timer 4, and timer 5.
(iii) A13 to A15 (Address bus 13 to 15) ··· output
These comprise an address bus that is used for external access. These pins operate as the A13 to
A15 bit address output pins within a 22-bit address. The output changes in synchronization with the
rising edge of the clock in the T1 state of the bus cycle. When the timing sets the bus cycle to inactive,
the previous bus cycle’s address is retained.
(iv) SI4 (Serial input 4) ··· input
This is the serial receive data input pin of CSI4.
(v) SO4 (Serial output 4) ··· output
This is the serial transmit data output pin of CSI4.
(vi) SCK4 (Serial clock 4) ··· 3-state I/O
This is the I/O pin of the CSI4 serial clock.
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(5) P40 to P47 (Port 4) ··· 3-state I/O
P40 to P47 constitute an 8-bit I/O port that can be set to input or output pins in 1-bit units.
P40 to P47 can also function as a time division address/data bus (AD0 to AD7) when memory is expanded
externally.
The I/O signal level uses the bus interface power supply pins BVDD
and BVSS as a reference.
(a) Port function
P40 to P47 can be set to input or output in 1-bit units using the port 4 mode register (PM4).
(b) Alternate functions (External expansion function)
P40 to P47 can be set as AD0 to AD7 using the memory expansion mode register (MM).
(i) AD0 to AD7 (Address/data bus 0 to 7) ··· 3-state I/O
These comprise a multiplexed address/data bus that is used for external access. At the address timing
(T1 state), these pins operate as AD0 to AD7 (22-bit address) output pins. At the data timing (T2, TW,
T3), they operate as the lower 8-bit I/O bus pins for 16-bit data. The output changes in synchronization
with the rising edge of the clock in each state within the bus cycle. When the timing sets the bus cycle
to inactive, these pins go into a high-impedance state.
(6) P50 to P57 (Port 5) ··· 3-state I/O
P50 to P57 constitute an 8-bit I/O port that can be set to input or output in 1-bit units.
P50 to P57 can also function as I/O port pins and as a time division address/data buses (AD8 to AD15) when
memory is expanded externally.
The I/O signal level uses the bus interface power supply pins BVDD and BVSS as reference.
(a) Port function
P50 to P57 can be set to input or output in 1-bit units using the port 5 mode register (PM5).
(b) Alternate functions (External expansion function)
P50 to P57 can be set as AD8 to AD15 using the memory expansion mode register (MM).
(i) AD8 to AD15 (Address/data bus 8 to 15) ··· 3-state I/O
These comprise a multiplexed address/data bus that is used for external access. At the address timing
(T1 state), these pins operate as AD8 to AD15 (22-bit address) output pins. At the data timing (T2, TW,
T3), they operate as the higher 8-bit I/O bus pins for 16-bit data. The output changes in
synchronization with the rising edge of the clock in each state within the bus cycle. When the timing
sets the bus cycle to inactive, these pins go into a high-impedance state.
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(7) P60 to P65 (Port 6) ··· 3-state I/O
P60 to P65 constitute a 6-bit I/O port that can be set to input or output in 1-bit units.
P60 to P65 can also function as an address bus (A16 to A21) when memory is expanded externally. When the
port 6 is accessed in 8-bit units, the higher 2 bits of port 6 are ignored when they are written to and 00 is read
when they are read.
The I/O signal level uses the bus interface power supply pins BVDD
and BVSS as reference.
(a) Port function
P60 to P65 can be set to input or output in 1-bit units using the port 6 mode register (PM6).
(b) Alternate functions (External expansion function)
P60 to P65 can be set as A16 to A21 using the memory expansion mode register (MM).
(i) A16 to A21 (Address bus 16 to 21) ··· output
These comprise an address bus that is used for external access. These pins operate as the higher 6-
bit address output pins within a 22-bit address. The output changes in synchronization with the rising
edge of the clock in the T1 state of the bus cycle. When the timing sets the bus cycle to inactive, the
previous bus cycle’s address is retained.
(8) P70 to P77 (Port 7), P80 to P83 (Port 8) ··· input
P70 to P77 constitute an 8-bit input-only port in which all the pins are fixed to input mode. P80 to P83 constitute
a 4-bit input-only port in which all the pins are fixed to input.
P70 to P77 and P80 to P83 can also function as analog input pins for the A/D converter.
(a) Port function
P70 to P77 and P80 to P83 are input-only pins.
(b) Alternate functions
P70 to P77 also function as ANI0 to ANI7 and P80 to P83 also function as ANI8 to ANI11.
(i) ANI0 to ANI11 (Analog input 0 to 11) ··· input
These are analog input pins for the A/D converter.
Connect a capacitor between these pins and AVSS to prevent noise-related operation faults. Also, do
not apply voltage that is outside the range for AVSS and AV
the A/D converter. If it is possible for noise above the AV
to pins that are being used as inputs for
REF
range or below the AVSS to enter, clamp
REF
these pins using a diode that has a small VF value.
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(9) P90 to P96 (Port 9) ··· 3-state I/O
P90 to P96 constitute a 7-bit I/O port that can be set to input or output pins in 1-bit units.
P90 to P96 can also function as control signal output pins and bus hold control signal output pins when memory
is expanded externally.
During 8-bit access of port 9, the highest bit is ignored during a write operation and is read as a “0” during a read
operation.
The I/O signal level uses the bus interface power supply pins BVDD
and BVSS as a reference.
(a) Port function
P90 to P96 can be set to input or output in 1-bit units using the port 9 mode register (PM9).
(b) Alternate functions (External expansion function)
P90 to P96 can be set to operate as control signal outputs for external memory expansion using the
memory expansion mode register (MM).
(i) LBEN (Lower byte enable) ··· output
This is a lower byte enable signal output pin for the external 16-bit data bus. During byte access of
odd-numbered addresses, these pins are set as inactive (high level). The output changes in
synchronization with the rising edge of the clock in the T1 state of the bus cycle. When the timing sets
the bus cycle as inactive, the previous bus cycle’s address is retained.
(ii) UBEN (Upper byte enable) ··· output
This is an upper byte enable signal output pin for the external 16-bit data bus. During byte access of
even-numbered addresses, these pins are set as inactive (high level). The output changes in
synchronization with the rising edge of the clock in the T1 state of the bus cycle. When the timing sets
the bus cycle as inactive, the previous bus cycle’s address is retained.
Access UBEN LBEN AD0
Word access 0 0 0
Halfword access 0 0 0
Byte access Even-numbered address 1 0 0
Odd-numbered address 0 1 1
(iii) R/W (Read/write status) ··· output
This is an output pin for the status signal pin that indicates whether the bus cycle is a read cycle or
write cycle during external access. High level is set during a read cycle and low level is set during a
write cycle. The output changes in synchronization with the rising edge of the clock in the T1 state of
the bus cycle. High level is set when the timing sets the bus cycle as inactive.
(iv) DSTB (Data strobe) ··· output
This is an output pin for the external data bus’s access strobe signal. Output becomes active (low
level) during the T2 and TW states of the bus cycle. Output becomes inactive (high level) when the
timing sets the bus cycle as inactive.
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CHAPTER 2 PIN FUNCTIONS
(v) ASTB (Address strobe) ··· output
This is an output pin for the external address bus’s latch strobe signal. Output becomes active (low
level) in synchronization with the falling edge of the clock during the T1 state of the bus cycle, and
becomes inactive (high level) in synchronization with the falling edge of the clock during the T3 state of
the bus cycle. Output becomes inactive when the timing sets the bus cycle as inactive.
(vi) HLDAK (Hold acknowledge) ··· output
This is an output pin for the acknowledge signal that indicates high impedance status for the address
bus, data bus, and control bus when the V850/SB1 and V850/SB2 receive a bus hold request.
The address bus, data bus, and control bus are set to high impedance status when this signal is active.
(vii) HLDRQ (Hold request) ··· input
This is an input pin by which an external device requests the V850/SB1 and V850/SB2 to release the
address bus, data bus, and control bus. This pin accepts asynchronous input for CLKOUT. When this
pin is active, the address bus, data bus, and control bus are set to high impedance status. This occurs
either when the V850/SB1 and V850/SB2 complete execution of the current bus cycle or immediately if
no bus cycle is being executed, then the HLDAK signal is set as active and the bus is released.
(viii) WRL (Write strobe low level data) ··· output
This is a write strobe signal output pin for the lower data in the external 16-bit data bus. Output occurs
during the write cycle, similar to DSTB.
(ix) WRH (Write strobe high level data) ··· output
This is a write strobe signal output pin for the higher data in the external 16-bit data bus. Output occurs
during the write cycle, similar to DSTB.
(x) RD (Read strobe) ··· output
This is a read strobe signal output pin for the external 16-bit data bus. Output occurs during the read
cycle, similar to DSTB.
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CHAPTER 2 PIN FUNCTIONS
(10) P100 to P107 (Port 10) ··· 3-state I/O
P100 to P107 constitute an 8-bit I/O port that can be set to input or output in 1-bit units.
P100 to P107 can also function as a real-time output port, an address bus (A5 to A12) when memory is
expanded externally, key return input, and IEBus data I/O (V850/SB2 only).
P100 to P107 can be selected as normal output or N-ch open-drain output.
(a) Port function
P100 to P107 can be set to input or output in 1-bit units using the port 10 mode register (PM10).
(b) Alternate functions
(i) RTP0 to RTP7 (Real-time output port 0 to 7) ··· output
These pins comprise a real-time output port.
(ii) A5 to A12 (Address bus 5 to 12) ··· output
These comprise the address bus that is used for external access. These pins operate as the A5 to A12
bit address output pins within a 22-bit address. The output changes in synchronization with the rising
edge of the clock in the T1 state of the bus cycle. When the timing sets the bus cycle as inactive, the
previous bus cycle’s address is retained.
(iii) KR0 to KR7 (Key return 0 to 7) ... input
These are key return input pins. Their operations are specified by the key return mode register (KRM).
(iv) IERX (IEBus receive data) ... input
This is an IEBus data input signal. This pin is only available in the V850/SB2.
(v) IETX (IEBus transmit data) ... output
This is an IEBus data output signal. This pin is only available in the V850/SB2.
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CHAPTER 2 PIN FUNCTIONS
(11) P110 to P113 (Port 11) ··· 3-state I/O
P110 to P113 constitute a 4-bit I/O port that can be set to input or output in 1-bit units.
P110 to P113 can also function as an address bus (A1 to A4) when memory is expanded externally, signal
(WAIT) that inserts waits into the bus cycle and a control.
(a) Port function
P110 to P113 can be set to input or output in 1-bit units using the port 11 mode register (PM11).
(b) Alternate functions
(i) A1 to A4 (Address bus 1 to 4) ··· output
These comprise the address bus that is used for external access. These pins operate as the lower 4-
bit address output pins within a 22-bit address. The output changes in synchronization with the rising
edge of the clock in the T1 state of the bus cycle. When the timing sets the bus cycle as inactive, the
previous bus cycle’s address is retained.
(ii) WAIT (Wait) ··· input
This is an input pin for the control signal used to insert waits into the bus cycle. This pin is sampled at
the falling edge of the clock during the T2 or TW state of the bus cycle.
ON/OFF switching of the wait function is performed by the port alternate function control register (PAC).
Caution Because the supply voltage to the I/O buffer of the WAIT pin is EVDD, if the voltage of
EVDD and that of BVDD differ, use EVDD as the voltage of the external wait signal,
instead of BVDD.
(12) RESET (Reset) ··· input
The RESET pin is an asynchronous input and inputs a signal that has a constant low level width regardless of
the status of the operating clock. When this signal is input, a system reset is executed as the first priority ahead
of all other operations.
In addition to being used for ordinary initialization/start operations, this pin can also be used to release a
standby mode (HALT, IDLE, or STOP mode).
(13) REGC (Regulator control) ... input
This pin is used to connect the capacitor for the regulator.
(14) CLKOUT (Clock out) … output
This pin outputs the bus clock generated internally.
(15) X1, X2 (Crystal)
These pins are used to connect the resonator that generates the main clock.
(16) XT1, XT2 (Crystal for subclock)
These pins are used to connect the resonator that generates the subclock.
(17) AVDD (Analog VDD)
This is the analog positive power supply pin for the A/D converter or alternate-function port.
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CHAPTER 2 PIN FUNCTIONS
(18) AVSS (Analog VSS)
This is the ground pin for the A/D converter or alternate-function port.
(19) AVREF (Analog reference voltage) … input
This is the reference voltage supply pin for the A/D converter.
(20) BVDD (Power supply for bus interface)
This is the positive power supply pin for the bus interface and its alternate-function ports.
(21) BVSS (Ground for bus interface)
This is the ground pin for the bus interface and its alternate-function ports.
(22) EVDD (Power supply for port)
This is the positive power supply pin for I/O ports and alternate-function pins (except for the alternate-function
ports of the bus interface).
(23) EVSS (Ground for port)
This is the ground pin for I/O ports and alternate-function pins (except for the alternate-function ports of the bus
interface).
(24) VDD (Power supply)
This is the positive power supply pin. All VDD
(25) V
SS (Ground)
This is the ground pin. All VSS
(26) V
PP (Programming power supply)
pins should be grounded.
pins should be connected to a positive power supply.
This is the positive power supply pin used for flash memory programming mode.
This pin is used in the flash memory versions. In normal operation mode, connect directly to VSS
(27) IC (Internally connected)
This is an internally connected pin used in the mask ROM versions. Be sure to connect directly to VSS.
.
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CHAPTER 2 PIN FUNCTIONS
2.4 Pin I/O Circuit Types, I/O Buffer Power Supplies and Connection of Unused Pins
(1/2)
Pin Alternate Function I/O
I/O Circuit Type Recommended Connection Method
Buffer
Power
Supply
P00 NMI
EV
DD
8-A
P01 to P04 INTP0 to INTP3
P05 INTP4/ADTRG
P06 INTP5/RTPTRG
P07 INTP6
P10 SI0/SDA0 10-A
EV
DD
P11 SO0 26
P12 SCK0/SCL0 10-A
P13 SI1/RXD0 8-A
P14 SO1/TXD0 26
P15 SCK1/ASCK0
P20 SI2/SDA1 10-A
EV
DD
10-A
P21 SO2 26
P22 SCK2/SCL1 10-A
P23 SI3/RXD1 8-A
P24 SO3/TXD1 26
P25 SCK3/ASCK1 10-A
P26, P27 TI2/TO2, TI3/TO3
P30, P31 TI00, TI01
EV
DD
8-A
8-A
P32 TI10/SI4
P33 TI11/SO4
10-A
P34 TO0/A13/SCK4
P35 TO1/A14 5-A
P36 TI4/TO4/A15
8-A
P37 TI5/TO5
P40 to P47 AD0 to AD7
BV
DD
5 Input: Independently connect to BVDD or BVSS via a resistor
P50 to P57 AD8 to AD15
P60 to P65 A16 to A21
P70 to P77 ANI0 to ANI7
AV
DD
9 Independently connect to AVDD or AVSS via a resistor
P80 to P83 ANI8 to ANI11
Input: Independently connect to EV
Output: Leave open
Output: Leave open
or EVSS via a resistor
DD
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CHAPTER 2 PIN FUNCTIONS
(2/2)
Pin Alternate Function I/O
I/O Circuit Type Recommended Connection Method
Buffer
Power
Supply
P90 LBEN/WRL
P91 UBEN
BV
DD
5 Input: Independently connect to EVDD or EVSS via a resistor
Output: Leave open
P92 R/W/WRH
P93 DSTB/RD
P94 ASTB
P95 HLDAK
P96 HLDRQ
P100 to P103 RTP0 /A5 /KR 0 t o
RTP3/A8/KR3
EV
DD
10-A
Input: Independently connect to EV
Output: Leave open
or EVSS via a resistor
DD
P104 RTP4/A9/KR4/IERX
P105 RTP5/A10/KR5/IETX
P106, P107 RT P6/ A11/KR6,
RTP7/A12/KR7
P110 A1/WAIT
EV
DD
5-A
P111 to P113 A 2 t o A 4
AV
REF
−−−Connect to AV
CLKOUT − BV
RESET − EV
DD
DD
4 Leave open
2 −
via a resistor
SS
X1 −−− −
X2 −−− −
XT1 −−16 Connect to VSS via a resistor
XT2 −−16 Leave open
Note 1
V
IC
V
AV
AV
BV
BV
EV
EV
PP
SS
Note 2
DD
SS
DD
SS
DD
SS
−−−Connect to V
−−−Connect directly to V
−−− −
−−− −
−−− −
−−− −
−−− −
−−− −
−−− −
SS
SS
Notes 1. Flash memory versions only
2. Mask ROM versions only
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2.5 Pin I/O Circuits
CHAPTER 2 PIN FUNCTIONS
(1/2)
Type 2
IN
Schmitt-triggered input with hysteresis characteristics
Type 4
V
DD
Data
Output
disable
P-ch
N-ch
OUT
Type 5-A
enable
disable
Input enable
Type 8-A
Output disable
Pullup
Data
Output
Pullup
enable
Data
V
DD
P-ch
N-ch
P-ch
N-ch
V
DD
P-ch
IN/OUT
V
DD
V
DD
P-ch
IN/OUT
Push-pull output that can be set for high impedance output
(both P-ch and N-ch off).
Type 5 Type 9
V
DD
Data
P-ch
IN/OUT
Output
N-
ch
disable
Input enable
P-ch
N-
ch
+
-
V
(threshold voltage)
REF
Input enable
Comparator
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CHAPTER 2 PIN FUNCTIONS
Type 10-A Type 26
V
DD
Pullup
enable
Data
V
P-ch
P-ch
DD
Pullup
enable
Data
V
P-ch
(2/2)
V
DD
P-ch
DD
Open drain
Output disable
Type 16
Feedback cut-off
P-ch
XT1
XT2
N-ch
IN/OUT
Open drain
Output disable
IN/OUT
N-ch
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CHAPTER 3 CPU FUNCTIONS
The CPU of the V850/SB1 and V850/SB2 is based on RISC architecture and executes most instructions in one
clock cycle by using a 5-stage pipeline.
3.1 Features
• Minimum instruction execution time V850/SB1 (A version, B version): 50 ns (@20 MHz internal operation)
V850/SB2 (A version, B version): 79 ns (@12.58 MHz internal operation)
V850/SB2 (H version): 53 ns (@18.87 MHz internal operation)
• Address space: 16 MB linear
• Thirty-two 32-bit general-purpose registers
• Internal 32-bit architecture
• Five-stage pipeline control
• Multiplication/division instructions
• Saturated operation instructions
• One-clock 32-bit shift instruction
• Load/store instruction with long/short format
• Four types of bit manipulation instructions
• SET1
•CLR1
•NOT1
•TST1
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CHAPTER 3 CPU FUNCTIONS
3.2 CPU Register Set
The CPU registers of the V850/SB1 and V850/SB2 can be classified into two categories: a general-purpose
program register set and a dedicated system register set. All the registers are 32 bits wide. For details, refer to V850
Series Architecture User’s Manual
Figure 3-1. CPU Register Set
System register setProgram register set
31 0 31 0
Zero Register
r0
Reserved for Address Register
r1
r2
Stack Pointer (SP)
r3
Global Pointer (GP)
r4
Text Pointer (TP)
r5
r6
r7
r8
r9
r10
r11
r12
r13
r14
r15
r16
r17
r18
r19
r20
r21
r22
r23
r24
r25
r26
r27
r28
r29
Element Pointer (EP)
r30
Link Pointer (LP)
r31
EIPC
EIPSW
31 0
FEPC
FEPSW
31 0
ECR Exception Cause Register
31 0
PSW Program Status Word
Exception/Interrupt PC
Exception/Interrupt PSW
Fatal Error PC
Fatal Error PSW
31 0
PC Program Counter
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CHAPTER 3 CPU FUNCTIONS
3.2.1 Program register set
The program register set includes general-purpose registers and a program counter.
(1) General-purpose registers
Thirty-two general-purpose registers, r0 to r31, are available. Any of these registers can be used as a data
variable or address variable.
However, r0 and r30 are implicitly used by instructions, and care must be exercised when using these registers.
Also, r1, r3, r4, r5, and r31 are implicitly used by the assembler and C compiler. Therefore, before using these
registers, their contents must be saved so that they are not lost. The contents must be restored to the registers
after the registers have been used.
There are cases when r2 is used by the real-time OS. If r2 is not used by the real-time OS, r2 can be used as a
variable register.
Table 3-1. Program Registers
Name Usage Operation
r0 Zero register Always holds 0
r1 Assembler-reserved register Working register for generating 32-bit immediate
r2 Address/data variable register (when r2 is not used by the real-time OS)
r3 Stack pointer Used to generate stack frame when function is called
r4 Global pointer Used to access global variable in data area
r5 Text pointer Register to indicate the start of the text area
r6 to r29 Address/data variable registers
r30 Element pointer Base pointer when memory is accessed
r31 Link pointer Used by compiler when calling function
PC Program counter Holds instruction address during program execution
Note
Note Area in which program code is mapped.
(2) Program counter (PC)
This register holds the address of the instruction under execution. The lower 24 bits of this register are valid, and
bits 31 to 24 are fixed to 0. If a carry occurs from bit 23 to 24, it is ignored.
Bit 0 is fixed to 0, and branching to an odd address cannot be performed.
After reset: 00000000H
Symbol 31 24 23 1 0
PC Fixed to 0 Instruction address under execution 0
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3.2.2 System register set
System registers control the status of the CPU and hold interrupt information.
Table 3-2. System Register Numbers
No. System Register Name Usage Operation
0EIPC
1 EIPSW
2 FEPC
3 FEPSW
4 ECR Interrupt source register If exception, maskable interrupt, or NMI occurs, this
5 PSW Program status word A program status word is a collection of flags that
6 to 31 Reserved
Interrupt status saving registers These registers save the PC and PSW when an
exception or interrupt occurs. Because only one set of
these registers is available, their contents must be
saved when multiple interrupts are enabled.
NMI status saving registers These registers save PC and PSW when NMI occurs.
register will contain information referencing the
interrupt source. The higher 16 bits of this register are
called FECC, to which exception code of NMI is set.
The lower 16 bits are called EICC, to which exception
code of exception/interrupt is set.
indicate program status (instruction execution result)
and CPU status.
To read/write these system registers, specify a system register number indicated by the system register load/store
instruction (LDSR or STSR instruction).
(1) Interrupt source register (ECR)
After reset: 00000000H
Symbol 31 16 15 0
ECR FECC EICC
FECC Exception code of NMI (For exception code, refer to
EICC Exception code of exception/interrupt
Table 5-1
.)
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(2) Program status word (PSW)
After reset: 00000020H
31 876543210
PSW RFU NP EP ID SAT CY OV S Z
RFU Reserved field (fixed to 0).
NP Non-maskable interrupt (NMI) servicing status
0 NMI servicing not under execution.
1 NMI servicing under execution.
EP Exception processing status
0 Exception processing not under execution.
1 Exception processing under execution.
CHAPTER 3 CPU FUNCTIONS
(1/2)
This flag is set (1) when an NMI is acknowledged, and disables multiple
interrupts. For details, refer to 5.2.3 NP flag.
This flag is set (1) when an exception is generated. Interrupt requests can be
acknowledged when this bit is set. For details, refer to 5.4.3 EP flag.
ID Maskable interrupt servicing specification
0 Maskable interrupt acknowledgment enabled (EI).
1 Maskable interrupt acknowledgment disabled (DI).
This flag is set (1) when a maskable interrupt request is acknowledged. For
details, refer to 5.3.6 ID flag.
Note
SAT
Saturation detection of operation result of saturation operation instruction
0 Not saturated.
This flag is not cleared (0) if the result of saturated operation instruction execution
is not saturated while this flag is set (1). To clear (0) this flag, write the PSW
directly.
1 Saturated.
CY Detection of carry or borrow of operation result
0 Carry or borrow has not occurred.
1 Carry or borrow occurred.
Note
OV
Detection of overflow during operation
0 Overflow has not occurred.
1 Overflow occurred.
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