NEC V850/SA1 mPD703015, V850/SA1 mPD70F3017Y, V850/SA1 mPD703015Y, V850/SA1 mPD70F3017 User Manual

Preliminary User’s Manual

TM

V850/SA1

32-/16-Bit Single-Chip Microcontrollers
Hardware

PD703015

µµµµ

PD703015Y

µµµµ

PD70F3017

µµµµ

PD70F3017Y

µµµµ

Document No. U12768EJ2V0UM00 (2nd edition)
Date Published June 1998 N CP(K)

Printed in Japan

1997©

[MEMO]

2

NOTES FOR CMOS DEVICES

1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static
electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental
control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid
using insulators that easily build static electricity. Semiconductor devices must be stored and
transported in an anti-static container, static shielding bag or conductive material. All test and
measurement tools including work bench and floor should be grounded. The operator should be
grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar
precautions need to be taken for PW boards with semiconductor devices on it.

2 HANDLING OF UNUSED INPUT PINS FOR CMOS

Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input
levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each
unused pin should be connected to V
possibility of being an output pin. All handling related to the unused pins must be judged device
by device and related specifications governing the devices.

DD or GND with a resistor, if it is considered to have a

3 STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until
the reset signal is received. Reset operation must be executed immediately after power-on for
devices having reset function.

V850 Family, V850/SA1 is a trademark of NEC Corporation.
Windows is either a registered trademark or a trademark of Microsoft Corporation in the United States and/or
other countries.
UNIX is a registered trademark licensed by X/Open Company Limited in the United States and other
countries.

3

Purchase of NEC I2C components conveys a license under the Philips I2C Patent Rights to use these
components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined
by Philips.

The export of these products from Japan is regulated by the Japanese government. The export of some or all of these
products may be prohibited without governmental license. To export or re-export some or all of these products from a
country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.

Licence not needed : µPD70F3017,70F3017Y
The customer must judge the need for licence : µPD703015,703015Y

The information in this document is subject to change without notice.

No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from use of a device described herein or any other liability arising
from use of such device. No license, either express, implied or otherwise, is granted under any patents,
copyrights or other intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on
a customer designated "quality assurance program" for a specific application. The recommended applications
of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each
device before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
Anti-radioactive design is not implemented in this product.

M7 96. 5

4

Regional Information

Some information contained in this document may vary from country to country. Before using any NEC
product in your application, pIease contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:

•

Device availability

•

Ordering information

•

Product release schedule

•

Availability of related technical literature

•

Development environment specifications (for example, specifications for third-party tools and

components, host computers, power plugs, AC supply voltages, and so forth)

•

Network requirements

In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.

NEC Electronics Inc. (U.S.)

Santa Clara, California
Tel: [phone]
800-366-9782
Fax: [phone]
800-729-9288

NEC Electronics (Germany) GmbH

Duesseldorf, Germany
Tel: [phone]
Fax: [phone]

NEC Electronics (UK) Ltd.

Milton Keynes, UK
Tel: [phone]
Fax: [phone]

NEC Electronics Italiana s.r.1.

Milano, Italy
Tel: [phone]
Fax: [phone]

NEC Electronics (Germany) GmbH

Benelux Office
Eindhoven, The Netherlands
Tel: [phone]
Fax: [phone]

NEC Electronics (France) S.A.

Velizy-Villacoublay, France
Tel: [phone]
Fax: [phone]

NEC Electronics (France) S.A.

Spain Office
Madrid, Spain
Tel: [phone]
Fax: [phone]

NEC Electronics (Germany) GmbH

Scandinavia Office
Taeby, Sweden
Tel: [phone]
Fax: [phone]

NEC Electronics Hong Kong Ltd.

Hong Kong
Tel: [phone]
Fax: [phone]

NEC Electronics Hong Kong Ltd.

Seoul Branch
Seoul, Korea
Tel: [phone]
Fax: [phone]

NEC Electronics Singapore Pte. Ltd.

United Square, Singapore 1130
Tel: [phone]
Fax: [phone]

NEC Electronics Taiwan Ltd.

Taipei, Taiwan
Tel: [phone]
Fax: [phone]

NEC do Brasil S.A.

Cumbica-Guarulhos-SP, Brasil
Tel: [phone]
Fax: [phone]

J98. 2

5

Major Revisions in This Edition

p.23 121-pin fine pitch BGA has been added to
p.24 121-pin fine pitch BGA has been added to
p.57 The explanation of EP bit has been modified in
p.71 The description has been modified in

.

(MAM)

p.75
p.80
p.90
p.102
p.148, 149

p.152

p.153

p.155

p.156
p.157
p.160

p.162
p.164 TIn0 has been modified in

p.164

p.166

p.167

p.198 The description has been changed in
p.222
p.223

p.266 The explanation has been modified in
p.269
p.303
p.308
p.314
p.359, 362, 366 Erase/write voltage has been changed to VPP = 7.8 V

3.4.8 Peripheral I/O registers
Caution
Note
Note
Caution

(3) Capture/compare register n1 (CR01, CR11)
Caution

0, 1 (TMC0, TMC1)
Caution

1 (CRC0, CRC1)
Note

(TOC0, TOC1)
Caution

Figure 7-5 Format of Prescaler Mode Register 0 (PRM0)
Figure 7-6 Format of Prescaler Mode Register 1 (PRM1)
Figure 7-10 Control register Settings in PPG Output Operation

Figure 7-13

Specified

The following figures have been modified.

Figure 7-16 Timing of Pulse Width Measurement with Free Running Counter (with
both edges specified)
Figure 7-18 Timing of Pulse Width Measurement with Free Running Counter and Two
Capture Registers (with rising edge specified)
Figure 7-20 Timing of Pulse Width Measurement by Restarting (with rising edge
specified)

Caution
Figure 10-9 Format of IIC Control Register (IICC0)

been added to this figure.

Figure 10-23 Communication Reservation Flow Chart
Caution
Caution

11.5 (9) Reading A/D conversion result register (ADCR)

has been added to
has been added to
has been added to

has been added to

has been modified in

.

has been added to

.

has been added to

has been added to the following figures:

has been modified.

.

has been added to

has been added to
has been added to

has been modified.

3.4.9 Specific registers

4.7.1 Outline of function
Table 5-1 Interrupt Source List

7.1.3 (2) Capture/compare register n0 (CR00, CR10)

Figure 7-2 Format of 16-Bit Timer Mode Control Register

Figure 7-3 Format of Capture/Compare Control Register 0,

Figure 7-4 Format of 16-Bit Timer Output Control Register 0, 1

Figure 7-15 CRn1 Capture Operation with Rising Edge

10.3.2 (1) IIC control register (IICC0)

11.2 (2) A/D conversion result register (ADCR)

11.4.1 Basic operation

1.4 Ordering Information

1.5 Pin Configuration (Top View)

3.2.2 (2) Program status word (PSW)

3.4.6 (2) memory address output mode register

.

8.4.1 Operation as watch timer.

10.3.12 Communication reservation

has been added to this section.

Note

.

.

.

.

has been modified and

has been modified.

.

has been added.

.

Remark

.

.

.

and

has

The mark shows major revised points.

6

INTRODUCTION

Readers

This manual is intended for users who wish to understand the functions of the V850/SA1 (µPD703015,
703015Y, 70F3017, 70F3017Y) and design applicati on systems using these products.

Purpose

This manual is intended to help users understand the hardware functions described following the
organization below.

Organization

The V850/SA1 user’s manual is divided into two parts: hardware (this manual) and architecture
(V850 Family User’s Manual Architecture).

Hardware Architecture

•

Pin function

•

CPU function

•

Internal peripheral function

•

Flash memory programming mode

How to Read This Manual

To find the details of a register whose name is known:

Refer to

→

•

Data type

•

Register set

•

Instruction format and instruction set

•

Interrupt and exception

•

Pipeline operation

The manual assumes that the reader has general knowledge of electricity, logical
circuits and microcontrollers.

APPENDIX A REGISTER INDEX

.

Legend

To find the details of a function, etc. whose name is known:

Refer to

→

APPENDIX C INDEX

.

To understand the details of instruction functions:

Refer to

→

V850 Family User’s Manual Architecture

To understand the overall functions of the V850/SA1:

Read this manual according to the Table of Contents.

→

Data significance: Higher digits on the left and lower digits on the right
Active low : xxx (overscore over pin or signal name)
Memory map address :Top: highest, bottom: lowest

Note
Caution
Remark

: Footnote for item marked with
: Information requiring particular information
: Supplementary information

Note

in the text

Number representation : Binary … xxxxB or xxxx

Decimal number … xxxx
Hexadecimal … xxxxH

Prefixes indicating power of 2 (address space, memory capacity):

K (kilo) : 2
M (mega) : 220=1024
G (giga) : 230=1024

10

=1024

2

3

7

Related documents

The related documents indicted in this publication may included preliminary versions.
However, preliminary versions are not marked as such.

Related documents for V850/SA1

Document Name Document No.
V850 Family Architec ture User’s Manual U10243E
V850 Family Instructi on Tabl e U10229E

µ

PD703015 Data Sheet To be prepared

µ

PD703015Y Data Sheet To be prepared

µ

PD703017 Data Sheet To be prepared

µ

PD70F3017Y Data Sheet To be prepared

V850/SA1 Hardware User’s Manual This manual

Related documents for development tool (user’s manual)

Document Name Document No.
IE-703002-MC (In-circuit em ul ator) U11595E
IE-703017-MC-EM1 (In-circui t emulator option board) U12898E
CA850 (C compiler package) Operation (UNIX based) U11013E

Operation (Windows based) U11068E
Assembly Language U10543E
C Language U11010E
Project Manager U11991E

ID850 (C source debugger) Operation (UNIX based) U12209E

Operation (Windows based) U11196E
Installation (UNIX based) U12210E

RX850 (Real Time OS) Fundamental U11037E

Technical U11117E
Nucleus Installati on U11038E
Debugger (Windows based) U11158E

AZ850 (System Perform ance Analyzer) Operation U11181E

8

CONTENTS

CHAPTER 1 INTRODUCTION............................................................................................................. 21

1.1 General.................................................................................................................................................. 21

1.2 Features ................................................................................................................................................ 21

1.3 Application Fields ................................................................................................................................ 23

1.4 Ordering Information ........................................................................................................................... 23

1.5 Pin Configuration (Top View).............................................................................................................. 24

1.6 Function Blocks ................................................................................................................................... 27

1.6.1 Internal Block Diagram................................................................................................................ 27

1.6.2 On-chip units............................................................................................................................... 28

CHAPTER 2 PIN FUNCTIONS............................................................................................................ 31

2.1 List of Pin Functions............................................................................................................................ 31

2.2 Pin States.............................................................................................................................................. 37

2.3 Description of Pin Functions .............................................................................................................. 38

2.4 Pins’ I/O Circuit Types and Handling When Not Used...................................................................... 49

2.5 Pins’ I/O Circuits .................................................................................................................................. 51

CHAPTER 3 CPU FUNCTIONS........................................................................................................... 53

3.1 Features ................................................................................................................................................ 53

3.2 CPU Register Set.................................................................................................................................. 54

3.2.1 Program register set.................................................................................................................... 55

3.2.2 System register set ..................................................................................................................... 56

3.3 Operation Modes.................................................................................................................................. 58

3.4 Address Space ..................................................................................................................................... 59

3.4.1 CPU address space.................................................................................................................... 59

3.4.2 Image (virtual address space)..................................................................................................... 60

3.4.3 Wrap-around of CPU address space.......................................................................................... 61

3.4.4 Memory map............................................................................................................................... 62

3.4.5 Area............................................................................................................................................. 63

3.4.6 External expansion mode............................................................................................................ 69

3.4.7 Recommended use of address space......................................................................................... 72

3.4.8 Peripheral I/O registers............................................................................................................... 75

3.4.9 Specific registers........................................................................................................................ 80

CHAPTER 4 BUS CONTROL FUNCTION ......................................................................................... 83

4.1 Features ................................................................................................................................................ 83

4.2 Bus Control Pins and Control Register.............................................................................................. 83

4.2.1 Bus control pins........................................................................................................................... 83

4.2.2 Control register............................................................................................................................ 84

4.3 Bus Access........................................................................................................................................... 84

4.3.1 Number of access clocks............................................................................................................ 84

9

4.3.2 Bus width..................................................................................................................................... 85

4.4 Memory Block Function....................................................................................................................... 86

4.5 Wait Function........................................................................................................................................ 87

4.5.1 Programmable wait function........................................................................................................ 87

4.5.2 External wait function.................................................................................................................. 88

4.5.3 Relations between programmable wait and external wait........................................................... 88

4.6 Idle State Insertion Function ............................................................................................................... 89

4.7 Bus Hold Function................................................................................................................................ 90

4.7.1 Outline of function ....................................................................................................................... 90

4.7.2 Bus hold procedure..................................................................................................................... 91

4.7.3 Operation in power save mode ................................................................................................... 91

4.8 Bus Timing............................................................................................................................................ 92

4.9 Bus Priority ........................................................................................................................................... 99

4.10 Memory Boundary Operation Condition ............................................................................................ 99

4.10.1 Program space.......................................................................................................................... 99

4.10.2 Data space................................................................................................................................ 99

CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION................................................. 101

5.1 Features ................................................................................................................................................ 101

5.2 Non-Maskable Interrupt ....................................................................................................................... 104

5.2.1 Accepting operation..................................................................................................................... 105

5.2.2 Restore........................................................................................................................................ 107

5.2.3 NP flag......................................................................................................................................... 108

5.2.4 Noise elimination circuit of NMI pin............................................................................................. 108

5.2.5 Edge detection function of NMI pin ............................................................................................. 109

5.3 Maskable Interrupts.............................................................................................................................. 110

5.3.1 Operation..................................................................................................................................... 110

5.3.2 Restore........................................................................................................................................ 112

5.3.3 Priorities of maskable interrupts.................................................................................................. 113

5.3.4 Interrupt control register (xxICn).................................................................................................. 117

5.3.5 In-service priority register (ISPR)................................................................................................ 119

5.3.6 Maskable interrupt status flag ..................................................................................................... 119

5.3.7 Watchdog timer mode register (WDTM)...................................................................................... 120

5.3.8 Noise elimination......................................................................................................................... 120

5.3.9 Edge detection function............................................................................................................... 121

5.4 Software Exception .............................................................................................................................. 122

5.4.1 Operation..................................................................................................................................... 122

5.4.2 Restore........................................................................................................................................ 123

5.4.3 EP flag......................................................................................................................................... 124

5.5 Exception Trap ..................................................................................................................................... 124

5.5.1 Illegal op code definition.............................................................................................................. 124

5.5.2 Operation..................................................................................................................................... 124

5.5.3 Restore........................................................................................................................................ 125

5.6 Priority Control ..................................................................................................................................... 127

5.6.1 Priorities of interrupts and exceptions......................................................................................... 127

5.6.2 Multiple interrupt processing ....................................................................................................... 127

5.7 Interrupt Latency Time......................................................................................................................... 130

10

5.8 Periods Where Interrupt is Not Acknowledged ................................................................................. 130

CHAPTER 6 CLOCK GENERATION FUNCTION............................................................................. 131

6.1 General.................................................................................................................................................. 131

6.2 Composition ......................................................................................................................................... 131

6.3 Clock Output Function......................................................................................................................... 132

6.3.1 Control registers.......................................................................................................................... 132

6.4 Power Saving Functions...................................................................................................................... 135

6.4.1 General ....................................................................................................................................... 135

6.4.2 HALT mode................................................................................................................................. 136

6.4.3 IDLE mode.................................................................................................................................. 139

6.4.4 Software STOP mode ................................................................................................................. 141

6.5 Oscillation Stabilization Time ............................................................................................................. 142

CHAPTER 7 TIMER/COUNTER FUNCTION...................................................................................... 145

7.1 16-bit Timer (TM0, TM1) ....................................................................................................................... 145

7.1.1 Overview..................................................................................................................................... 145

7.1.2 Function ...................................................................................................................................... 145

7.1.3 Configuration............................................................................................................................... 147

7.1.4 Timer 0, 1 Control Register......................................................................................................... 150

7.2 Operation .............................................................................................................................................. 158

7.2.1 Operation as interval timer (16 bits)............................................................................................ 158

7.2.2 PPG output operation.................................................................................................................. 160

7.2.3 Pulse width measurement........................................................................................................... 161

7.2.4 Operation as external event counter........................................................................................... 168

7.2.5 Operation to output square wave................................................................................................ 169

7.2.6 Operation to output one-shot pulse............................................................................................. 171

7.2.7 Cautions...................................................................................................................................... 175

7.3 8-bit Timer (TM2-TM5).......................................................................................................................... 178

7.3.1 Functions..................................................................................................................................... 178

7.3.2 Configuration............................................................................................................................... 179

7.3.3 Timer n control register............................................................................................................... 181

7.4 Operation .............................................................................................................................................. 185

7.4.1 Operating as an interval timer (8-bit operation)........................................................................... 185

7.4.2 Operating as external event counter........................................................................................... 187

7.4.3 Operating as square wave output (8-bit resolution).................................................................... 188

7.4.4 Operating as 8-bit PWM output................................................................................................... 189

7.4.5 Cautions...................................................................................................................................... 194

CHAPTER 8 WATCH TIMER.............................................................................................................. 195

8.1 Function................................................................................................................................................ 195

8.2 Configuration........................................................................................................................................ 196

8.3 Watch Timer Control Register............................................................................................................. 197

8.4 Operation .............................................................................................................................................. 198

8.4.1 Operation as watch timer............................................................................................................ 198

11

8.4.2 Operation as interval timer.......................................................................................................... 199

CHAPTER 9 WATCHDOG TIMER...................................................................................................... 201

9.1 Functions .............................................................................................................................................. 201

9.2 Configuration........................................................................................................................................ 203

9.3 Watchdog Timer Control Register ...................................................................................................... 203

9.4 Operation .............................................................................................................................................. 206

9.4.1 Operating as watchdog timer ...................................................................................................... 206

9.4.2 Operating as interval timer.......................................................................................................... 207

9.5 Standby Function Control Register .................................................................................................... 208

CHAPTER 10 SERIAL INTERFACE FUNCTION .............................................................................. 209

10.1 Overview ............................................................................................................................................... 209

10.2 3-wire Serial I/O (CSI0-CSI2)................................................................................................................ 209

10.2.1 Configuration............................................................................................................................. 210

10.2.2 CSIn control registers................................................................................................................ 211

10.2.3 Operations................................................................................................................................. 213

10.3 I2C Bus (

10.3.1 Configuration............................................................................................................................. 220

10.3.2 I

10.3.3 I2C bus mode functions.............................................................................................................. 232

10.3.4 I2C bus definitions and control methods.................................................................................... 233

10.3.5 I2C interrupt requests (INTIIC0)................................................................................................. 240

10.3.6 Interrupt request (INTIIC0) generation timing and wait control.................................................. 260

10.3.7 Address match detection method.............................................................................................. 261

10.3.8 Error detection........................................................................................................................... 262

10.3.9 Extension code.......................................................................................................................... 262

10.3.10 Arbitration................................................................................................................................ 263

10.3.11 Wake up function..................................................................................................................... 265

10.3.12 Communication reservation..................................................................................................... 266

10.3.13 Other cautions......................................................................................................................... 270

10.3.14 Communication operations...................................................................................................... 271

10.3.15 Timing of data communication ................................................................................................ 273

10.4 Asynchronous Serial Interface (UART0, UART1) .............................................................................. 280

10.4.1 Configuration............................................................................................................................. 280

10.4.2 UARTn control registers............................................................................................................ 282

10.4.3 Operations................................................................................................................................. 287

10.4.4 Asynchronous serial interface (UARTn) mode.......................................................................... 288

10.4.5 Standby function........................................................................................................................ 300

µµµµ

PD703015Y, 70F3017Y)........................................................................................................ 217

2

C control register..................................................................................................................... 222

CHAPTER 11 A/D CONVERTER........................................................................................................ 301

11.1 Function ................................................................................................................................................ 301

11.2 Configuration........................................................................................................................................ 303

11.3 Control Registers ................................................................................................................................ 305

11.4 Operation .............................................................................................................................................. 308

12

11.4.1 Basic operation ......................................................................................................................... 308

11.4.2 Input voltage and conversion result .......................................................................................... 310

11.4.3 A/D converter operation mode.................................................................................................. 311

11.5 Notes on Using A/D Converter............................................................................................................ 314

CHAPTER 12 DMA FUNCTIONS ....................................................................................................... 317

12.1 Functions.............................................................................................................................................. 317

12.2 Transfer Completion Interrupt Request............................................................................................. 317

12.3 Control Registers................................................................................................................................. 317

CHAPTER 13 REAL-TIME OUTPUT FUNCTION (RTO) ................................................................. 321

13.1 Function................................................................................................................................................ 321

13.2 Configuration........................................................................................................................................ 322

13.3 RTO Control Registers......................................................................................................................... 323

13.4 Operation.............................................................................................................................................. 326

13.5 Usage .................................................................................................................................................... 327

13.6 Notes..................................................................................................................................................... 327

CHAPTER 14 PORT FUNCTION........................................................................................................ 329

14.1 Port Configuration................................................................................................................................ 329

14.2 Port Pin Function ................................................................................................................................. 329

14.2.1 Port 0......................................................................................................................................... 329

14.2.2 Port 1......................................................................................................................................... 333

14.2.3 Port 2......................................................................................................................................... 336

14.2.4 Port 3......................................................................................................................................... 339

14.2.5 Ports 4 and 5............................................................................................................................. 341

14.2.6 Port 6......................................................................................................................................... 343

14.2.7 Ports 7 and 8............................................................................................................................. 345

14.2.8 Port 9......................................................................................................................................... 346

14.2.9 Port 10....................................................................................................................................... 348

14.2.10 Port 11..................................................................................................................................... 350

14.2.11 Port 12..................................................................................................................................... 353

CHAPTER 15 RESET FUNCTION...................................................................................................... 357

15.1 General.................................................................................................................................................. 357

15.2 Pin Operations...................................................................................................................................... 357

CHAPTER 16 FLASH MEMORY (

µµµµ

PD70F3017, 70F3017Y)........................................................... 359

16.1 Features................................................................................................................................................ 359

16.2 Writing by Flash Writer........................................................................................................................ 359

16.3 Programming Environment................................................................................................................. 360

16.4 Communication System ...................................................................................................................... 360

16.5 Pin Connection..................................................................................................................................... 362

13

16.5.1 VPP pin....................................................................................................................................... 362

16.5.2 Serial interface pin..................................................................................................................... 362

16.5.3 RESET pin................................................................................................................................. 364

16.5.4 Port pin...................................................................................................................................... 364

16.5.5 Other signal pins ....................................................................................................................... 364

16.5.6 Power supply............................................................................................................................. 364

16.6 Programming Method .......................................................................................................................... 365

16.6.1 Flash memory control................................................................................................................ 365

16.6.2 Flash memory programming mode............................................................................................ 365

16.6.3 Selection of communication mode ............................................................................................ 366

16.6.4 Communication command......................................................................................................... 366

16.6.5 Resources used ........................................................................................................................ 367

APPENDIX A REGISTER INDEX........................................................................................................ 369

APPENDIX B LIST OF INSTRUTION SET ........................................................................................ 375

APPENDIX C INDEX ............................................................................................................................ 383

14

LIST OF FIGURES (1/5)

Fig. No. Title Page

3-1 CPU Address Space............................................................................................................................... 59

3-2 Image on Address Space ....................................................................................................................... 60

3-3 Memory Map........................................................................................................................................... 62

3-4 Internal ROM Area (with Mask ROM Internal Version)...........................................................................63

3-5 External Memory Area (when expanded to 64 K, 256 K, or 1 Mbytes)................................................... 67

3-6 External Memory Area (when expanded to 4 Mbytes)............................................................................ 68

3-7 Memory Expansion Mode Register (MM) Format...................................................................................70

3-8 Memory Address Output Mode Register (MAM) Format ........................................................................ 71

3-9 Recommended Memory Map (Flash Memory Internal Version)............................................................. 74

4-1 Example of Inserting Wait States............................................................................................................ 88

5-1 Non-Maskable Interrupt Processing ....................................................................................................... 105

5-2 Accepting Non-Maskable Interrupt Request........................................................................................... 106

5-3 RETI Instruction Processing................................................................................................................... 107

5-4 Rising Edge Specification Register (EGP0) Format............................................................................... 109

5-5 Falling Edge Specification Register (EGN0) Format .............................................................................. 109

5-6 Maskable Interrupt Processing............................................................................................................... 111

5-7 RETI Instruction Processing................................................................................................................... 112

5-8 Example of Interrupt Nesting Process.................................................................................................... 114

5-9 Example of Processing Interrupt Requests Simultaneously Generated................................................. 116

5-10 Interrupt Control Register (xxICn) Format .............................................................................................. 117

5-11 Inservice Priority Register (ISPR) Format............................................................................................... 119

5-12 Watchdog Timer Mode Register (WDTM) Format.................................................................................. 120

5-13 Software Exception Processing.............................................................................................................. 122

5-14 RETI Instruction Processing ................................................................................................................... 123

5-15 Exception Trap Processing..................................................................................................................... 125

5-16 RETI Instruction Processing ................................................................................................................... 126

5-17 Pipeline Operation at Interrupt Request Acknowledge........................................................................... 130

6-1 Format of Processor Clock Control Register (PCC)............................................................................... 132

6-2 Format of Power Saving Control Register (PSC).................................................................................... 134

6-3 Format of Oscillation Stabilization Time Select Register (OSTS)........................................................... 135

7-1 Block Diagram of TM0 and TM1............................................................................................................. 146

7-2 Format of 16-Bit Timer Mode Control Register 0, 1 (TMC0, TMC1)....................................................... 151

7-3 Format of Capture/Compare Control Register 0, 1 (CRC0, CRC1)........................................................ 153

7-4 Format of 16-Bit Timer Output Control Register 0, 1 (TOC0, TOC1)...................................................... 155

7-5 Format of Prescaler Mode Register 0 (PRM0)........................................................................................ 156

7-6 Format of Prescaler Mode Register 1 (PRM1)........................................................................................ 157

7-7 Control Register Settings When Timer 0 Operates as Interval Timer..................................................... 158

7-8 Configuration of Interval Timer ............................................................................................................... 159

7-9 Timing of Interval Timer Operation......................................................................................................... 159

7-10 Control Register Settings in PPG Output Operation............................................................................... 160

15

LIST OF FIGURES (2/5)

Fig. No. Title Page

7-11 Control Register Settings for Pulse Width Measurement with

Free Running Counter and One Capture Register ................................................................................ 161

7-12 Configuration for Pulse Width Measurement with Free Running Counter ............................................. 162

7-13 Timing of Pulse Width Measurement with Free Running Counter and

One Capture Register (with both edges specified)................................................................................ 162

7-14 Control Register Settings for Measurement of Two Pulse Widths with Free Running Counter ............. 163

7-15 CRn1 Capture Operation with Rising Edge Specified............................................................................ 164

7-16 Timing of Pulse Width Measurement with Free Running Counter (with both edges specified) ............. 164

7-17 Control Register Settings for Pulse Width Measurement

with Free Running Counter and Two Capture Registers ....................................................................... 165

7-18 Timing of Pulse Width Measurement with Free Running Counter and

Two Capture Registers (with rising edge specified)............................................................................... 166

7-19 Control Register Settings for Pulse Width Measurement by Restarting ................................................ 167

7-20 Timing of Pulse Width Measurement by Restarting (with rising edge specified) ................................... 167

7-21 Control Register Settings in External Event Counter Mode................................................................... 168

7-22 Configuration of External Event Counter ............................................................................................... 169

7-23 Timing of External Event Counter Operation (with rising edge specified).............................................. 169

7-24 Control Register Settings in Square Wave Output Mode....................................................................... 170

7-25 Timing of Square Wave Output Operation............................................................................................. 171

7-26 Control Register Settings for One-Shot Pulse Output with Software Trigger......................................... 172

7-27 Timing of One-Shot Pulse Output Operation with Software Trigger ...................................................... 173

7-28 Control Register Settings for One-Shot Pulse Output with External Trigger.......................................... 174

7-29 Timing of One-Shot Pulse Output Operation with External Trigger (with rising edge specified)............ 175

7-30 Start Timing of 16-Bit Timer Register n.................................................................................................. 175

7-31 Timing after Changing Compare Register during Timer Count Operation............................................. 176

7-32 Data Hold Timing of Capture Register................................................................................................... 176

7-33 Operation Timing of OVFn Flag............................................................................................................. 177

7-34 Block Diagram of TM2-TM5................................................................................................................... 179

7-35 Format of TM2, TM3 Timer Clock Selection Register 2 and 3 (TCL2, TCL3)........................................ 181

7-36 Format of TM4, TM5 Timer Clock Selection Register 4 and 5 (TCL4, TCL5)........................................ 182

7-37 Format of 8-Bit Timer Mode Control Register 2-5 (TMC2-TMC5).......................................................... 183

7-38 Timing of Interval Timer Operation ........................................................................................................ 185

7-39 Timing of External Event Counter Operation (when rising edge is set) ................................................. 188

7-40 Timing of PWM Output........................................................................................................................... 190

7-41 Timing of Operation Based on CRn0 Transitions .................................................................................. 191

7-42 Cascade Connection Mode with 16-Bit Resolution................................................................................ 193

7-43 Start Timing of Timer n .......................................................................................................................... 194

7-44 Timing After Compare Register Changes During Timer Counting......................................................... 194

8-1 Block Diagram of Watch Timer.............................................................................................................. 195

8-2 Format of Watch Timer Mode Control Register (WTM) ......................................................................... 197

8-3 Operation Timing of Watch Timer/Interval Timer................................................................................... 199

9-1 Block Diagram of Watchdog Timer........................................................................................................ 201

16

LIST OF FIGURES (3/5)

Fig. No. Title Page

9-2 Format of Oscillation Stabilization Time Selection Register (OSTS)...................................................... 203

9-3 Format of Watchdog Timer Clock Selection Register (WDCS)............................................................... 204

9-4 Format of Watchdog Timer Mode Register (WDTM).............................................................................. 205

9-5 Format of Oscillation Stabilization Time Selection Register (OSTS)...................................................... 208

10-1 Block Diagram of 3-wire Serial I/O.......................................................................................................... 210

10-2 Format of Serial Operation Mode Register 0-2 (CSIM0-CSIM2) ............................................................ 211

10-3 Format of Serial Clock Selection Registers 0-2 (CSIS0-CSIS2)............................................................. 212

10-4 Format of Serial Operation Mode Register 0-2 (CSIM0-CSIM2) ............................................................ 213

10-5 Format of Serial Operation Mode Registers 0-2 (CSIM0-CSIM2)........................................................... 214

10-6 Timing of 3-wire Serial I/O Mode ............................................................................................................ 215

10-7 Block Diagram of I2C............................................................................................................................... 218

10-8 Serial Bus Configuration Example Using I2C Bus................................................................................... 219

10-9 Format of IIC Control Register (IICC0) ................................................................................................... 223

10-10 Format of IIC Status Register (IICS0)..................................................................................................... 227

10-11 Format of IIC Clock Select Register (IICCL0)......................................................................................... 230

10-12 Pin Configuration Diagram...................................................................................................................... 232

10-13 I2C Bus’s Serial Data Transfer Timing .................................................................................................... 233

10-14 Start Conditions ...................................................................................................................................... 233

10-15 Address .................................................................................................................................................. 234

10-16 Transfer Direction Specification.............................................................................................................. 235

10-17 ACK Signal ............................................................................................................................................. 236

10-18 Stop Condition ........................................................................................................................................ 237

10-19 Wait Signal ............................................................................................................................................. 238

10-20 Arbitration Timing Example..................................................................................................................... 264

10-21 Communication Reservation Timing....................................................................................................... 267

10-22 Timing for Accepting Communication Reservations............................................................................... 268

10-23 Communication Reservation Flow Chart ................................................................................................ 269

10-24 Master Operation Flow Chart.................................................................................................................. 271

10-25 Slave Operation Flow Chart.................................................................................................................... 272

10-26 Example of Master to Slave Communication

(when 9-clock Wait Is Selected for Both Master and Slave)................................................................... 274

10-27 Example of Slave to Master Communication

(when 9-clock Wait Is Selected for Both Master and Slave)................................................................... 277

10-28 Block Diagram of UARTn........................................................................................................................ 281

10-29 Format of Asynchronous Serial Interface Mode Register 0, 1 (ASIM0, ASIM1)..................................... 283

10-30 Format of Asynchronous Serial Interface Status Registers 0, 1 (ASIS0, ASIS1) ................................... 284

10-31 Format of Baud Rate Generator Control Registers 0, 1 (BRGC0, BRGC1)............................................ 285

10-32 Format of Baud Rate Generator Mode Control Registers 0, 1 (BRGMC0, BRGMC1)............................ 286

10-33 Error Tolerance (when k = 0), including Sampling Errors....................................................................... 294

10-34 Format of Transmit/Receive Data in Asynchronous Serial Interface...................................................... 295

10-35 Timing of Asynchronous Serial Interface Transmit Completion Interrupt ............................................... 297

10-36 Timing of Asynchronous Serial Interface Receive Completion Interrupt ................................................ 298

10-37 Receive Error Timing.............................................................................................................................. 299

17

LIST OF FIGURES (4/5)

Fig. No. Title Page

11-1 Block Diagram of A/D Converter............................................................................................................ 302

11-2 Format of A/D Converter Mode Register (ADM) .................................................................................... 305

11-3 Format of Analog Input Channel Specification Register (ADS) ............................................................. 307

11-4 Basic Operation of A/D Converter.......................................................................................................... 309

11-5 Relation between Analog Input Voltage and A/D Conversion Result .................................................... 310

11-6 A/D Conversion by Hardware Start (with falling edge specified) ........................................................... 312

11-7 A/D Conversion by Software Start ......................................................................................................... 313

11-8 Processing of Analog Input Pin.............................................................................................................. 315

11-9 A/D Conversion End Interrupt Generation Timing ................................................................................. 316

11-10 Processing of AVDD Pin........................................................................................................................ 316

12-1 Format of DMA Peripheral I/O Address Registers 0 to 2 (DIOA0 to DIOA2) ......................................... 317

12-2 Format of DMA On-chip RAM Address Registers 0 to 2 (DRA0 to DRA2) ............................................ 318

12-3 Format of DMA Byte Count Registers 0 to 2 (DBC0 to DBC2) .............................................................. 318

12-4 Format of DMA Channel Control Registers 0 to 2 (DCHC0 to DCHC2)................................................. 319

13-1 Block Diagram of RTO........................................................................................................................... 321

13-2 Configuration of Real-Time Output Buffer Registers ............................................................................. 322

13-3 Format of Real-Time Output Port Mode Register (RTPM)..................................................................... 324

13-4 Format of Real-Time Output Port Control Register (RTPC)................................................................... 325

13-5 Example of Operation Timing of RTO (when EXTR = 0, BYTE = 0)...................................................... 326

14-1 Format of Port 0 (P0) ............................................................................................................................. 329

14-2 Format of Port 0 Mode Register (PM0).................................................................................................. 331

14-3 Format of Pull-up Resistance Option Register 0 (PU0) ......................................................................... 331

14-4 Format of Rising Edge Enable Register (EGP0).................................................................................... 332

14-5 Format of Falling Edge Enable Register (EGN0)................................................................................... 332

14-6 Format of Port 1 (P1) ............................................................................................................................. 333

14-7 Format of Port 1 Mode Register (PM1).................................................................................................. 334

14-8 Format of Pull-up Resistance Option Register 1 (PU1) ......................................................................... 335

14-9 Format of Port 1 Function Register (PF1).............................................................................................. 335

14-10 Format of Port 2 (P2) ............................................................................................................................. 336

14-11 Format of Port 2 Mode Register (PM2).................................................................................................. 337

14-12 Format of Pull-up Resistance Option Register 2 (PU2) ......................................................................... 338

14-13 Format of Port 2 Function Register (PF2).............................................................................................. 338

14-14 Format of Port 3 (P3) ............................................................................................................................. 339

14-15 Format of Port 3 Mode Register (PM3).................................................................................................. 340

14-16 Format of Pull-up Resistance Option Register 3 (PU3) ......................................................................... 341

14-17 Format of Ports 4 and 5 (P4 and P5)..................................................................................................... 341

14-18 Format of Port 4 Mode Register, Port 5 Mode Register (PM4, PM5)..................................................... 343

14-19 Format of Port 6 (P6) ............................................................................................................................. 343

14-20 Format of Port 6 Mode Register (PM6).................................................................................................. 344

14-21 Format of Ports 7 and 8 (P7 and P8)..................................................................................................... 345

14-22 Format of Port 9 (P9) ............................................................................................................................. 346

18

LIST OF FIGURES (5/5)

Fig. No. Title Page

14-23 Format of Port 9 Mode Register (PM9)................................................................................................... 347

14-24 Format of Port 10 (P10).......................................................................................................................... 348

14-25 Format of Port 10 Mode Register (PM10)............................................................................................... 349

14-26 Format of Pull-up Resistance Option Register 10 (PU10)...................................................................... 350

14-27 Format of Port 10 Function Register (PF10) ........................................................................................... 350

14-28 Format of Port 11 (P11).......................................................................................................................... 351

14-29 Format of Port 11 Mode Register (PM11)............................................................................................... 352

14-30 Format of Pull-up Resistance Option Register 11 (PU11)...................................................................... 352

14-31 Format of Port 12 (P12).......................................................................................................................... 353

14-32 Format of Port 12 Mode Register (PM12)............................................................................................... 354

14-33 Format of Port 12 Mode Control Register (PMC12)................................................................................ 355

15-1 System Reset Timing.............................................................................................................................. 357

19

LIST OF TABLES

Table. No. Title Page

3-1 Program Registers................................................................................................................................. 55

3-2 System Register Numbers..................................................................................................................... 56

3-3 Interrupt/Exception Table....................................................................................................................... 64

4-1 Bus Priority............................................................................................................................................. 99

5-1 Interrupt Source List............................................................................................................................... 102

6-1 Operating Statuses during HALT Mode................................................................................................. 137

6-2 Operating Statuses during IDLE Mode.................................................................................................. 139

6-3 Operating States during Software STOP Mode..................................................................................... 141

7-1 Configuration of Timer 0 ........................................................................................................................ 147

7-2 Valid Edge of TIn0 Pin and Capture Trigger of CRn0............................................................................ 148

7-3 Valid Edge of TIn1 Pin and Capture Trigger of CRn0............................................................................ 148

7-4 Timer 2-5 Configuration......................................................................................................................... 179

8-1 Interval Time of Interval Timer............................................................................................................... 196

8-2 Configuration of Watch Timer................................................................................................................ 196

8-3 Interval Time of Interval Timer............................................................................................................... 199

9-1 Runaway Detection Time for Watchdog Timer...................................................................................... 202

9-2 Interval Time.......................................................................................................................................... 202

9-3 Watchdog Timer Configuration.............................................................................................................. 203

9-4 Runaway Detection Time of Watchdog Timer ....................................................................................... 206

9-5 Interval Time of Interval Timer............................................................................................................... 207

10-1 Configuration of CSIn............................................................................................................................. 210

10-2 Configuration of I2C................................................................................................................................ 220

10-3 INTIIC0 Timing and Wait Control........................................................................................................... 260

10-4 Extension Code Bit Definitions............................................................................................................... 262

10-5 Status during Arbitration and Interrupt Request Generation Timing...................................................... 264

10-6 Wait Periods........................................................................................................................................... 266

10-7 Configuration of UARTn......................................................................................................................... 280

10-8 Relation between Main Clock and Baud Rate ....................................................................................... 293

10-9 Receive Error Causes............................................................................................................................ 299

11-1 Configuration of A/D Converter.............................................................................................................. 303

13-1 Configuration of RTO............................................................................................................................. 322

13-2 Operation When Real-Time Output Buffer Registers Are Manipulated.................................................. 323

13-3 Operation Mode and Output Trigger of Real-Time Output Port............................................................. 325

16-1 List of Communication Systems............................................................................................................. 366

20

CHAPTER 1 INTRODUCTION

The V850/SA1 is a product in NEC’s V850 Family of single-chip microcontrollers designed for real-time control

operations. This chapter presents a brief overview of the V850/SA1.

1.1 General

The V850/SA1 is a 32-/16-bit single-chip microcontroller that includes the V850 Family’s CPU core, and peripheral

functions such as ROM/RAM, a timer/counter, a serial interface, an A/D converter, a timer, and DMA, controller.

In addition to its highly real-time responsiveness and one-clock-pitch execution of instructions, the V850/SA1
includes a hardware multiplier for multiplication instructions, saturation instructions, and bit manipulation instructions,
all of which are instructions suited for digital servo control applications. As a real-time control system, this device
provides a high level of cost performance suitable for applications ranging from low-power camcorders and other AV
equipment to portable telephone equipment such as cellular phones and PHS phone systems.

1.2 Features

{ Number of instructions: 74
{ Minimum instruction execution time

59 ns (when main system clock (fXX) is operating at 17 MHz)

30.5 µs (when subsystem clock fXT is operating at 32.768 kHz)

{ General-purpose registers 32 bits × 32 registers
{ Instruction set Signed multiplication (16 × 16 → 32): 1 or 2 clocks

(able to execute instructions in parallel continuously without creating any register
hazards).
Saturation operations (overflow and underflow detection functions are included)
32-bit shift instruction: 1 clock
Bit manipulation instructions
Load/store instructions with long/short format

{ Memory space 16 Mbytes of linear address space (for programs and data)

External expandability: expandable to 4 Mbytes
Memory block allocation function: 2 Mbytes per block
Programmable wait function
Idle state insertion function

21

CHAPTER 1 INTRODUCTION

{ External bus interface 16-bit data bus (address/data multiplex)

Address bus: separate output enabled
Bus hold function
External wait function

{ On-chip memory

{ Interrupts and exceptions External interrupts: 8 (including NMIs)

{ I/O lines Total: 85 (13 input ports and 72 I/O ports)
{ Timer/counter 16-bit timer: 2 channels (PWM output)

{ Watch timer When operating under subsystem or main system clock: 1 channel
{ Watchdog timer 1 channel
{ Serial interface (SIO) Asynchronous serial interface (UART)

{ A/D converter 10-bit resolution: 12 channels
{ DMA controller On-chip RAM ←→ on-chip peripheral I/O: 3 channels
{ RTP 8 bits × 1 ch or 4 bits × 2 ch
{ Clock generator During main system clock or subsystem clock operation

{ Power-saving functions HALT/IDLE/STOP modes
{ Package 100-pin plastic LQFP (fine pitch, 14 × 14 mm, resin thickness: 1.40 mm)

{ CMOS structure All static circuits

µ

PD703015, 703015Y (ROM: 128 Kbytes, RAM: 4 Kbytes)

µ

PD70F3017, 70F3017Y (Flash memory: 256 Kbytes, RAM: 8 Kbytes)

Internal interrupts: 30 sources
Exceptions: 1 source
Interrupt priority levels are freely selectable (among 8 levels)

8-bit timer: 4 channels (PWM output, cascade connection enabled)

Clock-synchronized serial interface (CSI)
I2C bus interface (I2C) (µPD703015Y or 70F3017Y only)

UART: 1 ch
CSI: 1 ch
UART/CSI: 1 ch
I2C/CSI: 1 ch
UART dedicated baud rate generator: 2 channels

5-level CPU clock (including slew rate and sub operations)

121-pin fine pitch BGA (12 × 12 mm)

22

CHAPTER 1 INTRODUCTION

1.3 Application Fields

Low-power portable equipment, for example, cellular phones, PHSs, and camcorders.

1.4 Ordering Information

Part Number Package On-chip ROM

µ

PD703015GC-

µ

PD703015S1-

µ

PD703015YGC-

µ

PD703015YS1-

µ

PD70F3017GC-8EU 100-pin plastic LQFP (fine pitch) (14 × 14 mm) Flash memory

µ

PD70F3017S1-YJC 121-pin fine plastic B GA (12 × 12 mm) Flash memory

µ

PD70F3017YGC-8EU 100-pin plastic LQFP (fine pitch) (14 × 14 mm) Flash memory

µ

PD70F3017YS1-YJC 121-pin fine pitch BGA (12 × 12 mm) Flash memory

Remarks 1.

×××

-8EU 100-pin plastic LQFP (fine pitch) (14 × 14 mm) Mask ROM

×××

-YJC 121-pin fine pitch BGA (12 × 12 mm) Mask ROM

×××

-8EU 100-pin plastic LQFP (fine pitch) (14 × 14 mm) Mask ROM

×××

-YJC 121-pin fine pitch BGA (12 × 12 mm) Mask ROM

××× indicates the ROM code suffix.

2.

ROM-less devices are not provided.

23

1.5 Pin Configuration (Top View)

100-pin plastic LQFP (fine pitch) (14 × 14 mm)

•µPD703015GC-×××-8EU

•µPD703015YGC-×××-8EU

•µPD70F3017GC-8EU

•µPD70F3017YGC-8EU

P20/SI2

P15/SCK1/ASCK0

P14/SO1/TXD0

CHAPTER 1 INTRODUCTION

Note 2

Note 2

P13/SI1/RXD0

P12/SCK0/SCL

P11/SO0

P10/SI0/SDA

P07/INTP6

P06/INTP5/RTPTRG

P05/INTP4/ADTRG

P04/INTP3

P03/INTP2

P02/INTP1

P01/INTP0

P00/NMI

P83/ANI11

P82/ANI10

P81/ANI9

P80/ANI8

P77/ANI7

P76/ANI6

P75/ANI5

P74/ANI4

P73/ANI3

P72/ANI2

P21/SO2
P22/SCK2
P23/RXD1
P24/TXD1

P25/ASCK1

V

V
P26/TI2/TO2
P27/TI3/TO3

P30/TI00
P31/TI01
P32/TI10

P33/TI11
P34/TO0/A13
P35/TO1/A14

P36/TI4/TO4/A15

P37/TI5/TO5

IC/V

PP

Note 1

P100/RTP0/A5
P101/RTP1/A6
P102/RTP2/A7
P103/RTP3/A8

P104/RTP4/A9
P105/RTP5/A10
P106/RTP6/A11

9998979695949392919089888786858483828180797877

100

1
2
3
4
5

DD
SS

6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

76

P71/ANI1
P70/ANI0

REF

AV
AV

SS

AV

DD

P65/A21
P64/A20
P63/A19
P62/A18
P61/A17
P60/A16
P57/AD15
P56/AD14
P55/AD13
P54/AD12
P53/AD11
P52/AD10
P51/AD9
P50/AD8

SS

BV
BV

DD

P47/AD7
P46/AD6
P45/AD5
P44/AD4

26272829303132333435363738394041424344454647484950

SS

DD

X2

X1

V

V

XT2

P111/A2

P112/A3

P113/A4

RESET

P114/XT1

CLKOUT

P91/UBEN

P120/WAIT

P90/LBEN/WRL

P94/ASTB

P95/HLDAK

P96/HLDRQ

P93/DSTB/RD

P92/R/W/WRH

P40/AD0

P41/AD1

P42/AD2

P43/AD3

P110/A1

P107/RTP7/A12

Notes 1.

24

µ

PD703015Y, 703015Y : IC

µ

PD70F3017, 70F3017Y: VPP (connect directly to VSS during normal operation mode)

2.

SCL and SDA are valid only for the µPD703015Y and 70F3017Y.

121-pin fine pitch BGA (12 × 12 mm)

•µPD703015S1-×××-YJC

•µPD703015YS1-×××-YJC

•µPD70F3017S1-YJC

•µPD70F3017YS1-YJC

Top View Bottom View

CHAPTER 1 INTRODUCTION

13
12
11
10

9
8
7
6
5
4
3
2
1

ABCDEFGHJKLMN

Pin

Number

Pin Name

A1 P20 B8 P83 D2 V

A2 P15 B9 P80 D3 V

A3 V

SS

A4 P13 B11 AV

A5 P11 B12 AV

Pin
Number

Pin Name

Pin
Number

Pin Name

B10 P75 D11 AV

SS
SS

D12 AV
D13 AV

DD
SS

DD
DD
DD

A6 P06 B13 P71 E1 P25 H3 P35 L5 V

A7 P03 C1 P22 E2 V

DD

NMLKJHGFEDCBA

Pin
Number

Pin Name

G11 P60 K13 BV
G12 P56 L1 P104 M8 V

Pin
Number

Pin Name

DD

Pin
Number

M7 V

Pin Name

SS
SS

G13 P57 L2 P105 M9 P92
H1 P34 L3 RESET M10 P95
H2 P37 L4 V

DD
SS

M11 P41
M12 P45

H11 P55 L6 X2 M13 P44
A8 P00 C2 P23 E3 P30 H12 P53 L7 P90 N1 P107
A9 P81 C3 V

SS

E11 AV
A10 P76 C4 P24 E12 P64 J1 IC/V
A11 P73 C5 P07 E13 P65 J2 IC/V
A12 P72 C6 P04 F1 P26 J3 P100 L11 BV
A13 AV

SS

C7 P01 F2 P27 J11 P52 L12 BV

B1 P21 C8 P82 F3 P33 J12 P50 L13 BV

DD

H13 P54 L8 P120 N2 P110

Note

PP

L9 P93 N3 P112

Note

PP

L10 P96 N4 V

SS
SS
SS

N5 XT1
N6 V
N7 V

DD

SS
SS

B2 P14 C9 P77 F11 P63 J13 P51 M1 P106 N8 CLKOUT
B3 V
B4 P12 C11 AV
B5 P10 C12 P70 G1 P31 K3 P103 M4 V
B6 P05 C13 AV
B7 P02 D1 V

SS

C10 P74 F12 P61 K1 P101 M2 P111 N9 P91

SS

REF

DD

F13 P62 K2 P102 M3 P113 N10 P94

DD

N11 P40
G2 P32 K11 P46 M5 XT2 N12 P42
G3 P36 K12 P47 M6 X1 N13 P43

Note

µ

PD703015, 703015Y: IC

µ

PD70F3017, 70F3017Y: VPP (Connect directly to VSS at the normal operation mode.)

Remarks 1.

Alternate pin names are omitted. An alternate pin is identical to 100-pin plastic LQFP.

2.

D4 pin is not necessary for the pin processing.

25

CHAPTER 1 INTRODUCTION

Pin Identification

A1-A21 : Address Bus P90-P96 : Port9
AD0-AD15 : Address/Data Bus P100-P107 : Port10
ADTRG : AD Trigger Input P110-P114 : Port11
ANI0-ANI11 : Analog Input P120 : Port12
ASCK0, ASCK1 : Asynchronous Serial Clock RD : Read
ASTB : Address Strobe RESET : Reset
AV
AV
AV
BV
BV

DD
REF
SS
DD
SS

: Analog V
: Analog Reference Voltage RTPTRG : RTP Trigger
: Analog V
: Power Supply for Bus Interface RXD0, RXD1 : Receive Data
: Ground for Bus Interface SCK0-SCK2 : Serial Clock

DD

SS

RTP0-RTP7 : Real-time Port

R/W : Read/Write Status

CLKOUT : Clock Output SCL : Serial Clock
DSTB : Data Strobe SDA : Serial Data
HLDAK : Hold Acknowledge SI0-SI2 : Serial Input
HLDRQ : Hold Request SO0-SO2 : Serial Output
IC : Internally Connected TI00, TI01, TI10, TI11, TI2-TI5
INTP0-INTP6 : Interrupt Request From Peripherals : Timer Input
LBEN : Lower Byte Enable TO0-TO5 : Timer Output
NMI : Non-maskable Interrupt Request TXD0,TXD1 : Transmit Data
P00-P07 : Port0 UBEN : Upper Byte Enable
P10-P15 : Port1 V
P20-P27 : Port2 V
P30-P37 : Port3 V

DD
PP
SS

: Power Supply
: Programming Power Supply

: Ground
P40-P47 : Port4 WAIT : Wait
P50-P57 : Port5 WRH : Write Strobe High Level Data
P60-P65 : Port6 WRL : Write Strobe Low Level Data
P70-P77 : Port7 X1, X2 : Cry stal for Main Clock
P80-P83 : Port8 XT1, XT2 : Crystal for Sub-clock

26

1.6 Function Blocks

1.6.1 Internal Block Diagram

CHAPTER 1 INTRODUCTION

INTP0-INTP6

TI00, TI01
TI10, TI11

TO0, TO1

TI2/TO2
TI3/TO3
TI4/TO4
TI5/TO5

SI0/SDA

SCK0/SCL

SO1/TXD0

SI1/RXD0

SCK1/ASCK0

ASCK1

NMI

SO0

Note 3
Note 3

SO2

S12

SCK2
TXD1

RXD1

INTC

Timer/counter
16-bit timer:

TM0, TM1
8-bit timer:

TM2 to TM5

SIO

2

C

Note 4

CSI0/I

CSI1/UART0

CSI2

UART1

DMAC:3ch

Watch timer

Watchdog
timer

ROM

Note 1

RAM

Note 2

P114

P120

CPU

PC

32-bit
barrel
shifter

System
register

General­purpose
registers
32 bits × 32

Ports RTP

P10-P15

P20-P27

P30-P37

P40-P47

P50-P57

P60-P65

P70-P77

P80-P83

P90-P96

P100-P107

P110-P113

Multiplier
16 ×16– 32

ALU

P00-P07

Instruction
queue

RTPTRG

RTP0-RTP7

BCU

A/D
converter

SS

DD

REF

AV

AV

AV

HLDRQ (P96)
HLDAK (P95)

ASTB (P94)
DSTB/RD (P93)
R/W/WRH (P92)
UBEN (P91)

LBEN/WRL (P90)
WAIT

A1-A12
(P100-P107, P110-P113)

A13-A15 (P34-P36)
A16-A21 (P60-P65)
AD0-AD15

(P40-P47, P50-P57)

CG

ADTRG

ANI0-ANI11

CLKOUT
X1
X2
XT1 (P114)

XT2
RESET

DD

V
V

SS

BV

DD

BV

SS

Note 3

V

PP

Note 4

IC

Notes 1.

µ

PD703015, 703015Y: 128 Kbytes (mask ROM)

µ

PD70F3017, 70F3017Y: 256 Kbytes (flash memory)

2.

µ

PD703015, 703015Y: 4 Kbytes

µ

PD70F3017, 70F3017Y: 8 Kbytes

3.

SDA and SCL pins are valid only for µPD703015Y and 70F3017Y.

4.

I2C function is valid only for µPD703015Y and 70F3017Y.

5.

µ

PD70F3017, 70F3017Y

6.

µ

PD703015, 703015Y

27

CHAPTER 1 INTRODUCTION

1.6.2 On-chip units

(1) CPU

The CPU uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic
logic operations, data transfers, and almost all other instruction processing.
Other dedicated on-chip hardware, such as the multiplier (16 bits × 16 bits → 32 bits) and the barrel shifter (32
bits) help accelerate processing of complex instructions.

(2) Bus control unit (BCU)

The BCU starts a required external bus cycle based on the physical address obtained by the CPU. When an
instruction is fetched from external memory space and the CPU does not send a bus cycle start request, the
BCU generates a prefetch address and prefetches the instruction code. The prefetched instruction code is
stored in an instruction queue.

DD

The V850/SA1 is equipped with BV

and BVSS as power supply pins for the bus interface. These provide an

external interface using a lower voltage level compared to the VDD and VSS pins.

(3) ROM

This consists of a 128-Kbyte mask ROM or a 256-Kbyte flash memory mapped to the address space starting at
00000000H. Both types of memory are accessed by the CPU in one clock cycle when an instruction is fetched.

(4) RAM

This consists of a 4-Kbyte RAM mapped to the address space starting at FFFFE000H if the device includes
mask ROM, or an 8-Kbyte RAM mapped to the address space starting at FFFFD000H if the device includes flash
memory. RAM can be accessed by the CPU in one clock cycle.

(5) Interrupt controller (INTC)

This controller handles hardware interrupt requests (NMI, INTP0-INTP6) from on-chip peripheral hardware and
external hardware. Eight levels of interrupt priorities can be specified for these interrupt requests, and
multiplexed servicing control can be performed for interrupt sources.

(6) Clock generator (CG)

The clock generator includes two types of oscillators, each for main system clock (fXX) and for subsystem clock
(fXT), generates five types of clocks (fXX, fXX/2, fXX/4, fXX/8, and fXT), and supplies one of them as operating clocks
for the CPU (f

cpu

).

28

CHAPTER 1 INTRODUCTION

(7) Timer/counter

A two-channel 16-bit timer/event counter and a four-channel 8-bit timer/event counter are both on chip, which
enables measurement of pulse intervals and frequency as well as programmable pulse output.
The two-channel 8-bit timer/event counter can be connected via a cascade connection to enable use as a 16-bit
timer.

(8) Watch timer

This timer counts the reference time period (0.5 seconds) for counting the clock (the 32.768-kHz subsystem
clock or the 16.777-MHz main system clock). At the same time, the watch timer can be used as an interval timer
for the main system clock.

(9) Watchdog timer

A watchdog timer has been included to detect runaway programs, system abnormalities, etc.
It can also be used as an interval timer.
When used as a watchdog timer, it generates a nonmaskable interrupt request (INTWDT) after an overflow
occurs. When used as an interval timer, it generates a maskable interrupt request (INTWDTM) after an overflow
occurs.

(10) Serial interface (SIO)

The V850/SA1 includes two kinds of serial interfaces: an asynchronous serial interface (UART) and a clock-

2

synchronized serial interface (CSI). These plus the I

C bus interface comprise four channels. One of these
channels is switchable between the UART and CSI and another is switchable between CSI and I2C, while the
remaining two channels are fixed (one as UART and one as CSI).

For UART, data is transferred via the TXDn and RXDn pins.
For CSI, data is transferred via the SOn, SIn, and SCKn pins.
For I2C, data is transferred via the SDA and SCL pins.
For UART only, there is a two-channel dedicated baud rate generator on chip.

(11) A/D converter

This high-speed, high-resolution 10-bit A/D converter includes 12 analog input pins. Conversion uses the
successive conversion method.

(12) DMA controller

A three-channel DMA controller is on chip. This controller transfers data between the on-chip RAM and on-cihip
peripheral I/O devices in response to interrupt requests sent by on-chip peripheral I/O.

(13) RTP

The RTP is a real-time output function that transfers previously set 8-bit data to an output latch when an
external trigger signal occurs or when there is a coincidence signal in a timer compare register. It can also be
used for 4-bit × 2 ch.

29

CHAPTER 1 INTRODUCTION

(14) Ports

As shown below, following ports have general port functions and control pin functions.

Port I/O Port Function Control Function
P0 8-bit I/O General port NMI, external i nterrupt, A/D converter trigger, RTP tri gger
P1 6-bit I/O Serial interface
P2 8-bit I/O Serial interface, ti m er output
P3 8-bit I/O Timer I/O, external addres s bus
P4 8-bit I/O External address/data bus
P5
P6 6-bit I/O External address bus
P7 8-bit input A /D converter analog input
P8 4-bit input
P9 7-bit I/O External bus interfac e control signal I/O
P10 8-bit I/O Real-time output port, external address bus
P11 4-bit I/O,

1-bit input

P12 1-bit I/O Wait control

External address bus, sub clock input

30

CHAPTER 2 PIN FUNCTIONS

2.1 List of Pin Functions

The names and functions of this product’s pins are listed below. These pins can be divided into port pins and non-

port pins according to their functions.

(1) Port pins

Pin Name I/O PULL Function Alternate Function
P00 I/O Yes NMI
P01 INTP0
P02 INTP1
P03 INTP2
P04 INTP3
P05 INTP4/ADTRG
P06 INTP5/RTPTRG
P07 INTP6
P10 I/O Yes SI0/SDA
P11 SO0
P12 SCK0/SCL
P13 SI1/RXD0
P14 SO1/TXD0
P15 SCK1/ASCK0
P20 I/O Yes SI2
P21 SO2
P22 SCK2
P23 RXD1
P24 TXD1
P25 ASCK1
P26 TI2/TO2
P27 TI3/TO3

Port 0

8-bit I/O port
Input/output mode can be specified bitwise

Port 1

6-bit I/O port
Input/output mode can be specified bitwise

Port 2

8-bit I/O port
Input/output mode can be specified bitwise

(1/3)

Remark

PULL: on-chip pull-up resistor

31

CHAPTER 2 PIN FUNCTIONS

Pin Name I/O PULL Function Alternate Function

(2/3)

P30 I/O Yes TI00
P31 TI01
P32 TI10
P33 TI11
P34 TO0/A13
P35 TO1/A14
P36 TI4/TO4/A15
P37 TI5/TO5
P40 I/O No AD0
P41 AD1
P42 AD2
P43 AD3
P44 AD4
P45 AD5
P46 AD6
P47 AD7
P50 I/O No AD8
P51 AD9
P52 AD10
P53 AD11
P54 AD12
P55 AD13
P56 AD14
P57 AD15
P60 I/O No A16
P61 A17
P62 A18
P63 A19
P64 A20
P65 A21

Port 3

8-bit I/O port
Input/output mode can be specified bitwise

Port 4

8-bit I/O port
Input/output mode can be specified bitwise

Port 5

8-bit I/O port
Input/output mode can be specified bitwise

Port 6

6-bit I/O port
Input/output mode can be specified bitwise

Remark

32

PULL: on-chip pull-up resistor

CHAPTER 2 PIN FUNCTIONS

Pin Name I/O PULL Function Alternate Function

(3/3)

P70 Input No ANI0
P71 ANI1
P72 ANI2
P73 ANI3
P74 ANI4
P75 ANI5
P76 ANI6
P77 ANI7
P80 Input No ANI8
P81 ANI9
P82 ANI10
P83 ANI11
P90 I/O No LBEN/WRL
P91 UBEN
P92 R/W/WRH
P93 DSTB/RD
P94 ASTB
P95 HLDAK
P96 HLDRQ
P100 I/ O Yes RTP0/A5
P101 RTP1/A6
P102 RTP2/A7
P103 RTP3/A8
P104 RTP4/A9
P105 RTP5/A10
P106 RTP6/A11
P107 RTP7/A12
P110 I/ O Yes A1
P111 A2
P112 A3
P113 A4
P114 Input No XT1
P120 I/O No WAIT

Port 7

8-bit input port
Input mode can be specified bi twise

Port 8

4-bit input port
Input mode can be specified bi twise

Port 9

7-bit I/O port
Input/output mode can be specified bitwise

Port 10

8-bit I/O port
Input/output mode can be specified bitwise

Port 11

5-bit I/O port
Input/output mode can be specified bitwise
Fixed as input mode in P114 only .

Port 12

1-bit I/O port

Remark

PULL: on-chip pull-up resistor

33

CHAPTER 2 PIN FUNCTIONS

(2) Non-port pins

Pin Name I/O PULL Function Alternate Function
A1-A4 Output No Low-order address bus used for external memory expansion P 110-P 113
A5-A12 P100/RTP0-

P107/RTP7
A13 P34/TO0
A14 P35/TI1
A15 P36/TI4/TO4
A16-A21 Output No High-order address bus us ed for external memory expansion P60-P65
AD0-AD7 I/O No P40-P47
AD8-AD15
ADTRG Input Yes A/D convert er external trigger input P05/INTP4
ANI0-ANI7 Input No Analog input to A/D converter P70-P77
ANI8-ANI11 Input No P80-P83
ASCK0 Input Yes Serial clock input for UART0 and UART1 P15/SCK1
ASCK1 P25
ASTB Output No External address strobe signal output P94
AV
AV
AV
BV
BV

DD

REF

SS

DD

SS

−−

Input

−−

−−

−−

CLKOUT Output
DSTB Output No Ex t ernal data strobe signal output P93/RD
HLDAK Output No Bus hold ack nowl edge output P95
HLDRQ Input No Bus hold request input P96
INTP0-INTP3 I/O Yes External interrupt reques t input (analog noise elimination) P 01-P04
INTP4 Ex ternal interrupt request input (digital noise el i m i nation) P05/ADTRG
INTP5 P06/RTPTRG
INTP6 P07
LBEN Output No External data bus’s low-order byte enable signal output P90/WRL
NMI Input Yes Nonmaskable interrupt request input P00
RD Output No Read strobe s i gnal output P93/DSTB
RESET Input
RTP0-RTP7 Output Yes Real-time output port P100/A5-P107/A12

16-bit multiplexed address /data bus used for external memory
expansion

Positive power supply for A/D converter

−

Reference voltage input for A / D converter
Ground potential for A/D conv ert er
Positive power supply for bus interface
Ground potential for bus interface

−

Internal system clock output

−

System reset input

P50-P57

−

−

−

−

−

−

−

(1/3)

Remark

34

PULL: on-chip pull-up resistor

CHAPTER 2 PIN FUNCTIONS

Pin Name I/O PULL Function Alternate Function
RTPTRG Input Yes RTP external trigger input P06/INTP5
R/W Output No External read/ wri t e status output P92/WRH
RXD0 Input Yes Serial receive data input for UART0 and UART1 P13/SI1
RXD1 P23
SCK0 I/O Yes Serial clock I/O (3-wire type) for CSI0 to CSI2 P12/SCL
SCK1 P15/ASCK0
SCK2 P22
SCL I/O Yes Serial clock I/O for I2C (µPD703015Y, 70F3017Y only) P12/SCK0
SDA I/O Yes

Serial transmit/receive data I/O for I2C (µPD703015Y, 70F3017Y only)

P10/SI0
SI0 Input Yes Serial receive dat a i nput (3-wi re type) for CSI0 to CSI2 P10/SDA
SI1 P13/RXD0
SI2 P20
SO0 Output Yes S eri al transmit data output (3-wire type) for CSI0 to CSI2 P11
SO1 P14/TXD0
SO2 P21
TI00 Input Yes Shared as external capture trigger input and external count

P30

clock input for TM0
TI01 External capture trigger input f or TM 0 P31
TI10 Shared as external capture trigger input and external count

P32

clock input for TM1
TI11 External capture trigger input f or TM 1 P33
TI2 Ex t ernal count clock input for TM2 P26/TO2
TI3 Ex t ernal count clock input for TM3 P27/TO3
TI4 Ex t ernal count clock input for TM4 P36/TO4/A15
TI5 Ex t ernal count clock input for TM5 P37/TO5
TO0, TO1 Out put Yes Pulse signal out put for TM0, TM1 P34/A13, P35/A14
TO2 Pulse s ignal output for TM2 P26/TI2
TO3 Pulse s ignal output for TM3 P27/TI3
TO4 Pulse s ignal output for TM4 P36/TI4/A15
TO5 Pulse s ignal output for TM5 P37/TI5
TXD0 Output Yes Serial transmit data output for UART0 and UART1 P14/SO1
TXD1 P24
UBEN Output No High-order byte enable signal output for external data bus P91

DD

V

PP

V

−−

−−

Positive power supply pi n

High-voltage apply pin for program write/ verify (only in produc ts

−

−

that feature flash memory)

SS

V

−−

GND potential

−

(2/3)

Remark

PULL: on-chip pull-up resistor

35

CHAPTER 2 PIN FUNCTIONS

Pin Name I/O PULL Function Alternate Function
WAIT I nput No Control signal input for inserting wait in bus cycle P120
WRH Output No High-order byte write strobe signal output for external data bus P92/R/W
WRL Low-order byte write strobe si gnal output for external data bus P90/LBEN
X1 Input No Resonator connection for main clock
X2
XT1 Input No Resonator connection for subsystem clock P114
XT2
IC

− −

− −

−−

Internally connected (µPD703015, 703015Y only)

−

−

(3/3)

Remark

PULL: on-chip pull-up resistor

36

CHAPTER 2 PIN FUNCTIONS

2.2 Pin States

The operating states of various pins are described below with reference to their operating states.

Operating State

Pin
AD0-AD15 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
A1-A15 Hi-Z Held Held Held Held Held
A16-A21 Hi-Z Hi-Z Hi-Z Held Hi-Z Held
LBEN, UBEN Hi-Z Hi-Z Hi-Z Held Hi-Z Held
R/W Hi-Z Hi-Z Hi-Z H Hi-Z H
DSTB, WRL, WRH, RD Hi-Z Hi-Z Hi-Z H Hi-Z H
ASTB Hi-Z Hi-Z Hi-Z H Hi-Z H
HLDRQ
HLDAK Hi-Z Hi-Z Hi-Z Operating L Operating
WAIT
CLKOUT Hi-Z L L

Note

“L” when in clock output inhibit mode

Remark

Hi-Z : High impedance

Reset STOP Mode IDLE Mode HALT Mode Bus Hold Idle State

−−−

−−−−−−

Operating Operati ng Operating

Operating

Note

Operating

Note

Operating

Held : State is held during previously set external bus cycle
L : Low-level output
H : High-level output

− : Sampled without input

Note

37

CHAPTER 2 PIN FUNCTIONS

2.3 Description of Pin Functions

(1) P00 to P07 (Port 0) ··· 3-state I/O

Port 0 is an 8-bit I/O port that can be set bitwise for input or output.
P00 to P07 can function as I/O port pins and can also function as NMI inputs, external interrupt request inputs,
external triggers for the A/D converter, or external triggers for the real-time output port. The port mode or control
mode can be selected bitwise and each pin’s valid edge is specified in the EGP0 and EGN0 registers.

(a) Port mode

P00 to P07 can be set bitwise as input or output according to the contents of port 0 mode register (PM0).

(b) Control modes

P00 to P07 can be set bitwise to port mode or a control mode according to the contents of the external
interrupt rising edge enable register (EGP0) or the external interrupt falling edge enable register (EGN0).

(i) NMI (Non-maskable Interrupt Request) ··· input

This pin accepts input of non-maskable interrupt request signals.

(ii) INTP0 to INTP6 (Interrupt Request from Peripherals) ··· input

These are external interrupt request input pins.

(iii) ADTRG (AD Trigger Input) ··· input

This is the A/D converter’s external trigger input pin. This pin is controlled with A/D converter mode
register (ADM).

(iv) RTPTRG (Real-Time Port Trigger Input) ··· input

This is the real-time output port’s external trigger input pin. This pin is controlled with real-time output
port control register (RTPC).

38

CHAPTER 2 PIN FUNCTIONS

(2) P10 to P15 (Port 1) ··· 3-state I/O

Port 1 is a 6-bit I/O port in which input and output pins can be specified bitwise.
P10 to P15 can function as I/O port pins and can also operate as input or output pins for the serial interface.
These pins can be set bitwise to port mode or a control mode.
P10 to P12, P14, and P15 can select normal output and N-ch open drain output.

(a) Port mode

P10 to P15 can be set bitwise as input or output pins according to the contents of port 1 mode register
(PM1).

(b) Control modes

P10 to P15 can be set bitwise to port mode or a control mode according to the contents of the port 1 register
(P1) or port 1 mode register (PM1).

(i) SI0, SI1 (Serial Input 0, 1) ··· input

These pins accept input of the serial receive data of CSI0 and CSI1.

(ii) SO0, SO1 (Serial Output 0, 1) ··· output

These pins accept output of the serial transmit data of CSI0 and CSI1.

(iii) SCK0, SCK1 (Serial Clock 0, 1) ··· 3-state I/O

These are the serial clock I/O pins for CSI0 and CSI1.

(iv) SDA (Serial Data) ··· I/O

2

This is the serial transmit/receive data I/O pin for I

C (µPD703015Y, 70F3017Y only).

(v) SCL (Serial Clock) ··· I/O

This is the serial clock I/O pin for I2C (µPD703015Y, 70F3017Y only).

(vi) RXD0 (Receive Data 0) ··· input

This is the input pin for UART0 serial receive data.

(vii) TXD0 (Transmit Data 0) ··· output

This is the output pin for UART0 serial transmit data.

(viii)ASCK0 (Asynchronous Serial Clock 0) ··· input

This is the input pin for UART0 serial baud rate clock.

39

CHAPTER 2 PIN FUNCTIONS

(3) P20 to P27 (Port 2) ··· 3-state I/O

Port 2 is an 8-bit I/O port in which input and output pins can be specified bitwise.
P20 to P27 can function as I/O port pins and can also operate as input or output pins for the serial interface.
These pins can be set bitwise to port mode or a control mode.
P21 and P22 can select normal output and N-ch open drain output.

(a) Port mode

P20 to P27 can be set bitwise as input or output pins according to the contents of port 2 mode register
(PM2).

(b) Control modes

P20 to P27 can be set bitwise to port mode or a control mode according to the contents of the port 2 register
(P2) and port 2 mode register (PM2).

(i) SI2 (Serial Input 2) ··· input

This pin accepts input of the CSI2 serial receive data.

(ii) SO2 (Serial Output 2) ··· output

This pin accepts output of the CSI2 serial transmit data.

(iii) SCK2 (Serial Clock 2) ··· 3-state I/O

This is the CSI2 serial clock I/O pin.

(iv) RXD1 (Receive Data 1) ··· input

This is the input pin for UART1 serial receive data.

(v) TXD1 (Transmit Data 1) ··· output

This is the output pin for UART1 serial transmit data.

(vi) ASCK1 (Asynchronous Serial Clock 1) ··· input

This is the input pin for UART1 serial clock.

(vii) TI2, TI3 (Timer Input 2, 3) ··· input

These are the external counter clock input pins for timer 2 and timer 3.

(viii)TO2, TO3 (Timer Output 2, 3) ··· output

These are the pulse signal output pins for timer 2 and timer 3.

40

CHAPTER 2 PIN FUNCTIONS

(4) P30 to P37 (Port 3) ··· 3-state I/O

Port 3 is an 8-bit I/O port in which input and output pins can be specified bitwise.
P30 to P37 can function as I/O port pins and can also operate as input or output pins for the timer/counter.
These pins can be set bitwise to port mode or a control mode.

(a) Port mode

P30 to P37 can be set bitwise as input or output pins according to the contents of port 3 mode register
(PM3).

(b) Control modes

P30 to P37 can be set bitwise to port mode or a control mode according to the contents of the port 3 register
(P3) and port 3 mode register (PM3).

(i) TI00, TI01, TI10, TI11, TI4, TI5 (Timer Input 00, 01, 10, 11, 4, 5) ··· input

These pins accept external count clock input from timer 0, timer 1, timer 4, and timer 5.

(ii) TO0, TO1, TO4, TO5 (Timer Output 0, 1, 4, 5) ··· output

These pins output pulse signals from timer 0, timer 1, timer 4, and timer 5.

(iii) A13 to A15 (Address 13 to 15) ··· output

These are address bus that is used for external access. These pins operate as A13 to A15 bit address
output pins within a 22-bit address. The output changes in synchronization with the rising edge of the
clock in the T1 state of the bus cycle. When the timing sets the bus cycle as inactive, the previous bus
cycle’s address is retained.

(5) P40 to P47 (Port 4) ··· 3-state I/O

Port 4 is an 8-bit I/O port in which input and output pins can be specified bitwise.
P40 to P47 can function as I/O port pins and can also operate as a time division address/data bus (AD0 to AD7)
when using external memory expansion. These pins can be set bitwise to port mode or a control mode.

DD

The I/O signal level uses the bus interface power supply pins BV

and BVSS as a reference.

(a) Port mode

P40 to P47 can be set bitwise as input or output pins according to the contents of port 4 mode register
(PM4).

41

CHAPTER 2 PIN FUNCTIONS

(b) Control mode (external expansion mode)

P40 to P47 can be set as AD0 to AD7 according to the contents of the memory expansion register (MM).

(i) AD0 to AD7 (Address/Data 0 to 7) ··· 3-state I/O

These are multiplexed address/data bus that is used for external access. Under address timing (T1
state), these pins operate as AD0 to AD7 (22-bit address) output pins. Under data timing (T2, TW, T3),
they operate as low-order 8-bit I/O bus pins for 16-bit data. The output changes in synchronization with
the rising edge of the clock in each state within the bus cycle. When the timing sets the bus cycle as
inactive, these pins are set for high impedance.

(6) P50 to P57 (Port 5) ··· 3-state I/O

Port 5 is an 8-bit I/O port in which input and output pins can be specified bitwise.
P50 to P57 can function as I/O port pins and can also operate as a time division address/data bus (AD8 to AD15)
when using external memory expansion. These pins can be set bitwise to port mode or a control mode.

DD

The I/O signal level uses the bus interface power supply pins BV

and BVSS as a reference.

(a) Port mode

P50 to P57 can be set bitwise as input or output pins according to the contents of port 5 mode register
(PM5).

(b) Control mode (external expansion mode)

P50 to P57 can be set as AD8 to AD15 according to the contents of the memory expansion register (MM).

(i) AD8 to AD15 (Address/Data 8 to 15) ··· 3-state I/O

These are multiplexed address/data bus that is used for external access. Under address timing (T1
state), these pins operate as AD8 to AD15 (22-bit address) output pins. Under data timing (T2, TW,
T3), they operate as high-order 8-bit I/O bus pins for 16-bit data. The output changes in
synchronization with the rising edge of the clock in each state within the bus cycle. When the timing
sets the bus cycle as inactive, these pins are set for high impedance.

(7) P60 to P65 (Port 6) ··· 3-state I/O

Port 6 is a 6-bit I/O port in which input and output pins can be specified bitwise.
P60 to P65 can function as I/O port pins and can also operate as an address bus (A16 to A21) when using
external memory expansion. These pins can be set bitwise to port mode or a control mode.
The I/O signal level uses the bus interface power supply pins BVDD and BVSS as a reference.

42

CHAPTER 2 PIN FUNCTIONS

(a) Port mode

P60 to P65 can be set bitwise as input or output pins according to the contents of port 6 mode register
(PM6).

(b) Control mode (external expansion mode)

P60 to P65 can be set as A16 to A21 according to the contents of the memory expansion register (MM).

(i) A16 to A21 (Address 16 to 21) ··· output

These are address bus that is used for external access. These pins operate as the high-order 6-bit
address output pins within a 22-bit address. The output changes in synchronization with the rising edge
of the clock in the T1 state of the bus cycle. When the timing sets the bus cycle as inactive, the
previous bus cycle’s address is retained.

(8) P70 to P77 (Port 7), P80 to P83 (Port 8) ··· input

Port 7 is an 8-bit input-only port in which all pins are fixed as input pins. Port 8 is a 4-bit input-only port.
P70 to P77 and P80 to P83 can function as input ports and can also function as analog input pins for the A/D
converter when under control mode. However, they cannot be switched between these input port and analog
input pin.

(a) Port mode

P70 to P77 and P80 to P83 are input-only pins.

(b) Control mode (external expansion mode)

P70 to P77 are shared as pins ANI0 to ANI7 and P80 to P83 are shared as ANI8 to ANI11, but these
alternate functions are not switchable.

(i) ANI0 to ANI11 (Analog Input 0 to 11) ··· output

These are analog input pins for the A/D converter.

SS

Connect a capacitor between these pins and AV
not apply voltage that is outside the range for AVSS and AV
the A/D converter. If it is possible for noise above the AV

to prevent noise-related operation faults. Also, do

REF

to pins that are being used as inputs for

REF

range or below the AVSS to enter, clamp

using a diode that has a small VF value.

43

CHAPTER 2 PIN FUNCTIONS

(9) P90 to P96 (Port 9) ··· 3-state I/O

Port 9 is a 7-bit I/O port in which input and output pins can be specified bitwise.
P90 to P96 can function as I/O port pins and can also operate as control signal output pins and bus hold control
signal output pins when using external memory expansion.
During 8-bit access of port 9, the highest-order bit is ignored during a write operation and is read as a “0” during
a read operation. Port mode or a control mode can be specified bitwise.

DD

The I/O signal level uses the bus interface power supply pins BV

and BVSS as a reference.

(a) Port mode

P90 to P96 can be set bitwise as input or output pins according to the contents of port 9 mode register
(PM9).

(b) Control modes (external expansion mode)

P90 to P96 can be set to operate as control signal outputs for external memory expansion according to the
contents of the memory expansion register (MM).

(i) LBEN (Lower Byte Enable) ··· output

This is a lower byte enable (LBEN) signal output pin for an external 16-bit data bus. The output
changes in synchronization with the rising edge of the clock in the T1 state of the bus cycle. When the
timing sets the bus cycle as inactive, the previous bus cycle’s address is retained.

(ii) UBEN (Upper Byte Enable) ··· output

This is an upper byte enable (UBEN) signal output pin for an external 16-bit data bus. During byte
access of even-numbered addresses, these pins are set as inactive (high level). The output changes in
synchronization with the rising edge of the clock in the T1 state of the bus cycle. When the timing sets
the bus cycle as inactive, the previous bus cycle’s address is retained.

Access UBEN LBEN A0
Word access 0 0 0
Half word access 0 0 0
Byte access Even-numbered address 1 0 0

Odd-numbered address 0 1 1

44

CHAPTER 2 PIN FUNCTIONS

(iii) R/W (Read/Write Status) ··· output

In this mode, this pin is output for the status signal that indicates whether the bus cycle is a read cycle
or write cycle during external access. High level is set during the read cycle and low level is set during
the write cycle. The output changes in synchronization with the rising edge of the clock in the T1 state
of the bus cycle. High level is set when the timing sets the bus cycle as inactive.

(iv) DSTB (Data Strobe) ··· output

In this mode, this pin is output pin for the external data bus’s access strobe signal. Output becomes
active (low level) during the T2 and TW states of the bus cycle. Output becomes inactive (high level)
when the timing sets the bus cycle as inactive.

(v) ASTB (Address Strobe) ··· output

In this mode, this pin is output pin for the external address bus’s latch strobe signal. Output becomes
active (low level) in synchronization with the falling edge of the clock during the T1 state of the bus
cycle, and becomes inactive (high level) in synchronization with the falling edge of the clock during the
T3 state of the bus cycle. Output becomes inactive when the timing sets the bus cycle as inactive.

(vi) HLDAK (Hold Acknowledge) ··· output

In this mode, this pin is output pin for the acknowledge signal that indicates high impedance status for
the address bus, data bus, and control bus when the V850/SA1 receives a bus hold request.
The address bus, data bus, and control bus are set to high impedance status when this signal is active.

(vii) HLDRQ (Hold Request) ··· input

In this mode, this pin is input pin by which an external device requests the V850/SA1 to release the
address bus, data bus, and control bus. This pin accepts asynchronous input for CLKOUT. When this
pin is active, the address bus, data bus, and control bus are set to high impedance status. This occurs
either when the V850/SA1 completes execution of the current bus cycle or immediately if no bus cycle
is being executed, then the HLDAK signal is set as active and the bus is released.

(viii)WRL (Write Strobe Low Level Data) ··· output

In this mode, this is write strobe signal output pin for the low-order data in an external 16-bit data bus.
Output occurs during the write cycle, similar to DSTB.

45

CHAPTER 2 PIN FUNCTIONS

(ix) WRH (Write Strobe High Level Data) ··· output

In this mode, this is write strobe signal output pin for the high-order data in an external 16-bit data bus.
Output occurs during the write cycle, similar to DSTB.

(x) RD (Read) ··· output

In this mode, this is read strobe signal output pin for an external 16-bit data bus. Output occurs during
the read cycle, similar to DSTB.

(10) P100 to P107 (Port 10) ··· 3-state I/O

Port 10 is an 8-bit I/O port in which input and output pins can be specified bitwise.
P100 to P107 can function as I/O port pins and can also operate as a real-time output port.
P100 to P107 can select normal output and N-ch open drain output.

(a) Port mode

P100 to P107 can be set bitwise as input or output pins according to the contents of port 10 mode register
(PM10).

(b) Control mode

P100 to P107 can be set bitwise to port mode or control mode according to the contents of the port 10
register (P10) and port 10 mode register (PM10).

(i) RTP0 to RTP7 (Real-time Port 0 to 7) ··· output

In this mode, these pins comprise a real-time output port.

(ii) A5 to A12 (Address 5 to 12) ··· output

These are address bus that is used for external access. These pins operate as A5 to A12 bit address
output pins within a 22-bit address. The output changes in synchronization with the rising edge of the
clock in the T1 state of the bus cycle. When the timing sets the bus cycle as inactive, the previous bus
cycle’s address is retained.

(11) P110 to P114 (Port 11) ··· 3-state I/O

Port 11 is a 5-bit I/O port in which input and output pins can be specified bitwise. However, P114 is fixed as the
XT1 input pin.

(a) Port mode

P110 to P114 can be set bitwise as inputs or outputs according to the contents of port 11 mode register
(PM11). However, P114 is fixed as an input.

(b) Control mode

P110 to P114 can be set bitwise to port mode or control mode according to the contents of the port 11
register (P11) and port 11 mode register (PM11).
P114 is fixed as the XT1 pin.

46

CHAPTER 2 PIN FUNCTIONS

(i) A1 to A4 (Address 1 to 4) ···output

These are address bus that is used for external access. These pins operate as the low-order 4-bit
address output pins within a 22-bit address. The output changes in synchronization with the rising
edge of the clock in the T1 state of the bus cycle. When the timing sets the bus cycle as inactive, the
previous bus cycle’s address is retained.

(ii) XT1 (Crystal for Sub-Clock) ··· input

This is the sub-clock input pin.

(12) P120 (Port 12) ··· 3-state I/O

Port 12 is an I/O port in which the input or output pin can be specified bitwise. P120 can function as an I/O port
and can also operate as a control signal (WAIT) pin when a wait is inserted in the bus cycle. This pin can be set
to port mode or control mode.

DD

The I/O signal level uses the bus interface power supply pins BV

and BVSS as a reference.

(a) Port mode

P120 can be set as an input or output pin according to the contents of port 12 mode register (PM12).

(b) Control mode

P120 can operate as the WAIT pin according to the contents of port 12 mode control register (PMC12).

(i) WAIT (Wait) ··· input

This is the input pin for the control signal used to insert waits into the bus cycle. This pin is sampled at
the falling edge of the clock during the T2 or TW state of the bus cycle.

(13) RESET (Reset) ··· input

RESET input is asynchronous input for a signal that has a constant low level width regardless of the operating
clock’s status. When this signal is input, a system reset is executed as the first priority ahead of all other
operations.
In addition to being used for ordinary initialization/start operations, this pin can also be used to cancel a standby
mode (HALT, IDLE, or STOP mode).

(14) X1, X2 (Crystal) … input

These pins are used to connect the resonator that generates the system clock.
These pins can also be used to input an external clock. When inputting an external clock, connect the X1 pin
and leave the X2 pin unconnected.

(15) XT2 (Crystal for Sub-Clock) ··· input

This pin is used to connect the resonator that generates the sub clock (subsystem clock).

47

CHAPTER 2 PIN FUNCTIONS

(16) AVDD (Analog VDD)

This is the analog power supply pin for the A/D converter.

(17) AVSS (Analog VSS)

This the ground pin for the A/D converter.

(18) AV

(Analog Reference Voltage) … input

REF

This is the reference voltage supply pin for the A/D converter.

(19) BVDD (Power Supply for Bus Interface)

This is the positive power supply pin for the bus interface.

(20) BVSS (Ground for Bus Interface)

This is the ground pin for the bus interface.

(21) VDD (Power Supply)

DD

These are the positive power supply pins. Both V

(22) V

(23) V

(Ground)

SS

These are the ground pins. Both V

(Programming Power Supply)

PP

SS

pins should be grounded.

pins should be connected to a positive power source.

This is the positive power supply pin used for flash memory programming mode.

µ

This pin is used in the

PD70F3017 and 70F3017Y.

(24) IC (Internally Connected)

This is an internally connected pin. This pin is used in the µPD703015 and 703015Y.

48

CHAPTER 2 PIN FUNCTIONS

2.4 Pins’ I/O Circuit Types and Handling When Not Used

Pin Alternate Func tion I/O Circuit Type Recommended Connection Method

(1/2)

P00 NMI 8-A During input : connect to V

SS

P01 to P04 INTP0 to INTP3 During output : leave open
P05 INTP4/ADTRG
P06 INTP5/RTPTRG
P07 INTP6
P10 SI0/SDA 10-A During input : connect to VDD or V

SS

P11 SO0 26 During output : l eave open
P12 SCK0/SCL 10-A
P13 SI1/RXD0 8-A
P14 SO1/TXD0 26
P15 SCK1/ASCK0 10-A
P20 SI2 8-A
P21 SO2 26
P22 SCK2 10-A
P23 RXD1 8-A
P24 TXD1 5-A
P25 ASCK1 8-A
P26, P27 TI2/TO2, TI3/TO3
P30, P31 TI00, TI01 8-A
P32, P33 TI10, TI11
P34, P35 TO0/A13, TO1/A14 5-A
P36 TI4/TO4/A15 8-A
P37 TI5/TO5
P40 to P47 AD0 to AD7 5 During input : connect to BVDD or BV
P50 to P57 AD8 to AD15

During output : leave open

P60 to P65 A16 to A21
P70 to P77 ANI0 to ANI7 9 Connect to AVSS or AV

DD

P80 to P83 ANI8 to ANI11

SS

49

CHAPTER 2 PIN FUNCTIONS

Pin Alternate Func tion I/O Circuit Type Recommended Connection Method

(2/2)

P90 LBEN/WRL 5 During input : connect to BVDD or BV
P91 UBEN

During output : leave open

P92 R/W/WRH
P93 DSTB/RD
P94 ASTB
P95 HLDAK
P96 HLDRQ
P100 to P107 RTP0/A5 to RTP7/A12 26 During input : connect to VDD or V
P110 to P113 A1 to A4 5-A

During output : leave open

SS

P114 XT1 16
P120 WAIT 5 During input : connect to BVDD or BV

During output : leave open

DD

AV

SS

AV

REF

AV
CLKOUT
RESET

PP

V
X2
XT2

−−

−−

Connect to V
Connect to V

−−

−

−

−−

−−

−

4 Leave open
2

Connect to V
Leave open (when external clock i s i nput to × 1 pin)

16 Leave open

DD

SS

−

SS

SS

SS

50

2.5 Pins’ I/O Circuits

CHAPTER 2 PIN FUNCTIONS

(1/2)

Type 2

IN

Schmitt trigger input having hysteresis characterist i cs

Type 4

V

DD

data

output

disable

P-ch

N-ch

OUT

Type 5-A

pullup

enable

output

disable

input enable

Type 8-A

output disable

data

pullup

enable

data

V

DD

P-ch

N-ch

V

P-ch

N-ch

V

DD

P-ch

IN/OUT

V

DD

P-ch

DD

IN/OUT

Push-pull output that c an be s et for high impedance output
(both P-ch and N-ch off).

Type 5 Type 9

V

DD

data

P-ch

IN/OUT

output

N-ch

disable

input enable

P-ch

N-

ch

+

-

REF

(threshold voltage)

V

input enable

comparator

51

CHAPTER 2 PIN FUNCTIONS

Type 10-A Type 26

V

DD

pullup

enable

data

V

P-ch

P-ch

DD

pullup

enable

data

V

P-ch

(2/2)

V

DD

P-ch

DD

open-drain

output disable

Type 16

feedback cut-off

P-ch

XT1

XT2

N-ch

IN/OUT

open-drain

output disable

IN/OUT

N-ch

52

CHAPTER 3 CPU FUNCTIONS

The CPU of the V850/SA1 is based on the RISC architecture and executes most instructions in one clock cycle by

using a 5-stage pipeline.

3.1 Features

• Minimum instruction execution time: 58 ns (at 17 MHz)

• Address space: 4 Mbytes linear

• Thirty-two 32-bit general registers

• Internal 32-bit architecture

• Five-stage pipeline control

• Multiplication/division instructions

• Saturated operation instructions

• Single-cycle 32-bit shift instruction

• Load/store instruction with long/short format

• Four types of bit manipulation instructions

•Set

• Clear

•Not

•Test

53

CHAPTER 3 CPU FUNCTIONS

3.2 CPU Register Set

The CPU registers of the V850/SA1 can be classified into two categories: a general-purpose program register set

and a dedicated system register set. All the registers are 32 bits width. For details, refer to

Manual Architecture

.

System register setProgram register set

31 0 31 0

Zero Register

r0

Reserved for Address Register

r1

Interrupt Stack Pointer

r2

Stack Pointer (SP)

r3

Global Pointer (GP)

r4

Text Pointer (TP)

r5
r6
r7
r8
r9
r10
r11
r12
r13
r14
r15
r16
r17
r18
r19
r20
r21
r22
r23
r24
r25
r26
r27
r28
r29

Element Pointer (EP)

r30

Link Pointer (LP)

r31

EIPC
EIPSW

31 0

FEPC
FEPSW

31 0

ECR Exception Cause Register

31 0

PSW Program Status Word

Exception/Interrupt PC
Exception/Interrupt PSW

Fatal Error PC
Fatal Error PSW

V850 Family User’s

31 0

PC Program Counter

54

CHAPTER 3 CPU FUNCTIONS

3.2.1 Program register set

The program register set includes general registers and a program counter.

(1) General registers

Thirty-two general registers, r0 to r31, are available. Any of these registers can be used as a data variable or
address variable.
However, r0 and r30 are implicitly used by instructions, and care must be exercised when using these registers.
Also, r1 to r5 and r31 are implicitly used by the assembler and C compiler. Therefore, before using these
registers, their contents must be saved so that they are not lost. The contents must be restored to the registers
after the registers have been used.

Table 3-1. Program Registers

Name Usage Operation
r0 Zero register Always holds 0
r1 Assembler-reserved register Working register for generating 32-bit immedi ate
r2 Interrupt stack pointer Stack pointer for interrupt handler
r3 Stack pointer Us ed t o generate st ack frame when function is called
r4 Global pointer Used to access global variable in data area
r5 Text pointer
r6 to r29
r30 El e m ent poi nter Base pointer register when memory is accessed
r31 Link pointer Used by compiler when calling funct ion
PC Program counter Holds instruct i on address during program execut i on

−

Register to indicate the start of the text area
Address/data variable registers

Note

Note

Area in which program code is mapped.

(2) Program counter

This register holds the address of the instruction under execution. The lower 24 bits of this regist e r a r e v a li d , a n d
bits 31 to 24 are fixed to 0. If a carry occurs from bit 23 to 24, it is ignored.
Bit 0 is fixed to 0, and branching to an odd address cannot be performed.

After reset: 00000000H

Symbol 31 24 23 1 0

PC Fixed to 0 Instruction address under execution 0

55

CHAPTER 3 CPU FUNCTIONS

3.2.2 System register set

System registers control the status of the CPU and hold interrupt information.

Table 3-2. System Register Numbers

No. System Regist er Name Usage Operation

0EIPC

EIPSW

1

2 FEPC
3 FEPSW
4 ECR Interrupt source register If exception, maskable interrupt, or NMI occurs, this

5 PSW Program status word Program status word is collect i on flags that indicate

6 to 31 Reserved

Status saving registers during
interrupt

Status saving registers for NMI These registers save PC and PSW when NMI occurs.

These registers save the PC and PSW when an
exception or interrupt occurs. Because only one set of
these registers is available, their contents must be
saved when multiple interrupts are enabled.

register will contain information referenci ng the
interrupt source. The high-order 16 bits of this register
are called FECC, to which exception code of NMI is
set. The low-order 16 bits are called EICC, to which
exception code of exception/interrupt is set.

program status (instruction execution resul t) and CPU
status.

To read/write these system registers, specify a system register number indicated by the system register load/store

instruction (LDSR or STSR instruction).

(1) Interrupt Source Register (ECR)

After reset: 00000000H

Symbol 31 16 15 0

ECR FECC EICC

FECC

EICC Exception code of excepti on/i nterrupt.

Exception code of NMI. (For exception code, refer to

Table 5-1

.)

56

CHAPTER 3 CPU FUNCTIONS

(2) Program Status Word (PSW)

After reset: 00000020H

Symbol31 876543210

PSW RFU NP EP ID SAT CY OV S Z

RFU Res erved field (fixed to 0).

NP Indicates that NMI processing is in progress. This flag is set when NMI is accepted, and

disables multiple interrupts.

EP Indicates that an exception processing is in progress. This flag is set at the generation of

exception. The interrupt request is acknowledged even if this bit is set.

ID Indic ates that accepting external interrupt request is disabled.

SAT This fl ag is set if resul t of executing saturated operation instruction overflows. If overflow

does not occur, value of previous operation is held.

CY This flag is set if carry or borrow occurs as result of operation. If carry or borrow does not

occur, it is reset.

OV Thi s f l ag is set if overflow occurs during operation (if overflow does not occur, it is reset).

S This flag is set if result of operation is negative. It is reset if result is positive.
Z This f l ag is set if result of operation is zero. If result is not zero, it is reset.

57

CHAPTER 3 CPU FUNCTIONS

3.3 Operation Modes

The V850/SA1 has the following operations modes.

(1) Normal operation mode (Single-chip mode)

After the system has been released from the reset status, the pins related to the bus interface are set for port
mode, execution branches to the reset entry address of the internal ROM, and instruction processing written in
the internal ROM is started. However, external expansion mode that connects external device to external
memory area is enabled by setting in the memory expansion mode register (MM) by instruction.

(2) Flash memory programming mode

This mode is provided only to the
erasable when the VPP voltage is applied to VPP pin . The state transition to the programming or erasing of the
flash memory is under investigation.

µ

PD70F3017 and 70F3017Y. The internal flash memory is programmable or

PP

V

0 Normal-operation mode

7.8 V Flash memory programming mode

DD

V

Setting prohibited

Operation Mode

58

CHAPTER 3 CPU FUNCTIONS

3.4 Address Space

3.4.1 CPU address space

The CPU of the V850/SA1 is of 32-bit architecture and supports up to 4 Gbytes of linear address space (data
space) during operand addressing (data access). When referencing instruction addresses, a linear address space
(program space) of up to 16 Mbytes is supported.

Figure 3-1 shows the CPU address space.

Figure 3-1. CPU Address Space

CPU address space

FFFFFFFFH

01000000H

00FFFFFFH

00000000H

Data area
(4-Gbyte linear)

Program area
(16-Mbyte linear)

59

CHAPTER 3 CPU FUNCTIONS

3.4.2 Image (virtual address space)

The core CPU supports 4 Gbytes of “virtual” addressing space, or 256 memory blocks, each containing 16-Mbyte
memory locations. In actuality, the same 16-Mbyte block is accessed regardless of the values of bits 31 to 24 of the
CPU address. Figure 3-2 shows the image of the virtual addressing space.

Because the higher 8 bits of a 32-bit CPU address are ignored and the CPU address is only seen as a 24-bit
external physical address, the physical location xx000000H is equally referenced by multiple address values
00000000H, 01000000H, 02000000H... through FE000000H, FF000000H.

Figure 3-2. Image on Address Space

CPU address space

FFFFFFFFH

Image

FF000000H

FEFFFFFFH

FE000000H

FDFFFFFFH

02000000H

01FFFFFFH

01000000H

00FFFFFFH

00000000H

Image

Image

Image

Image

Physical address space

On-chip peripheral I/O

Internal RAM

(Access prohibited)

Internal ROM

xxFFFFFFH

xx000000H

60

CHAPTER 3 CPU FUNCTIONS

3.4.3 Wrap-around of CPU address space

(1) Program space

Of the 32 bits of the PC (program counter), the higher 8 bits are set to “0”, and only the lower 24 bits are valid.
Even if a carry or borrow occurs from bit 23 to 24 as a result of branch address calculation, the higher 8 bits
ignore the carry or borrow and remain “0”.
Therefore, the lower-limit address of the program space, address 00000000H, and the upper-limit address
00FFFFFFH are contiguous addresses, and the program space is wrapped around at the boundary of these
addresses.

Caution No instruction can be fetched from the 4-Kbyte area of 00FFF000H to 00FFFFFFH because

this area is defined as peripheral I/O area. Therefore, do not execute any branch operation
instructions in which the destination address will reside in any part of this area.

Program space
00FFFFFEH
00FFFFFFH

00000000H
00000001H

Program space

(+) direction (–) direction

(2) Data space

The result of operand address calculation that exceeds 32 bits is ignored.
Therefore, the lower-limit address of the program space, address 00000000H, and the upper-limit address
FFFFFFFFH are contiguous addresses, and the data space is wrapped around at the boundary of these
addresses.

Data space
FFFFFFFEH
FFFFFFFFH

00000000H
00000001H

(+) direction (–) direction

Data space

61

3.4.4 Memory map

The V850/SA1 reserves areas as shown below.

CHAPTER 3 CPU FUNCTIONS

Figure 3-3. Memory Map

Mask ROM
internal version

xxFFFFFFH

xxFFF000H

xxFFEFFFH

xxFFE000H

xxFFDFFFH

xx100000H

xx0FFFFFH

Flash memory
internal version

xxFFFFFFH

xxFFF000H

xxFFEFFFH

xxFFC000H

xxFFBFFFH

xx100000H

xx0FFFFFH

Single-chip mode Single-chip mode

(external expansion mode)

On-chip peripheral

I/O area

Internal RAM area

(access prohibited)

On-chip peripheral

I/O area

Internal RAM area

External memory

area

4 KB

4 KB: Mask ROM internal version
12KB: Flash memory internal version

16 MB

xx000000H

xx000000H

Internal

ROM area

Internal

ROM area

1 MB

62

CHAPTER 3 CPU FUNCTIONS

3.4.5 Area

(1) Internal ROM area

A 1-Mbyte area corresponding to addresses 000000H to 0FFFFFH is reserved for the internal ROM area. The
V850/SA1 is provided with physical internal ROM as follows:

Physical internal ROM: 000000H to 01FFFFH (128 Kbytes) − Mask ROM internal version

000000H to 03FFFFH (256 Kbytes) − Flash memory internal version

The image is seen in the rest of the area.

Figure 3-4. Internal ROM Area (with Mask ROM Internal Version)

xx0FFFFFH

Image

xx0E0000H

xx0DFFFFH

Physical internal ROM

01FFFFH

xx040000H

xx03FFFFH

Image

xx020000H

xx01FFFFH

Image

xx000000H

Internal ROM

Interrupt/exception table

000000H

Interrupt/exception table

The V850/SA1 increases the interrupt response speed by assigning handler addresses corresponding to
interrupts/exceptions.
The collection of these handler addresses is called an interrupt/exception table, which is located in the internal
ROM area. Wh en an interrupt/e xception request is granted, execut ion jumps to the co rresponding destin ation
address, and the program written at that memory address is executed. Table 3-3 shows the sources of
interrupts/exceptions, and the corresponding addresses.

63

CHAPTER 3 CPU FUNCTIONS

Table 3-3. Interrupt/Exception Table

Start Address of Interrupt/Excepti on Table Interrupt/Exception Source
00000000H RESET
00000010H NMI
00000020H INTWDT
0000004nH TRAP0n (n = 0 to F)
0000005nH TRAP1n (n = 0 to F)
00000060H ILGOP
00000080H INTWDTM
00000090H INTP0
000000A0H INTP1
000000B0H INTP2
000000C0H INTP3
000000D0H INTP4
000000E0H INTP5
000000F0H INTP6
00000100H INTWTI
00000110H INTTM00
00000120H INTTM01
00000130H INTTM10
00000140H INTTM11
00000150H INTTM2
00000160H INTTM3
00000170H INTTM4
00000180H INTTM5
00000190H INTIIC0/INTCSI0
000001A0H INTSER0
000001B0H INTSR0/INTCSI1
000001C0H INTST0
000001D0H INTCSI2
000001E0H INTSER1
000001F0H INTSR1
00000200H INTST1
00000210H INTAD
00000220H INTDMA0
00000230H INTDMA1
00000240H INTDMA2
00000250H INTWT

64

CHAPTER 3 CPU FUNCTIONS

(2) Internal RAM area

The internal RAM is incorporated in the following area.

Physical internal RAM: FFE000H to FFEFFFH (4 Kbytes) … Mask ROM internal version

FFD000H to FFEFFFH (8 Kbytes) … Flash memory internal version

In the flash memory internal version, 12 Kbytes of FFC000H to FFEFFFH is reserved as an internal RAM area.
The image of FFE000H to FFEFFFH can be seen in the addresses of FFC000H to FFCFFFH.

Mask ROM
internal version

xxFFEFFFH xxFFEFFFH

Internal RAM

xxFFE000H

Note

The address FFC000H to FFCFFFH cannot be used.

Flash memory
internal version

Internal RAM

Note

Image

xxFFD000H
xxFFCFFFH

xxFFC000H

65

CHAPTER 3 CPU FUNCTIONS

(3) On-chip peripheral I/O area

A 4-Kbyte area of addresses FFF000H to FFFFFFH is reserved as an on-chip peripheral I/O area. The V850/SA1
is provided with a 1-Kbyte area of addresses FFF000H to FFF3FFH as a physical on-chip peripheral I/O area,
and its image can be seen on the rest of the area (FFF400H to FFFFFFH).
Peripheral I/O registers as sociated with the operation mode specification and the state monitoring for the on-chip
peripherals are all memory-mapped to the on chip peripheral I/O area. Program fetches are not allowed in this
area.

xxFFFFFFH

Image

xxFFFC00H

xxFFFBFFH

Image

xxFFF800H

xxFFF7FFH

Image

xxFFF400H

xxFFF3FFH

Image

xxFFF000H

Physical peripheral I/O

3FFH

Peripheral I/O

000H

Cautions 1. The least significant bit of an address is not decoded since all registers reside on an even

address. If an odd address (2n + 1) in the peripheral I/O area is referenced, the register at
the next lowest even address (2n) will be accessed.

2. If a register that can be accessed in byte units is accessed in half-word units, the higher 8
bits become undefined, if the access is a read operation. If a write access is made, only
the data in the lower 8 bits is written to the register.

3. If a register with n address that can be accessed only in halfword units is accessed with a
word operation, the operation is replaced with two halfword operations. The first
operation (lower 16 bits) accesses to the register with n address and the second
operation (higher 16 bits) accesses to the register with n + 2 address.

4. If a register with n address that can be accessed in word units is accessed with a word
operation, the operation is replaced with two halfword operations. The first operation
(lower 16 bits) accesses to the register with n address and the second operation (higher
16 bits) accesses to the register with n + 2 address.

5. Addresses that are not defined as registers are reserved for future expansion. If these
addresses are accessed, the operation is undefined and not guaranteed.

66

CHAPTER 3 CPU FUNCTIONS

(4) External memory area

The V850/SA1 can use an area of up to 100000H to FFBFFFH (16 Mbytes) for external memory accesses.
64 K, 256 K, 1 M, or 4 Mbytes of physical external memory can be allocated when the external expansion mode is
specified. In the area of other than the physical external memory, the image of the physical external memory can
be seen.
The internal RAM area and on-chip peripheral I/O area are not subject to external memory access.

Figure 3-5. External Memory Area (when expanded to 64 K, 256 K, or 1 Mbytes)

Mask ROM
internal version

xxFFFFFFH

xxFFDFFFH

xx100000H

Flash memory
internal version

xxFFFFFFH

xxFFBFFFH

xx100000H

On-chip peripheral I/O

Internal RAM

Image

Image

Image

Physical external memory

xFFFFH

External memory

x0000H

xx000000H

Internal ROM

xx000000H

67

CHAPTER 3 CPU FUNCTIONS

Figure 3-6. External Memory Area (when expanded to 4 Mbytes)

Mask ROM
internal version

xxFFFFFFH

xxFFDFFFH

xx100000H

Flash memory
internal version

xxFFFFFFH

xxFFBFFFH

xx100000H

On-chip peripheral I/O

Internal RAM

Image

Image

Image

Physical external memory

3FFFFFH

External memory

000000H

xx000000H

Internal ROM

xx000000H

68

CHAPTER 3 CPU FUNCTIONS

3.4.6 External expansion mode

The V850/SA1 allows external devices to be connected to the external memory space by using the pins of ports 4,
5, 6, and 9. To connect an external device, the port pins must be set in the external expansion mode by using the
memory expansion mode register (MM).

The address bus (A1 to A15) is set to maltiplexed output with data bus (D1 to D15), though separate output is also
available by setting the memory address output mode register (MAM) (See the User’s Manual of relevant in-circuit
emulator about debagging when using the separate bus).

Because the V850/SA1 is fixed to single-chip mode in the normal operation mode, the port/control mode alternate
pins become the port mode, thereby the external memory cannot be used. When the external memory is used
(external expansion mode), specify the MM register by the program.

(1) Memory expansion mode register (MM)

This register sets the mode of each pin of ports 4, 5, 6, and 9. In the external expansion mode, an external
device can be connected to the external memory area of up to 4 Mbytes. However, the external device cannot be
connected to the internal RAM area, on-chip peripheral I/O area, and internal ROM area in the single-chip mode
(access is restricted to external locations 100000H through FFE00H).
The MM register can be read/written in 8- or 1-bit units. However, bits 4 to 7 are fixed to 0.

69

CHAPTER 3 CPU FUNCTIONS

Figure 3-7. Memory Expansion Mode Register (MM) Format

After reset: 00H R/W Address: FFFFF04CH

Symbol76543210

MM 0 0 0 0 MM3 MM2 MM1 MM0

MM3 P95 and P96 Operation Modes

0 Port mode
1 E xternal expansion mode (HLDAK: P95, HLDRQ: P96)

MM2 MM1 MM 0 Addres s Space Port 4 Port 5 Port 6 Port 9

000 − Port mode
0 1 1 64-KB AD0 to AD8 to LBEN,

expansion mode AD7 AD15 UBEN,

1 0 0 256-KB

expansion mode

101 1-MB

expansion mode

11× 4-MB

expansion mode

Others RFU (reserved)

A16

A17

A18

A19

A20

A21

R/W, DSTB,

ASTB,

WRL,

WRH, RD

Remark

For the details of the operation of each port pin, refer to

2.3 Description of Pin Functions

.

70

CHAPTER 3 CPU FUNCTIONS

(2) Memory address output mode register (MAM)

Sets the mode of ports 3, 10, and 11. Separate output can be set for the address bus (A1 to A15) in the external
expansion mode.
Only writing in 8-bit units is available for the MAM register. If read is performed, undefined values will be read.
Bits 3 to 7 are fixed to 0.

Figure 3-8. Memory Address Output Mode Register (MAM) Format

After reset: 00H W Address: FFFFF068H

Symbol76543210

MAM 0 0 0 0 0 MAM2 MAM1 MAM0

MAM2 MAM1 MAM0 Address Space Port 11 Port 10 Port 3

000

0 1 0 32 bytes A1-A4

−

Port mode

0 1 1 512 bytes

100 8 Kbytes

1 0 1 16 Kbytes

1 1 0 32 Kbytes

1 1 1 64 Kbytes

A5-A8

A9-A12

A13

A14

A15

Caution Debugging the memory address output mode register (MAM) an in-circuit emulator is not

available. Also, setting the MAM register by software cannot switch to the separate bus.
Fordetails, refer to the relevant User’s Manual of in-circuit emulator.

Remark

For details of the operation of each port, see

2.3 Description of Pin Functions

.

71

CHAPTER 3 CPU FUNCTIONS

3.4.7 Recommended use of address space

The architecture of the V850/SA1 requires that a register that serves as a pointer be secured for address
generation in operand data accessing for data space. The address in this pointer register ±32 Kbytes can be
accessed directly from instruction. However, general register used as a pointer register is limited. Therefore, by
minimizing the deterioration of address calculation performance when changing the pointer value, the number of
usable general registers for handling variables is maximized, and the program size can be saved because instructions
for calculating pointer addresses are not requir ed.

To enhance the efficiency of using the pointer in connection with the memory map of the V850/SA1, the following
points are recommended:

(1) Program space

Of the 32 bits of the PC (program counter), the higher 8 bits are fixed to "0", and only the lower 24 bits are valid.
Therefore, a contiguous 16-Mbyte space, starting from address 00000000H, unconditionally corresponds to the
memory map of the program space.

(2) Data space

For the efficient use of resources to be performed through the wrap-around feature of the data space, the
continuous 8-Mbyte address spaces 00000000H to 007FFFFFH and FF800000H to FFFFFFFFH of the 4-Gbyte
CPU are used as the data space. With the V850/SA1, 16-Mbyte physical address space is seen as 256 images
in the 4-Gbyte CPU address space. The highest bit (bit 23) of this 24-bit address is assigned as address sign­extended to 32 bits.

72

CHAPTER 3 CPU FUNCTIONS

Application of wrap-around

For example, when R = r0 (zero register) is specified for the LD/ST disp16 [R] instruction, an addressing range of
00000000H ± 32 Kbytes can be referenced with the sign-extended, 16-bit displacement value. By mapping the
external memory in the 24-Kbyte area in the figure, all resources including on-chip hardware can be accessed
with one pointer.
The zero register (r0) is a register set to 0 by the hardware, and eliminates the need for additional registers for the
pointer.

Flash memory internal versionMask ROM internal version

0001FFFFH

00007FFFH

(R = ) 00000000H

FFFFF000H

FFFFE000H

Internal

ROM area

On-chip peripheral I/O area

Internal RAM area

External memory

area

4 KB
4 KB

24 KB

0001FFFFH
00007FFFH

(R = ) 00000000H

FFFFF000H

FFFFC000H

FFFF8000HFFFF8000H

Internal ROM
area

On-chip peripheral I/O area

Internal RAM
area

External memory
area

32 KB32 KB

4 KB

12 KB

16 KB

73

CHAPTER 3 CPU FUNCTIONS

Figure 3-9. Recommended Memory Map (Flash Memory Internal Version)

16 MB

FFFFFFFFH

FFFFF3C6H
FFFFF3C5H

FFFFF000H

FFFFEFFFH

FFFFC000H
FFFFBFFFH

FF800000H

FF7FFFFFH

01000000H

00FFFFFFH

00FFF000H

00FFEFFFH

00FFC000H

00FFBFFFH

Program space

On-chip

peripheral I/O

Internal

Note

RAM

Data space

On-chip

peripheral I/O

Internal

RAM

External
memory

On-chip

peripheral I/O

Internal

RAM

External
memory

Internal

ROM

xxFFFFFFH

xxFFF3C6H
xxFFF3C5H
xxFFF000H
xxFFEFFFH

xxFFC000H
xxFFBFFFH

xx800000H
xx7FFFFFH

xx100000H
xx0FFFFFH
xx040000H
xx03FFFFH

xx000000H

00800000H

007FFFFFH

8 MB

Note

This area cannot be us ed as a program area.

Remark

The arrows indicate the recommended area.

00100000H

000FFFFFH

00020000H

0001FFFFH

00000000H

External
memory

Internal

ROM

External
memory

Internal

ROM

74

CHAPTER 3 CPU FUNCTIONS

3.4.8 Peripheral I/O registers

Address Function Regist er Nam e S ym bol R/W

FFFFF000H Port 0 P0 R/ W
FFFFF002H Port 1 P1
FFFFF004H Port 2 P2
FFFFF006H Port 3 P3
FFFFF008H Port 4 P4
FFFFF00AH Port 5 P5
FFFFF00CH P ort 6 P6
FFFFF00EH Port 7 P7 R
FFFFF010H Port 8 P8
FFFFF012H Port 9 P9 R/W
FFFFF014H Port 10 P10
FFFFF016H Port 11 P11
FFFFF018H Port 12 P12
FFFFF020H Port 0 mode register PM0
FFFFF022H Port 1 mode register PM1
FFFFF024H Port 2 mode register PM2
FFFFF026H Port 3 mode register PM3
FFFFF028H Port 4 mode register PM4
FFFFF02AH Port 5 mode register PM5
FFFFF02CH Port 6 mode register PM6
FFFFF032H Port 9 mode register PM9
FFFFF034H Port 10 mode register PM10
FFFFF036H Port 11 mode register PM11
FFFFF038H Port 12 mode register PM12
FFFFF04CH Memory expansion mode register MM
FFFFF058H Port 12 mode control register PMC12
FFFFF060H Data wait control register DWC
FFFFF062H Bus cycle control register BCC
FFFFF064H System control register SYC
FFFFF068H Memory address output mode register MAM W
FFFFF070H Power save control register PSC R/W
FFFFF074H Processor clock control register PCC
FFFFF078H System status register SYS

Bit Units for
Manipulation After Reset

1 bit 8 bits 16 bits

{{

{{

{{

{{

{{

{{

{{

{{

{{

{{

{{

{{

{{

{{

{{

{{

{{

{{

{{

{{

{{

{{

{{

{{

{{

{{

{{

{

{{

{{

{{

Undefined

{

{

Note

00H

Note

00H

FFH

3FH

FFH

3FH
7FH

FFH

1FH
01H
00H

FFFFH

AAAAH

00H

C0H

03H
00H

(1/5)

Note

Resetting initializes registers to input mode and 00H cannot actually be read.

75

CHAPTER 3 CPU FUNCTIONS

Address Function Regist er Nam e S ym bol R/W

FFFFF080H Pull-up resistor option register 0 PU0 R/W
FFFFF082H Pull-up resistor option register 1 PU1
FFFFF084H Pull-up resistor option register 2 PU2
FFFFF086H Pull-up resistor option register 3 PU3
FFFFF094H Pull-up resistor option register 10 PU10
FFFFF096H Pull-up resistor option register 11 PU11
FFFFF0A2H Port 1 function register PF1
FFFFF0A4H Port 2 function register PF2
FFFFF0B4H Port 10 function register PF10
FFFFF0C0H Rising edge specification register 0 EGP0
FFFFF0C2H Falling edge specification register 0 EGN0
FFFFF100H Interrupt control register WDTIC
FFFFF102H Interrupt control register PIC0
FFFFF104H Interrupt control register PIC1
FFFFF106H Interrupt control register PIC2
FFFFF108H Interrupt control register PIC3
FFFFF10AH Interrupt control register PIC4
FFFFF10CH Interrupt control register PIC5
FFFFF10EH Interrupt control register PIC6
FFFFF110H Interrupt control register WTIIC
FFFFF112H Interrupt control register TMIC00
FFFFF114H Interrupt control register TMIC01
FFFFF116H Interrupt control register TMIC10
FFFFF118H Interrupt control register TMIC11
FFFFF11AH Interrupt control register TMIC2
FFFFF11CH Interrupt control register TMIC3
FFFFF11EH Interrupt control register TMIC4
FFFFF120H Interrupt control register TMIC5
FFFFF122H Interrupt control register CSIC0
FFFFF124H Interrupt control register SERIC0
FFFFF126H Interrupt control register CSIC1
FFFFF128H Interrupt control register STIC0
FFFFF12AH Interrupt control register CSIC2
FFFFF12CH Interrupt control register SERIC1
FFFFF12EH Interrupt control register SRIC1

Bit Units for
Manipulation After Reset

1 bit 8 bits 16 bits

{{

{{

{{

{{

{{

{{

{{

{{

{{

{{

{{

{{

{{

{{

{{

{{

{{

{{

{{

{{

{{

{{

{{

{{

{{

{{

{{

{{

{{

{{

{{

{{

{{

{{

{{

(2/5)

00H

47H

76

CHAPTER 3 CPU FUNCTIONS

Address Function Regist er Nam e Sym bol R/W

FFFFF130H Interrupt control register STIC1 R/W
FFFFF132H Interrupt control register ADIC
FFFFF134H Interrupt control register DMAIC0
FFFFF136H Interrupt control register DMAIC1
FFFFF138H Interrupt control register DMAIC2
FFFFF13AH Interrupt control register WTIC
FFFFF166H In-service priority register ISPR R
FFFFF170H Command register PRCMD W
FFFFF180H DMA peripheral I/O address register 0 DIOA 0 R/W
FFFFF182H DMA internal RAM address register 0 DRA0
FFFFF184H DMA byte count register 0 DBC0
FFFFF186H DMA channel control register 0 DCHC0
FFFFF190H DMA peripheral I/O address register 1 DIOA 1
FFFFF192H DMA internal RAM address register 1 DRA1
FFFFF194H DMA byte count register 1 DBC1
FFFFF196H DMA channel control register 1 DCHC1
FFFFF1A0H DMA peripheral I/O address register 2 DIOA2
FFFFF1A2H DMA internal RAM address register 2 DRA2
FFFFF1A4H DMA byte count register 2 DBC2
FFFFF1A6H DMA channel control register 2 DCHC2
FFFFF200H 16-bit timer register 0 TM0 R
FFFFF202H 16-bit capture/compare register 00 CR00
FFFFF204H 16-bit capture/compare register 01 CR01

Note
Note

FFFFF206H Prescaler mode register 0 PRM0 R/W
FFFFF208H 16-bit timer mode control register 0 TMC0
FFFFF20AH Capture/compare control register 0 CRC0
FFFFF20CH Timer output control register 0 TOC0
FFFFF210H 16-bit timer register 1 TM1 R
FFFFF212H 16-bit capture/compare register 10 CR10
FFFFF214H 16-bit capture/compare register 11 CR11

Note
Note

FFFFF216H Prescaler mode register 1 PRM1 R/W
FFFFF218H 16-bit timer mode control register 1 TMC1
FFFFF21AH Capture/compare control register 1 CRC1
FFFFF21CH Timer output control register 1 TOC1

Bit Units for
Manipulation After Reset

1 bit 8 bits 16 bits

{{

{{

{{

{{

{{

{{

{{

{

{

{

{

{

{

{

{

{

{

{

{

Undefined

Undefined

Undefined

{

{

{{

{

{{

{

{{

{

{{

{{

{{

{

{{

{{

{{

(3/5)

47H

00H

00H

00H

00H

0000H

00H

0000H

00H

Note

At compare mode: R/W
At capture mode : R

77

CHAPTER 3 CPU FUNCTIONS

Address Function Regist er Nam e S ym bol R/W

FFFFF240H 8-bit counter 2 TM2 R
FFFFF242H 8-bit compare register 2 CR20 R/W
FFFFF244H Timer clock selection register 2 TCL2
FFFFF246H 8-bit timer mode control register 2 TMC2
FFFFF24AH 16-bit counter 23 TM23 R
FFFFF24CH 16-bit compare register 23 CR23 R/W
FFFFF250H 8-bit counter 3 TM3 R
FFFFF252H 8-bit compare register 3 CR30 R/W
FFFFF254H Timer clock selection register 3 TCL3
FFFFF256H 8-bit timer mode control register 3 TMC3
FFFFF260H 8-bit counter 4 TM4 R
FFFFF262H 8-bit compare register 4 CR40 R/W
FFFFF264H Timer clock selection register 4 TCL4
FFFFF266H 8-bit timer mode control register 4 TMC4
FFFFF26AH 16-bit counter 45 TM45 R
FFFFF26CH 16-bit compare register 45 CR45 R/W
FFFFF270H 8-bit counter 5 TM5 R
FFFFF272H 8-bit compare register 5 CR50 R/W
FFFFF274H Timer clock selection register 5 TCL5
FFFFF276H 8-bit timer mode control register 5 TMC5
FFFFF2A0H Serial I/O shift register 0 SIO0
FFFFF2A2H Serial operation mode register 0 CSIM0
FFFFF2A4H Serial clock selection register 0 CSIS0
FFFFF2B0H Serial I/O shift register 1 SIO1
FFFFF2B2H Serial operation mode register 1 CSIM1
FFFFF2B4H Serial clock selection register 1 CSIS1
FFFFF2C0H Serial I/O shift register 2 SIO2
FFFFF2C2H Serial operation mode register 2 CSIM2
FFFFF2C4H S erial clock selection register 2 CSIS2
FFFFF300H Asynchronous serial interface mode register 0 ASIM0
FFFFF302H Asynchronous serial interface status register 0 ASIS0 R
FFFFF304H Baud rate generator control register 0 BRGC0 R/W
FFFFF306H Transmission shift register 0 TXS0 W
FFFFF308H Reception buffer register 0 RXB 0 R
FFFFF30EH Baud rate generator mode control register 0 BRGMC0 R/W

Bit Units for
Manipulation After Reset

1 bit 8 bits 16 bits

{

{

{

{{

{

{

{

{

{

{{

{

{

{

{{

{

{

{

{

{

{{

{

{{

{{

{

{{

{{

{

{{

{{

{{

{{

{

{

{

{

(4/5)

00H

04H

0000H

00H

04H
00H

04H

0000H

00H

04H
00H

00H

00H

FFH

00H

78

CHAPTER 3 CPU FUNCTIONS

Address Function Regist er Nam e Sym bol R/W

FFFFF310H Asynchronous serial interface mode register 1 ASIM1 R/W
FFFFF312H Asynchronous serial interface status register 1 ASIS1 R
FFFFF314H Baud rate generator control register 1 BRGC1 R/W
FFFFF316H Transmission shift register 1 TXS1 W
FFFFF318H Reception buffer register 1 RXB 1 R
FFFFF31EH Baud rate generator mode control register 1 BRGMC1 R/W

Note

Note

Note

Note

Note

IICC0
IICS0 R
IICCL0 R/W
SVA0
IIC0

FFFFF340H
FFFFF342H
FFFFF344H
FFFFF346H
FFFFF348H

IIC control register
IIC state register
IIC clock selection register
Slave address register

IIC shift register
FFFFF360H Watch timer mode register WTM
FFFFF380H Oscillation stable time selection register OSTS
FFFFF382H Watchdog timer clock selection register WDCS
FFFFF384H Watchdog timer mode register WDTM
FFFFF3A0H Real-time output buffer register L RTBL
FFFFF3A2H Real-time output buffer register H RTBH
FFFFF3A4H Real-time output port mode register RTPM
FFFFF3A6H Real-time output port control register RTPC
FFFFF3C0H A /D converter mode register ADM
FFFFF3C2H Analog input channel specification register ADS
FFFFF3C4H A /D conversion result register ADCR R
FFFFF3C6H A/D conversion result register (higher 8 bits) ADCRH

Bit Units for
Manipulation After Reset

1 bit 8 bits 16 bits

{{

{{

{

{

{

{

{{

{{

{{

{

{

{{

{

{

{{

{

{

{{

{{

{{

{{

{

{

(5/5)

00H

FFH

00H

04H
00H

0000H

00H

Note

µ

PD703015Y and 70F3017Y only

79

CHAPTER 3 CPU FUNCTIONS

3.4.9 Specific registers

Specific registers are registers that are protected from being written wi th illegal data due to erroneous program
execution, etc. The write access of these specific registers is executed in a specific sequence, and if abnormal store
operations occur, it is notified by the system status register (SYS). The V850/SA1 has two specific registers, the
power save control regis ter (PSC) and processor clock control register (PCC). For details of the PSC register, refer to

6.3.1 (2),

and for details of the PCC register, refer to

The following sequence shows the data setting of the specific registers.

<1> DMA operation is disabled.
<2> Set the PSW NP bit to 1 (interrupt disabled).
<3> Write any 8-bit data in the command register (PRCMD).
<4> Write the set data in the specific registers (by the following instructions).

• Store instruction (ST/SST instruction)

• Bit manipulation instruction (SET1/CLR1/NOT1 instruction)

<5> Return the PSW NP bit to 0 (interrupt disable canceled).
<6> Insert the NOP instructions (2 or 5 instructions).
<7> Enable DMA operation if required.

6.3.1 (1).

No special sequence is required when reading the specific registers.

Caution 1. If an interrupt request is accepted between the time PRCMD is issued <3> and the specific

register write operation <4> that follows immediately after, the write operation to the specific
register is not performed and a protection error (PRERR bit of SYS register is “1”) may occur.
Therefore, set the NP bit of PSW to 1 <2> to disable the acceptance of INT/NMI.
The above also applies when a bit manipulation instruction is used to set a specific register.
Moreover, to ensure that the execution routine following release of the STOP/IDLE mode is
performed correctly, insert the NOP instruction as a dummy instruction <6>. If the value of
the ID bit of PSW does not change as the result of execution of the instruction to return the NP
bit to 0 <5>, insert two NOP instructions, and if the value of the ID bit of PSW changes, insert
five NOP instructions.

80

CHAPTER 3 CPU FUNCTIONS

A description example is given below.

[Description example]: In case of PSC register
LDSR rX,5 ; NP bit = 1
ST.B r0,PRCMD [r0] ; Write to PRCMD
ST.B rD,PSC [r0] ; PSC register setting
LDSR rY,5 ; NP bit = 0
NOP ; Dummy instruction (2 or 5 instructions)

NOP
(next instruction) ; Execution routine following cancellation of STOP/IDLE mode

When saving the value of PSW, the value of PSW prior to setting the NP bit must be
transferred to the rY register.

.
.
.

.
.
.

rX: Value to be written to PSW
rY: Value to be written back to PSW
rD: Value to be set to PSC

Caution 2. The instructions (<5> interrupt disable cancel, <6> NOP instruction) following the store

instruction for the PSC register for setting the software STOP mode and IDLE mode are
executed before a power save mode is entered.

3. Be sure to stop DMA before a specific register is accessed.

81

CHAPTER 3 CPU FUNCTIONS

(1) Command register (PRCMD)

The command register (PRCMD) is a register used when write-accessing the specific register to prevent incorrect
writing to the specific registers due to the erroneous program execution.
This register can be written in 8-bit units. It becomes undefined values in a read cycle.
Occurrence of illegal store operations can be checked by the PRERR bit of the SYS register.

After reset: Undefined W Address: FFFFF170H

Symbol76543210

PRCMD REG7 REG6 REG5 REG4 REG3 REG2 REG1 REG0

REGn Registration Code

0/1 Any 8-bit data

(2) System status register (SYS)

This register is allocated with status flags showing the operating state of the entire system. This register can be
read/written in 8- or 1-bit units.

After reset: 00H R/W Address: FFFFF078H

Symbol76543210

SYS 0 0 0 PRERR 0 0 0 0

PRERR Detection of Protection Error

0 Protection error does not occur
1 Protection error occurs

Operation conditions of PRERR flag are shown as follows.

(a) Set conditions (PRERR = “1”)

(1) If the store instruction most recently executed to peripheral I/O does not write data to the PRCMD

register, but to the specific register.

(2) If the first store instruction executed after the write operation to the PRCMD register is to a peripheral I/O

register other than the specific registers.

(b) Reset conditions: (PRERR = “0”)

(1) When “0” is written to the PRERR flag of the SYS register.
(2) At system reset.

82

CHAPTER 4 BUS CONTROL FUNCTION

The V850/SA1 is provided with an external bus interface function by which external memories such as ROM and

RAM, and I/O can be connected.

4.1 Features

• 16-bit data bus

• External devices connected through multiplexed I/O port pins

• Wait function

• Programmable wait function, capable of inserting up to 3 wait states per 2 blocks

• External wait control through WAIT input pin

• Idle state insertion function

• Bus mastership arbitration function

• Bus hold function

4.2 Bus Control Pins and Control Register

4.2.1 Bus control pins

The following pins are used for interfacing to external devices:

External Bus Interf ace Function Corresponding Port (pins)
Address/data bus (AD0 to AD7) Port 4 (P40 to P47)
Address/data bus (AD8 to AD15) Port 5 (P 50 to P57)
Address bus (A16 to A21) Port 6 (P60 to P65)
Read/write control (LBEN, UBEN, R/W, DSTB, WRL, WRH, RD) Port 9 (P90 to P93)
Address strobe (ASTB ) Port 9 (P94)
Bus hold control (HLDRQ, HLDAK) Port 9 (P95, P96)
External wait control (WA IT) Port 12 (P120)

The bus interface function of each pin is enabled by specifying the memory expansion mode register (MM). For

the details of specifying an operation mode of the external bus interface, refer to

register (MM)

.

3.4.6 (1) Memory expansion mode

Caution For debugging using the separate bus, refer to the user’s manual of corresponding in-circuit

emulator.

83

CHAPTER 4 BUS CONTROL FUNCTION

4.2.2 Control register

(1) System control register (SYC)

This register switches control signals for bus interface.
The system control register can be read/written in 8- or 1-bit units.

After reset: 00H R/W Addres s: FFFFF064H

Symbol

SYC0000000BIC

76

BIC Bus Interface Control

0 DSTB, R/W, UBEN, LBEN signal outputs
1 RD, WRL, WRH, UBEN signal outputs

54

3210

4.3 Bus Access

4.3.1 Number of access clocks

The number of basic clocks necessary for accessing each resource is as follows:

Peripheral I/O (bus width)

Bus Cycle Type Internal ROM

(32 bits)
Instruction fetch 1 3 Disabled 3 + n
Operand data access 3 1 3 3 + n

Remarks 1.

Unit : Clock/access

2.

n : Number of wait insertions

Internal RAM

(32 bits)

Peripheral I/O

(16 bits)

External Memory

(16 bits)

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CHAPTER 4 BUS CONTROL FUNCTION

4.3.2 Bus width

CPU carries out peripheral I/O access and external memory access in 8-, 16-, or 32-bit. The following shows the

operation for each access.

(1) Byte access (8 bits)

Byte access is divided into two types, the access to even address and the access to odd address.

(a) Access to even address

15

7

0

Byte data External data bus

8
7

0

(b) Access to odd address

15

7

0

Byte data External data bus

8
7

0

(2) Halfword access (16 bits)

In halfword access to external memory, data is dealt with as it is because the data bus is fixed to 16 bits.

1515

00

Halfword data External data bus

(3) Word access (32 bits)

In word access to external memory, lower halfword is accessed first and then the upper halfword is accessed.

First

31

16
15

0
Word data External data bus

15

0

Second

31

16
15

0
Word data External data bus

15

0

85

CHAPTER 4 BUS CONTROL FUNCTION

4.4 Memory Block Function

The 16-Mbyte memory space is divided into memory blocks of 1-Mbyte units. The programmable wait function

and bus cycle operation mode can be independently controlled for every two memory blocks.

FFFFFFH

F00000H

EFFFFFH

E00000H

DFFFFFH

D00000H

CFFFFFH

C00000H

BFFFFFH

B00000H

AFFFFFH

A00000H

9FFFFFH

900000H

8FFFFFH

800000H

7FFFFFH

700000H

6FFFFFH

600000H

5FFFFFH

500000H

4FFFFFH

400000H

3FFFFFH

300000H

2FFFFFH

200000H

1FFFFFH

100000H

0FFFFFH

000000H

Block 15

Block 14

Block 13

Block 12

Block 11

Block 10

Block 9

Block 8

Block 7

Block 6

Block 5

Block 4

Block 3

Block 2

Block 1

Block 0

Peripheral I/O area

Internal RAM area

External memory area

Internal ROM area

86

CHAPTER 4 BUS CONTROL FUNCTION

4.5 Wait Function

4.5.1 Programmable wait function

To facilitate interfacing with low-speed memories and I/O devices, up to 3 data wait states can be inserted in a bus
cycle for two memory blocks. The number of wait states can be programmed by using data wait control register
(DWC). Immediately after the system has been reset, three data wait states are automatically programmed for all
memory blocks.

(1) Data wait control register (DWC)

This register can be read/written in 16-bit units.

After reset: FFFFH R/W Address: FFFFF060H

Symbol1514131211109876543210

DWC

DW61

DW00DW01DW10DW11DW20DW21DW30DW31DW40DW41DW50DW51DW60DW70DW71

DWn0DWn1
00 0
01 1
10 2
11 3

n Blocks into Which Wait States Are Inserted
0 Blocks 0/1
1 Blocks 2/3
2 Blocks 4/5
3 Blocks 6/7
4 Blocks 8/9
5 Blocks 10/11
6 Blocks 12/13
7 Blocks 14/15

Number of Wait States t o be I nserted

Block 0 is reserved for the internal ROM area. It is not subject to programmable wait control, regardless of the
setting of DWC, and is always accessed without wait states.
The internal RAM area of block 15 is not subject to programmable wait control and is always accessed without
wait states. The on-chip peripheral I/O area of this block is not subject to programmable wait control, either. The
only wait control is dependent upon the execution of each peripheral function.

87

CHAPTER 4 BUS CONTROL FUNCTION

4.5.2 External wait function

When an extremely slow device, I/O, or asynchronous system is connected, any number of wait states can be in-

serted in a bus cycle by sampling the external wait pin (WAIT) to synchronize with the external device.

The external WAIT signal does not affect the access times of the internal ROM, internal RAM, and on-chip periph­eral I/O areas. Input of the external WAIT signal can be done asynchronously to CLKOUT and is sampled at the fal­ling edge of the clock in the T2 and TW states of a bus cycle. If the setup/hold time of the WAIT input are not satis­fied, the wait state may or may not be inserted in the next state.

4.5.3 Relations between programmable wait and external wait

A wait cycle is inserted as a result of an OR operation between the wait cycle specified by the set value of pro­grammable wait and the wait cycle controlled by the WAIT pin. In other words, the number of wait cycles is deter­mined by the programmable wait value or the length of evaluation at the WAIT input pin.

Programmable wait

Wait control

Wait by WAIT pin

For example, if the number of programmable wait and the timing of the WAIT pin input signal is as illustrated be­low, three wait states will be inserted in the bus cycle.

Figure 4-1. Example of Inserting Wait States

T2 TW TW TW T3

Remark

T1

CLKOUT

WAIT pin

Wait by WAIT pin

Programmable wait

Wait control

{: valid sampling timing

88

CHAPTER 4 BUS CONTROL FUNCTION

4.6 Idle State Insertion Function

To facilitate interfacing with low-speed memory devices and meeting the data output float delay time on memory
read accesses, one idle state (TI) can be inserted into the current bus cycle after the T3 state. The bus cycle follow­ing continuous bus cycles starts after one idle state.

Specifying insertion of the idle state is programmable by using the bus cycle control register (BCC).

Immediately after the system has been reset, idle state insertion is automatically programmed for all memory
blocks.

(1) Bus cycle control register (BCC)

This register can be read/written in 16-bit units.

After reset: AAAAH R/W Address: FFFFF062H

Symbol1514131211109876543210

BCC

BCn1

0 Not inserted
1 Inserted

n Blocks into Which Idle State Is Inserted
0 Blocks 0/1
1 Blocks 2/3
2 Blocks 4/5
3 Blocks 6/7
4 Blocks 8/9
5 Blocks 10/11
6 Blocks 12/13
7 Blocks 14/15

Idle State Insert S pecification

Block 0 is reserved for the internal ROM area; therefore, no idle state is specified regardless of the BCC setting.
The internal RAM area and on-chip peripheral I/O area of block 15 are not subject to insertion of the idle state.
Be sure to set bits 0, 2, 4, 6, 8, 10, 12, and 14 to 0. If these bits are set to 1, the operation is not guaranteed.

0BC010BC110BC210BC310BC410BC510BC610BC71

89

CHAPTER 4 BUS CONTROL FUNCTION

4.7 Bus Hold Function

4.7.1 Outline of function

MM3 bit of the memory expansion register (MM) is set (1), the HLDRQ and HLDAK pin functions of P95 and P96

become valid.

When the HLDRQ pin becomes active (low) indicating that another bus master is requesting acquisition of the bus,
the external address/data bus and strobe pins go into a high-impedance state
status). When the HLDRQ pin becomes inactive (high) indicating that the request for the bus is cleared, these pins
are driven again.

During bus hold period, the internal operation continues until the next external memory access.

In the bus hold status, the HLDAK pin becomes active (low).

This feature can be used to design a system where two or more bus masters exist, such as when multi-processor
configuration is used and when a DMA controller is connected.

Bus hold request is not acknowledged between the first and the second word access. Bus hold request is also not
acknowledged between read access and write access in read modify write access of bit manipulation instruction.

Note

A1 to A15 pins are retained when the separate bus is used.

Note

, and the bus is released (bus hold

90

CHAPTER 4 BUS CONTROL FUNCTION

4.7.2 Bus hold procedure

The procedure of the bus hold function is illustrated below.

<1>HLDRQ = 0 accepted
<2>All bus cycle start request pending
<3>End of current bus cycle
<4>Bus idle status
<5>HLDAK = 0

<6>HLDRQ = 1 accepted
<7>HLDAK = 1
<8>Clears bus cycle start request pending
<9>Start of bus cycle

HLDRQ

HLDAK

<1><2><3><4><5><

4.7.3 Operation in power save mode

Nomal status

Bus hold status

Normal status

7

><8><9><6>

In the STOP or IDLE mode, the system clock is stopped. Consequently, the bus hold status is not set even if the

HLDRQ pin becomes active.

In the HALT mode, the HLDAK pin immediately becomes active when the HLDRQ pin becomes active, and the
bus hold status is set. When the HLDRQ pin becomes inactive, the HLDAK pin becomes inactive. As a result, the
bus hold status is cleared, and the HALT mode is set again.

91

CHAPTER 4 BUS CONTROL FUNCTION

4.8 Bus Timing

The V850/SA1 can execute the read/write control for an external device by the following two modes.

• Mode using DSTB, R/W, LBEN, UBEN, and ASTB signals

• Mode using RD, WRL, WRH, and ASTB signals

Set these modes by using the BIC bit of the system control register (SYC).

(1) Memory read (0 wait)

T1 T2 T3

CLKOUT (input)

A16 to A21 (output)

A1 to A15 (output)

AD0 to AD15

(input/output)

ASTB (output)

R/W (output)

WRH, WRL (output)

DSTB, RD (output)

Address

Address

DataAddress

H

92

Remarks 1.

UBEN, LBEN (output)

WAIT (input)

{ indicates the sampling timing when the number of programmable waits is set to 0.

2.

The broken line indicates the high-impedance state.

(2) Memory read (1 wait)

CHAPTER 4 BUS CONTROL FUNCTION

CLKOUT (input)

A16 to A21 (output)

A1 to A15 (output)

AD0 to AD15
(input/output)

ASTB (output)

R/W (output)

T1 T2 TW

Address

Address

Address

T3

Data

WRH, WRL (output)

DSTB, RD (output)

UBEN, LBEN (output)

WAIT (input)

Remarks 1.

{ indicates the sampling timing when the number of programmable waits is set to 0.

2.

The broken line indicates the high-impedance state.

H

93

(3) Memory read (0 wait, idle state)

CHAPTER 4 BUS CONTROL FUNCTION

CLKOUT (input)

A16 to A21 (output)

A1 to A15 (output)

AD0 to AD15
(input/output)

ASTB (output)

R/W (output)

T1 T2 T3

Address

Address

Address

Data

TI

WRH, WRL (output)

DSTB, RD (output)

UBEN, LBEN (output)

WAIT (input)

Remarks 1.

{ indicates the sampling timing when the number of programmable waits is set to 0.

2.

The broken line indicates the high-impedance state.

H

94

(4) Memory read (1 wait, idle state)

CHAPTER 4 BUS CONTROL FUNCTION

CLKOUT (input)

A16 to A21 (output)

A1 to A15 (output)

AD0 to AD15
(input/output)

ASTB (output)

R/W (output)

T1 T2 TW

Address

Address

Address

Data

T3

TI

WRH, WRL (output)

DSTB, RD (output)

UBEN, LBEN (output)

WAIT (input)

Remarks 1.

2.

H

{ indicates the sampling timing when the number of programmable waits is set to 0.
The broken line indicates the high-impedance state.

95

(5) Memory write (0 wait)

CLKOUT (input)

CHAPTER 4 BUS CONTROL FUNCTION

T1 T2 T3

A16 to A21 (output)

A1 to A15 (output)

AD0 to AD15
(input/output)

ASTB (output)

R/W (output)

RD (output)

H

Address

Address

Address

Data

Note

96

UBEN, LBEN (output)

Note

AD0 to AD7 output invalid data when odd address byte data is accessed.
AD8 to AD15 output invalid data when even address byte data is accessed.

Remarks 1.

DSTB (output)

WRH, WRL (output)

WAIT (input)

{ indicates the sampling timing when the number of programmable waits is set to 0.

2.

The broken line indicates the high-impedance state.

(6) Memory write (1 wait)

CHAPTER 4 BUS CONTROL FUNCTION

CLKOUT (input)

A16 to A21 (output)

A1 to A15 (output)

AD0 to AD15

(input/output)

ASTB (output)

R/W (output)

T1 T2 TW

Address

Address

Address

Data

T3

Note

RD (output)

DSTB (output)

WRH, WRL (output)

UBEN, LBEN (output)

WAIT (input)

Note

AD0 to AD7 output invalid data when odd address byte data is accessed.

H

AD8 to AD15 output invalid data when even address byte data is accessed.

Remarks 1.

{ indicates the sampling timing when the number of programmable waits is set to 0.

2.

The broken line indicates the high-impedance state.

97

(7) Bus hold timing

CLKOUT (input)

CHAPTER 4 BUS CONTROL FUNCTION

T2 T3 TH TH TH TH TI T1

HLDRQ (input)

HLDAK (output)

A16 to A21 (output)

A1 to A15 (output)

AD0 to AD15

(input/output)

ASTB (output)

R/W (output)

DSTB, RD,
WRH, WRL (output)

Address

Address

Data

Note1

Note2

Address

Undefined

Address

Address

UBEN, LBEN (output)

WAIT (input)

Notes 1.

2.

Remarks 1.

98

If HLDRQ signal is inactive (high-level) at the sampling timing, bus hold state is not entered.
If transmitted to bus hold status after write cycle, high-level may be output momentarily from R/W
pin immediately before HLDAK signal transmits from high-level to low-level.

{ indicates the sampling timing when the number of programmable waits is set to 0.

2.

The broken line indicates the high-impedance state.

CHAPTER 4 BUS CONTROL FUNCTION

4.9 Bus Priority

There are four external bus cycles: bus hold, operand data access, instruction fetch (branch), and instruction fetch
(continuous). The bus hold cycle is given the highest priority, followed by operand data access, instruction fetch
(branch), and instruction fetch (continuous) in that order.

The instruction fetch cycle may be inserted in between the read access and write access of read-modify-write ac­cess.

No instruction fetch cycle and bus hold are inserted between the lower half-word access and higher half-word ac­cess of word operations.

Table 4-1. Bus Priority

External Bus Cycle Priority
Bus hold 1
Operand data access 2
Instruction fetch (branch) 3
Instruction fetch (continuous) 4

4.10 Memory Boundary Operation Condition

4.10.1 Program space

(1) Do not execute branch to the on-chip peripheral I/O area or continuous fetch from the internal RAM area to pe-

ripheral I/O area. Of course, it is impossible to fetch from external memory. If branch or instruction fetch is exe­cuted nevertheless, the NOP instruction code is continuously fetched.

(2) A prefetch operation straddling over the on-chip peripheral I/O area (invalid fetch) does not take place if a branch

instruction exists at the upper-limit address of the internal RAM area.

4.10.2 Data space

Only the address aligned at the half-word (when the least significant bit of the address is “0”)/word (when the low-

est 2 bits of the address are “0”) boundary is accessed for data half-word (16 bits)/word (32 bits) long.

Therefore, access that straddles over the memory or memory block boundary does not take place.
For the details, refer to

V850 Family User’s Manual Architecture

.

99

[MEMO]

100