Page 1
User’s Manual
V850ES/KE1+
32-bit Single-Chip Microcontrollers
Hardware
μ
PD703302
μ
PD703302Y
μ
PD70F3302
μ
PD70F3302Y
Document No. U16896EJ2V0UD00 (2nd edition)
Date Published August 2006 N CP(K)
Printed in Japan
2004
Page 2
[MEMO]
2
User’s Manual U16896EJ2V0UD
Page 3
NOTES FOR CMOS DEVICES
1
VOLTAGE APPLICATION WAVEFORM AT INPUT PIN
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the
IL
CMOS device stays in the area between V
malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed,
and also in the transition period when the input level passes through the area between V
V
IH
(MIN).
HANDLING OF UNUSED INPUT PINS
2
Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is
possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to V
via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must
be judged separately for each device and according to related specifications governing the device.
3
PRECAUTION AGAINST ESD
A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as
much as possible, and quickly dissipate it when it has occurred. Environmental control must be
adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that
easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static
container, static shielding bag or conductive material. All test and measurement tools including work
benches and floors should be grounded. The operator should be grounded using a wrist strap.
Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for
PW boards with mounted semiconductor devices.
(MAX) and VIH (MIN) due to noise, etc., the device may
IL
(MAX) and
DD
or GND
4
STATUS BEFORE INITIALIZATION
Power-on does not necessarily define the initial status of a MOS device. Immediately after the power
source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does
not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the
reset signal is received. A reset operation must be executed immediately after power-on for devices
with reset functions.
5
POWER ON/OFF SEQUENCE
In the case of a device that uses different power supplies for the internal operation and external
interface, as a rule, switch on the external power supply after switching on the internal power supply.
When switching the power supply off, as a rule, switch off the external power supply and then the
internal power supply. Use of the reverse power on/off sequences may result in the application of an
overvoltage to the internal elements of the device, causing malfunction and degradation of internal
elements due to the passage of an abnormal current.
The correct power on/off sequence must be judged separately for each device and according to related
specifications governing the device.
6
INPUT OF SIGNAL DURING POWER OFF STATE
Do not input signals or an I/O pull-up power supply while the device is not powered. The current
injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and
the abnormal current that passes in the device at this time may cause degradation of internal elements.
Input of signals during the power off state must be judged separately for each device and according to
related specifications governing the device.
User’s Manual U16896EJ2V0UD
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Caution:
IECUBE is a registered trademark of NEC Electronics Corporation in Japan and Germany.
MINICUBE is a registered trademark of NEC Electronics Corporation in Japan and Germany or a trademark in
the United States of America.
EEPROM is a trademark of NEC Electronics Corporation.
Windows and Windows NT are either registered trademarks or trademarks of Microsoft Corporation in
the United States and/or other countries.
SuperFlash is a registered trademark of Silicon Storage Technology, Inc. in several countries
including the United States and Japan.
PC/AT is a trademark of International Business Machines Corporation.
SPARCstation is a trademark of SPARC International, Inc.
Solaris and SunOS are trademarks of Sun Microsystems, Inc.
μ
PD70F3302 and 70F3302Y use SuperFlash® technology licensed from Silicon Storage
Technology, Inc.
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User’s Manual U16896EJ2V0UD
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These commodities, technology or software, must be exported in accordance
with the export administration regulations of the exporting country.
Diversion contrary to the law of that country is prohibited.
•
The information in this document is current as of February, 2006. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC Electronics data
sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not
all products and/or types are available in every country. Please check with an NEC Electronics sales
representative for availability and additional information.
•
No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may
appear in this document.
•
NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from the use of NEC Electronics products listed in this document
or any other liability arising from the use of such products. No license, express, implied or otherwise, is
granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.
Descriptions of circuits, software and other related information in this document are provided for illustrative
•
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of a customer's equipment shall be done under the full
responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by
customers or third parties arising from the use of these circuits, software and information.
•
While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products,
customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To
minimize risks of damage to property or injury (including death) to persons arising from defects in NEC
Electronics products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment and anti-failure features.
•
NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and
"Specific".
The "Specific" quality grade applies only to NEC Electronics products developed based on a customerdesignated "quality assurance program" for a specific application. The recommended applications of an NEC
Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of
each NEC Electronics product before using it in a particular application.
"Standard":
"Special":
"Specific":
Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots.
Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support).
Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC
Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications
not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to
determine NEC Electronics' willingness to support a given application.
(Note)
(1)
"NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its
majority-owned subsidiaries.
(2)
"NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as
defined above).
M8E 02. 11-1
User’s Manual U16896EJ2V0UD
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PREFACE
Readers This manual is intended for users who wish to understand the functions of the
V850ES/KE1+ and design application systems using these products.
Purpose This manual is intended to give users an understanding of the hardware functions of the
V850ES/KE1+ shown in the Organization below.
Organization This manual is divided into two parts: Hardware (this manual) and Architecture (V850ES
Architecture User’s Manual).
Hardware Architecture
• Pin functions
• CPU function
• On-chip peripheral functions
• Flash memory programming
• Electrical specifications
How to Read This Manual It is assumed that the readers of this manual have general knowledge in the fields of
electrical engineering, logic circuits, and microcontrollers.
To find the details of a register where the name is known
→ Refer to APPENDIX C REGISTER INDEX.
To understand the details of an instruction function
→ Refer to the V850ES Architecture User’s Manual.
Register format
→ The name of the bit whose number is in angle brackets (<>) in the figure of the
register format of each register is defined as a reserved word in the device file.
To understand the overall functions of the V850ES/KE1+
→ Read this manual according to the CONTENTS.
To know the electrical specifications of the V850ES/KE1+
→ Refer to CHAPTER 28 ELECTRICAL SPECIFICATIONS.
The “yyy bit of the xxx register” is described as the “xxx.yyy bit” in this manual. Note with
caution that even if “xxx.yyy” is described as is in a program, however, the
compiler/assembler cannot recognize it correctly.
The mark <R> shows major revised points. The revised points can be easily searched by
copying an “<R>” in the PDF file and specifying it in the “Find what:” field.
• Data types
• Register set
• Instruction format and instruction set
• Interrupts and exceptions
• Pipeline operation
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User’s Manual U16896EJ2V0UD
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Conventions Data significance: Higher digits on the left and lower digits on the right
Active low representation: xxx (overscore over pin or signal name)
Memory map address: Higher addresses on the top and lower addresses on the bottom
Note: Footnote for item marked with Note in the text
Caution: Information requiring particular attention
Remark: Supplementary information
Numeric representation: Binary ... xxxx or xxxxB
Decimal ... xxxx
Hexadecimal ... xxxxH
Prefix indicating power of 2 (address space, memory capacity):
K (kilo): 2
10
= 1,024
M (mega): 220 = 1,0242
G (giga): 2
30
= 1,0243
Related Documents The related documents indicated in this publication may include preliminary versions.
However, preliminary versions are not marked as such.
Documents related to V850ES/KE1+
Document Name Document No.
V850ES Architecture User’s Manual U15943E
V850ES/KE1+ Hardware User’s Manual This manual
Documents related to development tools (user’s manuals)
Document Name Document No.
QB-V850MINI (On-Chip Debug Emulator) U17638E
QB-V850ESKX1H (In-Circuit Emulator) U17214E
CA850 Ver. 3.00 C Compiler Package
PM+ Ver. 6.00 Project Manager U17178E
ID850QB Ver. 3.10 Integrated Debugger Operation U17435E
RX850 Ver. 3.20 or Later Real-Time OS
RX850 Pro Ver. 3.20 Real-Time OS
AZ850 Ver. 3.30 System Performance Analyzer U17423E
PG-FP4 Flash Memory Programmer U15260E
Operation U17293E
C Language U17291E
Assembly Language U17292E
Link Directive U17294E
Basics U13430E
Installation U17419E
Technical U13431E
Task Debugger U17420E
Basics U13773E
Installation U17421E
Technical U13772E
Task Debugger U17422E
User’s Manual U16896EJ2V0UD
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CONTENTS
CHAPTER 1 INTRODUCTION..................................................................................................................17
1.1 K1 Series Product Lineup ......................................................................................................... 17
1.1.1 V850ES/Kx1+, V850ES/Kx1 products lineup................................................................................. 17
1.1.2 78K0/Kx1+, 78K0/Kx1 products lineup .......................................................................................... 20
1.2 Features ...................................................................................................................................... 23
1.3 Applications................................................................................................................................ 24
1.4 Ordering Information ................................................................................................................. 24
1.5 Pin Configuration (Top View).................................................................................................... 25
1.6 Function Block Configuration................................................................................................... 27
1.7 Overview of Functions............................................................................................................... 31
CHAPTER 2 PIN FUNCTIONS ................................................................................................................32
2.1 List of Pin Functions.................................................................................................................. 32
2.2 Pin I/O Circuits and Recommended Connection of Unused Pins......................................... 36
2.3 Pin I/O Circuits............................................................................................................................ 38
CHAPTER 3 CPU FUNCTIONS...............................................................................................................40
3.1 Features ...................................................................................................................................... 40
3.2 CPU Register Set........................................................................................................................ 41
3.2.1 Program register set ...................................................................................................................... 42
3.2.2 System register set ........................................................................................................................ 43
3.3 Operating Modes ........................................................................................................................ 49
3.4 Address Space ........................................................................................................................... 50
3.4.1 CPU address space....................................................................................................................... 50
3.4.2 Wraparound of CPU address space .............................................................................................. 51
3.4.3 Memory map.................................................................................................................................. 52
3.4.4 Areas ............................................................................................................................................. 54
3.4.5 Recommended use of address space ........................................................................................... 56
3.4.6 Peripheral I/O registers.................................................................................................................. 58
3.4.7 Special registers ............................................................................................................................ 65
3.4.8 Cautions......................................................................................................................................... 68
CHAPTER 4 PORT FUNCTIONS ............................................................................................................71
4.1 Features ...................................................................................................................................... 71
4.2 Basic Port Configuration........................................................................................................... 71
4.3 Port Configuration...................................................................................................................... 72
4.3.1 Port 0 ............................................................................................................................................. 78
4.3.2 Port 3 ............................................................................................................................................. 80
4.3.3 Port 4 ............................................................................................................................................. 85
4.3.4 Port 5 ............................................................................................................................................. 87
4.3.5 Port 7 ............................................................................................................................................. 90
4.3.6 Port 9 ............................................................................................................................................. 91
4.3.7 Port CM.......................................................................................................................................... 97
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4.3.8 Port DL ...........................................................................................................................................99
4.4 Block Diagrams........................................................................................................................ 101
4.5 Port Register Setting When Alternate Function Is Used ..................................................... 119
4.6 Cautions.................................................................................................................................... 123
4.6.1 Cautions on bit manipulation instruction for port n register (Pn) ................................................... 123
4.6.2 Hysteresis characteristics.............................................................................................................124
CHAPTER 5 CLOCK GENERATION FUNCTION ...............................................................................125
5.1 Overview ................................................................................................................................... 125
5.2 Configuration............................................................................................................................ 126
5.3 Registers................................................................................................................................... 128
5.4 Operation .................................................................................................................................. 133
5.4.1 Operation of each clock................................................................................................................133
5.4.2 Clock output function ....................................................................................................................133
5.4.3 External clock input function.........................................................................................................133
5.5 PLL Function ............................................................................................................................ 134
5.5.1 Overview ......................................................................................................................................134
5.5.2 Register ........................................................................................................................................134
5.5.3 Usage ...........................................................................................................................................135
CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) .................................................................136
6.1 Overview ................................................................................................................................... 136
6.2 Functions .................................................................................................................................. 136
6.3 Configuration............................................................................................................................ 137
6.4 Registers................................................................................................................................... 139
6.5 Operation .................................................................................................................................. 150
6.5.1 Interval timer mode (TP0MD2 to TP0MD0 bits = 000)..................................................................151
6.5.2 External event count mode (TP0MD2 to TP0MD0 bits = 001)......................................................161
6.5.3 External trigger pulse output mode (TP0MD2 to TP0MD0 bits = 010)..........................................169
6.5.4 One-shot pulse output mode (TP0MD2 to TP0MD0 bits = 011) ...................................................181
6.5.5 PWM output mode (TP0MD2 to TP0MD0 bits = 100)...................................................................188
6.5.6 Free-running timer mode (TP0MD2 to TP0MD0 bits = 101).........................................................197
6.5.7 Pulse width measurement mode (TP0MD2 to TP0MD0 bits = 110) .............................................214
6.5.8 Timer output operations................................................................................................................220
6.6 Eliminating Noise on Capture Trigger Input Pin (TIP0a)...................................................... 221
6.7 Cautions.................................................................................................................................... 223
CHAPTER 7 16-BIT TIMER/EVENT COUNTER 0..............................................................................224
7.1 Functions .................................................................................................................................. 224
7.2 Configuration............................................................................................................................ 225
7.3 Registers................................................................................................................................... 231
7.4 Operation .................................................................................................................................. 238
7.4.1 Interval timer operation.................................................................................................................238
7.4.2 Square wave output operation......................................................................................................241
7.4.3 External event counter operation..................................................................................................244
7.4.4 Operation in clear & start mode entered by TI010 pin valid edge input ........................................247
7.4.5 Free-running timer operation ........................................................................................................262
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7.4.6 PPG output operation .................................................................................................................. 271
7.4.7 One-shot pulse output operation.................................................................................................. 274
7.4.8 Pulse width measurement operation............................................................................................ 279
7.5 Special Use of TM01................................................................................................................. 287
7.5.1 Rewriting CR011 register during TM01 operation........................................................................ 287
7.5.2 Setting LVS01 and LVR01 bits .................................................................................................... 287
7.6 Cautions .................................................................................................................................... 289
CHAPTER 8 8-BIT TIMER/EVENT COUNTER 5 ............................................................................... 293
8.1 Functions .................................................................................................................................. 293
8.2 Configuration............................................................................................................................ 294
8.3 Registers ................................................................................................................................... 297
8.4 Operation .................................................................................................................................. 300
8.4.1 Operation as interval timer........................................................................................................... 300
8.4.2 Operation as external event counter............................................................................................ 302
8.4.3 Square-wave output operation..................................................................................................... 303
8.4.4 8-bit PWM output operation ......................................................................................................... 305
8.4.5 Operation as interval timer (16 bits)............................................................................................. 308
8.4.6 Operation as external event counter (16 bits).............................................................................. 310
8.4.7 Square-wave output operation (16-bit resolution) ........................................................................ 311
8.4.8 Cautions....................................................................................................................................... 312
CHAPTER 9 8-BIT TIMER H ............................................................................................................... 313
9.1 Functions .................................................................................................................................. 313
9.2 Configuration............................................................................................................................ 313
9.3 Registers ................................................................................................................................... 316
9.4 Operation .................................................................................................................................. 320
9.4.1 Operation as interval timer/square wave output........................................................................... 320
9.4.2 PWM output mode operation ....................................................................................................... 323
9.4.3 Carrier generator mode operation................................................................................................ 329
CHAPTER 10 INTERVAL TIMER, WATCH TIMER ........................................................................... 336
10.1 Interval Timer BRG................................................................................................................... 336
10.1.1 Functions ..................................................................................................................................... 336
10.1.2 Configuration ............................................................................................................................... 336
10.1.3 Registers...................................................................................................................................... 338
10.1.4 Operation ..................................................................................................................................... 340
10.2 Watch Timer.............................................................................................................................. 341
10.2.1 Functions ..................................................................................................................................... 341
10.2.2 Configuration ............................................................................................................................... 341
10.2.3 Register ....................................................................................................................................... 342
10.2.4 Operation ..................................................................................................................................... 344
10.3 Cautions .................................................................................................................................... 346
CHAPTER 11 WATCHDOG TIMER FUNCTIONS .............................................................................. 347
11.1 Watchdog Timer 1 .................................................................................................................... 347
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11.1.1 Functions......................................................................................................................................347
11.1.2 Configuration ................................................................................................................................349
11.1.3 Registers ......................................................................................................................................349
11.1.4 Operation......................................................................................................................................351
11.2 Watchdog Timer 2.................................................................................................................... 353
11.2.1 Functions......................................................................................................................................353
11.2.2 Configuration ................................................................................................................................354
11.2.3 Registers ......................................................................................................................................354
11.2.4 Operation......................................................................................................................................356
CHAPTER 12 REAL-TIME OUTPUT FUNCTION (RTO)....................................................................357
12.1 Function .................................................................................................................................... 357
12.2 Configuration............................................................................................................................ 358
12.3 Registers................................................................................................................................... 359
12.4 Operation .................................................................................................................................. 361
12.5 Usage ........................................................................................................................................ 362
12.6 Cautions.................................................................................................................................... 362
12.7 Security Function..................................................................................................................... 363
CHAPTER 13 A/D CONVERTER ..........................................................................................................365
13.1 Overview ................................................................................................................................... 365
13.2 Functions .................................................................................................................................. 365
13.3 Configuration............................................................................................................................ 366
13.4 Registers................................................................................................................................... 368
13.5 Operation .................................................................................................................................. 377
13.5.1 Basic operation............................................................................................................................. 377
13.5.2 Trigger modes ..............................................................................................................................378
13.5.3 Operation modes ..........................................................................................................................379
13.5.4 Power fail detection function......................................................................................................... 382
13.5.5 Setting method .............................................................................................................................383
13.6 Cautions.................................................................................................................................... 385
13.7 How to Read A/D Converter Characteristics Table .............................................................. 391
CHAPTER 14 ASYNCHRONOUS SERIAL INTERFACE (UART) .....................................................395
14.1 Features .................................................................................................................................... 395
14.2 Configuration............................................................................................................................ 396
14.3 Registers................................................................................................................................... 398
14.4 Interrupt Request Signals ....................................................................................................... 407
14.5 Operation .................................................................................................................................. 408
14.5.1 Data format...................................................................................................................................408
14.5.2 Transmit operation........................................................................................................................409
14.5.3 Continuous transmission operation ..............................................................................................411
14.5.4 Receive operation.........................................................................................................................415
14.5.5 Reception error............................................................................................................................. 417
14.5.6 Parity types and corresponding operation ....................................................................................418
14.5.7 Receive data noise filter ...............................................................................................................419
14.5.8 SBF transmission/reception (UART0 only) ...................................................................................420
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14.6 Dedicated Baud Rate Generator n (BRGn) ............................................................................ 424
14.6.1 Baud rate generator n (BRGn) configuration ............................................................................... 424
14.6.2 Serial clock generation................................................................................................................. 425
14.6.3 Baud rate setting example ........................................................................................................... 428
14.6.4 Allowable baud rate range during reception................................................................................. 429
14.6.5 Transfer rate during continuous transmission.............................................................................. 431
14.7 Cautions .................................................................................................................................... 431
CHAPTER 15 CLOCKED SERIAL INTERFACE 0 (CSI0) ................................................................ 432
15.1 Features .................................................................................................................................... 432
15.2 Configuration............................................................................................................................ 433
15.3 Registers ................................................................................................................................... 436
15.4 Operation .................................................................................................................................. 445
15.4.1 Transmission/reception completion interrupt request signal (INTCSI0n) ..................................... 445
15.4.2 Single transfer mode.................................................................................................................... 447
15.4.3 Continuous transfer mode............................................................................................................ 450
15.5 Output Pins ............................................................................................................................... 458
CHAPTER 16 I2C BUS .......................................................................................................................... 459
16.1 Features .................................................................................................................................... 459
16.2 Configuration............................................................................................................................ 462
16.3 Registers ................................................................................................................................... 464
16.4 Functions .................................................................................................................................. 477
16.4.1 Pin configuration .......................................................................................................................... 477
16.5 I2C Bus Definitions and Control Methods .............................................................................. 478
16.5.1 Start condition.............................................................................................................................. 478
16.5.2 Addresses.................................................................................................................................... 479
16.5.3 Transfer direction specification .................................................................................................... 479
16.5.4 ACK ............................................................................................................................................. 480
16.5.5 Stop condition .............................................................................................................................. 481
16.5.6 Wait state..................................................................................................................................... 482
<R>
16.5.7 Wait state cancellation method...................................................................................................... 484
16.6 I2C Interrupt Request Signals (INTIIC0) .................................................................................. 485
16.6.1 Master device operation............................................................................................................... 486
16.6.2 Slave device operation (when receiving slave address (match with address)) ............................ 489
16.6.3 Slave device operation (when receiving extension code) ............................................................ 493
16.6.4 Operation without communication................................................................................................ 497
16.6.5 Arbitration loss operation (operation as slave after arbitration loss) ............................................ 497
16.6.6 Operation when arbitration loss occurs (no communication after arbitration loss)....................... 499
16.7 Interrupt Request Signal (INTIIC0) Generation Timing and Wait Control........................... 506
16.8 Address Match Detection Method .......................................................................................... 507
16.9 Error Detection ......................................................................................................................... 507
16.10 Extension Code ........................................................................................................................ 508
16.11 Arbitration ................................................................................................................................. 509
16.12 Wakeup Function ..................................................................................................................... 510
16.13 Communication Reservation .................................................................................................. 511
16.13.1 When communication reservation function is enabled (IICF0.IICRSV0 bit = 0) ........................... 511
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16.13.2 When communication reservation function is disabled (IICF0.IICRSV0 bit = 1) ...........................514
16.14 Cautions.................................................................................................................................... 515
16.15 Communication Operations.................................................................................................... 516
16.15.1 Master operation in single master system ....................................................................................517
16.15.2 Master operation in multimaster system.......................................................................................518
16.15.3 Slave operation.............................................................................................................................521
16.16 Timing of Data Communication.............................................................................................. 524
CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION................................................ 531
17.1 Overview ................................................................................................................................... 531
17.1.1 Features .......................................................................................................................................531
17.2 Non-Maskable Interrupts......................................................................................................... 534
17.2.1 Operation......................................................................................................................................537
17.2.2 Restore.........................................................................................................................................538
17.2.3 NP flag..........................................................................................................................................539
17.3 Maskable Interrupts ................................................................................................................. 540
17.3.1 Operation......................................................................................................................................540
17.3.2 Restore.........................................................................................................................................542
17.3.3 Priorities of maskable interrupts ...................................................................................................543
17.3.4 Interrupt control register (xxlCn) ...................................................................................................547
17.3.5 Interrupt mask registers 0, 1, 3 (IMR0, IMR1, IMR3)....................................................................549
17.3.6 In-service priority register (ISPR)..................................................................................................550
17.3.7 ID flag ........................................................................................................................................... 551
17.3.8 Watchdog timer mode register 1 (WDTM1) .................................................................................. 552
17.4 External Interrupt Request Input Pins (NMI, INTP0 to INTP7) ............................................. 553
17.4.1 Noise elimination ..........................................................................................................................553
17.4.2 Edge detection..............................................................................................................................555
17.5 Software Exceptions................................................................................................................ 559
17.5.1 Operation......................................................................................................................................559
17.5.2 Restore.........................................................................................................................................560
17.5.3 EP flag..........................................................................................................................................561
17.6 Exception Trap ......................................................................................................................... 562
17.6.1 Illegal opcode ...............................................................................................................................562
17.6.2 Debug trap.................................................................................................................................... 564
17.7 Multiple Interrupt Servicing Control ...................................................................................... 566
17.8 Interrupt Response Time......................................................................................................... 568
17.9 Periods in Which Interrupts Are Not Acknowledged by CPU ............................................. 569
17.10 Cautions.................................................................................................................................... 569
CHAPTER 18 KEY INTERRUPT FUNCTION ......................................................................................570
18.1 Function .................................................................................................................................... 570
18.2 Register..................................................................................................................................... 571
CHAPTER 19 STANDBY FUNCTION ...................................................................................................572
19.1 Overview ................................................................................................................................... 572
19.2 Registers................................................................................................................................... 575
19.3 HALT Mode ............................................................................................................................... 578
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19.3.1 Setting and operation status ........................................................................................................ 578
19.3.2 Releasing HALT mode................................................................................................................. 578
19.4 IDLE Mode................................................................................................................................. 580
19.4.1 Setting and operation status ........................................................................................................ 580
19.4.2 Releasing IDLE mode.................................................................................................................. 580
19.5 STOP Mode ............................................................................................................................... 582
19.5.1 Setting and operation status ........................................................................................................ 582
19.5.2 Releasing STOP mode ................................................................................................................ 582
19.5.3 Securing oscillation stabilization time when STOP mode is released .......................................... 584
19.6 Subclock Operation Mode....................................................................................................... 585
19.6.1 Setting and operation status ........................................................................................................ 585
19.6.2 Releasing subclock operation mode ............................................................................................ 585
19.7 Sub-IDLE Mode......................................................................................................................... 587
19.7.1 Setting and operation status ........................................................................................................ 587
19.7.2 Releasing sub-IDLE mode ........................................................................................................... 587
CHAPTER 20 RESET FUNCTION........................................................................................................ 589
20.1 Overview ................................................................................................................................... 589
20.2 Configuration............................................................................................................................ 589
20.3 Register to Check Reset Source............................................................................................. 590
20.4 Reset Sources .......................................................................................................................... 591
20.4.1 Reset operation via RESET pin ................................................................................................... 591
20.4.2 Reset operation by WDTRES1 signal.......................................................................................... 595
20.4.3 Reset operation by WDTRES2 signal.......................................................................................... 596
20.4.4 Power-on-clear reset operation.................................................................................................... 597
20.4.5 Reset operation by low-voltage detector...................................................................................... 600
20.4.6 Reset operation by clock monitor................................................................................................. 601
20.5 Reset Output Function............................................................................................................. 602
CHAPTER 21 CLOCK MONITOR ........................................................................................................ 603
21.1 Function .................................................................................................................................... 603
21.2 Registers ................................................................................................................................... 603
21.3 Operation .................................................................................................................................. 605
21.4 Internal Oscillation Clock Operation Mode ........................................................................... 608
21.4.1 Setting and operation status ........................................................................................................ 608
21.4.2 Releasing internal oscillation clock operation mode .................................................................... 608
21.5 Internal Oscillation HALT Mode.............................................................................................. 611
21.5.1 Setting and operation status ........................................................................................................ 611
21.5.2 Releasing internal oscillation HALT mode ................................................................................... 611
CHAPTER 22 LOW-VOLTAGE DETECTOR ....................................................................................... 613
22.1 Function .................................................................................................................................... 613
22.2 Configuration............................................................................................................................ 613
22.3 Registers ................................................................................................................................... 614
22.4 Operation .................................................................................................................................. 616
CHAPTER 23 POWER-ON-CLEAR CIRCUIT...................................................................................... 618
14
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Function.................................................................................................................................... 618
23.1
23.2 Configuration............................................................................................................................ 618
23.3 Operation .................................................................................................................................. 619
CHAPTER 24 ROM CORRECTION FUNCTION.................................................................................. 620
24.1 Overview ................................................................................................................................... 620
24.2 Control Registers..................................................................................................................... 621
24.2.1 Correction address registers 0 to 3 (CORAD0 to CORAD3) ........................................................621
24.2.2 Correction control register (CORCN)............................................................................................622
24.3 ROM Correction Operation and Program Flow..................................................................... 622
CHAPTER 25 MASK OPTION/OPTION BYTE ....................................................................................624
25.1 Mask Option (Mask ROM Versions) ....................................................................................... 624
25.2 Option Byte (Flash Memory Versions)................................................................................... 625
CHAPTER 26 FLASH MEMORY...........................................................................................................626
26.1 Features .................................................................................................................................... 626
26.2 Memory Configuration............................................................................................................. 627
26.3 Functional Outline ................................................................................................................... 628
26.4 Rewriting by Dedicated Flash Programmer .......................................................................... 632
26.4.1 Programming environment ...........................................................................................................632
26.4.2 Communication mode...................................................................................................................633
26.4.3 Flash memory control ................................................................................................................... 638
26.4.4 Selection of communication mode................................................................................................639
26.4.5 Communication commands ..........................................................................................................640
26.4.6 Pin connection ..............................................................................................................................641
26.5 Rewriting by Self Programming ............................................................................................. 646
26.5.1 Overview ......................................................................................................................................646
26.5.2 Features .......................................................................................................................................647
26.5.3 Standard self programming flow ................................................................................................... 648
26.5.4 Flash functions .............................................................................................................................649
26.5.5 Pin processing ..............................................................................................................................649
26.5.6 Internal resources used ................................................................................................................650
<R>
<R>
CHAPTER 27 ON-CHIP DEBUG FUNCTION ......................................................................................651
27.1 ROM Security Function ........................................................................................................... 651
27.1.1 Security ID....................................................................................................................................651
27.1.2 Setting ..........................................................................................................................................652
27.2 Cautions.................................................................................................................................... 653
CHAPTER 28 ELECTRICAL SPECIFICATIONS..................................................................................654
CHAPTER 29 PACKAGE DRAWINGS .................................................................................................676
CHAPTER 30 RECOMMENDED SOLDERING CONDITIONS............................................................678
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Page 16
APPENDIX A DEVELOPMENT TOOLS............................................................................................... 680
A.1 Software Package..................................................................................................................... 683
A.2 Language Processing Software.............................................................................................. 683
A.3 Control Software ...................................................................................................................... 683
A.4 Debugging Tools (Hardware) .................................................................................................. 684
A.4.1 When using IECUBE QB-V850ESKX1H...................................................................................... 684
<R>
A.4.2 When using MINICUBE QB-V850MINI ........................................................................................ 686
A.5 Debugging Tools (Software) ................................................................................................... 688
A.6 Embedded Software................................................................................................................. 689
A.7 Flash Memory Writing Tools ................................................................................................... 689
APPENDIX B INSTRUCTION SET LIST ............................................................................................. 690
B.1 Conventions.............................................................................................................................. 690
B.2 Instruction Set (in Alphabetical Order) .................................................................................. 693
APPENDIX C REGISTER INDEX ......................................................................................................... 700
<R>
APPENDIX D REVISION HISTORY ..................................................................................................... 706
D.1 Major Revisions in This Edition .............................................................................................. 706
16
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CHAPTER 1 INTRODUCTION
1.1 K1 Series Product Lineup
1.1.1 V850ES/Kx1+, V850ES/Kx1 products lineup
•
64-pin plastic LQFP (10 × 10 mm, 0.5 mm pitch)
•
64-pin plastic TQFP (12 × 12 mm, 0.65 mm pitch)
V850ES/KE1
μ
PD70F3207HY
PD70F3207H
μ
Single-power flash: 128 KB,
RAM: 4 KB
•
80-pin plastic TQFP (12 × 12 mm, 0.5 mm pitch)
•
80-pin plastic QFP (14 × 14 mm, 0.65 mm pitch)
PD703207Y
μ
PD703207
μ
Mask ROM: 128 KB,
RAM: 4 KB
V850ES/KF1
μ
PD70F3211HY
PD70F3211H
μ
Single-power flash: 256 KB,
RAM: 12 KB
μ
PD70F3210HY
PD70F3210H
μ
Single-power flash: 128 KB,
RAM: 6 KB
PD70F3210Y
μ
PD70F3210
μ
Two-power flash: 128 KB,
RAM: 6 KB
•
100-pin plastic LQFP (14 × 14 mm, 0.5 mm pitch)
•
100-pin plastic QFP (14 × 20 mm, 0.65 mm pitch)
μ
PD703211Y
PD703211
μ
Mask ROM: 256 KB,
RAM: 12 KB
μ
PD703210Y
PD703210
μ
Mask ROM: 128 KB,
RAM: 6 KB
PD703209Y
μ
μ
PD703209
Mask ROM: 96 KB,
RAM: 4 KB
PD703208Y
μ
PD703208
μ
Mask ROM: 64 KB,
RAM: 4 KB
V850ES/KG1
μ
PD70F3215HY
PD70F3215H
μ
Single-power flash: 256 KB,
RAM: 16 KB
PD70F3214HY
μ
PD70F3214H
μ
Single-power flash: 128 KB,
RAM: 6 KB
PD70F3214Y
μ
PD70F3214
μ
Two-power flash: 128 KB,
RAM: 6 KB
•
144-pin plastic LQFP (20 × 20 mm, 0.5 mm pitch)
μ
PD703215Y
PD703215
μ
Mask ROM: 256 KB,
RAM: 16 KB
PD703214Y
μ
PD703214
μ
Mask ROM: 128 KB,
RAM: 6 KB
PD703213Y
μ
PD703213
μ
Mask ROM: 96 KB,
RAM: 4 KB
μ
PD703212Y
PD703212
μ
Mask ROM: 64 KB,
RAM: 4 KB
V850ES/KJ1
PD70F3218HY
μ
μ
PD70F3218H
Single-power flash: 256 KB,
RAM: 16 KB
μ
PD70F3217HY
PD70F3217H
μ
Single-power flash: 128 KB,
RAM: 6 KB
PD70F3217Y
μ
μ
PD70F3217
Two-power flash: 128 KB,
RAM: 6 KB
μ
PD703217Y
PD703217
μ
Mask ROM: 128 KB,
RAM: 6 KB
PD703216Y
μ
μ
PD703216
Mask ROM: 96 KB,
RAM: 6 KB
V850ES/KE1+
μ
PD70F3302Y
PD70F3302
μ
Single-power flash: 128 KB,
RAM: 4 KB
V850ES/KF1+
μ
PD70F3308Y
PD70F3308
μ
Single-power flash: 256 KB,
RAM: 12 KB
PD70F3306Y
μ
PD70F3306
μ
Single-power flash: 128 KB,
RAM: 6 KB
V850ES/KG1+
PD70F3313Y
μ
PD70F3313
μ
Single-power flash: 256 KB,
RAM: 16 KB
PD70F3311Y
μ
PD70F3311
μ
Single-power flash: 128 KB,
RAM: 6 KB
V850ES/KJ1+
PD70F3318Y
μ
PD70F3318
μ
Single-power flash: 256 KB,
RAM: 16 KB
μ
PD70F3316Y
PD70F3316
μ
Single-power flash: 128 KB,
RAM: 6 KB
μ
PD703302Y
PD703302
μ
Mask ROM: 128 KB,
RAM: 4 KB
PD703308Y
μ
PD703308
μ
Mask ROM: 256 KB,
RAM: 12 KB
PD703313Y
μ
PD703313
μ
Mask ROM: 256 KB,
RAM: 16 KB
User’s Manual U16896EJ2V0UD
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Page 18
CHAPTER 1 INTRODUCTION
The function list of the V850ES/Kx1+ is shown below.
Product Name V850ES/KE1+ V850ES/KF1+ V850ES/KG1+ V850ES/KJ1+
Number of pins 64 pins 80 pins 100 pins 144 pins
Internal
memory
(KB)
Mask ROM 128 − − 256 − − 256 − − −
Flash memory − 128 128 − 256 128 − 256 128 256
RAM 4 6 12 6 16 6 16
Supply voltage 2.7 to 5.5 V
Minimum instruction execution time 50 ns @20 MHz
Clock
X1 input 2 to 10 MHz
Subclock 32.768 kHz
Internal oscillator 240 kHz (TYP.)
Port
CMOS input 8 8 8 16
CMOS I/O
Note 1
41 (4)
57 (6)
Note 1
72 (8)
Note 1
106 (12)
Note 1
N-ch open-drain I/O 2 2 4 6
Timer
16-bit (TMP) 1 ch 1 ch 1 ch 1 ch
16-bit (TM0) 1 ch 2 ch 4 ch 6 ch
8-bit (TM5) 2 ch 2 ch 2 ch 2 ch
8-bit (TMH) 2 ch 2 ch 2 ch 2 ch
Interval timer 1 ch 1 ch 1 ch 1 ch
Watch 1 ch 1 ch 1 ch 1 ch
WDT1 1 ch 1 ch 1 ch 1 ch
WDT2 1 ch 1 ch 1 ch 1 ch
RTO 6 bits × 1 ch 6 bits × 1 ch 6 bits × 1 ch 6 bits × 2 ch
Serial
interface
CSI 2 ch 2 ch 2 ch 3 ch
Automatic transmit/receive
− 1 ch 2 ch 2 ch
3-wire CSI
UART 1 ch 1 ch 2 ch 2 ch
UART supporting LIN-bus 1 ch 1 ch 1 ch 1 ch
2CNote 2
I
External
bus
Address space − 128 KB 3 MB 15 MB
Address bus − 16 bits 22 bits 24 bits
1 ch 1 ch 1 ch 2 ch
Mode − Multiplex only Multiplex/separate
DMA controller − − 4 ch 4 ch
10-bit A/D converter 8 ch 8 ch 8 ch 16 ch
8-bit D/A converter − − 2 ch 2 ch
External 9 9 9 9 Interrupt
Internal
Note 2
29/30
26/27
Note 2
41/42
Note 2
46/48
Note 2
Key return input 8 ch 8 ch 8 ch 8 ch
Reset
RESET pin Provided
POC 2.7 V or less fixed
LVI 3.1 V/3.3 V ±0.15 V or 3.5 V/3.7 V/3.9 V/4.1 V/4.3 V ±0.2 V (selectable by software)
Clock monitor Provided (monitor by internal oscillator)
WDT1 Provided
WDT2 Provided
ROM correction 4 None
Regulator None Provided
Standby function HALT/IDLE/STOP/sub-IDLE mode
Operating ambient temperature TA = −40 to +85°C
Notes 1. Number of channels in parentheses indicates the number of pins for which the N-ch open-drain output
can be selected by software.
2. Only in products with an I
2
C bus (Y products). For the product name, refer to each user’s manual.
18
User’s Manual U16896EJ2V0UD
Page 19
CHAPTER 1 INTRODUCTION
The function list of the V850ES/Kx1 is shown below.
Product Name V850ES/KE1 V850ES/KF1 V850ES/KG1 V850ES/KJ1
Number of pins 64 pins 80 pins 100 pins 144 pins
Internal
memory
(KB)
Mask ROM 128 − 64/
Flash memory − 128 − − 128 − 256 − − 128 − 256 − 128 256
128 − 256 − 64/
96
128 − 256 − 96/128 − −
96
RAM 4 4 6 12 4 6 16 6 16
Supply voltage 2.7 to 5.5 V
Minimum instruction execution time 50 ns @20 MHz
Clock
X1 input 2 to 10 MHz
Subclock 32.768 kHz
Internal oscillator −
Port
CMOS input 8 8 8 16
CMOS I/O
Note 1
41 (4)
57 (6)
Note 1
72 (8)
Note 1
106 (12)
Note 1
N-ch open-drain I/O 2 2 4 6
Timer
16-bit (TMP) 1 ch − 1 ch − 1 ch − 1 ch
16-bit (TM0) 1 ch 2 ch 4 ch 6 ch
8-bit (TM5) 2 ch 2 ch 2 ch 2 ch
8-bit (TMH) 2 ch 2 ch 2 ch 2 ch
Interval timer 1 ch 1 ch 1 ch 1 ch
Watch 1 ch 1 ch 1 ch 1 ch
WDT1 1 ch 1 ch 1 ch 1 ch
WDT2 1 ch 1 ch 1 ch 1 ch
RTO 6 bits × 1 ch 6 bits × 1 ch 6 bits × 1 ch 6 bits × 2 ch
Serial
interface
CSI 2 ch 2 ch 2 ch 3 ch
Automatic transmit/receive
− 1 ch 2 ch 2 ch
3-wire CSI
UART 2 ch 2 ch 2 ch 3 ch
UART supporting LIN-bus − − − −
2CNote 2
I
External
bus
Address space − 128 KB 3 MB 15 MB
Address bus − 16 bits 22 bits 24 bits
1 ch 1 ch 1 ch 2 ch
Mode − Multiplex only Multiplex/separate
DMA controller − − − −
10-bit A/D converter 8 ch 8 ch 8 ch 16 ch
8-bit D/A converter − − 2 ch 2 ch
External 8 8 8 8 Interrupt
Internal
Note 2
25/26
25/26
Note 2
28/29
Note 2
30/31
Note 2
33/34
Note 2
38/40
Note 2
41/43
Key return input 8 ch 8 ch 8 ch 8 ch
Reset
RESET pin Provided
POC None
LVI None
Clock monitor None
WDT1 Provided
WDT2 Provided
ROM correction 4
Regulator None Provided
Standby function HALT/IDLE/STOP/sub-IDLE mode
Operating ambient temperature TA = −40 to +85°C
Notes 1. Number of channels in parentheses indicates the number of pins for which the N-ch open-drain output
can be selected by software.
2. Only in products with an I
2
C bus (Y products). For the product name, refer to each user’s manual.
Note 2
User’s Manual U16896EJ2V0UD
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Page 20
CHAPTER 1 INTRODUCTION
1.1.2 78K0/Kx1+, 78K0/Kx1 products lineup
30-pin SSOP (7.62 mm 0.65 mm pitch)
78K0/KB1
PD78F0103
μ
Two-power flash: 24 KB,
RAM: 768 B
44-pin LQFP (10 × 10 mm 0.8 mm pitch)
Mask ROM: 24 KB,
RAM: 768 B
Mask ROM: 16 KB,
RAM: 768 B
Mask ROM: 8 KB,
RAM: 512 B
78K0/KC1
μ
PD78F0114
Two-power flash: 32 KB,
RAM: 1 KB
Mask ROM: 32 KB,
RAM: 1 KB
Mask ROM: 24 KB,
RAM: 1 KB
Mask ROM: 16 KB,
RAM: 512 B
Mask ROM: 8 KB,
RAM: 512 B
52-pin LQFP (10 × 10 mm 0.65 mm pitch)
78K0/KD1
PD78F0124
μ
Two-power flash: 32 KB,
RAM: 1 KB
Mask ROM: 32 KB,
RAM: 1 KB
Mask ROM: 24 KB,
RAM: 1 KB
Mask ROM: 16 KB,
RAM: 512 B
Mask ROM: 8 KB,
RAM: 512 B
64-pin LQFP, TQFP (10 × 10 mm 0.5 mm pitch, 12 × 12 mm 0.65 mm pitch, 14 × 14 mm 0.8 mm pitch)
78K0/KE1
μ
PD78F0138
Flash memory: 60 KB,
RAM: 2 KB
μ
PD78F0134
Flash memory: 32 KB,
RAM: 1 KB
Mask ROM: 60 KB,
RAM: 2 KB
Mask ROM: 48 KB,
RAM: 2 KB
Mask ROM: 32 KB,
RAM: 1 KB
Mask ROM: 24 KB,
RAM: 1 KB
Mask ROM: 16 KB,
RAM: 512 B
Mask ROM: 8 KB,
RAM: 512 B
80-pin TQFP, QFP (12 × 12 mm 0.5 mm pitch, 14 × 14 mm 0.65 mm pitch)
78K0/KF1
PD78F0148
μ
Flash memory: 60 KB,
RAM: 2 KB
Mask ROM: 60 KB,
RAM: 2 KB
Mask ROM: 48 KB,
RAM: 2 KB
Mask ROM: 32 KB,
RAM: 1 KB
Mask ROM: 24 KB,
RAM: 1 KB
Note Products with an on-chip debug function
PD780103
μ
PD780102
μ
PD780101
μ
PD780114
μ
μ
PD780113
PD780112
μ
μ
PD780111
PD780124
μ
μ
PD780123
PD780122
μ
PD780121
μ
μ
PD780138
PD780136
μ
μ
PD780134
PD780133
μ
μ
PD780132
μ
PD780131
PD780148
μ
μ
PD780146
PD780144
μ
μ
PD780143
78K0/KB1+
PD78F0103H
μ
Single-power flash: 24 KB,
RAM: 768 B
μ
PD78F0102H
Single-power flash: 16 KB,
RAM: 768 B
μ
PD78F0101H
Single-power flash: 8 KB,
RAM: 512 B
78K0/KC1+
μ
PD78F0114H/HD
Single-power flash: 32 KB,
RAM: 1 KB
μ
PD78F0113H
Single-power flash: 24 KB,
RAM: 1 KB
PD78F0112H
μ
Single-power flash: 16 KB,
RAM: 512 B
Note
78K0/KD1+
PD78F0124H/HD
μ
Single-power flash: 32 KB,
RAM: 1 KB
μ
PD78F0123H
Single-power flash: 24 KB,
RAM: 1 KB
PD78F0122H
μ
Single-power flash: 16 KB,
RAM: 512 B
Note
78K0/KE1+
PD78F0138H/HD
μ
Single-power flash: 60 KB,
RAM: 2 KB
PD78F0136H
μ
Single-power flash: 48 KB,
RAM: 2 KB
PD78F0134H
μ
Single-power flash: 32 KB,
RAM: 1 KB
PD78F0133H
μ
Single-power flash: 24 KB,
RAM: 1 KB
μ
PD78F0132H
Single-power flash: 16 KB,
RAM: 512 B
Note
78K0/KF1+
μ
PD78F0148H/HD
Single-power flash: 60 KB,
RAM: 2 KB
Note
20
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CHAPTER 1 INTRODUCTION
The list of functions in the 78K0/Kx1 is shown below.
Part Number
78K0/KB1 78K0/KC1 78K0/KD1 78K0/KE1 78K0/KF1
Item
Number of pins 30 pins 44 pins 52 pins 64 pins 80 pins
Internal
memory
(KB)
Mask ROM 8
Flash memory
16/
− 8/
24
24
−
16
24/
− 8/
32
32
−
16
24/
− 8/
32
32
−
16
−
24/
32
− 48/
60
32
−
− 24/
60
32
48/
−
60
60
−
RAM 0.5 0.75 0.5 1 0.5 1 0.5 1 2 1 2
Power supply voltage VDD = 2.5 to 5.5 V
Minimum instruction execution time
μ
s (when 12 MHz, VDD =
0.166
4.0 to 5.5 V)
μ
s (when 10 MHz, VDD =
0.2
3.5 to 5.5 V)
μ
s (when 8.38 MHz, VDD
0.238
<Connect REGC pin to V
0.166
μ
s (when 12 MHz, VDD = 4.0 to 5.5 V)
μ
s (when 10 MHz, VDD = 3.5 to 5.5 V)
0.2
0.238
μ
s (when 8.38 MHz, VDD = 3.0 to 5.5 V)
μ
s (when 5 MHz, VDD = 2.5 to 5.5 V)
0.4
Notes 1, 2
DD>
= 3.0 to 5.5 V)
μ
s (when 5 MHz, VDD = 2.5
0.4
to 5.5 V)
Clock
X1 input 2 to 12 MHz
Subclock
−
32.768 kHz
Internal oscillator 240 kHz (TYP.)
Port
CMOS I/O 17 19 26 38 54
CMOS input 4 8
CMOS output 1
Timer
N-ch open-drain I/O
−
16 bits (TM0) 1 ch 2 ch 1 ch 2 ch
4
8 bits (TM5) 1 ch 2 ch
8 bits (TMH) 2 ch
For watch
−
1 ch
WDT 1 ch
Serial
interface
3-wire CSI
Automatic transmit/
Note 3
1 ch 2 ch 1 ch 2 ch
−
1 ch
receive 3-wire CSI
Note 3
UART
−
1 ch
UART supporting LIN-bus 1 ch
10-bit A/D converter 4 ch 8 ch
External 6 7 8 9 9 Interrupt
Internal 11 12 15 16 19 17 20
Key return input
Reset
RESET pin Provided
−
4 ch 8 ch
POC 2.85 V ±0.15 V/3.5 V ±0.20 V (selectable by mask option)
LVI 2.85 V/3.1 V/3.3 V ±0.15 V/3.5 V/3.7 V/3.9 V/4.1 V/4.3 V ±0.2 V (selectable by software)
Clock monitor Provided
WDT Provided
Clock output/buzzer output
− Clock output
Provided
only
Multiplier/divider
ROM correction
−
−
16 bits × 16 bits, 32 bits ÷ 16 bits
Provided
−
Standby function HALT/STOP mode
Operating ambient temperature
Standard and special (A) grade products: −40 to +85°C
Special (A1) grade products: −40 to +110°C (mask ROM version),
−40 to +105°C (flash memory version)
Special (A2) grade products: −40 to +125°C (mask ROM version)
Notes 1. If the POC circuit detection voltage (VPOC) is used with 2.85 V ±0.15 V, then use the products in the voltage
range of 3.0 to 5.5 V.
2. If the POC circuit detection voltage (V
POC) is used with 3.5 V ±0.2 V, then use the products in the voltage
range of 3.7 to 5.5 V.
3. Select either of the functions of these alternate-function pins.
User’s Manual U16896EJ2V0UD
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Page 22
CHAPTER 1 INTRODUCTION
The list of functions in the 78K0/Kx1+ is shown below.
Part Number
Item
Number of pins 30 pins 44 pins 52 pins 64 pins 80 pins
Flash memory 8 16/24 16 24/32 16 24/32 16 24/32 48/60 60 Internal
memory
(KB)
RAM 0.5 0.75 0.5 1 0.5 1 0.5 1 2 2
Power supply voltage VDD = 2.5 to 5.5 V (with internal oscillation clock or subclock: VDD = 2.0 to 5.5 V
Minimum instruction execution time 0.125 μs (when 16 MHz, VDD = 4.0 to 5.5 V), 0.2 μs (when 10 MHz, VDD = 3.5 to 5.5 V),
Clock
Crystal/ceramic 2 to 16 MHz
RC 3 to 4 MHz
Subclock
Internal oscillator 240 kHz (TYP.)
Ports
CMOS I/O 17 19 26 38 54
CMOS input 4 8
CMOS output 1
N-ch open-drain I/O
Timer
16 bits (TM0) 1 ch 2 ch
8 bits (TM5) 1 ch 2 ch
8 bits (TMH) 2 ch
For watch
WDT 1 ch
Serial
interface
3-wire CSI
Automatic transmit/
Note 2
1 ch 2 ch
receive 3-wire CSI
Note 2
UART
UART supporting LIN-bus 1 ch
10-bit A/D converter 4 ch 8 ch
Interrupts
External 6 7 8 9 9
Internal 11 12 15 16 19 20
Key return input
Reset
RESET pin Provided
POC 2.1 V ±0.1 V (detection voltage is fixed)
LVI 2.35 V/2.6 V/2.85 V/3.1 V/3.3 V ±0.15 V/3.5 V/3.7 V/3.9 V/4.1 V/4.3 V ±0.2 V
Clock monitor Provided
WDT Provided
Clock output/buzzer output
External bus interface
Multiplier/divider
ROM correction
Self-programming function Provided
Product with on-chip debug
function
Standby function HALT/STOP mode
Operating ambient temperature TA = −40 to +85°C
78K0/KB1+ 78K0/KC1+ 78K0/KD1+ 78K0/KE1+ 78K0/KF1+
Note 1
)
0.238
μ
s (when 8.38 MHz, VDD = 3.0 to 5.5 V), 0.4 μs (when 5 MHz, VDD = 2.5 to 5.5 V)
−
−
−
−
−
−
−
4 ch 8 ch
32.768 kHz
4
1 ch
1 ch
1 ch
(selectable by software)
−
Clock output
Provided
only
−
−
−
μ
PD78F0114HD, 78F0124HD, 78F0138HD, 78F0148HD
16 bits × 16 bits, 32 bits ÷ 16 bits
Provided
Provided
−
Notes 1. Because the POC circuit detection voltage (VPOC) is 2.1 V ±0.1 V, use the products in the voltage range of
2.2 to 5.5 V.
2. Select either of the functions of these alternate-function pins.
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CHAPTER 1 INTRODUCTION
1.2 Features
{ Minimum instruction execution time: 50 ns (operation at main clock (fXX) = 20 MHz)
{ General-purpose registers: 32 bits × 32 registers
{ CPU features: Signed multiplication (16 × 16 → 32): 1 to 2 clocks
(Instructions without creating register hazards can be continuously executed in parallel)
Saturated operations (overflow and underflow detection functions are included)
32-bit shift instruction: 1 clock
Bit manipulation instructions
Load/store instructions with long/short format
{ Memory space: 64 MB of linear address space
• Internal memory
{ Interrupts and exceptions
Non-maskable interrupts: 3 sources
Maskable interrupts: 32 sources (
33 sources (μPD703302Y, 70F3302Y)
Software exceptions: 32 sources
Exception trap: 1 source
{ I/O lines: Total: 51
{ Key interrupt function
{ Timer function
16-bit timer/event counter P: 1 channel
16-bit timer/event counter 0: 1 channel
8-bit timer/event counter 5: 2 channels
8-bit timer H: 2 channels
8-bit interval timer BRG: 1 channel
Watch timer/interval timer: 1 channel
Watchdog timers
Watchdog timer 1 (also usable as oscillation stabilization timer): 1 channel
Watchdog timer 2: 1 channel
{ Serial interface
Asynchronous serial interface (UART) (supporting LIN): 1 channel
Asynchronous serial interface (UART): 1 channel
3-wire serial I/O (CSI0): 2 channels
I
(
{ A/D converter: 10-bit resolution × 8 channels
{ Real-time output port: 6 bits × 1 channel
{ Standby functions: HALT/IDLE/STOP modes, subclock/sub-IDLE modes, internal oscillation clock
{ ROM correction: 4 correction addresses specifiable
{ Clock generator
Main clock oscillation (f
CPU clock (f
Clock-through mode/PLL mode selectable
μ
PD703302, 703302Y (Mask ROM: 128 KB/RAM: 4 KB)
μ
PD70F3302, 70F3302Y (Single-power flash memory: 128 KB/RAM: 4 KB)
μ
PD703302, 70F3302)
2
C bus interface (I2C): 1 channel
μ
PD703302Y, 70F3302Y)
operation/internal oscillation HALT modes
X)/subclock oscillation (fXT)/internal oscillator (fR)
CPU) 7 steps (fXX, fXX/2, fXX/4, fXX/8, fXX/16, fXX/32, fXT)
User’s Manual U16896EJ2V0UD
23
Page 24
{ Internal oscillator: 240 kHz (TYP.)
Remark For frequency characteristics (error) of internal oscillator, refer to CHAPTER 28 ELECTRICAL
SPECIFICATIONS.
{ Reset
• Reset by RESET pin
• Reset by overflow of watchdog timer 1 (WDTRES1)
• Reset by overflow of watchdog timer 2 (WDTRES2)
• Reset by low-voltage detector (LVIRES)
• Reset by power-on-clear (POCRES)
• Reset by clock monitor (CLMRES)
• Reset output function (P00/TOH0 pin)
{ Low-voltage detector (LVI)
{ Power-on-clear (POC) circuit
{ Clock monitor (CLM) circuit
{ Package: 64-pin plastic TQFP (12 × 12)
64-pin plastic LQFP (fine pitch) (10 × 10)
1.3 Applications
{ Automotive
• System control of body electrical system (power windows, keyless entry reception, etc.)
• Submicrocontroller of control system
{ Home audio, car audio
{ AV equipment
{ PC peripheral devices (keyboards, etc.)
{ Household appliances
• Outdoor units of air conditioners
• Microwave ovens, rice cookers
{ Industrial devices
• Pumps
• Vending machines
• FA
<R>
1.4 Ordering Information
Part Number Package Quality Grade
μ
PD703302GK-×××-9ET-A
μ
PD703302GB-×××-8EU-A
μ
PD703302YGK-×××-9ET-A
μ
PD703302YGB-×××-8EU-A
μ
PD70F3302GK-9ET-A
μ
PD70F3302GB-8EU-A
μ
PD70F3302YGK-9ET-A
μ
PD70F3302YGB-8EU-A
Remarks 1. ××× indicates ROM code suffix.
2. Products with -A at the end of the part number are lead-free products.
CHAPTER 1 INTRODUCTION
64-pin plastic TQFP (12 × 12)
64-pin plastic LQFP (fine pitch) (10 × 10)
64-pin plastic TQFP (12 × 12)
64-pin plastic LQFP (fine pitch) (10 × 10)
64-pin plastic TQFP (12 × 12)
64-pin plastic LQFP (fine pitch) (10 × 10)
64-pin plastic TQFP (12 × 12)
64-pin plastic LQFP (fine pitch) (10 × 10)
Standard
Standard
Standard
Standard
Standard
Standard
Standard
Standard
24
User’s Manual U16896EJ2V0UD
Page 25
1.5 Pin Configuration (Top View)
64-pin plastic TQFP (12 × 12)
64-pin plastic LQFP (fine pitch) (10 × 10)
μ
PD703302GK-×××-9ET-A
μ
PD703302GB-×××-8EU-A
μ
PD703302YGK-×××-9ET-A
μ
PD703302YGB-×××-8EU-A
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
IC
Note 1
AV
AV
/FLMD0
NC
RESET
P00/TOH0
P01/TOH1
P02/NMI
P03/INTP0
P04/INTP1
REF0
Note 1
V
Note 2
V
X1
X2
XT1
XT2
SS
DD
SS
CHAPTER 1 INTRODUCTION
μ
PD70F3302GK-9ET-A
μ
PD70F3302GB-8EU-A
μ
PD70F3302YGK-9ET-A
μ
PD70F3302YGB-8EU-A
Note 3
P70/ANI0
P71/ANI1
P72/ANI2
P73/ANI3
P74/ANI4
P75/ANI5
P76/ANI6
P77/ANI7
P39/SCL0
Note 3
P38/SDA0
PDL7
Note 1
PDL6
PDL5/FLMD1
PDL4
PDL3
PDL2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PDL1
PDL0
PCM1/CLKOUT
PCM0
P915/INTP6
P914/INTP5
P913/INTP4
P99/SCK01
P98/SO01
P97/SI01
P96/TI51/TO51
P91/KR7/RXD1
P90/KR6/TXD1
P55/KR5/RTP05
P54/KR4/RTP04
EV
DD
P40/SI00
P05/INTP2
P06/INTP3
Notes 1. IC pin: Connect directly to V
FLMD0 pin: Connect to V
FLMD1 pin: Used only in the
SS in normal operation mode (
μ
P30/TXD0
P41/SO00
P42/SCK00
P31/RXD0/INTP7
P33/TIP00/TOP00
P32/ASCK0/ADTRG/TO01
SS (
μ
PD703302, 703302Y).
PD70F3302 and 70F3302Y.
2. Leave the NC pin open.
3. The SCL0 and SDA0 pins can be used only in the
Caution Make EV
DD the same potential as VDD.
User’s Manual U16896EJ2V0UD
SS
EV
P35/TI010/TO01
P34/TIP01/TOP01
P50/KR0/TI011/RTP00
μ
PD703302Y and 70F3302Y.
P53/KR3/RTP03
P51/KR1/TI50/RTP01
P52/KR2/TO50/RTP02
μ
PD70F3302, 70F3302Y).
25
Page 26
CHAPTER 1 INTRODUCTION
Pin identification
ADTRG: A/D trigger input
ANI0 to ANI7: Analog input
ASCK0: Asynchronous serial clock
AV
REF0: Analog reference voltage
AV
SS: Ground for analog
CLKOUT: Clock output
EV
DD: Power supply for port
EV
SS: Ground for port
FLMD0, FLMD1: Flash programming mode
IC: Internally connected
INTP0 to INTP7: External interrupt input
KR0 to KR7: Key return
NC: Non-connection
NMI: Non-maskable interrupt request
P00 to P06: Port 0
P30 to P35, P38, P39: Port 3
P40 to P42: Port 4
P50 to P55: Port 5
P70 to P77: Port 7
P90, P91, P96 to P99,
P913 to P915: Port 9
PDL0 to PDL7: Port DL
RESET: Reset
RTP00 to RTP05: Real-time output port
RXD0, RXD1: Receive data
SCK00, SCK01: Serial clock
SCL0: Serial clock
SDA0: Serial data
SI00, SI01: Serial input
SO00, SO01: Serial output
TI010, TI011,
TI50, TI51,
TIP00, TIP01: Timer input
TO01,
TO50, TO51,
TOH0, TOH1,
TOP00, TOP01: Timer output
TXD0, TXD1: Transmit data
V
DD: Power supply
VSS: Ground
X1, X2: Crystal for main clock
XT1, XT2: Crystal for subclock
PCM0, PCM1: Port CM
26
User’s Manual U16896EJ2V0UD
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1.6 Function Block Configuration
(1) Internal block diagram
NMI
INTP0 to INTP7
TI010, TI011
TO01
TIP00, TIP01
TOP00, TOP01
INTC
16-bit
timer/event
counter 0: 1 ch
16-bit timer/
event counter
P: 1 ch
CHAPTER 1 INTRODUCTION
ROM
PC
Note 1
RAM
4 KB
32-bit barrel
shifter
System
registers
General-purpose
registers
32 bits × 32
CPU
Multiplier
16 × 16 → 32
ALU
Instruction
queue
BCU
TI50, TI51
TO50, TO51
TOH0, TOH1
SO00, SO01
SI00, SI01
SCK00, SCK01
Note 2
SDA0
Note 2
SCL0
TXD0, TXD1
RXD0, RXD1
ASCK0
RTP00 to RTP05
8-bit
timer/event
counter 5: 2 ch
8-bit timer H:
2 ch
CSI0: 2 ch
Note 2
I2C
:
1 ch
UART
: 2 ch
Watchdog
timer: 2 ch
RTO: 1 ch
ROM
correction
PDL0 to PDL7
Internal
oscillator
Key interrupt
function
Watch timer
Port
P70 to P77
PCM0, PCM1
CLM
P50 to P55
P90, P91, P96 to P99, P913 to P915
Notes 1. μPD703302, 703302Y: 128 KB (mask ROM)
2. Only in the
3. Only in the
4. Only in the
μ
PD70F3302, 70F3302Y: 128 KB (flash memory)
μ
PD703302Y, 70F3302Y
μ
PD703302, 703302Y
μ
PD70F3302, 70F3302Y
P40 to P42
P00 to P06
P30 to P35, P38, P39
KR0 to KR7
A/D
converter
SS
REF0
AV
AV
ANI0 to ANI7
ADTRG
CG
POC
LVI
Note 3
IC
EV
DD
EV
SS
FLMD0, FLMD1
V
SS
Note 4
CLKOUT
X1
X2
XT1
XT2
RESET
V
DD
User’s Manual U16896EJ2V0UD
27
Page 28
(2) Internal units
(a) CPU
The CPU uses five-stage pipeline control to enable single-clock execution of address calculations,
arithmetic logic operations, data transfers, and almost all other types of instruction processing.
Other dedicated on-chip hardware, such as a multiplier (16 bits × 16 bits → 32 bits) and a barrel shifter
(32 bits) help accelerate complex processing.
(b) Bus control unit (BCU)
The BCU controls the internal bus.
(c) ROM
This consists of a 128 KB mask ROM or flash memory mapped to the address spaces from 0000000H to
001FFFFH.
ROM can be accessed by the CPU in one clock cycle during instruction fetch.
(d) RAM
This consists of a 4 KB RAM mapped to the address spaces from 3FFE000H to 3FFEFFFH.
RAM can be accessed by the CPU in one clock cycle during data access.
(e) Interrupt controller (INTC)
This controller handles hardware interrupt requests (NMI, INTP0 to INTP7) from on-chip peripheral
hardware and external hardware. Eight levels of interrupt priorities can be specified for these interrupt
requests, and multiplexed servicing control can be performed.
(f) Clock generator (CG)
A main clock oscillator and subclock oscillator are provided and generate the main clock oscillation
frequency (f
There are two modes: In the clock-through mode, f
the PLL mode, fX is used multiplied by 4.
The CPU clock frequency (f
(g) Timer/counter
One 16-bit timer/event counter 0 channel, one 16-bit timer/event counter P channel, and two 8-bit
timer/event counter 5 channels are incorporated, enabling measurement of pulse intervals and frequency
as well as programmable pulse output.
Two 8-bit timer/event counter 5 channels can be connected in cascade to configure a 16-bit timer.
Two 8-bit timer H channels enabling programmable pulse output are provided on chip.
(h) Watch timer
This timer counts the reference time (0.5 seconds) for counting the clock from the subclock (32.768 kHz)
or f
BRG (32.768 kHz) from the clock generator. At the same time, the watch timer can be used as an
interval timer.
CHAPTER 1 INTRODUCTION
X) and subclock frequency (fXT), respectively.
X is used as the main clock frequency (fXX) as is. In
CPU) can be selected from among fXX, fXX/2, fXX/4, fXX/8, fXX/16, fXX/32, and fXT.
28
User’s Manual U16896EJ2V0UD
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CHAPTER 1 INTRODUCTION
(i) Watchdog timer
Two watchdog timer channels are provided on chip to detect program loops and system abnormalities.
Watchdog timer 1 can be used as an interval timer. When used as a watchdog timer, it generates a non-
maskable interrupt request signal (INTWDT1) or system reset signal (WDTRES1) after an overflow occurs.
When used as an interval timer, it generates a maskable interrupt request signal (INTWDTM1) after an
overflow occurs.
Watchdog timer 2 operates by default following reset release.
It generates a non-maskable interrupt request signal (INTWDT2) or system reset signal (WDTRES2) after
an overflow occurs.
(j) Serial interface (SIO)
The V850ES/KE1+ includes three kinds of serial interfaces: an asynchronous serial interface (UARTn)
(supporting 1-channel LIN), a clocked serial interface (CSI0n), and an I
2
C bus interface (I2C0), and can
simultaneously use up to five channels.
For UARTn, data is transferred via the TXDn and RXDn pins.
For CSI0n, data is transferred via the SO0n, SI0n, and SCK0n pins.
2
For I
C0, data is transferred via the SDA0 and SCL0 pins.
I2C0 is provided only in the μPD703302Y and 70F3302Y.
Remark n = 0, 1
(k) A/D converter
This high-speed, high-resolution 10-bit A/D converter includes 8 analog input pins. Conversion is
performed using the successive approximation method.
(l) ROM correction
This function is used to replace part of a program in the mask ROM with that contained in the internal
RAM. Up to four correction addresses can be specified.
(m) Key interrupt function
A key interrupt request signal (INTKR) can be generated by inputting a falling edge to the eight key input
pins.
(n) Real-time output function
This function transfers 6-bit data set beforehand to output latches upon occurrence of a timer compare
register match signal.
A 1-channel 6-bit data real-time output function is provided on chip.
(o) Clock monitor
The clock monitor samples the main clock (f
X) using the internal oscillation clock (fR), and generates a
reset request signal when the oscillation of the main clock is stopped.
(p) Low-voltage detector (LVI)
The low-voltage detector compares the supply voltage (V
an internal interrupt signal or internal reset signal when V
DD) and detection voltage (VLVI), and generates
DD < VLVI.
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CHAPTER 1 INTRODUCTION
(q) Power-on-clear (POC) circuit
The power-on-clear circuit generates an internal reset signal at power on.
The power-on-clear circuit compares the supply voltage (V
an internal reset signal when V
DD < VPOC.
DD) and detection voltage (VPOC), and generates
(r) Ports
As shown below, the following ports have general-purpose port functions and control pin functions.
Port I/O Alternate Function
P0 7-bit I/O NMI, external interrupt, timer output
P3 8-bit I/O Serial interface, timer I/O, external interrupt, A/D converter trigger
P4 3-bit I/O Serial interface
P5 6-bit I/O Timer I/O, key interrupt function, real-time output function
P7 8-bit input A/D converter analog input
P9 9-bit I/O Serial interface, timer I/O, external interrupt, key interrupt function
PCM 2-bit I/O Clock output
PDL 8-bit I/O
−
30
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Page 31
<R>
<R>
CHAPTER 1 INTRODUCTION
1.7 Overview of Functions
Part Number
ROM 128 KB 128 KB (single-power flash memory) Internal
memory
Memory space 64 MB
General-purpose registers 32 bits × 32 registers
Main clock
(oscillation frequency)
Subclock
(oscillation frequency)
Minimum instruction
execution time
DSP function 32 × 32 = 64: 200 to 250 ns (at 20 MHz)
I/O ports 51
Timer 16-bit timer/event counter P: 1 channel
Real-time output port
A/D converter 10-bit resolution × 8 channels
Serial interface CSI: 2 channels
Interrupt sources
Power save function
Operating supply voltage 4.5 to 5.5 V (at 20 MHz)/2.7 to 5.5 V (at 10 MHz)
Package 64-pin plastic TQFP (12 × 12 mm)
High-speed RAM 4 KB
Ceramic/crystal/external clock
When PLL not used (2 to 10 MHz: 2.7 to 5.5 V)
When PLL used (2 to 5 MHz: 4.5 to 5.5 V, 2 to 2.5 MHz: 2.7 to 5.5 V)
• Input: 8
• I/O: 43 (among these, N-ch open-drain output selectable: 4, fixed to N-ch open-drain output: 2)
16-bit timer/event counter 0: 1 channel
8-bit timer/event counter 5: 2 channels
(16-bit timer/event counter: Usable as 1 channel)
8-bit timer H: 2 channels
Watchdog timer: 2 channels
Watch timer: 1 channel
8-bit interval timer: 1 channel
UART (supporting LIN): 1 channel
UART: 1 channel
2
C bus: 1 channel
I
Dedicated baud rate generator: 2 channels
μ
PD703302, 703302Y
50 ns (When main clock operated at (fXX) = 20 MHz)
Note 1
Crystal/external clock
(32.768 kHz)
32 × 32 + 32 = 32: 300 ns (at 20 MHz)
16 × 16 = 32: 50 to 100 ns (at 20 MHz)
16 × 16 + 32 = 32: 150 ns (at 20 MHz)
4 bits × 1, 2 bits × 1, or 6 bits × 1
External: 10 (10)
STOP/IDLE/HALT/sub-IDLE mode
64-pin plastic LQFP (fine pitch) (10 × 10 mm)
Note 2
, internal: 27/26
μ
PD70F3302, 70F3302Y
Note 1
Notes 1. Only in the μPD703302Y, 70F3302Y
2. The figure in parentheses indicates the number of external interrupts for which STOP mode can be
released.
User’s Manual U16896EJ2V0UD
31
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CHAPTER 2 PIN FUNCTIONS
The names and functions of the pins of the V850ES/KE1+ are described below, divided into port pins and non-port
pins.
The pin I/O buffer power supplies are divided into two systems; AV
REF0 and EVDD. The relationship between these
power supplies and the pins is shown below.
Table 2-1. Pin I/O Buffer Power Supplies
Power Supply Corresponding Pins
AVREF0 Port 7
EVDD RESET, ports 0, 3 to 5, 9, CM, DL
2.1 List of Pin Functions
(1) Port pins
Pin Name Pin No. I/O Pull-up Resistor
P00 12 TOH0
P01 13 TOH1
P02 14 NMI
P03 15 INTP0
P04 16 INTP1
P05 17 INTP2
P06 18
P30 22 TXD0
P31 23 RXD0/INTP7
P32 24 ASCK0/ADTRG/TO01
P33 25 TIP00/TOP00
P34 26 TIP01/TOP01
P35 27
P38 55 SDA0
P39 56
P40 19 SI00
P41 20 SO00
P42 21
I/O Yes
I/O
I/O Yes
Yes
No
Note 1
Port 0
I/O port
Input/output can be specified in 1-bit units.
Port 3
I/O port
Input/output can be specified in 1-bit units.
P38 and P39 are fixed to N-ch open-drain
output.
Port 4
I/O port
Input/output can be specified in 1-bit units.
P41 and P42 can be specified as N-ch open-
drain output in 1-bit units.
Function Alternate Function
INTP3
TI010/TO01
Note 2
Note 2
SCL0
SCK00
(1/2)
Notes 1. An on-chip pull-up resistor can be provided by a mask option (only in the μPD703302, 703302Y).
2. Only in the
32
μ
PD703302Y, 70F3302Y
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Page 33
CHAPTER 2 PIN FUNCTIONS
(2/2)
Pin Name Pin No. I/O Pull-up Resistor Function Alternate Function
P50 28 TI011/RTP00/KR0
P51 29 TI50/RTP01/KR1
P52 30 TO50/RTP02/KR2
P53 31 RTP03/KR3
P54 34 RTP04/KR4
P55 35
P70 64 ANI0
P71 63 ANI1
P72 62 ANI2
P73 61 ANI3
P74 60 ANI4
P75 59 ANI5
P76 58 ANI6
P77 57
P90 36 TXD1/KR6
P91 37 RXD1/KR7
P96 38 TI51/TO51
P97 39 SI01
P98 40 SO01
P99 41 SCK01
P913 42 INTP4
P914 43 INTP5
P915 44
PCM0 45 –
PCM1 46
PDL0 47 −
PDL1 48 −
PDL2 49 −
PDL3 50 −
PDL4 51 −
PDL5 52 FLMD1
PDL6 53 −
PDL7 54
I/O Yes
Input No
I/O Yes Port 9
I/O Yes Port CM
I/O
Yes
Port 5
I/O port
Input/output can be specified in 1-bit units.
Port 7
Input port
I/O port
Input/output can be specified in 1-bit units.
P98 and P99 can be specified as N-ch opendrain output in 1-bit units.
I/O port
Input/output can be specified in 1-bit units.
Port DL
I/O port
Input/output can be specified in 1-bit units.
RTP05/KR5
ANI7
INTP6
CLKOUT
Note
−
Note Only in the μPD70F3302, 70F3302Y
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CHAPTER 2 PIN FUNCTIONS
(2) Non-port pins
Pin Name Pin No. I/O Pull-up Resistor
ADTRG 24 Input Yes A/D converter external trigger input P32/ASCK0/TO01
ANI0 64 P70
Input No Analog voltage input for A/D converter
ANI1 63 P71
ANI2 62 P72
ANI3 61 P73
ANI4 60 P74
ANI5 59 P75
ANI6 58 P76
ANI7 57
ASCK0 24 Input Yes UART0 serial clock input P32/ADTRG/TO01
AVREF0 1 – – Reference voltage for A/D converter and
AVSS 2 – – Ground potential for A/D converter and
CLKOUT 46 Output No Internal system clock output PCM1
EVDD 33 – – Positive power supply for external –
EVSS 32 – – Ground potential for external –
Note 1
FLMD0
FLMD1
IC
INTP0 15 P03
3 No –
Note 1
52
Note 2
3 – – Internally connected –
Input
Yes
Input Yes
INTP1 16 P04
INTP2 17
INTP3 18 External interrupt request input
INTP4 42 P913
INTP5 43 P914
INTP6 44 P915
INTP7 23
KR0 28 P50/TI011/RTP00
Input Yes Key return input
KR1 29 P51/TI50/RTP01
KR2 30 P52/TO50/RTP02
KR3 31 P53/RTP03
KR4 34 P54/RTP04
KR5 35 P55/RTP05
KR6 36 P90/TXD1
KR7 37
NC 5 – – Not internally connected. Leave open. –
NMI 14 Input Yes External interrupt input
RESET 9 Input – System reset input –
Function Alternate Function
positive power supply for alternate-function
ports
alternate-function ports
Flash programming mode setting pin
External interrupt request input
(maskable, analog noise elimination)
(maskable, digital + analog noise elimination)
External interrupt request input
(maskable, analog noise elimination)
(non-maskable, analog noise elimination)
P77
–
–
PDL5
P05
P06
P31/RXD0
P91/RXD1
P02
Notes 1. Only in the μPD70F3302, 70F3302Y
μ
2. Only in the
PD703302, 703302Y
(1/2)
34
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CHAPTER 2 PIN FUNCTIONS
(2/2)
Pin Name Pin No. I/O Pull-up Resistor Function Alternate Function
RTP00 28 P50/TI011/KR0
Output Yes Real-time output port
RTP01 29 P51/TI50/KR1
RTP02 30 P52/TO50/KR2
RTP03 31 P53/KR3
RTP04 34 P54/KR4
RTP05 35
RXD0 23 Serial receive data input for UART0 P31/INTP7
RXD1 37
SCK00 21 P42
SCK01 41
Note 1
SCL0
56 I/O No
Input Yes
Serial receive data input for UART1 P91/KR7
I/O Yes Serial clock I/O for CSI00 and CSI01
N-ch open-drain output can be specified in 1-
bit units.
Note 2
Serial clock I/O for I2C0
P55/KR5
P99
P39
Fixed to N-ch open-drain output
SDA0
Note 1
55 I/O No
Note 2
Serial transmit/receive data I/O for I2C0
P38
Fixed to N-ch open-drain output
SI00 19 Serial receive data input for CSI00 P40
SI01 39
SO00 20 P41
SO01 40
TI010 27 Capture trigger input/external event input for TM01 P35/TO01
Input Yes
Serial receive data input for CSI01 P97
Output Yes Serial transmit data output for CSI00 and CSI01
N-ch open-drain output can be specified in 1-bit
units.
Input Yes
P98
TI011 28 Capture trigger input for TM01 P50/RTP00/KR0
TI50 29 External event input for TM50 P51/RTP01/KR1
TI51 38 External event input for TM51 P96/TO51
TIP00 25 Capture trigger input/external event input for
P33/TOP00
TMP0
TIP01 26
24 P32/ASCK0/ADTRG TO01
27
Output Yes
Capture trigger input for TMP0 P34/TOP01
Timer output for TM01
P35/TI010
TO50 30 Timer output for TM50 P52/RTP02/KR2
TO51 38 Timer output for TM51 P96/TI51
TOH0 12 Timer output for TMH0 P00
TOH1 13 Timer output for TMH1 P01
TOP00 25 P33/TIP00
TOP01 26
TXD0 22 Serial transmit data output for UART0 P30
Output Yes
TXD1 36
Timer output for TMP0
P34/TIP01
Serial transmit data output for UART1 P90/KR6
VDD 4 – – Positive power supply pin for internal –
VSS 6 – – Ground potential for internal –
X1 7 Input No –
X2 8 – No
XT1 10 Input No –
XT2 11 – No
Connecting resonator for main clock
–
Connecting resonator for subclock
–
Notes 1. Only in the μPD703302Y, 70F3302Y
μ
2. An on-chip pull-up resistor can be provided by a mask option (only in the
PD703302Y).
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CHAPTER 2 PIN FUNCTIONS
2.2 Pin I/O Circuits and Recommended Connection of Unused Pins
Pin Alternate Function Pin No. I/O Circuit Type Recommended Connection
P00 TOH0 12
5-A
P01 TOH1 13
P02 NMI 14
5-W
P03 to P06 INTP0 to INTP3 15 to 18
P30 TXD0 22 5-A
P31 RXD0/INTP7 23
5-W
P32 ASCK0/ADTRG 24
P33 TIP00/TOP00 25
P34 TIP01/TOP01 26
P35 TI010/TO01 27
<R>
Note 1
55
13-AE
13-AD
<R>
Note 1
56
13-AE
13-AD
P40 SI00 19 5-W
P41 SO00 20 10-E
P42 SCK00 21 10-F
P50 TI011/RTP00/KR0 28
8-A
P51 TI50/RTP01/KR1 29
P52 TO50/RTP02/KR2 30
P53 RTP03/KR3 31
P54 RTP04/KR4 34
10-A
P55 RTP05/KR5 35
P70 to P77 ANI0 to ANI7 64 to 57 9-C Connect to AVREF0 or AVSS.
P90 TXD1/KR6 36
8-A
P91 RXD1/KR7 37
P96 TI51/TO51 38
P97 SI01 39 5-W
P98 SO01 40 10-E
P99 SCK01 41 10-F
P913 to P915 INTP4 to INTP6 42 to 44 5-W
PCM0 – 45
5-A
PCM1 CLKOUT 46
PDL0 to PDL4 – 47 to 51
PDL5 FLMD1
Note 3
52
PDL6, PDL7 – 53, 54
Notes 1. Only in the μPD703302Y, 70F3302Y
μ
2. Only in the
3. Only in the
PD703302, 703302Y
μ
PD70F3302, 70F3302Y
Input: Independently connect to EV
via a resistor.
Output: Leave open.
Note 2
P38 SDA0
Note 3
Note 2
P39 SCL0
Note 3
Input: Independently connect to EV
via a resistor.
Output: Leave open.
(1/2)
DD or EVSS
DD or EVSS
36
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<R>
CHAPTER 2 PIN FUNCTIONS
(2/2)
Pin Alternate Function Pin No. I/O Circuit Type Recommended Connection
AVREF0 – 1 – Directly connect to VDD.
AVSS – 2 – –
EVDD – 33 – –
EVSS – 32 – –
Note 1
IC
– 3 –
Directly connect to EV
SS or VSS or pull down
with a 10 kΩ resistor.
NC – 5 – Leave open.
RESET – 9 2 Connect to EVDD via a resistor.
FLMD0
Note 2
– 3 –
Directly connect to EV
SS or VSS or pull down
with a 10 kΩ resistor.
VDD – 4 – –
VSS – 6 – –
X1 – 7 – –
X2 – 8 – –
XT1 – 10 16 Directly connect to VSS
Note 3
.
XT2 – 11 16 Leave open.
Notes 1. Only in the μPD703302, 703302Y
2. Only in the
μ
PD70F3302, 70F3302Y
3. Be sure to set the PSMR.XTSTP bit to 1 when this pin is not used.
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2.3 Pin I/O Circuits
Type 2
IN
CHAPTER 2 PIN FUNCTIONS
Type 9-C
P-ch
IN
N-ch
AV
AV
SS
REF0
Comparator
+
–
(threshold voltage)
(1/2)
Schmitt-triggered input with hysteresis characteristics
Type 5-A
Pull-up
enable
Data
Output
disable
V
DD
P-ch
N-ch
V
V
DD
P-ch
SS
Input
enable
Type 5-W
Pull-up
enable
Data
Output
disable
DD
V
P-ch
N
-ch
V
P-ch
SS
IN/OUT
V
DD
IN/OUT
Type 10-A
Pull-up
enable
Data
Open drain
Output
disable
Type 10-E
Pull-up
enable
Data
Open drain
Output
disable
V
V
DD
DD
P-ch
N-ch
Input enable
P-ch
N-ch
V
SS
P-ch
V
SS
V
P-ch
V
DD
IN/OUT
DD
IN/OUT
38
Type 8-A
Pull-up
enable
Data
Output
disable
Input
enable
Input
enable
V
V
DD
Type 10-F
Pull-up
P-ch
DD
V
P-ch
IN/OUT
N-ch
V
SS
enable
Data
Open drain
Output
disable
V
DD
P-ch
N-ch
V
SS
DD
P-ch
IN/OUT
Input
enable
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<R>
Type 13-AD
Data
Output
disable
Input
enable
CHAPTER 2 PIN FUNCTIONS
(2/2)
Type 16
Feedback cut-off
IN/OUT
N
-ch
V
SS
XT1 XT2
P-ch
Type 13-AE
Data
Output
disable
Input
enable
Remark Read V
V
DD
Mask
option
IN/OUT
N
-ch
V
SS
DD as EVDD. Also, read VSS as EVSS.
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The CPU of the V850ES/KE1+ is based on the RISC architecture and executes most instructions in one clock
cycle by using 5-stage pipeline control.
3.1 Features
{ Number of instructions: 83
{ Minimum instruction execution time: 50.0 ns (@ 20 MHz operation: 4.5 to 5.5 V)
<R>
100 ns (@ 10 MHz operation: 2.7 to 5.5 V)
{ Memory space Program (physical address) space: 64 MB linear
Data (logical address) space: 4 GB linear
{ General-purpose registers: 32 bits × 32
{ Internal 32-bit architecture
{ 5-stage pipeline control
{ Multiply/divide instructions
{ Saturated operation instructions
{ 32-bit shift instruction: 1 clock
{ Load/store instruction with long/short format
{ Four types of bit manipulation instructions
• SET1
• CLR1
• NOT1
• TST1
CHAPTER 3 CPU FUNCTIONS
40
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CHAPTER 3 CPU FUNCTIONS
3.2 CPU Register Set
The CPU registers of the V850ES/KE1+ can be classified into two categories: a general-purpose program register
set and a dedicated system register set. All the registers have 32-bit width.
For details, refer to the V850ES Architecture User’s Manual.
(1) Program register set (2) System register set
31 0 31 0
r0
r1
r2
r3
r4
r5
r6
r7
r8
r9
r10
r11
r12
r13
r14
r15
r16
r17
r18
r19
r20
r21
r22
r23
r24
r25
r26
r27
r28
r29
r30
r31
(Zero register)
(Assembler-reserved register)
(Stack pointer (SP))
(Global pointer (GP))
(Text pointer (TP))
(Element pointer (EP))
(Link pointer (LP))
EIPC
EIPSW
FEPC
FEPSW
ECR (Interrupt source register)
PSW (Program status word)
CTPC
CTPSW
DBPC
DBPSW
CTBP (CALLT base pointer)
(Interrupt status saving register)
(Interrupt status saving register)
(NMI status saving register)
(NMI status saving register)
(CALLT execution status saving register)
(CALLT execution status saving register)
(Exception/debug trap status saving register)
(Exception/debug trap status saving register)
31 0
PC (Program counter)
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CHAPTER 3 CPU FUNCTIONS
3.2.1 Program register set
The program register set includes general-purpose registers and a program counter.
(1) General-purpose registers (r0 to r31)
Thirty-two general-purpose registers, r0 to r31, are available. All of these registers can be used as a data
variable or address variable.
However, r0 and r30 are implicitly used by instructions and care must be exercised when using these registers.
r0 always holds 0 and is used for operations that use 0 and offset 0 addressing. r30 is used as a base pointer
when performing memory access with the SLD and SST instructions.
Also, r1, r3 to r5, and r31 are implicitly used by the assembler and C compiler. Therefore, before using these
registers, their contents must be saved so that they are not lost, and they must be restored to the registers
after the registers have been used. There are cases when r2 is used by the real-time OS. If r2 is not used by
the real-time OS, r2 can be used as a variable register.
Table 3-1. Program Registers
Name Usage Operation
r0 Zero register Always holds 0
r1 Assembler-reserved register Working register for generating 32-bit immediate
r2 Address/data variable register (when r2 is not used by the real-time OS to be used)
r3 Stack pointer Used to generate stack frame when function is called
r4 Global pointer Used to access global variable in data area
r5 Text pointer Register to indicate the start of the text area (area for placing program code)
r6 to r29 Address/data variable register
r30 Element pointer Base pointer when memory is accessed
r31 Link pointer Used by compiler when calling function
PC Program counter Holds instruction address during program execution
(2) Program counter (PC)
This register holds the address of the instruction under execution. The lower 26 bits of this register are valid,
and bits 31 to 26 are fixed to 0. If a carry occurs from bit 25 to bit 26, it is ignored.
Bit 0 is fixed to 0, and branching to an odd address cannot be performed.
31 26 25 1 0
PC
Fixed to 0 Instruction address under execution 0
After reset
00000000H
42
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CHAPTER 3 CPU FUNCTIONS
3.2.2 System register set
System registers control the status of the CPU and hold interrupt information.
Read from and write to system registers are performed by setting the system register numbers shown below with
the system register load/store instructions (LDSR, STSR instructions).
Table 3-2. System Register Numbers
<R>
System
Register No.
0 Interrupt status saving register (EIPC)
1 Interrupt status saving register (EIPSW)
2 NMI status saving register (FEPC)
3 NMI status saving register (FEPSW)
System Register Name
Note 1
Yes Yes
Note 1
Yes Yes
Note 1
Yes Yes
Note 1
Yes Yes
Operand Specification Enabled
LDSR
Instruction
STSR
Instruction
4 Interrupt source register (ECR) No Yes
5 Program status word (PSW) Yes Yes
6 to 15
Reserved numbers for future function expansion (The operation is not guaranteed
No No
if accessed.)
16 CALLT execution status saving register (CTPC) Yes Yes
17 CALLT execution status saving register (CTPSW) Yes Yes
18 Exception/debug trap status saving register (DBPC) Yes
19 Exception/debug trap status saving register (DBPSW) Yes
Note 2
Yes
Note 2
Yes
Note 2
Note 2
20 CALLT base pointer (CTBP) Yes Yes
21 to 31
Reserved numbers for future function expansion (The operation is not guaranteed
No No
if accessed.)
Notes 1. Since only one set of these registers is available, the contents of this register must be saved by the
program when multiple interrupt servicing is enabled.
2. These registers can be accessed only during the interval between the execution of the DBTRAP
instruction or illegal opcode and the DBRET instruction.
Caution Even if bit 0 of EIPC, FEPC, or CTPC is set (1) by the LDSR instruction, bit 0 is ignored during return
with the RETI instruction following interrupt servicing (because bit 0 of PC is fixed to 0). When
setting a value to EIPC, FEPC, and CTPC, set an even number (bit 0 = 0).
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CHAPTER 3 CPU FUNCTIONS
(1) Interrupt status saving registers (EIPC, EIPSW)
There are two interrupt status saving registers, EIPC and EIPSW.
Upon occurrence of a software exception or a maskable interrupt, the contents of the program counter (PC)
are saved to EIPC and the contents of the program status word (PSW) are saved to EIPSW (upon occurrence
of a non-maskable interrupt (NMI), the contents are saved to the NMI status saving registers (FEPC, FEPSW)).
The address of the next instruction following the instruction executed when a software exception or maskable
interrupt occurs is saved to EIPC, except for some instructions (refer to 17.9 Periods in Which Interrupts
Are Not Acknowledged by CPU).
The current PSW contents are saved to EIPSW.
Since there is only one set of interrupt status saving registers, the contents of these registers must be saved
by the program when multiple interrupt servicing is enabled.
Bits 31 to 26 of EIPC and bits 31 to 8 of EIPSW are reserved (fixed to 0) for future function expansion.
When the RETI instruction is executed, the values in EIPC and EIPSW are restored to the PC and PSW,
respectively.
31 0
EIPC
31 0
EIPSW
26 25
0 0 0 0
0 0 0 0 00 0 0 0 0 00 0 0 0 0 00 0 0 0 0
(PC contents saved)00
7
8
(PSW contents saved)00
After reset
0xxxxxxxH
(x: Undefined)
After reset
000000xxH
(x: Undefined)
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CHAPTER 3 CPU FUNCTIONS
(2) NMI status saving registers (FEPC, FEPSW)
There are two NMI status saving registers, FEPC and FEPSW.
Upon occurrence of a non-maskable interrupt (NMI), the contents of the program counter (PC) are saved to
FEPC and the contents of the program status word (PSW) are saved to FEPSW.
The address of the next instruction following the instruction executed when a non-maskable interrupt occurs is
saved to FEPC, except for some instructions.
The current PSW contents are saved to FEPSW.
Since there is only one set of NMI status saving registers, the contents of these registers must be saved by the
program when multiple interrupt servicing is performed.
Bits 31 to 26 of FEPC and bits 31 to 8 of FEPSW are reserved (fixed to 0) for future function expansion.
FEPC
FEPSW
31 0
31 0
00
26 25
0 0 0 0
0 0 0 0 00 0 0 0 0 00 0 0 0 0 00 0 0 0 0
(PC contents saved)00
8
7
(PSW contents saved)
After reset
0xxxxxxxH
(x: Undefined)
After reset
000000xxH
(x: Undefined)
(3) Interrupt source register (ECR)
Upon occurrence of an interrupt or an exception, the interrupt source register (ECR) holds the source of an
interrupt or an exception. The value held by ECR is the exception code coded for each interrupt source. This
register is a read-only register, and thus data cannot be written to it using the LDSR instruction.
ECR
31 0
FECC EICC
16 15
After reset
00000000H
Bit position Bit name Description
31 to 16 FECC Non-maskable interrupt (NMI) exception code
15 to 0 EICC Exception, maskable interrupt exception code
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(4) Program status word (PSW)
The program status word (PSW) is a collection of flags that indicate the program status (instruction execution
result) and the CPU status.
When the contents of this register are changed using the LDSR instruction, the new contents become valid
immediately following completion of LDSR instruction execution. Interrupt request acknowledgment is held
pending while a write to the PSW is being executed by the LDSR instruction.
Bits 31 to 8 are reserved (fixed to 0) for future function expansion.
CHAPTER 3 CPU FUNCTIONS
(1/2)
31 0
PSW
RFU
Bit position Flag name Description
31 to 8 RFU Reserved field. Fixed to 0.
7 NP
6 EP
5 ID
4 SAT
3 CY
2 OV
1 S
0 Z
Note
Note
Note
Indicates that non-maskable interrupt (NMI) servicing is in progress. This flag is set to 1 when
an NMI request is acknowledged, and disables multiple interrupts.
0: NMI servicing not in progress
1: NMI servicing in progress
Indicates that exception processing is in progress. This flag is set to 1 when an exception
occurs. Moreover, interrupt requests can be acknowledged even when this bit is set.
0: Exception processing not in progress
1: Exception processing in progress
Indicates whether maskable interrupt request acknowledgment is enabled.
0: Interrupt enabled
1: Interrupt disabled
Indicates that the result of executing a saturated operation instruction has overflowed and that
the calculation result is saturated. Since this is a cumulative flag, it is set to 1 when the result of
a saturated operation instruction becomes saturated, and it is not cleared to 0 even if the
operation results of successive instructions do not become saturated. This flag is neither set
nor cleared when arithmetic operation instructions are executed.
0: Not saturated
1: Saturated
Indicates whether carry or borrow occurred as the result of an operation.
0: No carry or borrow occurred
1: Carry or borrow occurred
Indicates whether overflow occurred during an operation.
0: No overflow occurred
1: Overflow occurred.
Indicates whether the result of an operation is negative.
0: Operation result is positive or 0.
1: Operation result is negative.
Indicates whether operation result is 0.
0: Operation result is not 0.
1: Operation result is 0.
Remark Note is explained on the following page.
87NP6EP5ID4
SAT3CY2OV
1
SZ
After reset
00000020H
46
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CHAPTER 3 CPU FUNCTIONS
Note During saturated operation, the saturated operation results are determined by the contents of the OV
flag and S flag. The SAT flag is set (to 1) only when the OV flag is set (to 1) during saturated operation.
(2/2)
Flag status
Maximum positive value exceeded 1 1 0 7FFFFFFFH
Maximum negative value exceeded 1 1 1 80000000H
Positive (maximum value not exceeded) 0
Negative (maximum value not exceeded)
Operation result status
SAT OV S
Holds value
before operation
0
1
Saturated
operation result
Actual operation
result
(5) CALLT execution status saving registers (CTPC, CTPSW)
There are two CALLT execution status saving registers, CTPC and CTPSW.
When the CALLT instruction is executed, the contents of the program counter (PC) are saved to CTPC, and
the program status word (PSW) contents are saved to CTPSW.
The contents saved to CTPC consist of the address of the next instruction after the CALLT instruction.
The current PSW contents are saved to CTPSW.
Bits 31 to 26 of CTPC and bits 31 to 8 of CTPSW are reserved (fixed to 0) for future function expansion.
CTPC
CTPSW
31 0
31 0
00
26 25
0 0 0 0
0 0 0 0 00 0 0 0 0 00 0 0 0 0 00 0 0 0 0
(PC contents saved)00
8
7
(PSW contents saved)
After reset
0xxxxxxxH
(x: Undefined)
After reset
000000xxH
(x: Undefined)
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CHAPTER 3 CPU FUNCTIONS
(6) Exception/debug trap status saving registers (DBPC, DBPSW)
There are two exception/debug trap status saving registers, DBPC and DBPSW.
Upon occurrence of an exception trap or debug trap, the contents of the program counter (PC) are saved to
DBPC, and the program status word (PSW) contents are saved to DBPSW.
The contents saved to DBPC consist of the address of the next instruction after the instruction executed when
an exception trap or debug trap occurs.
The current PSW contents are saved to DBPSW.
Bits 31 to 26 of DBPC and bits 31 to 8 of DBPSW are reserved (fixed to 0) for future function expansion.
DBPC
DBPSW
31 0
31 0
00
26 25
0 0 0 0
0 0 0 0 00 0 0 0 0 00 0 0 0 0 00 0 0 0 0
(PC contents saved) 00
(7) CALLT base pointer (CTBP)
The CALLT base pointer (CTBP) is used to specify table addresses and generate target addresses (bit 0 is
fixed to 0).
Bits 31 to 26 are reserved (fixed to 0) for future function expansion.
31 0
CTBP
26 25
0 0 0 0 0
(Base address) 00
8
7
(PSW contents saved)
After reset
0xxxxxxxH
(x: Undefined)
After reset
000000xxH
(x: Undefined)
After reset
0xxxxxxxH
(x: Undefined)
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CHAPTER 3 CPU FUNCTIONS
3.3 Operating Modes
The V850ES/KE1+ has the following operating modes.
(1) Normal operating mode
After the system has been released from the reset state, the pins related to the bus interface are set to the port
mode, execution branches to the reset entry address of the internal ROM, and instruction processing is started.
(2) Flash memory programming mode
This mode is valid only in flash memory versions (
When this mode is specified, the internal flash memory can be programmed by using a flash programmer.
(a) Specifying operating mode
The operating mode is specified according to the status (input level) of the FLMD0 and FLMD1 pins.
In the normal operating mode, input a low level to the FLMD0 pin during the reset period.
A high level is input to the FLMD0 pin by the flash programmer in the flash memory programming mode if
a flash programmer is connected. In the self-programming mode, input a high level to this pin from an
external circuit.
Fix the specification of these pins in the application system and do not change the setting of these pins
during operation.
FLMD0 FLMD1 Operating Mode
L
H L Flash memory programming mode
H H Setting prohibited
×
Remark H: High level
L: Low level
×: don’t care
Normal operating mode
μ
PD70F3302 and 70F3302Y).
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CHAPTER 3 CPU FUNCTIONS
3.4 Address Space
3.4.1 CPU address space
For instruction addressing, an internal ROM area of up to 1 MB, and an internal RAM area are supported in a linear
address space (program space) of up to 64 MB. For operand addressing (data access), up to 4 GB of a linear
address space (data space) is supported. The 4 GB address space, however, is viewed as 64 images of a 64 MB
physical address space. This means that the same 64 MB physical address space is accessed regardless of the
value of bits 31 to 26.
Figure 3-1. Address Space Image
Image 63
Program space
Use-prohibited area
Internal RAM area
Use-prohibited area
4 GB
64 MB
•
•
•
Image 1
Image 0
Data space
On-chip peripheral I/O area
Internal RAM area
64 MB
Use-prohibited area
Internal ROM area
(external memory area)
50
1 MB
Internal ROM area
(external memory area)
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CHAPTER 3 CPU FUNCTIONS
3.4.2 Wraparound of CPU address space
(1) Program space
Of the 32 bits of the program counter (PC), the higher 6 bits are fixed to 0 and only the lower 26 bits are valid.
Even if a carry or borrow occurs from bit 25 to bit 26 as a result of branch address calculation, the higher 6 bits
ignore this and remain 0.
Therefore, the lower-limit address of the program space, 00000000H, and the upper-limit address,
03FFFFFFH, are contiguous addresses, and the program space is wrapped around at the boundary of these
addresses.
Caution No instructions can be fetched from the 4 KB area of 03FFF000H to 03FFFFFFH because this
area is an on-chip peripheral I/O area. Therefore, do not execute any branch operation
instructions in which the destination address will reside in any part of this area.
(2) Data space
The result of an operand address calculation that exceeds 32 bits is ignored.
Therefore, the lower-limit address of the data space, address 00000000H, and the upper-limit address,
FFFFFFFFH, are contiguous addresses, and the data space is wrapped around at the boundary of these
addresses.
00000001H
00000000H
03FFFFFFH
03FFFFFEH
00000001H
Program space
(+) direction (–) direction
Program space
Data space
00000000H
FFFFFFFFH
FFFFFFFEH
Data space
(+) direction (–) direction
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CHAPTER 3 CPU FUNCTIONS
3.4.3 Memory map
The V850ES/KE1+ has reserved areas as shown below.
Figure 3-2. Data Memory Map (Physical Addresses)
3FFFFFFH
(80 KB)
3FEC000H
3FEBFFFH
On-chip peripheral I/O area
(4 KB)
Internal RAM area
(60 KB)
Use-prohibited area
3FFFFFFH
3FFF000H
3FFEFFFH
3FFF000H
3FFEFFFH
3FEC000H
Use-prohibited area
0100000H
00FFFFFH
0000000H
Internal ROM area
(1 MB)
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CHAPTER 3 CPU FUNCTIONS
Figure 3-3. Program Memory Map
03FFFFFFH
03FFF000H
03FFEFFFH
03FF0000H
03FEFFFFH
Use-prohibited area
(Program fetch disabled area)
Internal RAM area (60 KB)
Use-prohibited area
(Program fetch disabled area)
00100000H
000FFFFFH
00000000H
Internal ROM area
(1 MB)
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3.4.4 Areas
(1) Internal ROM area
An area of 1 MB from 0000000H to 00FFFFFH is reserved for the internal ROM area.
(a) Internal ROM (128 KB)
A 128 KB area from 0000000H to 001FFFFH is provided in the V850ES/KE1+.
Addresses 0020000H to 00FFFFFH are an access-prohibited area.
CHAPTER 3 CPU FUNCTIONS
Figure 3-4. Internal ROM Area (128 KB)
00FFFFFH
Access-prohibited
area
(2) Internal RAM area
An area of 60 KB maximum from 3FF0000H to 3FFEFFFH is reserved for the internal RAM area.
(a) Internal RAM (4 KB)
A 4 KB area from 3FFE000H to 3FFEFFFH is provided as physical internal RAM in the V850ES/KE1+.
Addresses 3FF0000H to 3FFDFFFH are an access-prohibited area.
Physical address space
3FFEFFFH
3FFE000H
3FFDFFFH
0020000H
001FFFFH
Internal ROM area
(128 KB)
0000000H
Figure 3-5. Internal RAM Area (4 KB)
Internal RAM area (4 KB)
Logical address space
FFFEFFFH
FFFE000H
FFFDFFFH
54
3FF0000H
Access-prohibited area
FFF0000H
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(3) On-chip peripheral I/O area
A 4 KB area from 3FFF000H to 3FFFFFFH is reserved as the on-chip peripheral I/O area.
Physical address space
CHAPTER 3 CPU FUNCTIONS
Figure 3-6. On-Chip Peripheral I/O Area
Logical address space
3FFFFFFH
On-chip peripheral I/O area
(4 KB)
3FFF000H
FFFFFFFH
FFFF000H
Peripheral I/O registers assigned with functions such as on-chip peripheral I/O operation mode specification
and state monitoring are mapped to the on-chip peripheral I/O area. Program fetches are not allowed in this
area.
Cautions 1. If word access of a register is attempted, halfword access to the word area is performed
twice, first for the lower bits, then for the higher bits, ignoring the lower 2 address bits.
2. If a register that can be accessed in byte units is accessed in halfword units, the higher 8
bits become undefined if the access is a read operation. If a write access is performed,
only the data in the lower 8 bits is written to the register.
3. Addresses that are not defined as registers are reserved for future expansion. If these
addresses are accessed, the operation is undefined and not guaranteed.
(4) Number of clocks for access
The following table shows the number of base clocks required for accessing each resource.
Area (Bus Width)
Bus Cycle Type
Instruction fetch (normal access) 1 1
Instruction fetch (branch) 2 2
Operand data access 3 1 3
Internal ROM
(32 Bits)
Internal RAM
(32 Bits)
Note 1
Note 1
On-Chip Peripheral I/O
Notes 1. If the access conflicts with a data access, the number of clock is incremented by 1.
2. This value varies depending on the setting of the VSWC register.
Remark Unit: Clocks/access
(16 Bits)
−
−
Note 2
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CHAPTER 3 CPU FUNCTIONS
3.4.5 Recommended use of address space
The architecture of the V850ES/KE1+ requires that a register that serves as a pointer be secured for address
generation when operand data in the data space is accessed. The address stored in this pointer ±32 KB can be
directly accessed by an instruction for operand data. Because the number of general-purpose registers that can be
used as a pointer is limited, however, by keeping the performance from dropping during address calculation when a
pointer value is changed, as many general-purpose registers as possible can be secured for variables, and the
program size can be reduced.
(1) Program space
Of the 32 bits of the PC (program counter), the higher 6 bits are fixed to 0, and only the lower 26 bits are valid.
Regarding the program space, therefore, a 64 MB space of contiguous addresses starting from 00000000H
unconditionally corresponds to the memory map.
To use the internal RAM area as the program space, access the addresses 3FFE000H to 3FFEFFFH (4 KB).
(2) Data space
With the V850ES/KE1+, it seems that there are sixty-four 64 MB address spaces on the 4 GB CPU address
space. Therefore, the least significant bit (bit 25) of a 26-bit address is sign-extended to 32 bits and allocated
as an address.
(a) Application example of wraparound
If R = r0 (zero register) is specified for the LD/ST disp16 [R] instruction, a range of addresses 00000000H
±32 KB can be addressed by sign-extended disp16. All the resources, including the internal hardware,
can be addressed by one pointer.
The zero register (r0) is a register fixed to 0 by hardware, and practically eliminates the need for registers
dedicated to pointers.
Example:
μ
PD703302, 703302Y
0001FFFFH
56
00007FFFH
(R = )
00000000H
FFFFF000H
FFFFEFFFH
FFFFE000H
FFFFDFFFH
FFFF8000H
Internal ROM area
On-chip peripheral
I/O area
Internal RAM
area
Access-prohibited
area
User’s Manual U16896EJ2V0UD
32 KB
4 KB
4 KB
24 KB
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CHAPTER 3 CPU FUNCTIONS
Figure 3-7. Recommended Memory Map
FFFFFFFFH
FFFFF000H
FFFFEFFFH
FFFFC000H
FFFEFFFFH
04000000H
03FFFFFFH
03FFF000H
03FFEFFFH
03FFE000H
03FFDFFFH
03FF0000H
03FEFFFFH
On-chip
peripheral I/O
Internal RAM
Note
Data spaceProgram space
On-chip
peripheral I/O
Internal RAM
On-chip
peripheral I/O
Internal RAM
Use prohibited
xFFFFFFFH
xFFFF000H
xFFFEFFFH
xFFFE000H
xFFFDFFFH
xFFE0000H
xFFEFFFFH
Program space
64 MB
00100000H
000FFFFFH
00020000H
0001FFFFH
00000000H
Use prohibited
Internal ROM
x0100000H
x00FFFFFH
Internal ROM
x0000000H
Internal ROM
Note Access to this area is prohibited. To access the on-chip peripheral I/O in this area, specify addresses
FFFF000H to FFFFFFFH.
Remarks 1.
indicates the recommended area.
2. This figure is the recommended memory map of the μPD703302 and 703302Y.
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CHAPTER 3 CPU FUNCTIONS
3.4.6 Peripheral I/O registers
Operable Bit Unit Address Function Register Name Symbol R/W
1 8 16
FFFFF004H Port DL register PDL R/W
FFFFF00CH Port CM register PCM R/W
FFFFF024H Port DL mode register PMDL R/W
FFFFF02CH Port CM mode register PMCM R/W
FFFFF04CH Port CM mode control register PMCCM R/W
FFFFF06EH System wait control register VSWC R/W
√ √
√ √
√ √
√ √
√ √
√ √
FFFFF100H Interrupt mask register 0 IMR0 R/W
FFFFF100H Interrupt mask register 0L IMR0L R/W
FFFFF101H Interrupt mask register 0H IMR0H R/W
√ √
√ √
FFFFF102H Interrupt mask register 1 IMR1 R/W
FFFFF102H Interrupt mask register 1L IMR1L R/W
FFFFF103H Interrupt mask register 1H IMR1H R/W
√ √
√ √
FFFFF106H Interrupt mask register 3 IMR3 R/W
FFFFF106H Interrupt mask register 3L IMR3L R/W
FFFFF110H Interrupt control register WDT1IC R/W
FFFFF112H Interrupt control register PIC0 R/W
FFFFF114H Interrupt control register PIC1 R/W
FFFFF116H Interrupt control register PIC2 R/W
FFFFF118H Interrupt control register PIC3 R/W
FFFFF11AH Interrupt control register PIC4 R/W
FFFFF11CH Interrupt control register PIC5 R/W
FFFFF11EH Interrupt control register PIC6 R/W
FFFFF124H Interrupt control register TM0IC10 R/W
FFFFF126H Interrupt control register TM0IC11 R/W
FFFFF128H Interrupt control register TM5IC0 R/W
FFFFF12AH Interrupt control register TM5IC1 R/W
FFFFF12CH Interrupt control register CSI0IC0 R/W
FFFFF12EH Interrupt control register CSI0IC1 R/W
FFFFF130H Interrupt control register SREIC0 R/W
FFFFF132H Interrupt control register SRIC0 R/W
FFFFF134H Interrupt control register STIC0 R/W
FFFFF136H Interrupt control register SREIC1 R/W
FFFFF138H Interrupt control register SRIC1 R/W
FFFFF13AH Interrupt control register STIC1 R/W
FFFFF13CH Interrupt control register TMHIC0 R/W
FFFFF13EH Interrupt control register TMHIC1 R/W
FFFFF142H Interrupt control register IICIC0
Note 2
R/W
FFFFF144H Interrupt control register ADIC R/W
FFFFF146H Interrupt control register KRIC R/W
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
Notes 1. The output latch is 00H. When input, the pin status is read.
2. Only in the
μ
PD703302Y, 70F3302Y
After Reset
Note 1
00H
Note 1
00H
FFH
FFH
00H
77H
FFFFH
√
FFH
FFH
FFFFH
√
FFH
FFH
FFFFH
√
FFH
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
(1/7)
58
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CHAPTER 3 CPU FUNCTIONS
Operable Bit UnitAddress Function Register Name Symbol R/W
1 8 16
FFFFF148H Interrupt control register WTIIC R/W
FFFFF14AH Interrupt control register WTIC R/W
FFFFF14CH Interrupt control register BRGIC R/W
FFFFF170H Interrupt control register LVIIC R/W
FFFFF172H Interrupt control register PIC7 R/W
FFFFF174H Interrupt control register TP0OVIC R/W
FFFFF176H Interrupt control register TP0CCIC0 R/W
FFFFF178H Interrupt control register TP0CCIC1 R/W
FFFFF1FAH In-service priority register ISPR R
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
FFFFF1FCH Command register PRCMD W
FFFFF1FEH Power save control register PSC R/W
FFFFF200H A/D converter mode register ADM R/W
FFFFF201H Analog input channel specification register ADS R/W
FFFFF202H Power fail comparison mode register PFM R/W
√ √
√ √
√ √
√ √
FFFFF203H Power fail comparison threshold register PFT R/W
FFFFF204H A/D conversion result register ADCR R
FFFFF205H A/D conversion result register H ADCRH R
FFFFF300H Key return mode register KRM R/W
FFFFF308H Selector operation control register 0 SELCNT0 R/W
FFFFF30AH Selector operation control register 1 SELCNT1 R/W
FFFFF318H Digital noise elimination control register NFC R/W
FFFFF400H Port 0 register P0 R/W
√ √
√ √
√ √
√ √
√ √
FFFFF406H Port 3 register P3 R/W
FFFFF406H Port 3 register L P3L R/W
FFFFF407H Port 3 register H P3H R/W
FFFFF408H Port 4 register P4 R/W
FFFFF40AH Port 5 register P5 R/W
√ √
√ √
√ √
√ √
FFFFF40EH Port 7 register P7 R
FFFFF412H Port 9 register P9 R/W
FFFFF412H Port 9 register L P9L R/W
FFFFF413H Port 9 register H P9H R/W
FFFFF420H Port 0 mode register PM0 R/W
√ √
√ √
√ √
FFFFF426H Port 3 mode register PM3 R/W
FFFFF426H Port 3 mode register L PM3L R/W
FFFFF427H Port 3 mode register H PM3H R/W
FFFFF428H Port 4 mode register PM4 R/W
FFFFF42AH Port 5 mode register PM5 R/W
√ √
√ √
√ √
√ √
FFFFF432H Port 9 mode register PM9 R/W
FFFFF432H Port 9 mode register L PM9L R/W
FFFFF433H Port 9 mode register H PM9H R/W
FFFFF440H Port 0 mode control register PMC0 R/W
√ √
√ √
√ √
Note The output latch is 00H or 0000H. When input, the pin status is read.
47H
47H
47H
47H
47H
47H
47H
47H
00H
Undefined
√
00H
00H
00H
00H
00H
√
√
Undefined
√
00H
00H
00H
00H
00H
√
00H
00H
00H
00H
Undefined
√
√
00H
00H
FFH
√
FFH
FFH
FFH
FFH
√
FFH
FFH
00H
(2/7)
After Reset
Undefined
Note
Note
0000H
Note
Note
Note
Note
Note
0000H
Note
Note
FFFFH
FFFFH
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CHAPTER 3 CPU FUNCTIONS
Operable Bit Unit Address Function Register Name Symbol R/W
1 8 16
FFFFF446H Port 3 mode control register PMC3 R/W
FFFFF446H Port 3 mode control register L PMC3L R/W
FFFFF447H Port 3 mode control register H PMC3H R/W
FFFFF448H Port 4 mode control register PMC4 R/W
FFFFF44AH Port 5 mode control register PMC5 R/W
FFFFF452H Port 9 mode control register PMC9 R/W
FFFFF452H Port 9 mode control register L PMC9L R/W
FFFFF453H Port 9 mode control register H PMC9H R/W
FFFFF466H Port 3 function control register PFC3 R/W
FFFFF46AH Port 5 function control register PFC5 R/W
FFFFF472H Port 9 function control register PFC9 R/W
FFFFF472H Port 9 function control register L PFC9L R/W
FFFFF473H Port 9 function control register H PFC9H R/W
FFFFF580H 8-bit timer H mode register 0 TMHMD0 R/W
FFFFF581H 8-bit timer H carrier control register 0 TMCYC0 R/W
FFFFF582H 8-bit timer H compare register 00 CMP00 R/W
FFFFF583H 8-bit timer H compare register 01 CMP01 R/W
FFFFF590H 8-bit timer H mode register 1 TMHMD1 R/W
FFFFF591H 8-bit timer H carrier control register 1 TMCYC1 R/W
FFFFF592H 8-bit timer H compare register 10 CMP10 R/W
FFFFF593H 8-bit timer H compare register 11 CMP11 R/W
FFFFF5A0H TMP0 control register 0 TP0CTL0 R/W
FFFFF5A1H TMP0 control register 1 TP0CTL1 R/W
FFFFF5A2H TMP0 I/O control register 0 TP0IOC0 R/W
FFFFF5A3H TMP0 I/O control register 1 TP0IOC1 R/W
FFFFF5A4H TMP0 I/O control register 2 TP0IOC2 R/W
FFFFF5A5H TMP0 option register 0 TP0OPT0 R/W
FFFFF5A6H TMP0 capture/compare register 0 TP0CCR0 R/W
FFFFF5A8H TMP0 capture/compare register 1 TP0CCR1 R/W
FFFFF5AAH TMP0 counter read buffer register TP0CNT R
FFFFF5C0H 16-bit timer counter 5 TM5 R
FFFFF5C0H 8-bit timer counter 50 TM50 R
FFFFF5C1H 8-bit timer counter 51 TM51 R
FFFFF5C2H 16-bit timer compare register 5 CR5 R/W
FFFFF5C2H 8-bit timer compare register 50 CR50 R/W
FFFFF5C3H 8-bit timer compare register 51 CR51 R/W
FFFFF5C4H Timer clock selection register 5 TCL5 R/W
FFFFF5C4H Timer clock selection register 50 TCL50 R/W
FFFFF5C5H Timer clock selection register 51 TCL51 R/W
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√
√
√
√
√
√
√
√
√
√
After Reset
0000H
√
00H
00H
00H
00H
0000H
√
00H
00H
00H
00H
0000H
√
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
0000H
√
0000H
√
0000H
√
0000H
√
00H
00H
0000H
√
00H
00H
0000H
√
00H
00H
(3/7)
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CHAPTER 3 CPU FUNCTIONS
Operable Bit UnitAddress Function Register Name Symbol R/W
1 8 16
FFFFF5C6H 16-bit timer mode control register 5 TMC5 R/W
FFFFF5C6H 8-bit timer mode control register 50 TMC50 R/W
FFFFF5C7H 8-bit timer mode control register 51 TMC51 R/W
FFFFF610H 16-bit timer counter 01 TM01 R
FFFFF612H 16-bit timer capture/compare register 010 CR010 R/W
FFFFF614H 16-bit timer capture/compare register 011 CR011 R/W
FFFFF616H 16-bit timer mode control register 01 TMC01 R/W
FFFFF617H Prescaler mode register 01 PRM01 R/W
FFFFF618H Capture/compare control register 01 CRC01 R/W
FFFFF619H 16-bit timer output control register 01 TOC01 R/W
FFFFF680H Watch timer operation mode register WTM R/W
FFFFF6C0H Oscillation stabilization time selection register OSTS R/W
FFFFF6C1H Watchdog timer clock selection register WDCS R/W
FFFFF6C2H Watchdog timer mode register 1 WDTM1 R/W
FFFFF6D0H Watchdog timer mode register 2 WDTM2 R/W
FFFFF6D1H Watchdog timer enable register WDTE R/W
FFFFF6E0H Real-time output buffer register L0 RTBL0 R/W
FFFFF6E2H Real-time output buffer register H0 RTBH0 R/W
FFFFF6E4H Real-time output port mode register 0 RTPM0 R/W
FFFFF6E5H Real-time output port control register 0 RTPC0 R/W
FFFFF706H Port 3 function control expansion register PFCE3 R/W
FFFFF802H System status register SYS R/W
FFFFF806H PLL control register PLLCTL R/W
FFFFF80CH Internal oscillation mode register RCM R/W
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
Note The value can be set to 00H or 01H by the option byte or a mask option setting.
For details, refer to CHAPTER 25 MASK OPTION/OPTION BYTE.
√
√
√
√
After Reset
0000H
√
00H
00H
0000H
√
0000H
√
0000H
√
00H
00H
00H
00H
00H
Note
00H
00H
67H
9AH
00H
00H
00H
00H
00H
00H
01H
00H
(4/7)
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CHAPTER 3 CPU FUNCTIONS
Operable Bit Unit Address Function Register Name Symbol R/W
1 8 16 32
FFFFF820H Power save mode register PSMR R/W
FFFFF828H Processor clock control register PCC R/W
FFFFF82EH CPU operation clock status register CCLS R
FFFFF840H Correction address register 0 CORAD0 R/W
FFFFF840H Correction address register 0L CORAD0L R/W
FFFFF842H Correction address register 0H CORAD0H R/W
FFFFF844H Correction address register 1 CORAD1 R/W
FFFFF844H Correction address register 1L CORAD1L R/W
FFFFF846H Correction address register 1H CORAD1H R/W
FFFFF848H Correction address register 2 CORAD2 R/W
FFFFF848H Correction address register 2L CORAD2L R/W
FFFFF84AH Correction address register 2H CORAD2H R/W
FFFFF84CH Correction address register 3 CORAD3 R/W
FFFFF84CH Correction address register 3L CORAD3L R/W
FFFFF84EH Correction address register 3H CORAD3H R/W
FFFFF860H Reset noise elimination control register RNZC R/W
FFFFF870H Clock monitor mode register CLM R/W
FFFFF880H Correction control register CORCN R/W
FFFFF888H Reset source flag register RESF R/W
FFFFF890H Low-voltage detection register LVIM R/W
FFFFF891H Low-voltage detection level selection register LVIS R/W
FFFFF8B0H Interval timer BRG mode register PRSM R/W
FFFFF8B1H Interval timer BRG compare register PRSCM R/W
FFFFFA00H Asynchronous serial interface mode register 0 ASIM0 R/W
FFFFFA02H Receive buffer register 0 RXB0 R
FFFFFA03H Asynchronous serial interface status register 0 ASIS0 R
FFFFFA04H Transmit buffer register 0 TXB0 R/W
FFFFFA05H Asynchronous serial interface transmit status register 0 ASIF0 R
FFFFFA06H Clock select register 0 CKSR0 R/W
FFFFFA07H Baud rate generator control register 0 BRGC0 R/W
FFFFFA08H LIN operation control register 0 ASICL0 R/W
FFFFFA10H Asynchronous serial interface mode register 1 ASIM1 R/W
FFFFFA12H Receive buffer register 1 RXB1 R
FFFFFA13H Asynchronous serial interface status register 1 ASIS1 R
FFFFFA14H Transmit buffer register 1 TXB1 R/W
FFFFFA15H Asynchronous serial interface transmit status register 1 ASIF1 R
FFFFFA16H Clock select register 1 CKSR1 R/W
FFFFFA17H Baud rate generator control register 1 BRGC1 R/W
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√
√
√
√
√
√
√
√
√
√
√
√
√
√
00H
03H
00H
√
√
√
√
√
√
√
√
00H
00H
00H
Note
00H
00H
00H
00H
01H
FFH
00H
FFH
00H
00H
FFH
16H
01H
FFH
After Reset
00000000H
√
0000H
0000H
00000000H
√
0000H
0000H
00000000H
√
0000H
0000H
00000000H
√
0000H
0000H
00H
FFH
00H
00H
FFH
Note The value varies depending on the reset source (refer to 20.3 (1) Reset source flag register (RESF)).
(5/7)
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CHAPTER 3 CPU FUNCTIONS
Operable Bit UnitAddress Function Register Name Symbol R/W
1 8 16
FFFFFB00H TIP00 noise elimination control register P0NFC R/W
FFFFFB04H TIP01 noise elimination control register P1NFC R/W
FFFFFC00H External interrupt falling edge specification register 0 INTF0 R/W
FFFFFC06H External interrupt falling edge specification register 3 INTF3 R/W
FFFFFC13H External interrupt falling edge specification register 9H INTF9H R/W
FFFFFC20H External interrupt rising edge specification register 0 INTR0 R/W
FFFFFC26H External interrupt rising edge specification register 3 INTR3 R/W
FFFFFC33H External interrupt rising edge specification register 9H INTR9H R/W
FFFFFC40H Pull-up resistor option register 0 PU0 R/W
FFFFFC46H Pull-up resistor option register 3 PU3 R/W
FFFFFC48H Pull-up resistor option register 4 PU4 R/W
FFFFFC4AH Pull-up resistor option register 5 PU5 R/W
FFFFFC52H Pull-up resistor option register 9 PU9 R/W
FFFFFC52H Pull-up resistor option register 9L PU9L R/W
FFFFFC53H Pull-up resistor option register 9H PU9H R/W
FFFFFC67H Port 3 function register H PF3H R/W
FFFFFC68H Port 4 function register PF4 R/W
FFFFFC73H Port 9 function register H PF9H R/W
FFFFFD00H Clocked serial interface mode register 00 CSIM00 R/W
FFFFFD01H Clocked serial interface clock selection register 0 CSIC0 R/W
FFFFFD02H Clocked serial interface receive buffer register 0 SIRB0 R
FFFFFD02H Clocked serial interface receive buffer register 0L SIRB0L R
FFFFFD04H Clocked serial interface transmit buffer register 0 SOTB0 R/W
FFFFFD04H Clocked serial interface transmit buffer register 0L SOTB0L R/W
FFFFFD06H Clocked serial interface read-only receive buffer register 0 SIRBE0 R
FFFFFD06H Clocked serial interface read-only receive buffer register 0L SIRBE0L R
FFFFFD08H Clocked serial interface initial transmit buffer register 0 SOTBF0 R/W
FFFFFD08H Clocked serial interface initial transmit buffer register 0L SOTBF0L R/W
FFFFFD0AH Serial I/O shift register 0 SIO00 R/W
FFFFFD0AH Serial I/O shift register 0L SIO00L R/W
FFFFFD10H Clocked serial interface mode register 01 CSIM01 R/W
FFFFFD11H Clocked serial interface clock selection register 1 CSIC1 R/W
FFFFFD12H Clocked serial interface receive buffer register 1 SIRB1 R
FFFFFD12H Clocked serial interface receive buffer register 1L SIRB1L R
FFFFFD14H Clocked serial interface transmit buffer register 1 SOTB1 R/W
FFFFFD14H Clocked serial interface transmit buffer register 1L SOTB1L R/W
FFFFFD16H Clocked serial interface read-only receive buffer register 1 SIRBE1 R
FFFFFD16H Clocked serial interface read-only receive buffer register 1L SIRBE1L R
FFFFFD18H Clocked serial interface initial transmit buffer register 1 SOTBF1 R/W
FFFFFD18H Clocked serial interface initial transmit buffer register 1L SOTBF1L R/W
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
(6/7)
After Reset
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
0000H
00H
00H
00H
00H
00H
00H
00H
0000H
00H
0000H
00H
0000H
00H
0000H
00H
00H
0000H
00H
00H
0000H
00H
0000H
00H
0000H
00H
0000H
00H
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CHAPTER 3 CPU FUNCTIONS
Operable Bit Unit Address Function Register Name Symbol R/W
1 8 16
FFFFFD1AH Serial I/O shift register 1 SIO01 R/W
FFFFFD1AH Serial I/O shift register 1L SIO01L R/W
FFFFFD80H IIC shift register 0 IIC0
FFFFFD82H IIC control register 0 IICC0
FFFFFD83H Slave address register 0 SVA0
FFFFFD84H IIC clock selection register 0 IICCL0
FFFFFD85H IIC function expansion register 0 IICX0
FFFFFD86H IIC status register 0 IICS0
FFFFFD8AH IIC flag register 0 IICF0
FFFFFF44H Pull-up resistor option register DL PUDL R/W
FFFFFF4CH Pull-up resistor option register CM PUCM R/W
Note
R/W
Note
R/W
Note
R/W √ 00H
Note
R/W
Note
R/W
Note
R
Note
R/W
√ √
√ √
√ √
√ √
√ √
√ √
√ √
Note Only in the μPD703302Y, 70F3302Y
√
0000H
√
√
00H
00H
00H
00H
00H
00H
00H
(7/7)
After Reset
00H
00H
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CHAPTER 3 CPU FUNCTIONS
3.4.7 Special registers
Special registers are registers that prevent invalid data from being written when an inadvertent program loop
occurs.
The V850ES/KE1+ has the following six special registers.
• Power save control register (PSC)
• Processor clock control register (PCC)
• Watchdog timer mode register (WDTM1)
• Clock monitor mode register (CLM)
• Reset source flag register (RESF)
• Low-voltage detection register (LVIM)
Moreover, there is also the PRCMD register, which is a protection register for write operations to the special
registers that prevents the application system from unexpectedly stopping due to an inadvertent program loop. Write
access to the special registers is performed with a special sequence and illegal store operations are notified to the
SYS register.
(1) Setting data to special registers
Setting data to a special register is done in the following sequence.
<1> Prepare the data to be set to the special register in a general-purpose register.
<2> Write the data prepared in step <1> to the PRCMD register.
<3> Write the setting data to the special register (using following instructions).
• Store instruction (ST/SST instruction)
• Bit manipulation instruction (SET1/CLR1/NOT1 instruction)
<4> to <8> Insert NOP instructions (5 instructions)
Note
.
Note When switching to the IDLE mode or the STOP mode (PSC.STP bit = 1), 5 NOP instructions must be
inserted immediately after switching is performed.
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[Description Example] When using PSC register (standby mode setting)
ST.B r11, PSMR[r0] ; PSMR register setting (IDLE, STOP mode setting)
<1> MOV 0x02, r10
<2> ST.B r10, PRCMD[r0] ; PRCMD register write
<3> ST.B r10, PSC[r0] ; PSC register setting
<4> NOP
<5> NOP
<6> NOP
<7> NOP
<8> NOP
Note
; Dummy instruction
Note
; Dummy instruction
Note
; Dummy instruction
Note
; Dummy instruction
Note
; Dummy instruction
(next instruction)
No special sequence is required to read special registers.
Note When switching to the IDLE mode or the STOP mode (PSC.STP bit = 1), 5 NOP instructions must be
inserted immediately after switching is performed.
Cautions 1. Interrupts are not acknowledged for the store instruction for the PRCMD register. This is
because continuous execution of store instructions by the program in steps <2> and <3>
above is assumed. If another instruction is placed between step <2> and <3>, the above
sequence may not be realized when an interrupt is acknowledged for that instruction,
which may cause malfunction.
2. The data written to the PRCMD register is dummy data, but use the same register as the
general-purpose register used for setting data to the special register (step <3>) when
writing to the PRCMD register (step <2>). The same applies to when using a general-
purpose register for addressing.
(2) Command register (PRCMD)
The PRCMD register is an 8-bit register used to prevent data from being written to registers that may have a
large influence on the system, possibly causing the application system to unexpectedly stop, when an
inadvertent program loop occurs. Only the first write operation to the special register following the execution of
a previously executed write operation to the PRCMD register, is valid.
As a result, register values can be overwritten only using a preset sequence, preventing invalid write
operations.
This register can only be written in 8-bit units (if it is read, an undefined value is returned).
After reset: Undefined W Address: FFFFF1FCH
CHAPTER 3 CPU FUNCTIONS
66
7
REG7PRCMD
6
REG65REG54REG43REG32REG21REG10REG0
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(3) System status register (SYS)
This register is allocated with status flags showing the operating state of the entire system.
This register can be read or written in 8-bit or 1-bit units.
After reset: 00H R/W Address: FFFFF802H
SYS 0 0 0 0 0 0 PRERR
0
CHAPTER 3 CPU FUNCTIONS
< >
PRERR
0
1
Protection error has not occurred
Protection error has occurred
Detection of protection error
The operation conditions of the PRERR flag are described below.
(a) Set conditions (PRERR = 1)
(i) When a write operation to the special register takes place without write operation being performed to
the PRCMD register (when step <3> is performed without performing step <2> as described in 3.4.7
(1) Setting data to special registers).
(ii) When a write operation (including bit manipulation instruction) to an on-chip peripheral I/O register
other than a special register is performed following write to the PRCMD register (when <3> in 3.4.7
(1) Setting data to special registers is not a special register).
Remark Regarding the special registers other than the WDTM register (PCC and PSC registers), even if
on-chip peripheral I/O register read (except bit manipulation instruction) (internal RAM access,
etc.) is performed in between write to the PRCMD register and write to a special register, the
PRERR flag is not set and setting data can be written to the special register.
(b) Clear conditions (PRERR = 0)
(i) When 0 is written to the PRERR flag
(ii) When system reset is performed
Cautions 1. If 0 is written to the PRERR bit of the SYS register that is not a special register
immediately following write to the PRCMD register, the PRERR bit becomes 0 (write
priority).
2. If data is written to the PRCMD register that is not a special register immediately
following write to the PRCMD register, the PRERR bit becomes 1.
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CHAPTER 3 CPU FUNCTIONS
3.4.8 Cautions
(1) Wait when accessing register
Be sure to set the following register before using the V850ES/KE1+.
• System wait control register (VSWC)
After setting the VSWC register, set the other registers as required.
When using an external bus, set the VSWC register and then set the various pins to the control mode by
setting the port-related registers.
(a) System wait control register (VSWC)
The VSWC register controls the bus access wait time for the on-chip peripheral I/O registers.
Access to the on-chip peripheral I/O register lasts 3 clocks (during no wait), but in the V850ES/KE1+,
waits are required according to the internal system clock frequency. Set the values shown below to the
VSWC register according to the internal system clock frequency that is used.
This register can be read or written in 8-bit units (Address: FFFFF06EH, After reset: 77H).
Operation Conditions Internal System Clock Frequency (fCLK) VSWC Register Setting Number of Waits
32 kHz ≤ fCLK < 16.6 MHz 00H 0 (no waits) 4.5 V ≤ VDD ≤ 5.5 V
16.6 MHz ≤ f
4.0 V ≤ VDD < 4.5 V 32 kHz ≤ fCPU ≤ 16 MHz 00H 0 (no waits)
<R>
<R>
32 kHz ≤ fCLK < 8.3 MHz 00H 0 (no waits) 2.7 V ≤ VDD < 4.0 V
8.3 MHz ≤ f
CLK ≤ 20 MHz 01H 1
CLK ≤ 10 MHz 01H 1
(b) Access to special on-chip peripheral I/O register
This product has two types of internal system buses.
One type is for the CPU bus and the other is for the peripheral bus to interface with low-speed peripheral
hardware.
Since the CPU bus clock and peripheral bus clock are asynchronous, if a conflict occurs during access
between the CPU and peripheral hardware, illegal data may be passed unexpectedly. Therefore, when
accessing peripheral hardware that may cause a conflict, the number of access cycles is changed so that
the data is received/passed correctly in the CPU. As a result, the CPU does not shift to the next
instruction processing and enters the wait status. When this wait status occurs, the number of execution
clocks of the instruction is increased by the number of wait clocks.
Note this with caution when performing real-time processing.
When accessing a special on-chip peripheral I/O register, additional waits may be required further to the
waits set by the VSWC register.
The access conditions at that time and the method to calculate the number of waits to be inserted
(number of CPU clocks) are shown below.
Number of waits to be added = (2 + m) × k [clocks]
Number of accesses to specific on-chip peripheral I/O register = 3 + m + (2 + m) × k (clocks)
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<R>
<R>
CHAPTER 3 CPU FUNCTIONS
Peripheral Function Register Name Access k
WDTM1 Write 1 to 5 Watchdog timer 1 (WDT1)
Note 1
<Calculation of number of waits
k = {(1/f
f
X) × 2/((2 + m)/fCPU)} + 1
X: Main clock oscillation frequency
>
Watchdog timer 2 (WDT2) WDTM2 Write 3 (fixed)
16-bit timer/event counter P0 (TMP0)
TP0CCR0, TP0CCR1,
Read 1
TP0CNT
<Calculation of number of waits
k = {(1/f
XX)/((2 + m)/fCPU)} + 1
Note 1
>
TP0CCR0, TP0CCR1 Write 0 to 2
Note 1
<Calculation of number of waits
k = {(1/f
XX) × 5/((2 + m)/fCPU)}
>
A wait occurs when performing continuous write to same register
16-bit timer/event counter 01 (TM01) TMC01 Read-modify-write 1 (fixed)
A wait occurs during write
Note 2
I2C0
IICS0 Read 1 (fixed)
Asynchronous serial interfaces 0, 1
ASIS0, ASIS1 Read 1 (fixed)
(UART0, UART1)
Real-time output function 0 (RTO0) RTBL0, RTBH0 Write (when
1
RTPC0.RTPOE0 bit = 0)
A/D converter
ADM, ADS, PFM, PFT Write 1 to 2
ADCR, ADCRH Read 1 to 2
<Calculation of number of waits
k = {(1/f
XX) × 2/[(2 + m)/fCPU]} + 1
Note 1
>
Notes 1. In the calculation of number of waits, the fractional part of its result must be multiplied by (1/f
and rounded down if (1/fCPU)/(2 + m) or lower, and rounded up if (1/fCPU)/(2 + m) is exceeded.
2. I
2
C0 is available only in the μPD703302Y and 70F3302Y.
Cautions 1. If fetched from the internal ROM or internal RAM, the number of waits is as shown above.
If fetched from the external memory, the number of waits may be decreased below these.
The effect of the external memory access cycles varies depending on the wait settings
and the like. However, the number of waits shown above is the maximum value, so no
higher value is generated.
2. Accessing the registers in which a wait occurs using an access method that causes a
wait is prohibited in the following statuses. If a wait cycle is generated, it can only be
cleared by a reset.
• When the CPU operates with the subclock and the main clock oscillation is stopped
• When the CPU operates with the internal oscillation clock
Remark In the calculation for the number of waits:
fCPU: CPU clock frequency
f
XX: Main clock frequency
m: Set value of bits 2 to 0 of the VSWC register
When the VSWC register = 00H: m = 0
When the VSWC register = 01H: m = 1
CPU)
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<R>
CHAPTER 3 CPU FUNCTIONS
(2) Restriction on conflict between sld instruction and interrupt request
(a) Description
If a conflict occurs between the decode operation of an instruction in <2> immediately before the sld
instruction following an instruction in <1> and an interrupt request before the instruction in <1> is complete,
the execution result of the instruction in <1> may not be stored in a register.
Instruction <1>
• ld instruction: ld.b, ld.h, ld.w, ld.bu, ld.hu
• sld instruction: sld.b, sld.h, sld.w, sld.bu, sld.hu
• Multiplication instruction: mul, mulh, mulhi, mulu
Instruction <2>
mov reg1, reg2
satadd reg1, reg2
and reg1, reg2
add reg1, reg2
mulh reg1, reg2
not reg1, reg2
satadd imm5, reg2
tst reg1, reg2
add imm5, reg2
shr imm5, reg2
satsubr reg1, reg2
or reg1, reg2
subr reg1, reg2
cmp reg1, reg2
sar imm5, reg2
<Example>
<i> ld.w [r11], r10 If the decode operation of the mov instruction <ii> immediately before the sld
•
•
•
instruction <iii> and an interrupt request conflict before execution of the ld
instruction <i> is complete, the execution result of instruction <i> may not be
stored in a register.
<ii> mov r10, r28
<iii> sld.w 0x28, r10
(b) Countermeasure
<1> When compiler (CA850) is used
Use CA850 Ver. 2.61 or later because generation of the corresponding instruction sequence can be
automatically suppressed.
<2> Countermeasure by assembler
When executing the sld instruction immediately after instruction <ii>, avoid the above operation
using either of the following methods.
• Insert a nop instruction immediately before the sld instruction.
• Do not use the same register as the sld instruction destination register in the above instruction
<ii> executed immediately before the sld instruction.
satsub reg1, reg2
xor reg1, reg2
sub reg1, reg2
cmp imm5, reg2
shl imm5, reg2
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CHAPTER 4 PORT FUNCTIONS
4.1 Features
{ Input-only ports: 8 pins
{ I/O ports: 43 pins
• Fixed to N-ch open-drain output: 2
• Switchable to N-ch open-drain output: 4
{ Input/output can be specified in 1-bit units
4.2 Basic Port Configuration
The V850ES/KE1+ incorporates a total of 51 I/O port pins consisting of ports 0, 3 to 5, 7, 9, CM, and DL (including
8 input-only port pins). The port configuration is shown below.
Port 0
Port 3
Port 4
Port 5
Port 7
P00
P06
P30
P35
P38
P39
P40
P42
P50
P55
P70
P77
Table 4-1. Pin I/O Buffer Power Supplies of V850ES/KE1+
Power Supply Corresponding Pins
AVREF0 Port 7
EVDD RESET, ports 0, 3 to 5, 9, CM, DL
P90
P91
P96
P99
P913
P915
PCM0
PCM1
PDL0
PDL7
Port 9
Port CM
Port DL
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4.3 Port Configuration
Item Configuration
Control registers
Ports
Pull-up resistors Software control: 41
Port n register (Pn: n = 0, 3 to 5, 7, 9, CM, DL)
Port n mode register (PMn: n = 0, 3 to 5, 9, CM, DL)
Port n mode control register (PMCn: n = 0, 3 to 5, 9, CM)
Port n function control register (PFCn: n = 3, 5, 9)
Port n function register (PFn: n = 3, 4, 9)
Port 3 function control expansion register (PFCE3)
Pull-up resistor option register (PUn: n = 0, 3 to 5, 9, CM, DL)
Input only: 8
I/O: 43
CHAPTER 4 PORT FUNCTIONS
Table 4-2. Port Configuration
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(1) Port n register (Pn)
Data I/O with external devices is performed by writing to and reading from the Pn register. The Pn register is
configured of a port latch that retains the output data and a circuit that reads the pin status.
Each bit of the Pn register corresponds to one pin of port n and can be read or written in 1-bit units.
After reset: 00H
Pn
Note
(output latch) R/W
Pn7
Pn6 Pn5 Pn4 Pn3 Pn2 Pn1 Pn0
CHAPTER 4 PORT FUNCTIONS
01237567
<R>
Pnm
0
1
0 is output
1 is output
Control of output data (in output mode)
Note Input-only port pins are undefined.
Writing to and reading from the Pn register are executed as follows depending on the setting of each register.
Table 4-3. Reading to/Writing from Pn Register
Setting of PMCn Register Setting of PMn Register Writing to Pn Register Reading from Pn Register
Port mode
(PMCnm bit = 0)
Output mode
(PMnm bit = 0)
Write to the output latch
The contents of the output latch are output
Note
.
The value of the output
latch is read.
from the pin.
Note
Note
.
.
The pin status is read.
• When alternate function is
output
The output status of the
alternate function is read.
Alternate-function mode
(PMCnm bit = 1)
Input mode
(PMnm bit = 1)
Output mode
(PMnm bit = 0)
Write to the output latch
The status of the pin is not affected.
Write to the output latch
The status of the pin is not affected.
The pin operates as an alternate-function
pin.
• When alternate function is
input
The output latch value is
read.
Input mode
(PMnm bit = 1)
Write to the output latch
.
The status of the pin is not affected.
The pin status is read.
Note
The pin operates as an alternate-function
pin.
Note The value written to the output latch is retained until a new value is written to the output latch.
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(2) Port n mode register (PMn)
PMn specifies the input mode/output mode of the port.
Each bit of the PMn register corresponds to one pin of port n and can be specified in 1-bit units.
After reset: FFH R/W
CHAPTER 4 PORT FUNCTIONS
PMn
PMn7
PMnm
0
1
PMn6 PMn5 PMn4 PMn3 PMn2 PMn1 PMn0
Output mode
Input mode
(3) Port n mode control register (PMCn)
PMCn specifies the port mode/alternate function.
Each bit of the PMCn register corresponds to one pin of port n and can be specified in 1-bit units.
After reset: 00H R/W
PMCn
PMCn7 PMCn6 PMCn5 PMCn4 PMCn3 PMCn2 PMCn1 PMCn0
PMCnm
0
Port mode
1
Alternate function mode
Control of I/O mode
Specification of operation mode
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(4) Port n function control register (PFCn)
PFCn is a register that specifies the alternate function to be used when one pin has two or more alternate
functions.
Each bit of the PFCn register corresponds to one pin of port n and can be specified in 1-bit units.
After reset: 00H R/W
CHAPTER 4 PORT FUNCTIONS
PFCn
PFCn7 PFCn6 PFCn5 PFCn4 PFCn3 PFCn2 PFCn1 PFCn0
PFCnm
0
1
Alternate function 1
Alternate function 2
Specification of alternate function
(5) Port n function control expansion register (PFCEn)
PFCEn is a register that specifies the alternate function to be used when one pin has three or more alternate
functions.
Each bit of the PFCEn register corresponds to one pin of port n and can be specified in 1-bit units.
After reset: 00H R/W
PFCEn
PFCn
PFCEn7 PFCEn6 PFCEn5 PFCEn4 PFCEn3 PFCEn2 PFCEn1 PFCEn0
PFCn7 PFCn6 PFCn5 PFCn4 PFCn3 PFCn2 PFCn1 PFCn0
PFCEnm
PFCnm
0
0
1
1
0
Alternate function 1
1
Alternate function 2
0
Alternate function 3
1
Alternate function 4
Specification of alternate function
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(6) Port n function register (PFn)
PFn is a register that specifies normal output/N-ch open-drain output.
Each bit of the PFn register corresponds to one pin of port n and can be specified in 1-bit units.
After reset: 00H R/W
CHAPTER 4 PORT FUNCTIONS
PFn
PFn7 PFn6 PFn5 PFn4 PFn3 PFn2 PFn1 PFn0
Note
PFnm
0
Normal output (CMOS output)
1
N-ch open-drain output
Control of normal output/N-ch open-drain output
Note The PFnm bit is valid only when the PMn.PMnm bit is 0 (output mode) regardless of the setting of the
PMCn register. When the PMnm bit is 1 (input mode), the set value in the PFn register is invalid.
Example <1> When the value of the PFn register is valid
PFnm bit = 1 … N-ch open-drain output is specified.
PMnm bit = 0 … Output mode is specified.
PMCnm bit = 0 or 1
<2> When the value of the PFn register is invalid
PFnm bit = 0 … N-ch open-drain output is specified.
PMnm bit = 1 … Input mode is specified.
PMCnm bit = 0 or 1
(7) Pull-up resistor option register (PUn)
PUn is a register that specifies the connection of an on-chip pull-up resistor.
Each bit of the PUn register corresponds to one pin of port n and can be specified in 1-bit units.
After reset: 00H R/W
76
PUn
PUn7 PUn6 PUn5 PUn4 PUn3 PUn2 PUn1 PUn0
PUnm
0
1
Not connected
Connected
Control of on-chip pull-up resistor connection
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(8) Port settings
Set the ports as follows.
Port mode
CHAPTER 4 PORT FUNCTIONS
Figure 4-1. Register Settings and Pin Functions
Output mode
Input mode
Alternate function
(when two alternate
functions are available)
Alternate function 1
Alternate function 2
Alternate function
(when three or more alternate
functions are available)
Alternate function 1
Alternate function 2
Alternate function 3
Alternate function 4
(a)
(b)
(c)
(d)
“0”
“1”
“0”
“1”
PMn register
PFCn register
PFCn register
PFCEn register
“0”
“1”
(a)
(b)
(c)
(d)
PMCn register
PFCEnm
0
0
1
1
PFCnm
0
1
0
1
Remark Switch to the alternate function using the following procedure.
<1> Set the PFCn and PFCEn registers.
<2> Set the PMCn register.
<3> Set the INTRn or INTFn register (to specify an external interrupt pin).
If the PMCn register is set first, an unintended function may be set while the PFCn and PFCEn
registers are being set.
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CHAPTER 4 PORT FUNCTIONS
4.3.1 Port 0
Port 0 is a 7-bit I/O port for which I/O settings can be controlled in 1-bit units.
Port 0 includes the following alternate functions.
Table 4-4. Alternate-Function Pins of Port 0
Yes
Note 1
Analog noise elimination
Analog/digital noise
elimination
Remark Block Type
–
D0-U
D1-SUIL
D1-SUIL
Pin No. Pin Name Alternate Function I/O PULL
12 P00
13 P01 TOH1 Output
14 P02 NMI Input D1-SUIL
15 P03 INTP0 Input D1-SUIL
16 P04 INTP1 Input D1-SUIL
17 P05 INTP2 Input
18 P06 INTP3 Input
Note 2
TOH0 Output D0-U
Notes 1. Software pull-up function
2. Only the P00 pin outputs a low level after reset (other port pins are in input mode).
Therefore, the low-level output from the P00 pin after reset can be used as a dummy reset signal from
the CPU.
Caution P02 to P06 have hysteresis characteristics when the alternate function is input, but not in the
port mode.
(1) Port 0 register (P0)
After reset: 00H (output latch) R/W Address: FFFFF400H
P0 P06 P05 P04 P03 P02 P01 P00
0
P0n
0
1
(2) Port 0 mode register (PM0)
After reset: FFH R/W Address: FFFFF420H
PM0 PM06 PM05 PM04 PM03 PM02 PM01 PM00
1
PM0n
0
1
78
0 is output
1 is output
Output mode
Input mode
Control of output data (in output mode) (n = 0 to 6)
Control of I/O mode (n = 0 to 6)
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(3) Port 0 mode control register (PMC0)
After reset: 00H R/W Address: FFFFF440H
CHAPTER 4 PORT FUNCTIONS
0PMC0 PMC06
PMC06
0
1
PMC05
0
1
PMC04
0
1
PMC03
0
1
PMC02
0
1
PMC01
0
1
I/O port
INTP3 input
I/O port
INTP2 input
I/O port
INTP1 input
I/O port
INTP0 input
I/O port
NMI input
I/O port
TOH1 output
PMC05
PMC04 PMC03 PMC02 PMC01 PMC00
Specification of P06 pin operation mode
Specification of P05 pin operation mode
Specification of P04 pin operation mode
Specification of P03 pin operation mode
Specification of P02 pin operation mode
Specification of P01 pin operation mode
PMC00
0
I/O port
TOH0 output
1
(4) Pull-up resistor option register 0 (PU0)
After reset: 00H R/W Address: FFFFFC40H
PU0 PU06 PU05 PU04 PU03 PU02 PU01 PU00
0
PU0n
0
1
Not connected
Connected
Specification of P00 pin operation mode
Control of on-chip pull-up resistor connection (n = 0 to 6)
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CHAPTER 4 PORT FUNCTIONS
4.3.2 Port 3
Port 3 is an 8-bit I/O port for which I/O settings can be controlled in 1-bit units.
Port 3 includes the following alternate functions.
Table 4-5. Alternate-Function Pins of Port 3
Pin No. Pin Name Alternate Function I/O PULL
22 P30 TXD0 Output D-U
23 P31 RXD0/INTP7 Input D1-SUIHL
24 P32 ASCK0/ADTRG/TO01 I/O E10-SUL
25 P33 TIP00/TOP00 I/O Gxx10-SUL
26 P34 TIP01/TOP01 I/O Gxx10-SUL
27 P35 TI010/TO01 I/O
55 P38 SDA0
56 P39 SCL0
Note 2
I/O D2-SNMUFH
Note 2
I/O
Note 1
Remark Block Type
Yes –
E10-SUL
Note 3
No
N-ch open-drain output
D2-SNMUFH
Notes 1. Software pull-up function
2. Only in the
μ
PD703302Y, 70F3302Y
3. An on-chip pull-up resistor can be provided by a mask option (only in the μPD703302, 703302Y).
Caution P31 to P35, P38, and P39 have hysteresis characteristics when the alternate function is input, but
not in the port mode.
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(1) Port 3 register (P3)
After reset: 00H (output latch) R/W Address: P3 FFFFF406H,
P3 (P3H
Note
CHAPTER 4 PORT FUNCTIONS
P3L FFFFF406H, P3H FFFFF407H
89101112131415
)
0 0 0 0 0 0 P39 P38
(P3L)
Note When reading from or writing to bits 8 to 15 of the P3 register in 8-bit or 1-bit units,
specify these bits as bits 0 to 7 of the P3H register.
Remark The P3 register can be read or written in 16-bit units.
However, when the higher 8 bits and the lower 8 bits of the P3 register are used as
the P3H register and as the P3L register, respectively, this register can be read or
written in 8-bit or 1-bit units.
(2) Port 3 mode register (PM3)
After reset: FFFFH R/W Address: PM3 FFFFF426H,
Note
) 1 1 1 1 1 PM39 PM38
0 0 P35 P34 P33 P32 P31 P30
P3n
0
1
0 is output
1 is output
1PM3 (PM3H
Control of output data (in output mode) (n = 0 to 5, 8, 9)
PM3L FFFFF426H, PM3H FFFFF427H
89101112131415
(PM3L)
1
PM3n
0
1
1 PM35 PM34 PM33 PM32 PM31 PM30
Control of I/O mode (n = 0 to 5, 8, 9)
Output mode
Input mode
Note When reading from or writing to bits 8 to 15 of the PM3 register in 8-bit or 1-bit units,
specify these bits as bits 0 to 7 of the PM3H register.
Remark The PM3 register can be read or written in 16-bit units.
When the higher 8 bits and the lower 8 bits of the PM3 register are used as the PM3H
register and as the PM3L register, respectively, this register can be read or written in
8-bit or 1-bit units.
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CHAPTER 4 PORT FUNCTIONS
(3) Port 3 mode control register (PMC3)
After reset: 0000H R/W Address: PMC3 FFFFF446H,
PMC3L FFFFF446H, PMC3H FFFFF447H
89101112131415
PMC3 (PMC3H
(PMC3L)
Note 1
)
00 00 00
0 0 PMC35 PMC34 PMC33 PMC32 PMC31 PMC30
PMC39
0
1
PMC38
0
1
PMC35
0
1
PMC34
0
1
I/O port
SCL0 I/O
I/O port
SDA0 I/O
I/O port
TI010 input/TO01 output
I/O port
TIP01 input/TOP01 output
Specification of P39 pin operation mode
Specification of P38 pin operation mode
Specification of P35 pin operation mode
Specification of P34 pin operation mode
PMC39
Note 2
PMC38
Note 2
PMC33
0
1
PMC32
0
1
PMC31
0
1
PMC30
0
1
I/O port
TIP00 input/TOP00 output
I/O port
ASCK0 input/ADTRG input/TO01 output
I/O port
RXD0 input/INTP7 input
I/O port
TXD0 output
Specification of P33 pin operation mode
Specification of P32 pin operation mode
Specification of P31 pin operation mode
Note 3
Specification of P30 pin operation mode
Notes 1. When reading from or writing to bits 8 to 15 of the PMC3 register in 8-bit or 1-bit units,
specify these bits as bits 0 to 7 of the PMC3H register.
2. Valid only in the μPD703302Y and 70F3302Y. In all other products, set this bit to 0.
3. The INTP7 and RXD0 pins are alternate-function pins. When using the pin as the
RXD0 pin, disable edge detection of the alternate-function INTP7 pin (clear the
INTF3.INTF31 and INTR3.INTR31 bits to 0). When using the pin as the INTP7 pin,
stop the UART0 receive operation (clear the ASIM0.RXE0 bit to 0).
Remark The PMC3 register can be read or written in 16-bit units.
When the higher 8 bits and the lower 8 bits of the PMC3 register are used as the
PMC3H register and as the PMC3L register, respectively, this register can be read or
written in 8-bit or 1-bit units.
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(4) Port 3 function register H (PF3H)
After reset: 00H R/W Address: FFFFFC67H
CHAPTER 4 PORT FUNCTIONS
PF3H 0 0 0 0 0 PF39 PF38
0
PF3n
0
1
Specification of normal port/alternate function (n = 8, 9)
When used as normal port (N-ch open-drain output)
When used as alternate-function (N-ch open-drain output)
Caution When using P38 and P39 as N-ch open-drain-output alternate-function pins, set in
the following sequence.
Be sure to set the port latch to 1 before setting the pin to N-ch open-drain output.
P3n bit = 1 → PF3n bit
= 1 → PMC3n bit = 1
(5) Port 3 function control register (PFC3)
After reset: 00H R/W Address: FFFFF466H
PFC3
0 0 PFC35 PFC34 PFC33 PFC32 0 0
Remark For details of specification of alternate-function pins, refer to 4.3.2 (7) Specifying
alternate-function pins of port 3.
(6) Port 3 function control expansion register (PFCE3)
After reset: 00H R/W Address: FFFFF706H
PFCE3
0 0 0 PFCE34 PFCE33 0 0 0
Remark For details of specification of alternate-function pins, refer to 4.3.2 (7) Specifying
alternate-function pins of port 3.
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CHAPTER 4 PORT FUNCTIONS
(7) Specifying alternate-function pins of port 3
PFC35 Specification of Alternate-Function Pin of P35 Pin
0 TI010 input
1 TO01 output
PFCE34 PFC34 Specification of Alternate-Function Pin of P34 Pin
0 0 Setting prohibited
0 1 Setting prohibited
1 0 TIP01 input
1 1 TOP01 output
PFCE33 PFC33 Specification of Alternate-Function Pin of P33 Pin
0 0 Setting prohibited
0 1 Setting prohibited
1 0 TIP00 input
1 1 TOP00 output
PFC32 Specification of Alternate-Function Pin of P32 Pin
0 ASCK0/ADTRG
1 TO01 output
Note
input
Note The ASCK0 and ADTRG pins are alternate-function pins. When using the pin as the ASCK0 pin, disable
the trigger input of the alternate-function ADTRG pin (clear the ADS.TRG bit to 0 or set the ADS.ADTMD bit
to 1). When using the pin as the ADTRG pin, do not set the UART0 operation clock to external input (set
the CKSR0.TPS03 to CKSR0.TPS00 bits to other than 1011).
Caution When the P3n pin is specified as an alternate function by the PMC3.PMC3n bit with the PFC3n
and PFCE3n bits maintaining the initial value (0), output becomes undefined. Therefore, to
specify the P3n pin as an alternate function, set the PFC3n and PFCE3n bits to 1 first and then
set the PMC3n bit to 1 (n = 3, 4).
(8) Pull-up resistor option register 3 (PU3)
After reset: 00H R/W Address: FFFFFC46H
84
PU3 0 PU35 PU34 PU33 PU32 PU31 PU30
0
PU3n
0
1
Control of on-chip pull-up resistor connection (n = 0 to 5)
Not connected
Connected
Caution An on-chip pull-up resistor can be provided for P38 and P39 by a mask option
μ
(only in the
PD703302, 703302Y).
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CHAPTER 4 PORT FUNCTIONS
4.3.3 Port 4
Port 4 is a 3-bit I/O port for which I/O settings can be controlled in 1-bit units.
Port 4 includes the following alternate functions.
Table 4-6. Alternate-Function Pins of Port 4
Yes
Note
Remark Block Type
N-ch open-drain output can
be selected.
D2-SUFL
Pin No. Pin Name Alternate Function I/O PULL
19 P40 SI00 Input – D1-SUL
20 P41 SO00 Output D0-UF
21 P42 SCK00 I/O
Note Software pull-up function
Caution P40 and P42 have hysteresis characteristics when the alternate function is input, but not in the
port mode.
(1) Port 4 register (P4)
After reset: 00H (output latch) R/W Address: FFFFF408H
P4 0 0 0 0 P42 P41 P40
0
P4n
0
1
(2) Port 4 mode register (PM4)
After reset: FFH R/W Address: FFFFF428H
PM4 1 1 1 1 PM42 PM41 PM40
1
PM4n
0
1
0 is output
1 is output
Output mode
Input mode
Control of output data (in output mode) (n = 0 to 2)
Control of I/O mode (n = 0 to 2)
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(3) Port 4 mode control register (PMC4)
After reset: 00H R/W Address: FFFFF448H
0PMC4 0 0 0 0 PMC42 PMC41 PMC40
CHAPTER 4 PORT FUNCTIONS
PMC42
0
I/O port
1
SCK00 I/O
PMC41
0
I/O port
1
SO00 output
PMC40
0
I/O port
1
SI00 input
(4) Port 4 function register (PF4)
After reset: 00H R/W Address: FFFFFC68H
PF4 0 0 0 0 PF42 PF41 0
0
PF4n
0
1
Control of normal output/N-ch open-drain output (n = 1, 2)
Normal output
N-ch open-drain output
Caution When using P41 and P42 as N-ch open-drain-output alternate-function pins, set in
the following sequence.
Be sure to set the port latch to 1 before setting the pin to N-ch open-drain output.
P4n bit = 1 → PF4n bit = 1 → PMC4n bit = 1
(5) Pull-up resistor option register 4 (PU4)
After reset: 00H R/W Address: FFFFFC48H
Specification of P42 pin operation mode
Specification of P41 pin operation mode
Specification of P40 pin operation mode
86
PU4 0 0 0 0 PU42 PU41 0
0
PU4n
0
1
Control of on-chip pull-up resistor connection (n = 1, 2)
Not connected
Connected
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CHAPTER 4 PORT FUNCTIONS
4.3.4 Port 5
Port 5 is a 6-bit I/O port for which I/O settings can be controlled in 1-bit units.
Port 5 includes the following alternate functions.
Table 4-7. Alternate-Function Pins of Port 5
Pin No. Pin Name Alternate Function I/O PULL
28 P50 TI011/RTP00/KR0 I/O E10-SULT
29 P51 TI50/RTP01/KR1 I/O E10-SULT
30 P52 TO50/RTP02/KR2 I/O E00-SUT
31 P53 RTP03/KR3 I/O Ex0-SUT
34 P54 RTP04/KR4 I/O Ex0-SUT
35 P55 RTP05/KR5 I/O
Note
Remark Block Type
Yes –
Ex0-SUT
Note Software pull-up function
(1) Port 5 register (P5)
After reset: 00H (output latch) R/W Address: FFFFF40AH
P5
0 0 P55 P54 P53 P52 P51 P50
P5n
0
1
(2) Port 5 mode register (PM5)
After reset: FFH R/W Address: FFFFF42AH
PM5
1
PM5n
0
1
Control of output data (in output mode) (n = 0 to 5)
0 is output
1 is output
1 PM55 PM54 PM53 PM52 PM51 PM50
Control of I/O mode (n = 0 to 5)
Output mode
Input mode
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(3) Port 5 mode control register (PMC5)
After reset: 00H R/W Address: FFFFF44AH
CHAPTER 4 PORT FUNCTIONS
PMC5
0 0 PMC55 PMC54 PMC53 PMC52 PMC51 PMC50
PMC55
0
1
PMC54
0
1
PMC53
0
1
PMC52
0
1
PMC51
0
1
PMC50
0
1
I/O port/KR5 input
RTP05 output
I/O port/KR4 input
RTP04 output
I/O port/KR3 input
RTP03 output
I/O port/KR2 input
TO50 output/RTP02 output
I/O port/KR1 input
TI50 input/RTP01 output
I/O port/KR0 input
TI011 input/RTP00 output
Specification of P55 pin operation mode
Specification of P54 pin operation mode
Specification of P53 pin operation mode
Specification of P52 pin operation mode
Specification of P51 pin operation mode
Specification of P50 pin operation mode
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(4) Port 5 function control register (PFC5)
Caution When the P5n pin is specified as an alternate function by the PMC5.PMC5n bit with the
PFC5n bit maintaining the initial value (0), output becomes undefined. Therefore, to specify
the P5n pin as alternate function 2, set the PFC5n bit to 1 first and then set the PMC5n bit to
1 (n = 3 to 5).
After reset: 00H R/W Address: FFFFF46AH
CHAPTER 4 PORT FUNCTIONS
PFC5
0 0 PFC55 PFC54 PFC53 PFC52 PFC51 PFC50
PFC55
1
RTP05 output
PFC54
1
RTP04 output
PFC53
1
RTP03 output
PFC52
0
TO50 output
1
RTP02 output
PFC51
0
TI50 input
1
RTP01 output
PFC50
0
TI011 input
1
RTP00 output
(5) Pull-up resistor option register 5 (PU5)
After reset: 00H R/W Address: FFFFFC4AH
Specification of alternate-function pin of P55 pin
Specification of alternate-function pin of P54 pin
Specification of alternate-function pin of P53 pin
Specification of alternate-function pin of P52 pin
Specification of alternate-function pin of P51 pin
Specification of alternate-function pin of P50 pin
PU5
0
PU5n
0
1
0 PU55 PU54 PU53 PU52 PU51 PU50
Control of on-chip pull-up resistor connection (n = 0 to 5)
Not connected
Connected
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CHAPTER 4 PORT FUNCTIONS
4.3.5 Port 7
Port 7 is an 8-bit input-only port for which all the pins are fixed to input.
Port 7 includes the following alternate functions.
Table 4-8. Alternate-Function Pins of Port 7
Pin No. Pin Name Alternate Function I/O PULL
64 P70 ANI0 Input A-A
63 P71 ANI1 Input A-A
62 P72 ANI2 Input A-A
61 P73 ANI3 Input A-A
60 P74 ANI4 Input A-A
59 P75 ANI5 Input A-A
58 P76 ANI6 Input A-A
57 P77 ANI7 Input
Note
Remark Block Type
No –
A-A
Note Software pull-up function
(1) Port 7 register (P7)
After reset: Undefined R Address: FFFFF40EH
P7
P77 P76 P75 P74 P73 P72 P71 P70
P7n
0
1
Input low level
Input high level
Input data read (n = 0 to 7)
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CHAPTER 4 PORT FUNCTIONS
4.3.6 Port 9
Port 9 is a 9-bit I/O port for which I/O settings can be controlled in 1-bit units.
Port 9 includes the following alternate functions.
Table 4-9. Alternate-Function Pins of Port 9
Yes
Note
Remark Block Type
–
Ex1-SUL
N-ch open-drain output can
be specified.
Analog noise elimination
Ex2-SUFL
Ex1-SUIL
Pin No. Pin Name Alternate Function I/O PULL
36 P90 TXD1/KR6 I/O Ex0-SUT
37 P91 RXD1/KR7 Input Ex1-SUHT
38 P96 TI51/TO51 I/O Ex0-SUT
39 P97 SI01 Input
40 P98 SO01 Output Ex0-UF
41 P99 SCK01 I/O
42 P913 INTP4 Input Ex1-SUIL
43 P914 INTP5 Input Ex1-SUIL
44 P915 INTP6 Input
Note Software pull-up function
Caution P97, P99, and P913 to P915 have hysteresis characteristics when the alternate function is input,
but not in the port mode.
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(1) Port 9 register (P9)
After reset: 00H (output latch) R/W Address: P9 FFFFF412H,
CHAPTER 4 PORT FUNCTIONS
P9L FFFFF412H, P9H FFFFF413H
Note
P915P9 (P9H
) P914 P913 0 0 0 P99 P98
89101112131415
(P9L)
Note When reading from or writing to bits 8 to 15 of the P9 register in 8-bit or 1-bit units,
specify these bits as bits 0 to 7 of the P9H register.
Remark The P9 register can be read or written in 16-bit units.
However, when the higher 8 bits and the lower 8 bits of the P9 register are used as
the P9H register and as the P9L register, respectively, these registers can be read or
written in 8-bit or 1-bit units.
(2) Port 9 mode register (PM9)
After reset: FFFFH R/W Address: PM9 FFFFF432H,
Note
) PM914 PM913 1 1 1 PM99 PM98
P97 P96 0 0 0 0 P91 P90
P9n
0
1
PM915PM9 (PM9H
Control of output data (in output mode) (n = 0, 1, 6 to 9, 13 to 15)
0 is output
1 is output
PM9L FFFFF432H, PM9H FFFFF433H
89101112131415
92
(PM9L)
PM97
PM9n
0
1
PM96 1 1 1 1 PM91 PM90
Control of I/O mode (n = 0, 1, 6 to 9, 13 to 15)
Output mode
Input mode
Note When reading from or writing to bits 8 to 15 of the PM9 register in 8-bit or 1-bit units,
specify these bits as bits 0 to 7 of the PM9H register.
Remark The PM9 register can be read or written in 16-bit units.
However, when the higher 8 bits and the lower 8 bits of the PM9 register are used as
the PM9H register and as the PM9L register, respectively, this register can be read or
written in 8-bit or 1-bit units.
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(3) Port 9 mode control register (PMC9)
After reset: 0000H R/W Address: PMC9 FFFFF452H,
CHAPTER 4 PORT FUNCTIONS
PMC9L FFFFF452H, PMC9H FFFFF453H
Note
PMC915PMC9 (PMC9H
) PMC914 PMC913 0 0 0 PMC99 PMC98
(PMC9L)
PMC97 PMC96 0 0 0 0 PMC91 PMC90
PMC915
0
1
PMC914
0
1
PMC913
0
1
PMC99
0
1
PMC98
0
1
I/O port
INTP6 input
I/O port
INTP5 input
I/O port
INTP4 input
I/O port
SCK01 I/O
I/O port
SO01 output
Specification of P915 pin operation mode
Specification of P914 pin operation mode
Specification of P913 pin operation mode
Specification of P99 pin operation mode
Specification of P98 pin operation mode
89101112131415
PMC97
0
1
PMC96
0
1
PMC91
0
1
PMC90
0
1
I/O port
SI01 input
I/O port/TI51 input
TO51 output
I/O port/KR7 input
RXD1 input
I/O port/KR6 input
TXD1 output
Specification of P97 pin operation mode
Specification of P96 pin operation mode
Specification of P91 pin operation mode
Specification of P90 pin operation mode
Note When reading from or writing to bits 8 to 15 of the PMC9 register in 8-bit or 1-bit units,
specify these bits as bits 0 to 7 of the PMC9H register.
Remark The PMC9 register can be read or written in 16-bit units.
However, when the higher 8 bits and the lower 8 bits of the PMC9 register are used
as the PMC9H register and as the PMC9L register, respectively, these registers can
be read or written in 8-bit or 1-bit units.
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(4) Port 9 function register H (PF9H)
After reset: 00H R/W Address: FFFFFC73H
CHAPTER 4 PORT FUNCTIONS
PF9H 0 0 0 0 0 PF99 PF98
0
PF9n
0
1
Control of normal output/N-ch open-drain output (n = 8, 9)
Normal output
N-ch open-drain output
Caution When using P98 and P99 as N-ch open-drain-output alternate-function pins, set
in the following sequence.
Be sure to set the port latch to 1 before setting the pin to N-ch open-drain
output.
P9n bit = 1 → PFC9n bit = 0/1 → PF9n bit = 1 → PMC9n bit = 1
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CHAPTER 4 PORT FUNCTIONS
(5) Port 9 function control register (PFC9)
Caution When port 9 is specified as an alternate function by the PMC9.PMC9n bit with the PFC9n bit
maintaining the initial value (0), output becomes undefined. Therefore, to specify port 9 as
alternate function 2, set the PFC9n bit to 1 first and then set the PMC9n bit to 1 (n = 0, 1, 6 to
9, 13 to 15).
After reset: 0000H R/W Address: PFC9 FFFFF472H,
PFC9L FFFFF472H, PFC9H FFFFF473H
89101112131415
PFC9 (PFC9H
Note
)
PFC915 PFC914 PFC913 0 0 0 PFC99 PFC98
(PFC9L)
PFC97 PFC96 0 0 0 0 PFC91 PFC90
PFC915
1
PFC914
1
PFC913
1
PFC99
1
PFC98
1
PFC97
1
PFC96
1
INTP6 input
INTP5 input
INTP4 input
SCK01 I/O
SO01 output
SI01 input
TO51 output
Specification of alternate-function pin of P915 pin
Specification of alternate-function pin of P914 pin
Specification of alternate-function pin of P913 pin
Specification of alternate-function pin of P99 pin
Specification of alternate-function pin of P98 pin
Specification of alternate-function pin of P97 pin
Specification of alternate-function pin of P96 pin
PFC91
1
PFC90
1
RXD1 input
TXD1 output
Specification of alternate-function pin of P91 pin
Specification of alternate-function pin of P90 pin
Note When reading from or writing to bits 8 to 15 of the PFC9 register in 8-bit or 1-bit units,
specify these bits as bits 0 to 7 of the PFC9H register.
Remark The PFC9 register can be read or written in 16-bit units.
However, when the higher 8 bits and the lower 8 bits of the PFC9 register are used as
the PFC9H register and as the PFC9L register, respectively, these registers can be
read or written in 8-bit or 1-bit units.
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(6) Pull-up resistor option register 9 (PU9)
After reset: 0000H R/W Address: PU9 FFFFFC52H,
PU9 (PU9H
Note
PU915 PU914 PU913 0 0 0 PU99 PU98
)
CHAPTER 4 PORT FUNCTIONS
PU9L FFFFFC52H, PU9H FFFFFC53H
89101112131415
(PU9L)
PU97 PU96 0 0 0 0 PU91 PU90
PU9n
Control of on-chip pull-up resistor connection (n = 0, 1, 6 to 9, 13 to 15)
0
Not connected
1
Connected
Note When reading from or writing to bits 8 to 15 of the PU9 register in 8-bit or 1-bit units,
specify these bits as bits 0 to 7 of the PU9H register.
Remark The PU9 register can be read or written in 16-bit units.
However, when the higher 8 bits and the lower 8 bits of the PU9 register are used as
the PU9H register and as the PU9L register, respectively, these registers can be read
or written in 8-bit or 1-bit units.
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CHAPTER 4 PORT FUNCTIONS
4.3.7 Port CM
Port CM is a 2-bit I/O port for which I/O settings can be controlled in 1-bit units.
Port CM includes the following alternate functions.
Table 4-10. Alternate-Function Pins of Port CM
Pin No. Pin Name Alternate Function I/O PULL
45 PCM0
46 PCM1 CLKOUT Output
− −
Note
Remark Block Type
Yes –
Note Software pull-up function
(1) Port CM register (PCM)
After reset: 00H (output latch) R/W Address: FFFFF00CH
0PCM 0 0 0 0 0 PCM1 PCM0
C-U
D0-U
PCMn
0
0 is output
1
1 is output
(2) Port CM mode register (PMCM)
After reset: FFH R/W Address: FFFFF02CH
1PMCM 1 1 1 1 1 PMCM1 PMCM0
PMCMn
0
Output mode
1
Input mode
(3) Port CM mode control register (PMCCM)
After reset: 00H R/W Address: FFFFF04CH
Control of output data (in output mode) (n = 0, 1)
Control of I/O mode (n = 0, 1)
0PMCCM 0 0 0 0 0 PMCCM1 0
PMCCM1
0
1
I/O port
CLKOUT output
Specification of PCM1 pin operation mode
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CHAPTER 4 PORT FUNCTIONS
(4) Pull-up resistor option register CM (PUCM)
After reset: 00H R/W Address: FFFFFF4CH
0PUCM 0 0 0 0 0 PUCM1 PUCM0
PUCMn
0
1
Not connected
Connected
Control of on-chip pull-up resistor connection (n = 0, 1)
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CHAPTER 4 PORT FUNCTIONS
4.3.8 Port DL
Port DL is an 8-bit I/O port for which I/O settings can be controlled in 1-bit units.
Port DL includes the following alternate functions.
Table 4-11. Alternate-Function Pins of Port DL
Pin No. Pin Name Alternate Function I/O PULL
47 PDL0
48 PDL1
49 PDL2
50 PDL3
51 PDL4
52 PDL5
53 PDL6
54 PDL7
− −
− −
− −
− −
− −
− −
− −
− −
Note
Remark Block Type
Yes –
Note Software pull-up function
C-U
C-U
C-U
C-U
C-U
C-U
C-U
C-U
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(1) Port DL register (PDL)
After reset: 00H (output latch) R/W Address: FFFFF004H
CHAPTER 4 PORT FUNCTIONS
PDL
PDL7 PDL6 PDL5 PDL4 PDL3 PDL2 PDL1 PDL0
PDLn
0
1
0 is output
1 is output
Control of output data (in output mode) (n = 0 to 7)
(2) Port DL mode register (PMDL)
After reset: FFH R/W Address: FFFFF024H
PMDL
PMDL7
PMDLn
0
1
PMDL6 PMDL5 PMDL4 PMDL3 PMDL2 PMDL1 PMDL0
Output mode
Input mode
(3) Pull-up resistor option register DL (PUDL)
After reset: 00H R/W Address: FFFFFF44H
Control of I/O mode (n = 0 to 7)
100
PUDL
PUDL7 PUDL6 PUDL5 PUDL4 PUDL3 PUDL2 PUDL1 PUDL0
PUDLn
0
1
Not connected
Connected
Control of on-chip pull-up resistor connection (n = 0 to 7)
User’s Manual U16896EJ2V0UD
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