Preliminary User’s Manual
V850ES/HG2
32-Bit Single-Chip Microcontrollers
Hardware
µ
PD70F3706
µ
PD70F3707
Document No. U17718EJ1V0UD00 (1st edition)
Date Published December 2005 N CP(K)
Printed in Japan
2005
[MEMO]
2
Preliminary User’s Manual U17718EJ1V0UD
NOTES FOR CMOS DEVICES
1
VOLTAGE APPLICATION WAVEFORM AT INPUT PIN
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the
CMOS device stays in the area between V
malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed,
and also in the transition period when the input level passes through the area between V
V
IH
(MIN).
HANDLING OF UNUSED INPUT PINS
2
Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is
possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to V
via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must
be judged separately for each device and according to related specifications governing the device.
3
PRECAUTION AGAINST ESD
A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as
much as possible, and quickly dissipate it when it has occurred. Environmental control must be
adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that
easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static
container, static shielding bag or conductive material. All test and measurement tools including work
benches and floors should be grounded. The operator should be grounded using a wrist strap.
Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for
PW boards with mounted semiconductor devices.
IL
(MAX) and VIH (MIN) due to noise, etc., the device may
IL
(MAX) and
DD
or GND
4
STATUS BEFORE INITIALIZATION
Power-on does not necessarily define the initial status of a MOS device. Immediately after the power
source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does
not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the
reset signal is received. A reset operation must be executed immediately after power-on for devices
with reset functions.
5
POWER ON/OFF SEQUENCE
In the case of a device that uses different power supplies for the internal operation and external
interface, as a rule, switch on the external power supply after switching on the internal power supply.
When switching the power supply off, as a rule, switch off the external power supply and then the
internal power supply. Use of the reverse power on/off sequences may result in the application of an
overvoltage to the internal elements of the device, causing malfunction and degradation of internal
elements due to the passage of an abnormal current.
The correct power on/off sequence must be judged separately for each device and according to related
specifications governing the device.
6
INPUT OF SIGNAL DURING POWER OFF STATE
Do not input signals or an I/O pull-up power supply while the device is not powered. The current
injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and
the abnormal current that passes in the device at this time may cause degradation of internal elements.
Input of signals during the power off state must be judged separately for each device and according to
related specifications governing the device.
Preliminary User’s Manual U17718EJ1V0UD
3
MINICUBE is a registered trademark of NEC Electronics Corporation in Japan and Germany.
•
The information contained in this document is being issued in advance of the production cycle for the
product. The parameters for the product may change before final production or NEC Electronics
Corporation, at its own discretion, may withdraw the product prior to its production.
•
Not all products and/or types are available in every country. Please check with an NEC Electronics sales
representative for availability and additional information.
No part of this document may be copied or reproduced in any form or by any means without the prior written consent
•
of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document.
NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property
•
rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC Electronics or others.
Descriptions of circuits, software and other related information in this document are provided for illustrative purposes
•
in semiconductor product operation and application examples. The incorporation of these circuits, software and
information in the design of a customer's equipment shall be done under the full responsibility of the customer. NEC
Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of
these circuits, software and information.
While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products,
•
customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
risks of damage to property or injury (including death) to persons arising from defects in NEC Electronics products,
customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and
anti-failure features.
NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and "Specific".
•
The "Specific" quality grade applies only to NEC Electronics products developed based on a customer-designated
"quality assurance program" for a specific application. The recommended applications of an NEC Electronics
products depend on its quality grade, as indicated below. Customers must check the quality grade of each NEC
Electronics product before using it in a particular application.
"Standard":
"Special":
"Specific":
Computers, office equipment, communications equipment, test and measurement equipment, audio and
visual equipment, home electronic appliances, machine tools, personal electronic equipment and
industrial robots.
Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life
support).
Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support
systems and medical equipment for life support, etc.
The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC
Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications
not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to
determine NEC Electronics' willingness to support a given application.
(Note)
(1)
"NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its
majority-owned subsidiaries.
(2)
"NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as
defined above).
M5 D 02 . 11-1
4
Preliminary User’s Manual U17718EJ1V0UD
PREFACE
Readers This manual is intended for users who wish to understand the functions of the
V850ES/HG2 and design application systems using the V850ES/HG2.
Purpose This manual is intended to give users an understanding of the hardware functions of
the V850ES/HG2 shown in the Organization below.
Organization This manual is divided into two parts: Hardware (this manual) and Architecture
(V850ES Architecture User’s Manual).
Hardware Architecture
• Pin functions • Data types
• CPU function • Register set
• On-chip peripheral functions • Instruction format and instruction set
• Flash memory programming • Interrupts and exceptions
• Electrical specifications (target) • Pipeline operation
How to Read This Manual It is assumed that the readers of this manual have general knowledge in the fields of
electrical engineering, logic circuits, and microcontrollers.
To understand the overall functions of the V850ES/HG2
→ Read this manual according to the CONTENTS.
To find the details of a register where the name is known
→ Use APPENDIX A REGISTER INDEX.
To understand the details of an instruction function
→ Refer to the V850ES Architecture User’s Manual available separately.
To know the electrical specifications of the V850ES/HG2
→ See CHAPTER 26 ELECTRICAL SPECIFICATIONS (TARGET).
Register format
→ The name of the bit whose number is in angle brackets (<>) in the figure of the
register format of each register is defined as a reserved word in the device file.
The “yyy bit of the xxx register” is described as the “xxx.yyy bit” in this manual. Note
with caution that if “xxx.yyy” is described as is in a program, however, the
compiler/assembler cannot recognize it correctly.
Preliminary User’s Manual U17718EJ1V0UD
5
Conventions Data significance: Higher digits on the left and lower digits on the right
Active low representation: xxx (overscore over pin or signal name)
Memory map address: Higher addresses on the top and lower addresses on
the bottom
Note: Footnote for item marked with Note in the text
Caution: Information requiring particular attention
Remark: Supplementary information
Numeric representation: Binary ... xxxx or xxxxB
Decimal ... xxxx
Hexadecimal ... xxxxH
Prefix indicating power of 2
(address space, memory
capacity): K (kilo): 2
M (mega): 2
G (giga): 2
10
= 1,024
20
= 1,0242
30
= 1,0243
6
Preliminary User’s Manual U17718EJ1V0UD
Related Documents The related documents indicated in this publication may include preliminary versions.
However, preliminary versions are not marked as such.
Documents related to V850ES/HG2
Document Name Document No.
V850ES Architecture User’s Manual U15943E
V850ES/HG2 Hardware User’s Manual This manual
Documents related to development tools
Document Name Document No.
CA850 Ver. 3.00 C Compiler Package
PM+ Ver. 6.00 Project Manager U17178E
ID850QB Ver. 3.10 Integrated Debugger Operation U17435E
SM850 Ver. 2.50 System Simulator Operation U16218E
SM850 Ver. 2.00 or Later System Simulator External Part User Open
RX850 Ver. 3.20 or Later Real-Time OS
RX850 Pro Ver. 3.20 Real-Time OS
AZ850 Ver. 3.30 System Performance Analyzer U17423E
PG-FP4 Flash Memory Programmer U15260E
Operation U17293E
C Language U17291E
Assembly Language U17292E
Link Directives U17294E
U14873E
Interface Specification
Basics U13430E
Installation U17419E
Technical U13431E
Task Debugger U17420E
Basics U13773E
Installation U17421E
Technical U13772E
Task Debugger U17422E
Preliminary User’s Manual U17718EJ1V0UD
7
CONTENTS
CHAPTER 1 INTRODUCTION..................................................................................................................16
1.1 General .....................................................................................................................................16
1.2 Features....................................................................................................................................18
1.3 Application Fields....................................................................................................................18
1.4 Ordering Information...............................................................................................................19
1.5 Pin Configuration (Top View) .................................................................................................20
1.6 Function Block Configuration ................................................................................................22
1.6.1 Internal block diagram................................................................................................................ 22
1.6.2 Internal units ..............................................................................................................................23
CHAPTER 2 PIN FUNCTIONS ................................................................................................................25
2.1 Pin Function List......................................................................................................................25
2.2 Description of Pin Functions..................................................................................................30
2.3 Pin I/O Circuit Types and Recommended Connection of Unused Pins.............................37
2.4 Pin I/O Circuits .........................................................................................................................39
2.5 Cautions ...................................................................................................................................40
CHAPTER 3 CPU FUNCTION .................................................................................................................41
3.1 Features....................................................................................................................................41
3.2 CPU Register Set .....................................................................................................................42
3.2.1 Program register set ..................................................................................................................43
3.2.2 System register set ....................................................................................................................44
3.3 Operation Modes .....................................................................................................................50
3.3.1 Specifying operation mode ........................................................................................................50
3.4 Address Space.........................................................................................................................51
3.4.1 CPU address space ...................................................................................................................51
3.4.2 Wraparound of CPU address space ..........................................................................................52
3.4.3 Memory map .............................................................................................................................. 53
3.4.4 Areas .........................................................................................................................................55
3.4.5 Recommended use of address space........................................................................................57
3.4.6 Peripheral I/O registers ..............................................................................................................60
3.4.7 Special registers ........................................................................................................................69
3.4.8 Cautions..................................................................................................................................... 73
CHAPTER 4 PORT FUNCTIONS ............................................................................................................76
4.1 Features....................................................................................................................................76
4.2 Basic Configuration of Ports..................................................................................................76
4.3 Port Functions .........................................................................................................................78
4.3.1 Operation of port function ..........................................................................................................78
4.3.2 Notes on setting port pins ..........................................................................................................79
4.3.3 Port 0 .........................................................................................................................................80
4.3.4 Port 1 .........................................................................................................................................86
4.3.5 Port 3 .........................................................................................................................................90
4.3.6 Port 4 .........................................................................................................................................97
4.3.7 Port 5 .......................................................................................................................................100
8
Preliminary User’s Manual U17718EJ1V0UD
4.3.8 Port 7 ....................................................................................................................................... 106
4.3.9 Port 9 ....................................................................................................................................... 108
4.3.10 Port CM ................................................................................................................................... 117
4.3.11 Port CS.................................................................................................................................... 119
4.3.12 Port CT .................................................................................................................................... 121
4.3.13 Port DL .................................................................................................................................... 123
4.3.14 Port pins that function alternately as on-chip debug function................................................... 125
4.3.15 Register settings to use port pins as alternate-function pins.................................................... 126
4.4 Block Diagrams of Port.........................................................................................................131
4.5 Cautions .................................................................................................................................157
4.5.1 Cautions on setting port pins ................................................................................................... 157
CHAPTER 5 CLOCK GENERATION FUNCTION ...............................................................................158
5.1 Overview.................................................................................................................................158
5.2 Configuration.........................................................................................................................159
5.3 Registers ................................................................................................................................161
5.4 Operation................................................................................................................................166
5.4.1 Operation of each clock ........................................................................................................... 166
5.4.2 Clock output function ............................................................................................................... 166
5.5 PLL Function..........................................................................................................................167
5.5.1 Overview ................................................................................................................................. 167
5.5.2 Registers ................................................................................................................................. 167
5.5.3 Usage ......................................................................................................................................171
CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) .................................................................172
6.1 Overview.................................................................................................................................172
6.2 Functions ...............................................................................................................................172
6.3 Configuration.........................................................................................................................173
6.4 Registers ................................................................................................................................175
6.5 Operation................................................................................................................................189
6.5.1 Interval timer mode (TPnMD2 to TPnMD0 bits = 000) ............................................................. 190
6.5.2 External event count mode (TPnMD2 to TPnMD0 bits = 001) ................................................. 200
6.5.3 External trigger pulse output mode (TPnMD2 to TPnMD0 bits = 010) ..................................... 208
6.5.4 One-shot pulse output mode (TPnMD2 to TPnMD0 bits = 011) .............................................. 220
6.5.5 PWM output mode (TPnMD2 to TPnMD0 bits = 100).............................................................. 227
6.5.6 Free-running timer mode (TPnMD2 to TPnMD0 bits = 101) .................................................... 236
6.5.7 Pulse width measurement mode (TPnMD2 to TPnMD0 bits = 110) ........................................ 253
6.5.8 Timer output operations........................................................................................................... 259
6.6 Timer Tuned Operation Function ........................................................................................260
6.7 Selector Function ..................................................................................................................264
6.8 Cautions .................................................................................................................................266
CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) ................................................................267
7.1 Overview.................................................................................................................................267
7.2 Functions ...............................................................................................................................267
7.3 Configuration.........................................................................................................................268
7.4 Registers ................................................................................................................................271
7.5 Operation................................................................................................................................289
Preliminary User’s Manual U17718EJ1V0UD
9
7.5.1 Interval timer mode (TQnMD2 to TQnMD0 bits = 000) ............................................................290
7.5.2 External event count mode (TQnMD2 to TQnMD0 bits = 001) ................................................299
7.5.3 External trigger pulse output mode (TQnMD2 to TQnMD0 bits = 010) ....................................308
7.5.4 One-shot pulse output mode (TQnMD2 to TQnMD0 bits = 011).............................................. 321
7.5.5 PWM output mode (TQnMD2 to TQnMD0 bits = 100) .............................................................330
7.5.6 Free-running timer mode (TQnMD2 to TQnMD0 bits = 101) ...................................................341
7.5.7 Pulse width measurement mode (TQnMD2 to TQnMD0 bits = 110) ........................................ 361
7.5.8 Triangular wave PWM mode (TQnMD2 to TQnMD0 = 111) ....................................................367
7.5.9 Timer output operations ...........................................................................................................368
7.6 Timer Tuned Operation Function........................................................................................ 369
7.7 Cautions ................................................................................................................................ 373
CHAPTER 8 16-BIT INTERVAL TIMER M (TMM) ............................................................................ 374
8.1 Overview................................................................................................................................ 374
8.2 Configuration ........................................................................................................................ 375
8.3 Register ................................................................................................................................. 376
8.4 Operation............................................................................................................................... 377
8.4.1 Interval timer mode ..................................................................................................................377
8.4.2 Cautions................................................................................................................................... 381
CHAPTER 9 WATCH TIMER FUNCTIONS ........................................................................................ 382
9.1 Functions............................................................................................................................... 382
9.2 Configuration ........................................................................................................................ 383
9.3 Registers ............................................................................................................................... 385
9.4 Operation............................................................................................................................... 389
9.4.1 Operation as watch timer .........................................................................................................389
9.4.2 Operation as interval timer ....................................................................................................... 390
9.4.3 Cautions................................................................................................................................... 391
CHAPTER 10 FUNCTIONS OF WATCHDOG TIMER 2 ................................................................... 392
10.1 Functions............................................................................................................................... 392
10.2 Configuration ........................................................................................................................ 393
10.3 Registers ............................................................................................................................... 394
10.4 Operation............................................................................................................................... 397
CHAPTER 11 A/D CONVERTER ......................................................................................................... 398
11.1 Overview................................................................................................................................ 398
11.2 Functions............................................................................................................................... 398
11.3 Configuration ........................................................................................................................ 399
11.4 Registers ............................................................................................................................... 402
11.5 Operation............................................................................................................................... 410
11.5.1 Basic operation ........................................................................................................................ 410
11.5.2 Trigger mode ...........................................................................................................................411
11.5.3 Operation mode ....................................................................................................................... 413
11.5.4 Power-fail compare mode ........................................................................................................ 417
11.6 Cautions ................................................................................................................................ 422
11.7 How to Read A/D Converter Characteristics Table........................................................... 426
10
Preliminary User’s Manual U17718EJ1V0UD
CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) ..............................................430
12.1 Features..................................................................................................................................430
12.2 Configuration.........................................................................................................................431
12.3 Registers ................................................................................................................................433
12.4 Interrupt Request Signals.....................................................................................................439
12.5 Operation................................................................................................................................440
12.5.1 Data format.............................................................................................................................. 440
12.5.2 SBF transmission/reception format.......................................................................................... 442
12.5.3 SBF transmission .................................................................................................................... 444
12.5.4 SBF reception.......................................................................................................................... 445
12.5.5 UART transmission.................................................................................................................. 446
12.5.6 Continuous transmission procedure ........................................................................................447
12.5.7 UART reception....................................................................................................................... 449
12.5.8 Reception errors ...................................................................................................................... 450
12.5.9 Parity types and operations ..................................................................................................... 452
12.5.10 Receive data noise filter ..........................................................................................................453
12.6 Dedicated Baud Rate Generator .......................................................................................... 454
12.7 Cautions .................................................................................................................................462
CHAPTER 13 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) ....................................................463
13.1 Features..................................................................................................................................463
13.2 Configuration.........................................................................................................................464
13.3 Registers ................................................................................................................................466
13.4 Interrupt Request Signals.....................................................................................................473
13.5 Operation................................................................................................................................474
13.5.1 Single transfer mode (master mode, transmission/reception mode)........................................ 474
13.5.2 Single transfer mode (master mode, reception mode)............................................................. 475
13.5.3 Continuous mode (master mode, transmission/reception mode)............................................. 476
13.5.4 Continuous mode (master mode, reception mode).................................................................. 477
13.5.5 Continuous reception mode (error).......................................................................................... 478
13.5.6 Continuous mode (slave mode, transmission/reception mode) ............................................... 479
13.5.7 Continuous mode (slave mode, reception mode) ....................................................................480
13.5.8 Clock timing............................................................................................................................. 481
13.6 Output Pin Status with Operation Disabled .......................................................................483
13.7 Operation Flow ......................................................................................................................484
13.8 Baud Rate Generator ............................................................................................................490
13.8.1 Baud rate generation ............................................................................................................... 491
13.9 Cautions .................................................................................................................................492
CHAPTER 14 DMA FUNCTION (DMA CONTROLLER) ....................................................................493
14.1 Features..................................................................................................................................493
14.2 Configuration.........................................................................................................................494
14.3 Registers ................................................................................................................................495
14.4 Transfer Targets .................................................................................................................... 503
14.5 Transfer Modes......................................................................................................................503
14.6 Transfer Types.......................................................................................................................504
14.7 DMA Channel Priorities ........................................................................................................505
14.8 Time Related to DMA Transfer.............................................................................................505
Preliminary User’s Manual U17718EJ1V0UD
11
DMA Transfer Start Factors................................................................................................. 506
14.9
14.10 DMA Abort Factors ............................................................................................................... 507
14.11 End of DMA Transfer ............................................................................................................ 507
14.12 Operation Timing .................................................................................................................. 507
14.13 Cautions ................................................................................................................................ 512
CHAPTER 15 INTERRUPT/EXCEPTION PROCESSING FUNCTION............................................... 516
15.1 Features................................................................................................................................. 516
15.2 Non-Maskable Interrupts ..................................................................................................... 520
15.2.1 Operation................................................................................................................................. 522
15.2.2 Restore ....................................................................................................................................523
15.2.3 NP flag.....................................................................................................................................524
15.3 Maskable Interrupts.............................................................................................................. 525
15.3.1 Operation................................................................................................................................. 525
15.3.2 Restore ....................................................................................................................................527
15.3.3 Priorities of maskable interrupts...............................................................................................528
15.3.4 Interrupt control register (xxICn) ..............................................................................................532
15.3.5 Interrupt mask registers 0 to 3 (IMR0 to IMR3)........................................................................ 534
15.3.6 In-service priority register (ISPR).............................................................................................536
15.3.7 ID flag ......................................................................................................................................537
15.3.8 Watchdog timer mode register 2 (WDTM2) .............................................................................537
15.4 Software Exception .............................................................................................................. 538
15.4.1 Operation................................................................................................................................. 538
15.4.2 Restore ....................................................................................................................................539
15.4.3 EP flag ..................................................................................................................................... 540
15.5 Exception Trap...................................................................................................................... 541
15.5.1 Illegal opcode definition ...........................................................................................................541
15.5.2 Debug trap ............................................................................................................................... 543
15.6 External Interrupt Request Input Pins (NMI and INTP0 to INTP10) ................................. 545
15.6.1 Noise elimination .....................................................................................................................545
15.6.2 Edge detection.........................................................................................................................545
15.7 Interrupt Acknowledge Time of CPU .................................................................................. 552
15.8 Periods in Which Interrupts Are Not Acknowledged by CPU.......................................... 553
15.9 Cautions ................................................................................................................................ 553
CHAPTER 16 KEY INTERRUPT FUNCTION ..................................................................................... 554
16.1 Function................................................................................................................................. 554
16.2 Register ................................................................................................................................. 555
16.3 Cautions ................................................................................................................................ 555
CHAPTER 17 STANDBY FUNCTION .................................................................................................. 556
17.1 Overview................................................................................................................................ 556
17.2 Registers ............................................................................................................................... 558
17.3 HALT Mode............................................................................................................................ 561
17.3.1 Setting and operation status ....................................................................................................561
17.3.2 Releasing HALT mode............................................................................................................. 561
17.4 IDLE1 Mode ........................................................................................................................... 563
17.4.1 Setting and operation status ....................................................................................................563
12
Preliminary User’s Manual U17718EJ1V0UD
17.4.2 Releasing IDLE1 mode............................................................................................................ 563
17.5 IDLE2 Mode............................................................................................................................565
17.5.1 Setting and operation status .................................................................................................... 565
17.5.2 Releasing IDLE2 mode............................................................................................................ 565
17.5.3 Securing setup time when releasing IDLE2 mode ................................................................... 567
17.6 STOP Mode ............................................................................................................................568
17.6.1 Setting and operation status .................................................................................................... 568
17.6.2 Releasing STOP mode............................................................................................................ 568
17.6.3 Securing oscillation stabilization time when releasing STOP mode......................................... 570
17.7 Subclock Operation Mode....................................................................................................571
17.7.1 Setting and operation status .................................................................................................... 571
17.7.2 Releasing subclock operation mode........................................................................................ 571
17.8 Sub-IDLE Mode......................................................................................................................573
17.8.1 Setting and operation status .................................................................................................... 573
17.8.2 Releasing sub-IDLE mode....................................................................................................... 574
CHAPTER 18 RESET FUNCTIONS......................................................................................................576
18.1 Overview.................................................................................................................................576
18.2 Registers to Check Reset Source........................................................................................577
18.3 Operation................................................................................................................................578
18.3.1 Reset operation via RESET pin ............................................................................................... 578
18.3.2 Reset operation by watchdog timer 2 ...................................................................................... 580
18.3.3 Reset operation by power-on clear circuit................................................................................ 581
18.3.4 Reset operation by low-voltage detector.................................................................................. 581
18.3.5 Reset operation by clock monitor ............................................................................................ 581
CHAPTER 19 CLOCK MONITOR ......................................................................................................... 582
19.1 Functions ...............................................................................................................................582
19.2 Configuration.........................................................................................................................582
19.3 Register ..................................................................................................................................583
19.4 Operation................................................................................................................................584
CHAPTER 20 POWER-ON CLEAR CIRCUIT .....................................................................................587
20.1 Function .................................................................................................................................587
20.2 Configuration.........................................................................................................................587
20.3 Operation................................................................................................................................588
CHAPTER 21 LOW-VOLTAGE DETECTOR........................................................................................589
21.1 Functions ...............................................................................................................................589
21.2 Configuration.........................................................................................................................589
21.3 Registers ................................................................................................................................590
21.4 Operation................................................................................................................................592
21.4.1 To use for internal reset signal ................................................................................................592
21.4.2 To use for interrupt .................................................................................................................. 594
21.5 RAM Retention Voltage Detection Operation.....................................................................595
21.6 Emulation Function...............................................................................................................596
CHAPTER 22 REGULATOR ..................................................................................................................597
Preliminary User’s Manual U17718EJ1V0UD
13
Overview................................................................................................................................ 597
22.1
22.2 Operation............................................................................................................................... 598
CHAPTER 23 FLASH MEMORY.......................................................................................................... 599
23.1 Features................................................................................................................................. 599
23.1.1 Erasure unit .............................................................................................................................600
23.2 Rewriting by Dedicated Flash Programmer....................................................................... 601
23.2.1 Programming environment....................................................................................................... 601
23.2.2 Communication mode..............................................................................................................602
23.2.3 Flash memory control ..............................................................................................................607
23.2.4 Selection of communication mode ...........................................................................................608
23.2.5 Communication commands .....................................................................................................609
23.2.6 Pin connection .........................................................................................................................610
23.2.7 Recommended circuit example for writing ...............................................................................614
23.3 Rewriting by Self Programming.......................................................................................... 615
23.3.1 Overview.................................................................................................................................. 615
23.3.2 Features...................................................................................................................................616
23.3.3 Standard self programming flow ..............................................................................................617
23.3.4 Flash functions.........................................................................................................................618
23.3.5 Pin processing .........................................................................................................................618
23.3.6 Internal resources used ...........................................................................................................619
CHAPTER 24 OPTION BYTE FUNCTION .......................................................................................... 620
CHAPTER 25 ON-CHIP DEBUG FUNCTION ..................................................................................... 621
25.1 Features................................................................................................................................. 621
25.2 Connection Circuit Example................................................................................................ 622
25.3 Interface Signals................................................................................................................... 623
25.4 Register ................................................................................................................................. 625
25.5 Operation............................................................................................................................... 626
25.6 ROM Security Function........................................................................................................ 627
25.6.1 Security ID ...............................................................................................................................627
25.6.2 Setting .....................................................................................................................................628
25.7 Cautions ................................................................................................................................ 629
CHAPTER 26 ELECTRICAL SPECIFICATIONS (TARGET).............................................................. 630
26.1 Absolute Maximum Ratings ................................................................................................ 630
26.2 Capacitance........................................................................................................................... 632
26.3 Operating Conditions........................................................................................................... 632
26.4 Oscillator Characteristics.................................................................................................... 633
26.4.1 Main clock oscillator characteristics.........................................................................................633
26.4.2 Subclock oscillator characteristics ...........................................................................................634
26.4.3 PLL characteristics ..................................................................................................................635
26.4.4 Internal oscillator characteristics..............................................................................................635
26.5 Voltage Regulator Characteristics...................................................................................... 635
26.6 DC Characteristics ............................................................................................................... 636
26.6.1 I/O level ...................................................................................................................................636
26.6.2 Pin leakage current..................................................................................................................637
14
Preliminary User’s Manual U17718EJ1V0UD
26.6.3 Supply current .........................................................................................................................638
26.7 Data Retention Characteristics............................................................................................639
26.8 AC Characteristics ................................................................................................................640
26.8.1 CLKOUT output timing ............................................................................................................ 641
26.9 Basic Operation.....................................................................................................................642
26.10 Flash Memory Programming Characteristics ....................................................................649
CHAPTER 27 PACKAGE DRAWING ...................................................................................................650
APPENDIX A REGISTER INDEX ..........................................................................................................651
APPENDIX B INSTRUCTION SET LIST..............................................................................................660
B.1 Conventions........................................................................................................................... 660
B.2 Instruction Set (in Alphabetical Order) ...............................................................................663
Preliminary User’s Manual U17718EJ1V0UD
15
CHAPTER 1 INTRODUCTION
The V850ES/HG2 is one of the products in the NEC Electronics V850 Series of single-chip microcontrollers
designed for low-power operation for real-time control applications.
1.1 General
The V850ES/HG2 is a 32-bit single-chip microcontroller that includes the V850ES CPU core and peripheral
functions such as ROM/RAM, a timer/counter, serial interfaces, and an A/D converter.
In addition to high real-time response characteristics and 1-clock-pitch basic instructions, the V850ES/HG2 features
multiply instructions, saturated operation instructions, bit manipulation instructions, etc., realized by a hardware
multiplier, as optimum instructions for digital servo control applications.
Table 1-1 lists the products of the V850ES/HG2.
16
Preliminary User’s Manual U17718EJ1V0UD
CHAPTER 1 INTRODUCTION
Table 1-1. V850ES/HG2 Product List
Part Number
µ
PD70F3706
µ
PD70F3707
Flash memory 128 KB 256 KB Internal memory
RAM 12 KB
Memory space Logical space 64 MB
General-purpose register 32 bits × 32 registers
Main clock (oscillation frequency)
Subclock (oscillation frequency)
Ceramic/crystal/external clock
• In PLL mode: f
• In clock through mode: f
X = 4 to 5 MHz
X = 4 to 5 MHz
Crystal/external clock: f
XT = 32.768 kHz
RC oscillation: 20 kHz
Internal oscillator fR = 200 kHz (TYP.)
Minimum instruction execution time 50 ns (main clock (fXX) = 20 MHz operation)
DSP function
32 × 32 = 64: 200 to 250 ns (at 20 MHz)
32 × 32 + 32 = 32: 300 ns (at 20 MHz)
16 × 16 = 32: 50 to 100 ns (at 20 MHz)
16 × 16 + 32 = 32: 150 ns (at 20 MHz)
I/O port I/O: 84
Timer
16-bit timer/event counter P: 4 channels
16-bit timer/event counter Q: 2 channels
16-bit interval timer M: 1 channel
Watchdog timer 2: 1 channel
Watch timer: 1 channel
A/D converter 10-bit resolution × 16 channels
Serial interface
CSIB: 2 channels
UARTA (for LIN): 3 channels
DMA controller 4 channels (transfer target: on-chip peripheral I/O, internal RAM)
Interrupt source External: 12 (12)
Note
, internal: 43
Power save function HALT/IDLE1/IDLE2/STOP/subclock/sub-IDLE mode
Reset
RESET pin input, watchdog timer 2 (WDT2), clock monitor (CLM), POC circuit, low-voltage
detector (LVI)
On-chip debug function Provided (RUN/break)
Operating power supply voltage 3.5 to 5.5 V (A/D converter: 4.0 to 5.5 V)
Operating ambient temperature −40 to +85°C
Package 100-pin plastic LQFP (fine pitch) (14 × 14 mm)
Note The figure in parentheses indicates the number of external interrupts that can release STOP mode.
Preliminary User’s Manual U17718EJ1V0UD
17
CHAPTER 1 INTRODUCTION
1.2 Features
Minimum instruction execution time: 50 ns (operating with main clock (fXX) of 20 MHz)
General-purpose registers: 32 bits × 32 registers
CPU features: Signed multiplication (16 × 16 → 32): 1 to 2 clocks
Signed multiplication (32 × 32 → 64): 1 to 5 clocks
Saturated operations (overflow and underflow detection functions included)
32-bit shift instruction: 1 clock
Bit manipulation instructions
Load/store instructions with long/short format
Memory space: 64 MB of linear address space (for programs and data)
• Internal memory: RAM: 12 KB
Flash memory: 128 KB/256 KB (see Ta ble 1-1)
Interrupts and exceptions: Non-maskable interrupts: 2 sources
Maskable interrupts: 53 sources
Software exceptions: 32 sources
Exception trap: 2 sources
I/O lines: I/O ports: 84
Timer function: 16-bit interval timer M (TMM): 1 channel
16-bit timer/event counter P (TMP): 4 channels
16-bit timer/event counter Q (TMQ): 2 channels
Watch timer: 1 channel
Watchdog timer 2: 1 channel
Serial interface: Asynchronous serial interface A (UARTA)
3-wire variable-length serial interface B (CSIB)
UARTA (supporting LIN): 3 channels
CSIB: 2 channels
A/D converter: 10-bit resolution: 16 channels
DMA controller: 4 channels
On-chip debug function: JTAG interface
Clock generator: During main clock or subclock operation
7-level CPU clock (f
XX, fXX/2, fXX/4, fXX/8, fXX/16, fXX/32, fXT)
Clock-through mode/PLL mode selectable
Internal oscillation clock: 200 kHz (TYP.)
Power-save functions: HALT/IDLE1/IDLE2/STOP/subclock/sub-IDLE mode
Package: 100-pin plastic LQFP (fine pitch) (14 × 14)
1.3 Application Fields
Consumer devices
18
Preliminary User’s Manual U17718EJ1V0UD
CHAPTER 1 INTRODUCTION
1.4 Ordering Information
Part Number Package On-Chip Flash Memory
µ
PD70F3706GC-8EA-A
µ
PD70F3707GC-8EA-A
Remark Products with -A at the end of the part number are lead-free products.
100-pin plastic LQFP (fine pitch) (14 × 14)
100-pin plastic LQFP (fine pitch) (14 × 14)
128 KB
256 KB
Preliminary User’s Manual U17718EJ1V0UD
19
1.5 Pin Configuration (Top View)
100-pin plastic LQFP (fine pitch) (14 × 14)
µ
PD70F3706GC-8EA-A
µ
PD70F3707GC-8EA-A
P70/ANI0
P71/ANI1
P72/ANI2
P73/ANI3
P74/ANI4
CHAPTER 1 INTRODUCTION
P75/ANI5
P76/ANI6
P77/ANI7
P78/ANI8
P79/ANI9
P710/ANI10
P711/ANI11
P712/ANI12
P713/ANI13
P714/ANI14
P715/ANI15
PDL13
PDL12
PDL11
PDL10
PDL9
PDL8
PDL7
PDL6
PDL5/FLMD1
AV
REF0
AV
P10/INTP9
P11/INTP10
EV
P00/TIP31/TOP31
P01/TIP30/TOP30
Note 1
FLMD0
V
Note 2
REGC
V
X1
X2
RESET
XT1
XT2
P02/NMI
P03/INTP0/ADTRG
P04/INTP1
P05/INTP2/DRST
P06/INTP3
P40/SIB0
P41/SOB0
P42/SCKB0
P30/TXDA0
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86
1
SS
2
3
4
DD
5
6
7
8
DD
9
10
SS
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
85
84 8283 81
41
43 4442 45
7780 7879 76
4946 4847 50
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
PDL4
PDL3
PDL2
PDL1
PDL0
DD
BV
BV
SS
PCT6
PCT4
PCT1
PCT0
PCM3
PCM2
PCM1/CLKOUT
PCM0
PCS1
PCS0
P915/INTP6
P914/INTP5
P913/INTP4/PCL
P912
P911
P910
P99/SCKB1
P98/SOB1
P31/RXDA0/INTP7
P32/ASCKA0/TOP01/TIP00/TOP00
Notes 1. Connect this pin to V
2. Connect the REGC pin to V
20
SS
P37
EV
DD
EV
P36
P38/TXDA2
P33/TIP01/TOP01
P34/TIP10/TOP10
P35/TIP11/TOP11
SS in the normal mode.
SS via a 4.7
Preliminary User’s Manual U17718EJ1V0UD
µ
P54/KR4/DCK
P55/KR5/DMS
P90/KR6/TXDA1
P91/KR7/RXDA1
P92/TIQ11/TOQ11
P39/RXDA2/INTP8
P50/KR0/TIQ01/TOQ01
P51/KR1/TIQ02/TOQ02
P52/KR2/TIQ03/TOQ03/DDI
P53/KR3/TIQ00/TOQ00/DDO
P93/TIQ12/TOQ12
F (preliminary value) capacitor.
P96/TIP21/TOP21
P94/TIQ13/TOQ13
P95/TIQ10/TOQ10
P97/SIB1/TIP20/TOP20
Pin identification
ADTRG:
ANI0 to ANI15:
ASCKA0:
AV
REF0:
AV
SS:
BV
DD:
BVSS:
CLKOUT:
DCK:
DDI:
DDO:
DMS:
DRST:
EV
DD:
EV
SS:
FLMD0, FLMD1:
INTP0 to INTP10:
KR0 to KR7:
NMI:
P00 to P06:
P10, P11:
P30 to P39:
P40 to P42:
P50 to P55:
P70 to P715:
P90 to P915:
PCL:
PCM0 to PCM3:
CHAPTER 1 INTRODUCTION
A/D trigger input
Analog input
Asynchronous serial clock
Analog reference voltage
Analog V
SS
Power supply for bus interface
Ground for bus interface
Clock output
Debug clock
Debug data input
Debug data output
Debug mode select
Debug reset
Power supply for port
Ground for port
Flash programming mode
External interrupt input
Key return
Non-maskable interrupt request
Port 0
Port 1
Port 3
Port 4
Port 5
Port 7
Port 9
Programmable clock output
Port CM
PCS0, PCS1:
PCT0, PCT1,
PCT4, PCT6:
PDL0 to PDL13:
REGC:
RESET:
RXDA0 to RXDA2:
SCKB0, SCKB1:
SIB0, SIB1:
SOB0, SOB1:
TIP00, TIP01,
TIP10, TIP11,
TIP20, TIP21,
TIP30, TIP31,
TIQ00 to TIQ03,
TIQ10 to TIQ13:
TOP00, TOP01,
TOP10, TOP11,
TOP20, TOP21,
TOP30, TOP31,
TOQ00 to TOQ03,
TOQ10 to TOQ13:
TXDA0 to TXDA2:
V
DD:
VSS:
X1, X2:
XT1, XT2:
Port CS
Port CT
Port DL
Regulator control
Reset
Receive data
Serial clock
Serial input
Serial output
Timer input
Timer output
Transmit data
Power supply
Ground
Crystal for main clock
Crystal for subclock
Preliminary User’s Manual U17718EJ1V0UD
21
1.6 Function Block Configuration
1.6.1 Internal block diagram
INTP0 to INTP10
TIQ00 to TIQ03
TIQ10 to TIQ13
TOQ00 to TOQ03
TOQ10 to TOQ13
TIP00 to TIP30,
TIP01 to TIP31
TOP00 to TOP30,
TOP01 to TOP31
SIB0, SIB1
SOB0, SOB1
SCKB0, SCKB1
TXDA0 to TXDA2
RXDA0 to RXDA2
KR0 to KR7
µ
Note
µ
NMI
ASCK0
PD70F3706: 128 KB
PD70F3707: 256 KB
INTC
16-bit timer/
counter Q:
2 ch
16-bit timer/
counter P:
4 ch
16-bit
interval
timer M:
1 ch
CSIB: 2 ch
UARTA:
3 ch
Watchdog
timer 2
Watch timer
Key return
function
CHAPTER 1 INTRODUCTION
Flash
memory
Note 1
RAM
12 KB
DMAC
PC
32-bit barrel
shifter
System
registers
General-purpose
registers 32 bits × 32
Port
P10, P11
P50 to P55
P40 to P42
P30 to P39
PCS0, PCS1
P90 to P915
PCM0 to PCM3
PDL0 to PDL13
P70 to P715
P00 to P06
PCT0, PCT1, PCT4, PCT6
ANI0 to ANI15
SS
A/D
converter
AV
AV
REF0
ADTRG
On-chip
debug
function
CPU
Multiplier
16 × 16 → 32
ALU
Internal
oscillator
CLM
Instruction
queue
BCU
CG
PLL
POC
Regulator
DRST
DMS
DDI
DCK
DDO
LVI
PCL
CLKOUT
XT1
XT2
X1
X2
RESET
V
DD
V
SS
REGC
FLMD0
FLMD1
BV
DD
BV
SS
EV
DD
EV
SS
22
Preliminary User’s Manual U17718EJ1V0UD
CHAPTER 1 INTRODUCTION
1.6.2 Internal units
(1) CPU
The CPU uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic
logic operations, data transfers, and almost all other instruction processing.
Other dedicated on-chip hardware, such as a multiplier (16 bits × 16 bits → 32 bits) and a barrel shifter (32
bits) contribute to faster complex processing.
(2) Bus control unit (BCU)
The BCU controls the internal buses.
(3) ROM
This is a 256 KB/128 KB flash memory mapped to addresses 0000000H to 003FFFFH/0000000H to
001FFFFH. It can be accessed from the CPU in one clock during instruction fetch.
(4) RAM
This is a 12 KB RAM mapped to addresses 3FFC000H to 3FFEFFFH. It can be accessed from the CPU in
one clock during data access.
(5) Interrupt controller (INTC)
This controller handles hardware interrupt requests (NMI, INTP0 to INTP10) from on-chip peripheral hardware
and external hardware. Eight levels of interrupt priorities can be specified for these interrupt requests, and
multiple servicing control can be performed.
(6) Clock generator (CG)
A main clock oscillator that generates the main clock oscillation frequency (f
X) and a subclock oscillator that
generates the subclock oscillation frequency (fXT) are available. As the main clock frequency (fXX), fX is used as
is in the clock-through mode and is multiplied by four in the PLL mode.
The CPU clock frequency (f
CPU) can be selected from seven types: fXX, fXX/2, fXX/4, fXX/8, fXX/16, fXX/32, and fXT.
(7) Internal oscillator
An internal oscillator is provided on chip. The oscillation frequency is 200 kHz (TYP.). An internal oscillator
supplies the clock for watchdog timer 2 and timer M.
(8) Timer/counter
Four-channel 16-bit timer/event counter P (TMP), two-channel 16-bit timer/event counter Q (TMQ), and one-
channel 16-bit interval timer M (TMM) are provided on chip.
(9) Watch timer
This timer counts the reference time period (0.5 s) for counting the clock (the 32.768 kHz from the subclock or
the 32.768 kHz f
BRG from prescaler 3). The watch timer can also be used as an interval timer for the main
clock.
Preliminary User’s Manual U17718EJ1V0UD
23
(10) Watchdog timer 2
A watchdog timer is provided on chip to detect inadvertent program loops, system abnormalities, etc.
Either the internal oscillation clock or the main clock can be selected as the source clock.
Watchdog timer 2 generates a non-maskable interrupt request signal (INTWDT2) or a system reset signal
(WDT2RES) after an overflow occurs.
(11) Serial interface
The V850ES/HG2 includes three kinds of serial interfaces: asynchronous serial interface A (UARTA) and 3-
wire variable-length serial interface B (CSIB).
In the case of UARTA, data is transferred via the TXDA0 to TXDA2 and RXDA0 to RXDA2 pins.
In the case of CSIB, data is transferred via the SOB0, SOB1, SIB0, SIB1, SCKB0, and SCKB1 pins.
(12) A/D converter
This 10-bit A/D converter includes 16 analog input pins. Conversion is performed using the successive
approximation method.
(13) DMA controller
A 4-channel DMA controller is provided on chip. This controller transfers data between the internal RAM and
on-chip peripheral I/O devices in response to interrupt requests sent by on-chip peripheral I/O.
(14) Key interrupt function
A key interrupt request signal (INTKR) can be generated by inputting a falling edge to key input pins (8
channels).
(15) On-chip debug function
An on-chip debug function that uses the JTAG (Joint Test Action Group) communication specifications is
provided. Switching between the normal port function and on-chip debugging function is done with the
control pin input level and the on-chip debug mode register (OCDM).
(16) Ports
The general-purpose port functions and control pin functions are provided. For details, see CHAPTER 4
PORT FUNCTIONS.
CHAPTER 1 INTRODUCTION
24
Preliminary User’s Manual U17718EJ1V0UD
CHAPTER 2 PIN FUNCTIONS
This section explains the names and functions of the pins of the V850ES/HG2.
2.1 Pin Function List
Three I/O buffer power supplies, AV
supplies and the pins is shown below.
Power Supply Corresponding Pin
AVREF0 Port 7
BVDD Port CM, port CS, port CT, port DL
EVDD Port 0, port 1, port 3, port 4, port 5, port 9, RESET
(1) Port pins
REF0, BVDD, and EVDD, are available. The relationship between the power
Table 2-1. Pin I/O Buffer Power Supplies
Table 2-2. List of Pins (Port Pins) (1/2)
Pin Name I/O Function Alternate Function
P00 TIP31/TOP31
P01 TIP30/TOP30
P02 NMI
P03 INTP0/ADTRG
P04 INTP1
P05 INTP2/D RST
P06
P10 INTP9
P11
P30 TXDA0
P31 RXDA0/INTP7
P32 ASCKA0/TIP00/TOP00/TOP01
P33 TIP01/TOP01
P34 TIP10/TOP10
P35 TIP11/TOP11
P36
P37
P38 TXDA2
P39
P40 SIB0
P41 SOB0
P42
I/O
I/O
I/O
I/O
Port 0
7-bit I/O port
Input/output can be specified in 1-bit units.
Port 1
2-bit I/O port
Input/output can be specified in 1-bit units.
Port 3
10-bit I/O port
Input/output can be specified in 1-bit units.
Port 4
3-bit I/O port
Input/output can be specified in 1-bit units.
INTP3
INTP10
−
−
RXDA2/INTP8
SCKB0
Preliminary User’s Manual U17718EJ1V0UD
25
CHAPTER 2 PIN FUNCTIONS
Table 2-2. List of Pins (Port Pins) (2/2)
Pin Name I/O Function Alternate Function
P50 KR0/TIQ01/TOQ01
P51 KR1/TIQ02/TOQ02
P52 KR2/TIQ03/TOQ03/DDI
P53 KR3/TIQ00/TOQ00/DDO
P54 KR4/DCK
P55
P70 to P715 I/O
P90 KR6/TXDA1
P91 KR7/RXDA1
P92 TIQ11/TOQ11
P93 TIQ12/TOQ12
P94 TIQ13/TOQ13
P95 TIQ10/TOQ10
P96 TIP21/TOP21
P97 SIB1/TIP20/TOP20
P98 SOB1
P99 SCKB1
P910
P911
P912
P913 INTP4/PCL
P914 INTP5
P915
PCM0
PCM1 CLKOUT
PCM2
PCM3
PCS0
PCS1
PCT0
PCT1
PCT4
PCT6
PDL0 to PDL4
PDL5 FLMD1
PDL6 to PDL13
I/O
I/O
I/O
I/O
I/O
I/O
Port 5
6-bit I/O port
Input/output can be specified in 1-bit units.
Port 7
16-bit I/O port
Input/output can be specified in 1-bit units.
Port 9
16-bit I/O port
Input/output can be specified in 1-bit units.
Port CM
4-bit I/O port
Input/output can be specified in 1-bit units.
Port CS
2-bit I/O port
Input/output can be specified in 1-bit units.
Port CT
4-bit I/O port
Input/output can be specified in 1-bit units.
Port DL
14-bit I/O port
Input/output can be specified in 1-bit units.
KR5/DMS
ANI0 to ANI15
−
−
−
INTP6
−
−
−
−
–
−
−
−
−
−
−
26
Preliminary User’s Manual U17718EJ1V0UD
CHAPTER 2 PIN FUNCTIONS
(2) Non-port pins
Table 2-3. List of Pins (Non-Port Pins) (1/3)
Pin Name I/O Function Alternate Function
Note
NMI
Input
INTP0 P03/ADTRG
INTP1 P04
INTP2 P05/DR ST
INTP3 P06
INTP4 P913/PCL
INTP5 P914
INTP6 P915
INTP7 P31/RXDA0
INTP8 P39/RXDA2
INTP9 P10
INTP10
TIP00 External event/clock input (TMP00) P32/ASCKA0/TOP00/TOP01
TIP01 External event input (TMP01) P33/TOP01
TIP10 External event/clock input (TMP10) P34/TOP10
TIP11 External event input (TMP11) P35/TOP11
TIP20 External event/clock input (TMP20) P97/SIB1/TOP20
TIP21 External event input (TMP21) P96/TOP21
TIP30 External event/clock input (TMP30) P01/TOP30
TIP31
TOP00 Timer output (TMP00) P32/ASCKA0/TIP00/TOP01
TOP10 Timer output (TMP10) P34/TIP10
TOP11 Timer output (TMP11) P35/TIP11
TOP20 Timer output (TMP20) P97/SIB1/TIP20
TOP21 Timer output (TMP21) P96/TIP21
TOP30 Timer output (TMP30) P01/TIP30
TOP31
TIQ00 External event/clock input (TMQ00) P53/KR3/TOQ00/DDO
TIQ01 External event input (TMQ01) P50/KR0/TOQ01
TIQ02 External event input (TMQ02) P51/KR1/TOQ02
TIQ03 External event input (TMQ03) P52/KR2/TOQ03/DDI
TIQ10
Input
Input
Output
Input
External interrupt input
(non-maskable, with analog noise eliminated)
External interrupt request input
(maskable, with analog noise eliminated)
External event input (TMP31) P00/TOP31
Timer output (TMP31) P00/TIP31
External event/clock input (TMQ10) P95/TOQ10
P02
P11
P32/ASCKA0/TIP00/TOP00 TOP01 Timer output (TMP01)
P33/TIP01
Note The NMI pin alternately functions as the P02 pin. It functions as the P02 pin after reset. To enable the NMI
pin, set the PMC0.PMC02 bit to 1. The initial setting of the NMI pin is “No edge detected”. Select the NMI
pin valid edge using INTF0 and INTR0 registers.
Preliminary User’s Manual U17718EJ1V0UD
27
CHAPTER 2 PIN FUNCTIONS
Table 2-3. List of Pins (Non-Port Pins) (2/3)
Pin Name I/O Function Alternate Function
TIQ11 External event input (TMQ11) P92/TOQ11
TIQ12 External event input (TMQ12) P93/TOQ12
TIQ13
TOQ00 Timer output (TMQ00) P53/KR3/TIQ00/DDO
TOQ01 Timer output (TMQ01) P50/KR0/TIQ01
TOQ02 Timer output (TMQ02) P51/KR1/TIQ02
TOQ03 Timer output (TMQ03) P52/KR2/TIQ03/DDI
TOQ10 Timer output (TMQ10) P95/TIQ10
TOQ11 Timer output (TMQ11) P92/TIQ11
TOQ12 Timer output (TMQ12) P93/TIQ12
TOQ13
SIB0 Serial receive data input (CSIB0) P40
SIB1
SOB0 Serial transmit data output (CSIB0) P41
SOB1
SCKB0 Serial clock I/O (CSIB0) P42
SCKB1
RXDA0 Serial receive data input (UARTA0) P31/INTP7
RXDA1 Serial receive data input (UARTA1) P91/KR7
RXDA2
TXDA0 Serial transmit data output (UARTA0) P30
TXDA1 Serial transmit data output (UARTA1) P90/KR6
TXDA2
ASCKA0 Input Baud rate clock input to UARTA0 P32/TIP00/TOP00/TOP01
ANI0 to ANI15 Input Analog voltage input to A/D converter P70 to P715
AVREF0 Input
AVSS
ADTRG Input A/D converter external trigger input P03/INTP0
KR0 P50/TIQ01/TOQ01
KR1 P51/TIQ02/TOQ02
KR2 P52/TIQ03/TOQ03/DDI
KR3 P53/TIQ00/TOQ00/DDO
KR4 P54/DCK
KR5 P55/DMS
KR6 P90/TXDA1
KR7
DMS Input Debug mode select P55/KR5
DDI Input Debug data input P52/KR2/TIQ03/TOQ03
DDO Output Debug data output P53/KR3/TIQ00/TOQ00
Input
External event input (TMQ13) P94/TOQ13
Output
Timer output (TMQ13) P94/TIQ13
Input
Serial receive data input (CSIB1) P97/TIP20/TOP20
Output
Serial transmit data output (CSIB1) P98
I/O
Serial clock I/O (CSIB1) P99
Input
Serial receive data input (UARTA2) P39/INTP8
Output
Serial transmit data output (UARTA2) P38
Reference voltage input to A/D converter,
positive power supply for alternate-function port 7
Ground potential for A/D and D/A converters (same potential
−
SS)
as V
Input Key interrupt input
−
−
P91/RXDA1
28
Preliminary User’s Manual U17718EJ1V0UD
CHAPTER 2 PIN FUNCTIONS
Table 2-3. List of Pins (Non-Port Pins) (3/3)
Pin Name I/O Function Alternate Function
DCK Input Debug clock input P54/KR4
DRST Input Debug reset input P05/INTP2
FLMD0
FLMD1
CLKOUT Output Internal system clock output PCM1
PCL Output Clock output (timing output of X1 input clock and subclock) P913/INTP4
REGC
RESET Input System reset input
X1 Input
X2
XT1 Input
XT2
VDD
VSS
BVDD
BVSS
EVDD
EVSS
Input Flash programming mode setting pins
Regulator output stabilizing capacitor connection
−
Main clock resonator connection
−
Subclock resonator connection
−
Positive power supply pin for internal circuitry
−
Ground potential for internal circuitry
−
Positive power supply pin for bus interface and alternate-function
−
ports
Ground potential for bus interface and alternate-function ports
−
Positive power supply pin for external circuitry (same potential as
−
DD)
V
Ground potential for external circuitry (same potential as VSS)
−
−
PDL5
−
−
−
−
−
−
−
−
−
−
−
−
Preliminary User’s Manual U17718EJ1V0UD
29
CHAPTER 2 PIN FUNCTIONS
2.2 Description of Pin Functions
(1) P00 to P06 (port 0) … 3-state I/O
P00 to P06 function as a 7-bit I/O port that can be set to input or output in 1-bit units.
Besides functioning as an I/O port, these pins operate as NMI input, external interrupt request signal input,
timer/counter I/O, external trigger of the A/D converter, and debug reset input.
This port can be set in the port mode or control mode in 1-bit units. The valid edge of each pin is specified by
the INTR0 and INTF0 registers.
An on-chip pull-up resistor can be connected to P00 to P06 by using pull-up resistor option register 0 (PU0).
(a) Port mode
P00 to P06 can be set in the input or output mode in 1-bit units, by using port mode register 0 (PM0).
(b) Control mode
(i) NMI (Non-maskable interrupt request) … input
This pin inputs a non-maskable interrupt request signal.
(ii) INTP0 to INTP3 (External interrupt input) … input
These pins input external interrupt request signals.
(iii) TIP30, TIP31 (Timer input) … input
These pins input an external count clock to timer P3 (TMP3).
(iv) TOP30, TOP31 (Timer output) … output
These pins output a pulse signal from timer P3 (TMP3).
(v) ADTRG (A/D trigger input) … input
This pin inputs an external trigger to the A/D converter. It is controlled by using A/D converter mode
register 0 (ADA0M0).
(vi) DRST (Debug reset) … input
This pin inputs a debug reset signal, a negative-logic signal that asynchronously initializes the on-chip
debug circuit. To deassert this signal, reset or invalidate the on-chip debug circuit. Deassert this
signal when the debug function is not used.
For details, see CHAPTER 25 ON-CHIP DEBUG FUNCTION.
30
Preliminary User’s Manual U17718EJ1V0UD
CHAPTER 2 PIN FUNCTIONS
(2) P10, P11 (port 1) … 3-state I/O
P10 and P11 function as a 2-bit I/O port that can be set to input or output in 1-bit units.
Besides functioning as an I/O port, these pins operate as external interrupt request signal input in the control
mode. This port can be set in the port mode or control mode in 1-bit units. The valid edge of each pin is
specified by INTR1 and INTF1 registers.
An on-chip pull-up resistor can be connected to P10 and P11 by using pull-up resistor option register 1 (PU1).
(a) Port mode
P10 and P11 can be set in the input or output mode in 1-bit units, by using port mode register 1 (PM1).
(b) Control mode
(i) INTP9, INTP10 (External interrupt input) … input
These pins input an external interrupt request signal.
(3) P30 to P39 (port 3) … 3-state I/O
P30 to P39 function as a 10-bit I/O port that can be set to input or output in 1-bit units.
Besides functioning as an I/O port, these pins operate as external interrupt request signal input, serial interface
I/O, and timer/counter I/O. This port can be set in the port mode or control mode in 1-bit units. The valid edge
of each pin is specified by the INTR3 and INTF3 registers.
An on-chip pull-up resistor can be connected to P30 to P39 by using pull-up resistor option register 3 (PU3).
(a) Port mode
P30 to P39 can be set in the input or output mode in 1-bit units, by using port mode register 3 (PM3).
(b) Control mode
(i) RXDA0, RXDA2 (Receive data) … input
These pins input the serial receive data of UARTA0 and UARTA2.
(ii) TXDA0, TXDA2 (Transmit data) … output
These pins output the serial transmit data of UARTA0 and UARTA2.
(iii) ASCKA0 (Asynchronous serial clock) … input
This is an input pin for UARTA0.
(iv) INTP7, INTP8 (External interrupt input) … input
These pins input an external interrupt request signal.
(v) TIP00, TIP01, TIP10, TIP11 (Timer input) … input
These are input pins for timers P0 and P1 (TMP0 and TMP1).
(vi) TOP00, TOP01, TOP10, TOP11 (Timer output) … output
These are output pins for timers P0 and P1 (TMP0 and TMP1).
Preliminary User’s Manual U17718EJ1V0UD
31
CHAPTER 2 PIN FUNCTIONS
(4) P40 to P42 (port 4) … 3-state I/O
P40 to P42 function as a 3-bit I/O port that can be set to input or output in 1-bit units.
Besides functioning as an I/O port, these pins operate as serial interface I/O. This port can be set in the port
mode or control mode in 1-bit units.
An on-chip pull-up resistor can be connected to P40 to P42 by using pull-up resistor option register 4 (PU4).
(a) Port mode
P40 to P42 can be set in the input or output mode in 1-bit units, by using port mode register 4 (PM4).
(b) Control mode
(i) SIB0 (Serial input) … input
This pin inputs the serial receive data of CSIB0.
(ii) SOB0 (Serial output) … output
This pin outputs the serial transmit data of CSIB0.
(iii) SCKB0 (serial clock) … 3-state I/O
This pin inputs/outputs the serial clock of CSIB0.
(5) P50 to P55 (Port 5) … 3-state I/O
P50 to P55 function as a 6-bit I/O port that can be set to input or output in 1-bit units.
Besides functioning as an I/O port, these pins operate as timer/counter I/O, debug function I/O, and key
interrupt input. This port can be set in the port mode or control mode in 1-bit units.
An on-chip pull-up resistor can be connected to P50 to P55 by using pull-up resistor option register 5 (PU5).
(a) Port mode
P50 to P55 can be set in the input or output mode in 1-bit units, by using port mode register 5 (PM5).
(b) Control mode
(i) KR0 to KR5 (Key return) … input
These pins input a key interrupt. Their operation is specified by using the key return mode register
(KRM) in the input port mode.
(ii) TIQ00, TIQ01, TIQ02, TIQ03 (Timer input) … input
These are input pins for timer Q0 (TMQ0).
(iii) TOQ00, TOQ01, TOQ02, TOQ03 (Timer output) … output
These are output pins for timer Q0 (TMQ0).
(iv) DDI (Debug data input) … input
This pin inputs debug data to the on-chip debug circuit.
For details, see CHAPTER 25 ON-CHIP DEBUG FUNCTION.
(v) DDO (Debug data output) … output
This pin outputs debug data from the on-chip debug circuit.
For details, see CHAPTER 25 ON-CHIP DEBUG FUNCTION.
32
Preliminary User’s Manual U17718EJ1V0UD
CHAPTER 2 PIN FUNCTIONS
(vi) DCK (Debug clock input) … input
This pin inputs a debug clock to the on-chip debug circuit.
For details, see CHAPTER 25 ON-CHIP DEBUG FUNCTION.
(vii) DMS (Debug mode select) … input
This pin selects the debug mode of the on-chip debug circuit.
For details, see CHAPTER 25 ON-CHIP DEBUG FUNCTION.
(6) P70 to P715 (port 7) … 3-state I/O
P70 to P715 function as a 16-bit I/O port that can be set to input or output in 1-bit units.
Besides functioning as an I/O port, these pins operate as analog input to the A/D converter in the control mode.
When using the analog input pins, however, set this port in the input mode. At this time, do not read the port.
(a) Port mode
P70 to P715 can be set in the input or output mode in 1-bit units, by using port mode registers 7L and 7H
(PM7L and PM7H).
(b) Control mode
P70 to P715 function alternately as the ANI0 to ANI15 pins.
(i) ANI0 to ANI15 (Analog input 0 to 15) … input
These pins input an analog signal to the A/D converter.
(7) P90 to P915 (port 9) … 3-state I/O
P90 to P915 function as a 16-bit I/O port that can be set to input or output in 1-bit units.
Besides functioning as an I/O port, these pins operate as serial interface I/O, timer/counter I/O, clock output,
external interrupt request signal input, and key interrupt input. This port can be set in the port mode or control
mode in 1-bit units. The valid edge of P913 to P915 is specified by INTR9H and INTF9H registers.
An on-chip pull-up resistor can be connected to P90 to P915 by using pull-up resistor option register 9 (PU9).
(a) Port mode
P90 to P915 can be set in the input or output mode in 1-bit units, by using port mode register 9 (PM9).
(b) Control mode
(i) SIB1 (Serial input) … input
This pin inputs the serial receive data of CSIB1.
(ii) SOB1 (Serial output) … output
This pin outputs the serial transmit data of CSIB1.
(iii) SCKB1 (Serial clock) … 3-state I/O
This pin inputs/outputs the serial clock of CSIB1.
(iv) RXDA1 (Receive data) … input
This pin inputs the serial receive data of UARTA1.
Preliminary User’s Manual U17718EJ1V0UD
33
CHAPTER 2 PIN FUNCTIONS
(v) TXDA1 (Transmit data) … output
This pin outputs the serial transmit data of UARTA1.
(vi) TIP20, TIP21 (Timer input) … input
These are input pins for timer P2 (TMP2).
(vii) TOP20, TOP21 (Timer output) … output
These are output pins for timer P2 (TMP2).
(viii) TIQ10, TIQ11, TIQ12, TIQ13 (Timer input) … input
These are input pins for timer Q1 (TMQ1).
(ix) TOQ10, TOQ11, TOQ12, TOQ13 (Timer output) … output
These are output pins for timer Q1 (TMQ1).
(x) PCL (Clock output) … output
This pin outputs a clock.
(xi) INTP4 to INTP6 (External interrupt input) … input
These pins input an external interrupt request signal.
(xii) KR6, KR7 (Key return) … input
These pins input a key interrupt. Their operation is specified by the key return mode register (KRM) in
the input port mode.
(8) PCM0 to PCM3 (port CM) … 3-state I/O
PCM0 to PCM3 function as a 4-bit I/O port that can be set to input or output in 1-bit units.
Besides functioning as an I/O port, these pins operate as bus clock output in the control mode.
(a) Port mode
PCM0 to PCM3 can be set in the input or output mode in 1-bit units, by using port mode register CM
(PMCM).
(b) Control mode
(i) CLKOUT (Clock output) … output
This pin outputs an internally generated bus clock.
(9) PCS0, PCS1 (port CS) … 3-state I/O
PCS0 and PCS1 function as a 2-bit I/O port that can be set to input or output in 1-bit units.
(a) Port mode
PCS0 and PCS1 can be set in the input or output mode in 1-bit units, by using port mode register CS
(PMCS).
34
Preliminary User’s Manual U17718EJ1V0UD
CHAPTER 2 PIN FUNCTIONS
(10) PCT0, PCT1, PCT4, PCT6 (port CT) … 3-state I/O
PCT0, PCT1, PCT4, and PCT6 function as a 4-bit I/O port that can be set to input or output in 1-bit units.
(a) Port mode
PCT0, PCT1, PCT4, and PCT6 can be set in the input or output mode in 1-bit units, by using port mode
register CT (PMCT).
(11) PDL0 to PDL13 (port DL) … 3-state I/O
PDL0 to PDL13 function as a 14-bit I/O port that can be set to input or output in 1-bit units.
PDL5 also functions as the FLMD1 pin when the flash memory is programmed (when a high level is input to
FLMD0). At this time, be sure to input a low level to the FLMD1 pin.
(a) Port mode
PDL0 to PDL13 can be set in the input or output mode in 1-bit units, by using port mode register DL
(PMDL).
(12) RESET (Reset) … input
RESET input is asynchronous input. When a signal with a fixed low level width is input to the RESET pin
regardless of the operating clock, the system is reset, taking precedence over all the other operations.
This pin is used to release the standby mode (HALT, IDLE, or STOP), as well as for normal initialization/start.
(13) X1, X2 (Crystal for main clock)
These pins are used to connect the resonator that generates the system clock.
(14) XT1, XT2 (Crystal for subclock)
These pins are used to connect the resonator that generates the subclock.
(15) AV
SS (Ground for analog)
This is a ground pin for the A/D converter and alternate-function ports.
(16) AV
REF0 (Analog reference voltage) … input
This pin supplies positive analog power to the A/D converter and alternate-function ports.
It also supplies a reference voltage to the A/D converter.
(17) EV
DD (Power supply for port)
This pin supplies positive power to the I/O ports and alternate-function pins.
(18) EV
SS (Ground for port)
This is a ground pin for the I/O ports and alternate-function pins.
(19) V
DD (Power supply)
This pin supplies positive power. Connect all the V
DD pins to a positive power supply.
Preliminary User’s Manual U17718EJ1V0UD
35
CHAPTER 2 PIN FUNCTIONS
(20) VSS (Ground)
This is a ground pin. Connect all the VSS pins to ground.
(21) FLMD0 (Flash programming mode) … input
This is a signal input pin for flash memory programming mode.
Connect this pin to V
SS in the normal operation mode.
(22) BVDD (Power supply for port)
This pin supplies positive power to the I/O ports and alternate-function pins.
(23) BV
SS (Ground for port)
This is a ground pin for the I/O ports and alternate-function pins.
(24) REGC (Regulator control) … input
This pin connects a capacitor for the regulator.
36
Preliminary User’s Manual U17718EJ1V0UD
CHAPTER 2 PIN FUNCTIONS
2.3 Pin I/O Circuit Types and Recommended Connection of Unused Pins
Pin
P00/TIP31/TOP31
P01/TIP30/TOP30
P02/NMI
P03/INTP0/ADTRG
P04/INTP1
P05/INTP2/DRST 5-AF
I/O Circuit
Type
5-W
Recommended Connection
Input: Independently connect to EV
Output: Leave open
Input: Independently connect to EV
Output: Leave open
DD or EVSS via a resistor
SS
(1/2)
P06/INTP3 5-W
Input: Independently connect to EV
Output: Leave open
P10/INTP9
5-W
P11/INTP10
P30/TXDA0 5-A
P31/RXDA0/INTP7
5-W
Input: Independently connect to EV
Output: Leave open
Input: Independently connect to EV
Output: Leave open
P32/ASCKA0/TIP00/TOP00/
TOP01
P33/TIP01/TOP01
P34/TIP10/TOP10
P35/TIP11/TOP11
P36
5-A
P37
P38/TXDA2
P39/RXDA2/INTP8 5-W
P40/SIB0 5-W
P41/SOB0 5-A
Input: Independently connect to EV
Output: Leave open
P42/SCKB0 5-W
P50/KR0/TIQ01/TOQ01
P51/KR1/TIQ02/TOQ02
5-W
Input: Independently connect to EV
Output: Leave open
P52/KR2/TIQ03/TOQ03/DDI
P53/KR3/TIQ00/TOQ00/DDO
P54/KR4/DCK
P55/KR5/DMS
P70/ANI0 to P79/ANI9
P710/ANI10, P711/ANI11
11-G
Input: Independently connect to AV
Output: Leave open
P712/ANI12 to P715/ANI15
P90/KR6/TXDA1
P91/KR7/RXDA1
5-W
Input: Independently connect to EV
Output: Leave open
P92/TIQ11/TOQ11
P93/TIQ12/TOQ12
P94/TIQ13/TOQ13
P95/TIQ10/TOQ10
DD or EVSS via a resistor
DD or EVSS via a resistor
DD or EVSS via a resistor
DD or EVSS via a resistor
DD or EVSS via a resistor
REF0 or AVSS via a resistor
DD or EVSS via a resistor
Preliminary User’s Manual U17718EJ1V0UD
37
CHAPTER 2 PIN FUNCTIONS
Pin
I/O Circuit
Recommended Connection
Type
P96/TIP21/TOP21
P97/SIB1/TIP20/TOP20
5-W
Input: Independently connect to EV
Output: Leave open
DD or EVSS via a resistor
P98/SOB1 5-A
P99/SCKB1 5-W
P910
5-A
P911
P912
P913/INTP4/PCL
P914/INTP5
5-W
Input: Independently connect to EV
Output: Leave open
DD or EVSS via a resistor
P915/INTP6
PCM0
PCM1/CLKOUT
5 Input: Independently connect to BV
Output: Leave open
DD or BVSS via a resistor
PCM2
PCM3
PCS0
PCS1
PCT0
PCT1
5 Input: Independently connect to BVDD or BVSS via a resistor
Output: Leave open
5 Input: Independently connect to BV
DD or BVSS via a resistor
Output: Leave open
PCT4
PCT6
PDL0 to PDL4
PDL5/FLMD1
5 Input: Independently connect to BV
Output: Leave open
DD or BVSS via a resistor
PDL6 to PDL13
AVREF0
AVSS
FLMD0
REGC
Note
−
− −
−
− −
RESET 2
X1
X2
− −
− −
Directly connect to VDD
Directly connect to VSS
−
XT1 16 Connect to VSS via a resistor
XT2 16 Leave open
VDD
VSS
BVDD
BVSS
EVDD
EVSS
− −
− −
− −
− −
− −
− −
Note If noise that exceeds the noise elimination width is input to the RESET pin during self programming, the
flash on-board mode may be entered depending on the capacitance charge end timing when a capacitor is
connected to the FLMD0 pin. Therefore, do not connect a capacitor to the FLMD0 pin.
(2/2)
38
Preliminary User’s Manual U17718EJ1V0UD
CHAPTER 2 PIN FUNCTIONS
2.4 Pin I/O Circuits
Figure 2-1. Pin I/O Circuit Types (1/2)
Type 2 Type 5-AF
Pull-up
enable
IN
Schmitt-triggered input with hysteresis characteristics
Pull-down
enable
Data
Output
disable
Input enable
V
DD
P-ch
N
-ch
DD
V
P-ch
N
-ch
IN/OUT
Type 5 Type 11-G
V
DD
Data
Output
disable
Input
enable
P-ch
N-ch
IN/OUT
Output
disable
Comparator
(Threshold voltage)
Data
+
_
V
REF
Input enable
AV
REF0
AV
P-ch
IN/OUT
N-ch
AV
P-ch
SS
N-ch
SS
Preliminary User’s Manual U17718EJ1V0UD
39
CHAPTER 2 PIN FUNCTIONS
Figure 2-1. Pin I/O Circuit Types (2/2)
Type 5-A
Pull-up
enable
Data
Output
disable
Input
enable
Type 5-W
Pull-up
enable
Data
Output
disable
V
DD
P-ch
N-ch
DD
V
P-ch
N
-ch
VDD
P-ch
DD
V
P-ch
Type 16
Feedback cut-off
P-ch
IN/OUT
XT1 XT2
IN/OUT
Input
enable
2.5 Cautions
Note that the following pin may temporarily output an undefined level, even during reset upon power application.
P53/KR3/TIQ00/TOQ00/DDO pin
40
Preliminary User’s Manual U17718EJ1V0UD
CHAPTER 3 CPU FUNCTION
The CPU of the V850ES/HG2 is based on RISC architecture and executes almost all instructions with one clock by
using a 5-stage pipeline.
3.1 Features
Minimum instruction execution time: 50 ns (at 20 MHz operation)
Memory space Program (physical address) space: 64 MB linear
Data (logical address) space: 4 GB linear
General-purpose registers: 32 bits × 32 registers
Internal 32-bit architecture
5-stage pipeline control
Multiplication/division instruction
Saturation operation instruction
32-bit shift instruction: 1 clock
Load/store instruction with long/short format
Four types of bit manipulation instructions
• SET1
• CLR1
• NOT1
• TST1
Preliminary User’s Manual U17718EJ1V0UD
41
CHAPTER 3 CPU FUNCTION
3.2 CPU Register Set
The registers of the V850ES/HG2 can be classified into two types: general-purpose program registers and
dedicated system registers. All the registers are 32 bits wide.
For details, refer to the V850ES Architecture User’s Manual.
(1) Program register set
(2) System register set
31 0 31 0
r0
(Zero register)
r1
(Assembler-reserved register)
r2
r3
(Stack pointer (SP))
r4
(Global pointer (GP))
r5
(Text pointer (TP))
r6
r7
r8
r9
r10
r11
r12
r13
r14
r15
r16
r17
r18
r19
r20
r21
r22
r23
r24
r25
r26
r27
r28
r29
r30
(Element pointer (EP))
r31
(Link pointer (LP))
EIPC
EIPSW
FEPC
FEPSW
ECR (Interrupt source register)
PSW (Program status word)
CTPC
CTPSW
DBPC
DBPSW
CTBP (CALLT base pointer)
(Interrupt status saving register)
(Interrupt status saving register)
(NMI status saving register)
(NMI status saving register)
(CALLT execution status saving register)
(CALLT execution status saving register)
(Exception/debug trap status saving register)
(Exception/debug trap status saving register)
31 0
PC (Program counter)
42
Preliminary User’s Manual U17718EJ1V0UD
CHAPTER 3 CPU FUNCTION
3.2.1 Program register set
The program registers include general-purpose registers and a program counter.
(1) General-purpose registers (r0 to r31)
Thirty-two general-purpose registers, r0 to r31, are available. Any of these registers can be used to store a
data variable or an address variable.
However, r0 and r30 are implicitly used by instructions and care must be exercised when these registers are
used. r0 always holds 0 and is used for an operation that uses 0 or addressing of offset 0. r30 is used by the
SLD and SST instructions as a base pointer when these instructions access the memory. r1, r3 to r5, and r31
are implicitly used by the assembler and C compiler. When using these registers, save their contents for
protection, and then restore the contents after using the registers. r2 is sometimes used by the real-time OS.
If the real-time OS does not use r2, it can be used as a register for variables.
Table 3-1. Program Registers
Name Usage Operation
r0 Zero register Always holds 0.
r1 Assembler-reserved register Used as working register to create 32-bit immediate data
r2 Register for address/data variable (if real-time OS does not use r2)
r3 Stack pointer Used to create a stack frame when a function is called
r4 Global pointer Used to access a global variable in the data area
r5 Text pointer Used as register that indicates the beginning of a text area (area
where program codes are located)
r6 to r29 Register for address/data variable
r30 Element pointer Used as base pointer to access memory
r31 Link pointer Used when the compiler calls a function
PC Program counter Holds the instruction address during program execution
Remark For furthers details on the r1, r3 to r5, and r31 that are used in the assembler and C compiler, refer
to the CA850 (C Compiler Package) Assembly Language User’s Manual.
(2) Program counter (PC)
The program counter holds the instruction address during program execution. The lower 26 bits of this register
are valid. Bits 31 to 26 are fixed to 0. A carry from bit 25 to 26 is ignored even if it occurs.
Bit 0 is fixed to 0. This means that execution cannot branch to an odd address.
31 26 25 1 0
PC
Fixed to 0 Instruction address during program execution
0
Default value
00000000H
Preliminary User’s Manual U17718EJ1V0UD
43
CHAPTER 3 CPU FUNCTION
3.2.2 System register set
The system registers control the status of the CPU and hold interrupt information.
These registers can be read or written by using system register load/store instructions (LDSR and STSR), using
the system register numbers listed below.
Table 3-2. System Register Numbers
System Register Name
Register
Number
Note 1
Note 1
Note 1
Note 1
0 Interrupt status saving register (EIPC)
1 Interrupt status saving register (EIPSW)
2 NMI status saving register (FEPC)
3 NMI status saving register (FEPSW)
4 Interrupt source register (ECR)
5 Program status word (PSW)
6 to 15 Reserved for future function expansion (operation is not guaranteed if these
Operand Specification System
LDSR Instruction STSR Instruction
√ √
√ √
√ √
√ √
× √
√ √
× ×
registers are accessed)
16 CALLT execution status saving register (CTPC)
17 CALLT execution status saving register (CTPSW)
18 Exception/debug trap status saving register (DBPC) √
19 Exception/debug trap status saving register (DBPSW) √
20 CALLT base pointer (CTBP)
21 to 31 Reserved for future function expansion (operation is not guaranteed if these
√ √
√ √
Note 2
√
Note 2
√
√ √
× ×
Note 2
Note 2
registers are accessed)
Notes 1. Because only one set of these registers is available, the contents of these registers must be saved by
program if multiple interrupts are enabled.
2. These registers can be accessed only during the interval between the execution of the DBTRAP
instruction or illegal opcode and the DBRET instruction.
Caution Even if EIPC or FEPC, or bit 0 of CTPC is set to 1 by the LDSR instruction, bit 0 is ignored when
execution is returned to the main routine by the RETI instruction after interrupt servicing (this is
because bit 0 of the PC is fixed to 0). Set an even value to EIPC, FEPC, and CTPC (bit 0 = 0).
Remark √: Can be accessed
×: Access prohibited
44
Preliminary User’s Manual U17718EJ1V0UD
CHAPTER 3 CPU FUNCTION
(1) Interrupt status saving registers (EIPC and EIPSW)
EIPC and EIPSW are used to save the status when an interrupt occurs.
If a software exception or a maskable interrupt occurs, the contents of the program counter (PC) are saved to
EIPC, and the contents of the program status word (PSW) are saved to EIPSW (these contents are saved to
the NMI status saving registers (FEPC and FEPSW) if a non-maskable interrupt occurs).
The address of the instruction next to the instruction under execution, except some instructions (see 15.8
Periods in Which Interrupts Are Not Acknowledged by CPU), is saved to EIPC when a software exception
or a maskable interrupt occurs.
The current contents of the PSW are saved to EIPSW.
Because only one set of interrupt status saving registers is available, the contents of these registers must be
saved by program when multiple interrupts are enabled.
Bits 31 to 26 of EIPC and bits 31 to 8 of EIPSW are reserved for future function expansion (these bits are
always fixed to 0).
The value of EIPC is restored to the PC and the value of EIPSW to the PSW by the RETI instruction.
EIPC
EIPSW
31 0
00
31 0
00
26 25
0 0 0 0
0 0 0 0 00 0 0 0 0 00 0 0 0 0 00 0 0 0 0
(Saved PC contents)
87
(Saved PSW
contents)
Default value
0xxxxxxxH
(x: Undefined)
Default value
000000xxH
(x: Undefined)
Preliminary User’s Manual U17718EJ1V0UD
45
CHAPTER 3 CPU FUNCTION
(2) NMI status saving registers (FEPC and FEPSW)
FEPC and FEPSW are used to save the status when a non-maskable interrupt (NMI) occurs.
If an NMI occurs, the contents of the program counter (PC) are saved to FEPC, and those of the program
status word (PSW) are saved to FEPSW.
The address of the instruction next to the one of the instruction under execution, except some instructions, is
saved to FEPC when an NMI occurs.
The current contents of the PSW are saved to FEPSW.
Because only one set of NMI status saving registers is available, the contents of these registers must be saved
by program when multiple interrupts are enabled.
Bits 31 to 26 of FEPC and bits 31 to 8 of FEPSW are reserved for future function expansion (these bits are
always fixed to 0).
The value of FEPC is restored to the PC and the value of FEPSW to the PSW by the RETI instruction.
FEPC
FEPSW
31 0
00
31 0
00
26 25
0 0 0 0
0 0 0 0 00 0 0 0 0 00 0 0 0 0 00 0 0 0 0
(Saved PC contents)
87
(Saved PSW
contents)
Default value
0xxxxxxxH
(x: Undefined)
Default value
000000xxH
(x: Undefined)
(3) Interrupt source register (ECR)
The interrupt source register (ECR) holds the source of an exception or interrupt if an exception or interrupt
occurs. This register holds the exception code of each interrupt source. Because this register is a read-only
register, data cannot be written to this register using the LDSR instruction.
ECR
31 0
FECC EICC
16 15
Default value
00000000H
Bit position Bit name Meaning
31 to 16 FECC Exception code of non-maskable interrupt (NMI)
15 to 0 EICC Exception code of exception or maskable interrupt
46
Preliminary User’s Manual U17718EJ1V0UD
CHAPTER 3 CPU FUNCTION
(4) Program status word (PSW)
The program status word (PSW) is a collection of flags that indicate the status of the program (result of
instruction execution) and the status of the CPU.
If the contents of a bit of this register are changed by using the LDSR instruction, the new contents are
validated immediately after completion of LDSR instruction execution. However if the ID flag is set to 1,
interrupt requests will not be acknowledged while the LDSR instruction is being executed.
Bits 31 to 8 of this register are reserved for future function expansion (these bits are fixed to 0).
PSW
31 0
RFU
87NP6EP5ID4
SAT3CY2OV
1
SZ
Default value
00000020H
Bit position Flag name Meaning
31 to 8 RFU Reserved field. Fixed to 0.
7 NP Indicates that a non-maskable interrupt (NMI) is being serviced. This bit is set to 1 when an
NMI request is acknowledged, disabling multiple interrupts.
0: NMI is not being serviced.
1: NMI is being serviced.
6 EP Indicates that an exception is being processed. This bit is set to 1 when an exception
occurs. Even if this bit is set, interrupt requests are acknowledged.
0: Exception is not being processed.
1: Exception is being processed.
5 ID Indicates whether a maskable interrupt can be acknowledged.
0: Interrupt enabled
1: Interrupt disabled
4 SAT
3 CY Indicates whether a carry or a borrow occurs as a result of an operation.
2 OV
1 S
0 Z Indicates whether the result of an operation is 0.
Note
Indicates that the result of a saturation operation has overflowed and is saturated. Because
this is a cumulative flag, it is set to 1 when the result of a saturation operation instruction is
saturated, and is not cleared to 0 even if the subsequent operation result is not saturated.
Use the LDSR instruction to clear this bit. This flag is neither set to 1 nor cleared to 0 by
execution of an arithmetic operation instruction.
0: Not saturated
1: Saturated
0: Carry or borrow does not occur.
1: Carry or borrow occurs.
Note
Indicates whether an overflow occurs during operation.
0: Overflow does not occur.
1: Overflow occurs.
Note
Indicates whether the result of an operation is negative.
0: The result is positive or 0.
1: The result is negative.
0: The result is not 0.
1: The result is 0.
(1/2)
Remark Also read Note on the next page.
Preliminary User’s Manual U17718EJ1V0UD
47
CHAPTER 3 CPU FUNCTION
Note The result of the operation that has performed saturation processing is determined by the contents of the
OV and S flags. The SAT flag is set to 1 only when the OV flag is set to 1 when a saturation operation is
performed.
SAT OV S
Maximum positive value is exceeded 1 1 0 7FFFFFFFH
Maximum negative value is exceeded 1 1 1 80000000H
Positive (maximum value is not exceeded) 0
Negative (maximum value is not exceeded)
Holds value
before operation
Flag status Status of operation result
0
1
Result of operation of
saturation processing
Operation result itself
(5) CALLT execution status saving registers (CTPC and CTPSW)
CTPC and CTPSW are CALLT execution status saving registers.
When the CALLT instruction is executed, the contents of the program counter (PC) are saved to CTPC, and
those of the program status word (PSW) are saved to CTPSW.
The contents saved to CTPC are the address of the instruction next to CALLT.
The current contents of the PSW are saved to CTPSW.
Bits 31 to 26 of CTPC and bits 31 to 8 of CTPSW are reserved for future function expansion (fixed to 0).
CTPC
CTPSW
31 0
00
31 0
00
26 25
0 0 0 0
0 0 0 0 00 0 0 0 0 00 0 0 0 0 00 0 0 0 0
(Saved PC contents)
87
(Saved PSW
contents)
Default value
0xxxxxxxH
(x: Undefined)
Default value
000000xxH
(x: Undefined)
(2/2)
48
Preliminary User’s Manual U17718EJ1V0UD
CHAPTER 3 CPU FUNCTION
(6) Exception/debug trap status saving registers (DBPC and DBPSW)
DBPC and DBPSW are exception/debug trap status registers.
If an exception trap or debug trap occurs, the contents of the program counter (PC) are saved to DBPC, and
those of the program status word (PSW) are saved to DBPSW.
The contents to be saved to DBPC are the address of the instruction next to the one that is being executed
when an exception trap or debug trap occurs.
The current contents of the PSW are saved to DBPSW.
This register can be read or written only during the interval between the execution of the DBTRAP instruction
or illegal opcode and the DBRET instruction.
Bits 31 to 26 of DBPC and bits 31 to 8 of DBPSW are reserved for future function expansion (fixed to 0).
The value of DBPC is restored to the PC and the value of DBPSW to the PSW by the DBRET instruction.
DBPC
DBPSW
31 0
00
31 0
00
26 25
0 0 0 0
0 0 0 0 00 0 0 0 0 00 0 0 0 0 00 0 0 0 0
(Saved PC contents)
87
(Saved PSW
contents)
Default value
0xxxxxxxH
(x: Undefined)
Default value
000000xxH
(x: Undefined)
(7) CALLT base pointer (CTBP)
The CALLT base pointer (CTBP) is used to specify a table address or generate a target address (bit 0 is fixed
to 0).
Bits 31 to 26 of this register are reserved for future function expansion (fixed to 0).
CTBP
31 0
00
26 25
0 0 0 0 0
(Base address)
Default value
0xxxxxxxH
(x: Undefined)
Preliminary User’s Manual U17718EJ1V0UD
49
CHAPTER 3 CPU FUNCTION
3.3 Operation Modes
The V850ES/HG2 has the following operation modes.
(1) Normal operation mode
In this mode, each pin related to the bus interface is set to the port mode after system reset has been released.
Execution branches to the reset entry address of the internal ROM, and then instruction processing is started.
(2) Flash memory programming mode
In this mode, the internal flash memory can be programmed by using a flash programmer.
(3) On-chip debug mode
The V850ES/HG2 is provided with an on-chip debug function that employs the JTAG (Joint Test Action Group)
communication specifications and that is executed via an on-chip debug emulator.
For details, see CHAPTER 25 ON-CHIP DEBUG FUNCTION.
3.3.1 Specifying operation mode
Specify the operation mode by using the FLMD0 and FLMD1 pins.
In the normal mode, input a low level to the FLMD0 pin when reset is released.
In the flash memory programming mode, a high level is input to the FLMD0 pin from the flash programmer if a flash
programmer is connected, but it must be input from an external circuit in the self-programming mode.
Operation When Reset Is Released
FLMD0 FLMD1
Operation Mode After Reset
L
H L Flash memory programming mode
H H Setting prohibited
×
Normal operation mode
Remark L: Low-level input
H: High-level input
×: Don’t care
50
Preliminary User’s Manual U17718EJ1V0UD
CHAPTER 3 CPU FUNCTION
3.4 Address Space
3.4.1 CPU address space
For instruction addressing, an internal ROM area of up to 1 MB, and an internal RAM area are supported in a linear
address space (program space) of up to 64 MB. For operand addressing (data access), up to 4 GB of a linear address
space (data space) is supported. The 4 GB address space, however, is viewed as 64 images of a 64 MB physical
address space. This means that the same 64 MB physical address space is accessed regardless of the value of bits
31 to 26.
Figure 3-1. Image on Address Space
Image 63
Program space
Use-prohibited area
Internal RAM area
Use-prohibited area
4 GB
64 MB
Image 1
Image 0
Data space
Peripheral I/O area
Internal RAM area
64 MB
Use-prohibited area
Internal ROM area
1 MB
Internal ROM area
Preliminary User’s Manual U17718EJ1V0UD
51
CHAPTER 3 CPU FUNCTION
3.4.2 Wraparound of CPU address space
(1) Program space
Of the 32 bits of the PC (program counter), the higher 6 bits are fixed to 0 and only the lower 26 bits are valid.
The higher 6 bits ignore a carry or borrow from bit 25 to 26 during branch address calculation.
Therefore, the highest address of the program space, 03FFFFFFH, and the lowest address, 00000000H, are
contiguous addresses. That the highest address and the lowest address of the program space are contiguous
in this way is called wraparound.
Caution Because the 4 KB area of addresses 03FFF000H to 03FFFFFFH is an on-chip peripheral I/O
area, instructions cannot be fetched from this area. Therefore, do not execute an operation in
which the result of a branch address calculation affects this area.
00000001H
00000000H
03FFFFFFH
03FFFFFEH
Program space
(+) direction (−) direction
Program space
(2) Data space
The result of an operand address calculation operation that exceeds 32 bits is ignored.
Therefore, the highest address of the data space, FFFFFFFFH, and the lowest address, 00000000H, are
contiguous, and wraparound occurs at the boundary of these addresses.
00000001H
00000000H
FFFFFFFFH
Data space
(+) direction (−) direction
52
FFFFFFFEH
Data space
Preliminary User’s Manual U17718EJ1V0UD
CHAPTER 3 CPU FUNCTION
3.4.3 Memory map
The areas shown below are reserved in the V850ES/HG2.
Figure 3-2. Data Memory Map (Physical Addresses)
03FFFFFFH
(80 KB)
03FEC000H
03FEBFFFH
On-chip peripheral I/O area
(4 KB)
Internal RAM area
(60 KB)
Use prohibited
Use prohibited
Note 1
03FFFFFFH
03FFF000H
03FFEFFFH
03FF0000H
03FEFFFFH
03FEF000H
03FEEFFFH
03FEC000H
Use prohibited
00100000H
000FFFFFH
Internal ROM area
(1 MB)
00000000H
Note 2
Notes 1. Use of addresses 03FEF000H to 03FEFFFFH is prohibited because these addresses are in the
same area as the on-chip peripheral I/O area.
2. Fetch access and read access to addresses 00000000H to 000FFFFFH is made to the internal ROM
area.
Preliminary User’s Manual U17718EJ1V0UD
53
CHAPTER 3 CPU FUNCTION
Figure 3-3. Program Memory Map
03FFFFFFH
03FFF000H
03FFEFFFH
Use prohibited
(program fetch prohibited area)
03FF0000H
03FEFFFFH
01000000H
00FFFFFFH
Internal RAM area (60 KB)
Use prohibited
(program fetch prohibited area)
Use prohibited
Note
00100000H
000FFFFFH
00000000H
Note For details, see 3.4.4 (2) Internal RAM area.
54
Preliminary User’s Manual U17718EJ1V0UD
Internal ROM area
(1 MB)
3.4.4 Areas
(1) Internal ROM area
Up to 1 MB is reserved as an internal ROM area.
(a) Internal ROM (128 KB)
128 KB are allocated to addresses 0000000H to 001FFFFH in the
Accessing addresses 0020000H to 00FFFFFH is prohibited.
Figure 3-4. Internal ROM Area (128 KB)
CHAPTER 3 CPU FUNCTION
00FFFFFH
Access-prohibited
area
0020000H
001FFFFH
µ
PD70F3706.
(b) Internal ROM (256 KB)
256 KB are allocated to addresses 0000000H to 003FFFFH in the
Accessing addresses 00040000H to 000FFFFFH is prohibited.
Internal ROM area
(128 KB)
0000000H
µ
Figure 3-5. Internal ROM Area (256 KB)
00FFFFFH
Access-prohibited
area
0040000H
003FFFFH
Internal ROM area
(256 KB)
PD70F3707.
0000000H
Preliminary User’s Manual U17718EJ1V0UD
55
(2) Internal RAM area
Up to 60 KB are reserved as the internal RAM area.
(a) Internal RAM (12 KB)
12 KB are allocated to addresses 03FFC000H to 03FFEFFFH in the V850ES/HG2.
Accessing addresses 03FF0000H to 03FFBFFFH is prohibited.
Figure 3-6. Internal RAM Area (12 KB)
Physical address space Logical address space
CHAPTER 3 CPU FUNCTION
03FFEFFFH
Internal RAM
03FFC000H
03FFBFFFH
Access-prohibited
area
03FF0000H
FFFFEFFFH
FFFFC000H
FFFFBFFFH
FFFF0000H
(3) On-chip peripheral I/O area
4 KB of addresses 03FFF000H to 03FFFFFFH are reserved as the on-chip peripheral I/O area.
Figure 3-7. On-Chip Peripheral I/O Area
Physical address space Logical address space
03FFFFFFH
On-chip peripheral I/O area
(4 KB)
03FFF000H
FFFFFFFFH
FFFFF000H
Peripheral I/O registers that have functions to specify the operation mode for and monitor the status of the on-
chip peripheral I/O are mapped to the on-chip peripheral I/O area. Program cannot be fetched from this area.
56
Preliminary User’s Manual U17718EJ1V0UD
CHAPTER 3 CPU FUNCTION
Cautions 1. When a register is accessed in word units, a word area is accessed twice in halfword
units in the order of lower area and higher area, with the lower 2 bits of the address
ignored.
2. If a register that can be accessed in byte units is accessed in halfword units, the higher 8
bits are undefined when the register is read, and data is written to the lower 8 bits.
3. Addresses not defined as registers are reserved for future expansion. The operation is
undefined and not guaranteed when these addresses are accessed.
3.4.5 Recommended use of address space
The architecture of the V850ES/HG2 requires that a register that serves as a pointer be secured for address
generation when operand data in the data space is accessed. The address stored in this pointer ±32 KB can be
directly accessed by an instruction for operand data. Because the number of general-purpose registers that can be
used as a pointer is limited, however, by keeping the performance from dropping during address calculation when a
pointer value is changed, as many general-purpose registers as possible can be secured for variables, and the
program size can be reduced.
(1) Program space
Of the 32 bits of the PC (program counter), the higher 6 bits are fixed to 0, and only the lower 26 bits are valid.
Regarding the program space, therefore, a 64 MB space of contiguous addresses starting from 00000000H
unconditionally corresponds to the memory map.
To use the internal RAM area as the program space, access addresses 03FFC000H to 03FFEFFFH (12 KB).
Caution If a branch instruction is at the upper limit of the internal RAM area, a prefetch operation
(invalid fetch) straddling the on-chip peripheral I/O area does not occur.
Preliminary User’s Manual U17718EJ1V0UD
57
CHAPTER 3 CPU FUNCTION
(2) Data space
With the V850ES/HG2, it seems that there are sixty-four 64 MB address spaces on the 4 GB CPU address
space. Therefore, the least significant bit (bit 25) of a 26-bit address is sign-extended to 32 bits and allocated
as an address.
(a) Application example of wraparound
If R = r0 (zero register) is specified for the LD/ST disp16 [R] instruction, a range of addresses 00000000H
±32 KB can be addressed by sign-extended disp16. All the resources, including the internal hardware, can
be addressed by one pointer.
The zero register (r0) is a register fixed to 0 by hardware, and practically eliminates the need for registers
dedicated to pointers.
Figure 3-8. Wraparound (
µ
PD70F3707)
0003FFFFH
00007FFFH
(R = )
00000000H
FFFFF000H
FFFFEFFFH
FFFFC000H
FFFEBFFFH
FFFF8000H
Internal ROM area
On-chip peripheral
I/O area
Internal RAM area
Access-prohibited
area
32 KB
4 KB
12 KB
16 KB
58
Preliminary User’s Manual U17718EJ1V0UD
CHAPTER 3 CPU FUNCTION
Figure 3-9. Recommended Memory Map
FFFFFFFFH
FFFFF000H
FFFFEFFFH
FFFF0000H
FFFEFFFFH
04000000H
03FFFFFFH
03FFF000H
03FFEFFFH
03FFC000H
03FFBFFFH
03FF0000H
03FEFFFFH
Use prohibited
Internal RAM
Data spaceProgram space
On-chip
peripheral I/O
Internal RAM
On-chip
peripheral I/O
Internal RAM
Use prohibited
FFFFFFFFH
FFFFF000H
FFFFEFFFH
FFFFC000H
FFFFBFFFH
FFFF0000H
FFFEFFFFH
Program space
64 MB
00100000H
000FFFFFH
00040000H
0003FFFFH
00000000H
Use prohibited
Internal ROM
Internal ROM
Remarks 1.
indicates the recommended area.
2. This figure is the recommended memory map of the µPD70F3707.
00100000H
000FFFFFH
Internal ROM
00000000H
Preliminary User’s Manual U17718EJ1V0UD
59
CHAPTER 3 CPU FUNCTION
3.4.6 Peripheral I/O registers
Address Function Register Name Symbol R/W
FFFFF004H Port DL PDL √ Undefined
FFFFF004H Port DLL PDLL
FFFFF005H Port DLH PDLH
FFFFF008H Port CS PCS
FFFFF00AH Port CT PCT
FFFFF00CH Port CM PCM
FFFFF024H Port mode register DL PMDL
FFFFF024H Port mode register DLL PMDLL
FFFFF025H Port mode register DLH PMDLH
FFFFF028H Port mode register CS PMCS
FFFFF02AH Port mode register CT PMCT
FFFFF02CH Port mode register CM PMCM
FFFFF04CH Port mode control register CM PMCCM
FFFFF06EH System wait control register
FFFFF080H DMA source address register 0L DSA0L
FFFFF082H DMA source address register 0H DSA0H
FFFFF084H DMA destination address register 0L DDA0L
FFFFF086H DMA destination address register 0H DDA0H
FFFFF088H DMA source address register 1L DSA1L
FFFFF08AH DMA source address register 1H DSA1H
FFFFF08CH DMA destination address register 1L DDA1L
FFFFF08EH DMA destination address register 1H DDA1H
FFFFF090H DMA source address register 2L DSA2L
FFFFF092H DMA source address register 2H DSA2H
FFFFF094H DMA destination address register 2L DDA2L
FFFFF096H DMA destination address register 2H DDA2H
FFFFF098H DMA source address register 3L DSA3L
FFFFF09AH DMA source address register 3H DSA3H
FFFFF09CH DMA destination address register 3L DDA3L
FFFFF09EH DMA destination address register 3H DDA3H
FFFFF0C0H DMA transfer count register 0 DBC0
FFFFF0C2H DMA transfer count register 1 DBC1
FFFFF0C4H DMA transfer count register 2 DBC2
FFFFF0C6H DMA transfer count register 3 DBC3
FFFFF0D0H DMA addressing control register 0 DADC0
FFFFF0D2H DMA addressing control register 1 DADC1
FFFFF0D4H DMA addressing control register 2 DADC2
FFFFF0D6H DMA addressing control register 3 DADC3
FFFFF0E0H DMA channel control register 0 DCHC0
FFFFF0E2H DMA channel control register 1 DCHC1
FFFFF0E4H DMA channel control register 2 DCHC2
FFFFF0E6H DMA channel control register 3 DCHC3
VSWC
Manipulatable Bits
1 8 16
R/W
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
Undefined
Undefined
Undefined
Undefined
Undefined
√
FFH
FFH
FFH
FFH
FFH
00H
77H
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
00H
00H
00H
00H
Default Value
FFFFH
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000H
0000H
0000H
0000H
(1/9)
60
Preliminary User’s Manual U17718EJ1V0UD
CHAPTER 3 CPU FUNCTION
Address Function Register Name Symbol R/W
FFFFF100H Interrupt mask register 0 IMR0
FFFFF100H Interrupt mask register 0L IMR0L
FFFFF101H Interrupt mask register 0H IMR0H
FFFFF102H Interrupt mask register 1 IMR1
FFFFF102H Interrupt mask register 1L IMR1L
FFFFF103H Interrupt mask register 1H IMR1H
FFFFF104H Interrupt mask register 2 IMR2
FFFFF104H Interrupt mask register 2L IMR2L
FFFFF105H Interrupt mask register 2H IMR2H
FFFFF106H Interrupt mask register 3 IMR3
FFFFF106H Interrupt mask register 3L IMR3L
FFFFF107H Interrupt mask register 3H IMR3H
FFFFF110H Interrupt control register LVIIC
FFFFF112H Interrupt control register PIC0
FFFFF114H Interrupt control register PIC1
FFFFF116H Interrupt control register PIC2
FFFFF118H Interrupt control register PIC3
FFFFF11AH Interrupt control register PIC4
FFFFF11CH Interrupt control register PIC5
FFFFF11EH Interrupt control register PIC6
FFFFF120H Interrupt control register PIC7
FFFFF122H Interrupt control register TQ0OVIC
FFFFF124H Interrupt control register TQ0CCIC0
FFFFF126H Interrupt control register TQ0CCIC1
FFFFF128H Interrupt control register TQ0CCIC2
FFFFF12AH Interrupt control register TQ0CCIC3
FFFFF12CH Interrupt control register TP0OVIC
FFFFF12EH Interrupt control register TP0CCIC0
FFFFF130H Interrupt control register TP0CCIC1
FFFFF132H Interrupt control register TP1OVIC
FFFFF134H Interrupt control register TP1CCIC0
FFFFF136H Interrupt control register TP1CCIC1
FFFFF138H Interrupt control register TP2OVIC
FFFFF13AH Interrupt control register TP2CCIC0
FFFFF13CH Interrupt control register TP2CCIC1
FFFFF13EH Interrupt control register TP3OVIC
FFFFF140H Interrupt control register TP3CCIC0
FFFFF142H Interrupt control register TP3CCIC1
FFFFF144H Interrupt control register TM0EQIC0
FFFFF146H Interrupt control register CB0RIC
FFFFF148H Interrupt control register CB0TIC
FFFFF14AH Interrupt control register CB1RIC
Manipulatable Bits
1 8 16
R/W
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
Default Value
FFFFH
√
FFH
FFH
FFFFH
√
FFH
FFH
FFFFH
√
FFH
FFH
FFFFH
√
FFH
FFH
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
(2/9)
Preliminary User’s Manual U17718EJ1V0UD
61
CHAPTER 3 CPU FUNCTION
Address Function Register Name Symbol R/W
FFFFF14CH Interrupt control register CB1TIC
FFFFF14EH Interrupt control register UA0RIC
FFFFF150H Interrupt control register UA0TIC
FFFFF152H Interrupt control register UA1RIC
FFFFF154H Interrupt control register UA1TIC
FFFFF156H Interrupt control register ADIC
FFFFF160H Interrupt control register KRIC
FFFFF162H Interrupt control register
FFFFF164H Interrupt control register WTIC
FFFFF166H Interrupt control register PIC8
FFFFF168H Interrupt control register PIC9
FFFFF16AH Interrupt control register PIC10
FFFFF16CH Interrupt control register TQ1OVIC
FFFFF16EH Interrupt control register TQ1CCIC0
FFFFF170H Interrupt control register TQ1CCIC1
FFFFF172H Interrupt control register TQ1CCIC2
FFFFF174H Interrupt control register TQ1CCIC3
FFFFF176H Interrupt control register UA2RIC
FFFFF178H Interrupt control register UA2TIC
FFFFF182H Interrupt control register DMAIC0
FFFFF184H Interrupt control register DMAIC1
FFFFF186H Interrupt control register DMAIC2
FFFFF188H Interrupt control register DMAIC3
FFFFF1FAH In-service priority register ISPR R
FFFFF1FCH Command register PRCMD W
FFFFF1FEH Power save control register PSC
FFFFF200H A/D converter mode register 0 ADA0M0
FFFFF201H A/D converter mode register 1 ADA0M1
FFFFF202H A/D converter channel specification register ADA0S
FFFFF203H A/D converter mode register 2 ADA0M2
FFFFF204H Power-fail compare mode register ADA0PFM
FFFFF205H Power-fail compare threshold value register ADA0PFT
FFFFF210H A/D conversion result register 0 ADA0CR0
FFFFF211H A/D conversion result register 0H ADA0CR0H
FFFFF212H A/D conversion result register 1 ADA0CR1
FFFFF213H A/D conversion result register 1H ADA0CR1H
FFFFF214H A/D conversion result register 2 ADA0CR2
FFFFF215H A/D conversion result register 2H ADA0CR2H
FFFFF216H A/D conversion result register 3 ADA0CR3
FFFFF217H A/D conversion result register 3H ADA0CR3H
FFFFF218H A/D conversion result register 4 ADA0CR4
FFFFF219H A/D conversion result register 4H ADA0CR4H
WTIIC
Manipulatable Bits
1 8 16
R/W
R/W
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
R
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
00H
Undefined
√
00H
00H
00H
00H
00H
00H
00H
√
Undefined
√
√
Undefined
√
√
Undefined
√
√
Undefined
√
√
Undefined
√
(3/9)
Default Value
Undefined
Undefined
Undefined
Undefined
Undefined
62
Preliminary User’s Manual U17718EJ1V0UD
CHAPTER 3 CPU FUNCTION
Address Function Register Name Symbol R/W
FFFFF21AH A/D conversion result register 5 ADA0CR5
FFFFF21BH A/D conversion result register 5H ADA0CR5H
FFFFF21CH A/D conversion result register 6 ADA0CR6
FFFFF21DH A/D conversion result register 6H ADA0CR6H
FFFFF21EH A/D conversion result register 7 ADA0CR7
FFFFF21FH A/D conversion result register 7H ADA0CR7H
FFFFF220H A/D conversion result register 8 ADA0CR8
FFFFF221H A/D conversion result register 8H ADA0CR8H
FFFFF222H A/D conversion result register 9 ADA0CR9
FFFFF223H A/D conversion result register 9H ADA0CR9H
FFFFF224H A/D conversion result register 10 ADA0CR10
FFFFF225H A/D conversion result register 10H ADA0CR10H
FFFFF226H A/D conversion result register 11 ADA0CR11
FFFFF227H A/D conversion result register 11H ADA0CR11H
FFFFF228H A/D conversion result register 12 ADA0CR12
FFFFF229H A/D conversion result register 12H ADA0CR12H
FFFFF22AH A/D conversion result register 13 ADA0CR13
FFFFF22BH A/D conversion result register 13H ADA0CR13H
FFFFF22CH A/D conversion result register 14 ADA0CR14
FFFFF22DH A/D conversion result register 14H ADA0CR14H
FFFFF22EH A/D conversion result register 15 ADA0CR15
FFFFF22FH A/D conversion result register 15H ADA0CR15H
FFFFF300H Key return mode register KRM
FFFFF308H Selector operation control register 0 SELCNT0
FFFFF318H Noise elimination control register NFC
FFFFF400H Port 0 P0
FFFFF402H Port 1 P1
FFFFF406H Port 3 P3 √ Undefined
FFFFF406H Port 3L P3L
FFFFF407H Port 3H P3H
FFFFF408H Port 4 P4
FFFFF40AH Port 5 P5
FFFFF40EH Port 7L P7L
FFFFF40FH Port 7H P7H
FFFFF412H Port 9 P9 √ Undefined
FFFFF412H Port 9L P9L
FFFFF413H Port 9H P9H
FFFFF420H Port mode register 0 PM0
FFFFF422H Port mode register 1 PM1
FFFFF426H Port mode register 3 PM3
FFFFF426H Port mode register 3L PM3L
FFFFF427H Port mode register 3H PM3H
Manipulatable Bits
1 8 16
R
R/W
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√
Undefined
√
√
Undefined
√
√
Undefined
√
√
Undefined
√
√
Undefined
√
√
Undefined
√
√
Undefined
√
√
Undefined
√
√
Undefined
√
√
Undefined
√
√
Undefined
√
00H
00H
00H
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
FFH
FFH
√
FFH
FFH
Default Value
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
FFFFH
(4/9)
Preliminary User’s Manual U17718EJ1V0UD
63
CHAPTER 3 CPU FUNCTION
Address Function Register Name Symbol R/W
FFFFF428H Port mode register 4 PM4
FFFFF42AH Port mode register 5 PM5
FFFFF42EH Port mode register 7L PM7L
FFFFF42FH Port mode register 7H PM7H
FFFFF432H Port mode register 9 PM9
FFFFF432H Port mode register 9L PM9L
FFFFF433H Port mode register 9H PM9H
FFFFF440H Port mode control register 0 PMC0
FFFFF442H Port mode control register 1 PMC1
FFFFF446H Port mode control register 3 PMC3
FFFFF446H Port mode control register 3L PMC3L
FFFFF448H Port mode control register 4 PMC4
FFFFF44AH Port mode control register 5 PMC5
FFFFF452H Port mode control register 9 PMC9
FFFFF452H Port mode control register 9L PMC9L
FFFFF453H Port mode control register 9H PMC9H
FFFFF460H Port function control register 0 PFC0
FFFFF466H Port function control register 3L PFC3L
FFFFF46AH Port function control register 5 PFC5
FFFFF472H Port function control register 9 PFC9
FFFFF472H Port function control register 9L PFC9L
FFFFF473H Port function control register 9H PFC9H
FFFFF540H TMQ0 control register 0 TQ0CTL0
FFFFF541H TMQ0 control register 1 TQ0CTL1
FFFFF542H TMQ0 I/O control register 0 TQ0IOC0
FFFFF543H TMQ0 I/O control register 1 TQ0IOC1
FFFFF544H TMQ0 I/O control register 2 TQ0IOC2
FFFFF545H TMQ0 option register 0 TQ0OPT0
FFFFF546H TMQ0 capture/compare register 0 TQ0CCR0
FFFFF548H TMQ0 capture/compare register 1 TQ0CCR1
FFFFF54AH TMQ0 capture/compare register 2 TQ0CCR2
FFFFF54CH TMQ0 capture/compare register 3 TQ0CCR3
FFFFF54EH TMQ0 counter read buffer register TQ0CNT R
FFFFF590H TMP0 control register 0 TP0CTL0
FFFFF591H TMP0 control register 1 TP0CTL1
FFFFF592H TMP0 I/O control register 0 TP0IOC0
FFFFF593H TMP0 I/O control register 1 TP0IOC1
FFFFF594H TMP0 I/O control register 2 TP0IOC2
FFFFF595H TMP0 option register 0 TP0OPT0
FFFFF596H TMP0 capture/compare register 0 TP0CCR0
FFFFF598H TMP0 capture/compare register 1 TP0CCR1
FFFFF59AH TMP0 counter read buffer register TP0CNT R
Manipulatable Bits
1 8 16
R/W
R/W
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ 0000H
√ √
√ √
√ √
√ √
√ √
√ √
√ 0000H
Default Value
FFH
FFH
FFH
FFH
FFFFH
√
FFH
FFH
00H
00H
0000H
√
00H
00H
00H
0000H
√
00H
00H
00H
00H
00H
0000H
√
00H
00H
00H
00H
00H
00H
00H
00H
0000H
√
0000H
√
0000H
√
0000H
√
00H
00H
00H
00H
00H
00H
0000H
√
0000H
√
(5/9)
64
Preliminary User’s Manual U17718EJ1V0UD
CHAPTER 3 CPU FUNCTION
Address Function Register Name Symbol R/W
FFFFF5A0H TMP1 control register 0 TP1CTL0
FFFFF5A1H TMP1 control register 1 TP1CTL1
FFFFF5A2H TMP1 I/O control register 0 TP1IOC0
FFFFF5A3H TMP1 I/O control register 1 TP1IOC1
FFFFF5A4H TMP1 I/O control register 2 TP1IOC2
FFFFF5A5H TMP1 option register 0 TP1OPT0
FFFFF5A6H TMP1 capture/compare register 0 TP1CCR0
FFFFF5A8H TMP1 capture/compare register 1 TP1CCR1
FFFFF5AAH TMP1 counter read buffer register TP1CNT R
FFFFF5B0H TMP2 control register 0 TP2CTL0
FFFFF5B1H TMP2 control register 1 TP2CTL1
FFFFF5B2H TMP2 I/O control register 0 TP2IOC0
FFFFF5B3H TMP2 I/O control register 1 TP2IOC1
FFFFF5B4H TMP2 I/O control register 2 TP2IOC2
FFFFF5B5H TMP2 option register 0 TP2OPT0
FFFFF5B6H TMP2 capture/compare register 0 TP2CCR0
FFFFF5B8H TMP2 capture/compare register 1 TP2CCR1
FFFFF5BAH TMP2 counter read buffer register TP2CNT R
FFFFF5C0H TMP3 control register 0 TP3CTL0
FFFFF5C1H TMP3 control register 1 TP3CTL1
FFFFF5C2H TMP3 I/O control register 0 TP3IOC0
FFFFF5C3H TMP3 I/O control register 1 TP3IOC1
FFFFF5C4H TMP3 I/O control register 2 TP3IOC2
FFFFF5C5H TMP3 option register 0 TP3OPT0
FFFFF5C6H TMP3 capture/compare register 0 TP3CCR0
FFFFF5C8H TMP3 capture/compare register 1 TP3CCR1
FFFFF5CAH TMP3 counter read buffer register TP3CNT R
FFFFF610H TMQ1 control register 0 TQ1CTL0
FFFFF611H TMQ1 control register 1 TQ1CTL1
FFFFF612H TMQ1 I/O control register 0 TQ1IOC0
FFFFF613H TMQ1 I/O control register 1 TQ1IOC1
FFFFF614H TMQ1 I/O control register 2 TQ1IOC2
FFFFF615H TMQ1 timer option register 0 TQ1OPT0
FFFFF616H TMQ1 capture/compare register 0 TQ1CCR0
FFFFF618H TMQ1 capture/compare register 1 TQ1CCR1
FFFFF61AH TMQ1 capture/compare register 2 TQ1CCR2
FFFFF61CH TMQ1 capture/compare register 3 TQ1CCR3
FFFFF61EH TMQ1 counter read buffer register TQ1CNT R
FFFFF680H Watch timer operation mode register WTM
FFFFF690H TMM0 control register 0 TM0CTL0
FFFFF694H TMM0 compare register 0 TM0CMP0
FFFFF6C0H Oscillation stabilization time select register OSTS
Manipulatable Bits
1 8 16
R/W
R/W
R/W
R/W
R/W
√ √
√ √
√ √
√ √
√ √
√ √
√ 0000H
√ √
√ √
√ √
√ √
√ √
√ √
√ 0000H
√ √
√ √
√ √
√ √
√ √
√ 0000H
√ √
√ √
√ √
√ √
√ √
√ √
√ 0000H
√ √
√ √
√
√
Default Value
00H
00H
00H
00H
00H
00H
0000H
√
0000H
√
00H
00H
00H
00H
00H
00H
0000H
√
0000H
√
00H
00H
00H
00H
00H
00H
0000H
√
0000H
√
00H
00H
00H
00H
00H
00H
0000H
√
0000H
√
0000H
√
0000H
√
00H
00H
0000H
√
06H
(6/9)
Preliminary User’s Manual U17718EJ1V0UD
65
CHAPTER 3 CPU FUNCTION
Address Function Register Name Symbol R/W
FFFFF6C1H PLL lockup time specification register PLLS
FFFFF6D0H Watchdog timer mode register 2 WDTM2
FFFFF6D1H Watchdog timer enable register WDTE
FFFFF706H Port function control expansion register 3L PFCE3L
FFFFF70AH Port function control expansion register 5 PFCE5
FFFFF712H Port function control expansion register 9 PFCE9
FFFFF712H Port function control expansion register 9L PFCE9L
FFFFF713H Port function control expansion register 9H PFCE9H
FFFFF802H System status register SYS
FFFFF80CH Internal oscillation mode register RCM
FFFFF810H DMA trigger factor register 0 DTFR0
FFFFF812H DMA trigger factor register 1 DTFR1
FFFFF814H DMA trigger factor register 2 DTFR2
FFFFF816H DMA trigger factor register 3 DTFR3
FFFFF820H Power save mode register PSMR
FFFFF824H Lock register LOCKR R
FFFFF828H Processor clock control register PCC
FFFFF82CH PLL control register PLLCTL
FFFFF82EH CPU operating clock status register CCLS R
FFFFF82FH Programmable clock mode register PCLM
FFFFF870H Clock monitor mode register CLM
FFFFF888H Reset source flag register RESF
FFFFF890H Low-voltage detection register LVIM
FFFFF891H Low-voltage detection level select register LVIS
FFFFF892H Internal RAM data status register RAMS
FFFFF8B0H Prescaler mode register 0 PRSM0
FFFFF8B1H Prescaler compare register 0 PRSCM0
FFFFF9FCH On-chip debug mode register OCDM
FFFFF9FEH Peripheral emulation register 1 PEMU1
FFFFFA00H UARTA0 control register 0 UA0CTL0
FFFFFA01H UARTA0 control register 1 UA0CTL1
FFFFFA02H UARTA0 control register 2 UA0CTL2
FFFFFA03H UARTA0 option control register 0 UA0OPT0
FFFFFA04H UARTA0 status register UA0STR
FFFFFA06H UARTA0 receive data register UA0RX R
FFFFFA07H UARTA0 transmit data register UA0TX
FFFFFA10H UARTA1 control register 0 UA1CTL0
FFFFFA11H UARTA1 control register 1 UA1CTL1
FFFFFA12H UARTA1 control register 2 UA1CTL2
FFFFFA13H UARTA1 option control register 0 UA1OPT0
FFFFFA14H UARTA1 status register UA1STR
Manipulatable Bits
1 8 16
R/W
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
R/W
R/W
R/W
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
Caution For details of the OCDM register, see CHAPTER 25 ON-CHIP DEBUG FUNCTION.
√
√
√
√
√
√
√
√
√
√
√
Default Value
03H
67H
9AH
00H
00H
0000H
√
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
03H
01H
00H
00H
00H
00H
00H
00H
01H
00H
00H
01H
00H
10H
00H
FFH
14H
00H
FFH
FFH
10H
00H
FFH
14H
00H
(7/9)
66
Preliminary User’s Manual U17718EJ1V0UD
CHAPTER 3 CPU FUNCTION
Address Function Register Name Symbol R/W
FFFFFA16H UARTA1 receive data register UA1RX R
FFFFFA17H UARTA1 transmit data register UA1TX R/W
FFFFFA20H UARTA2 control register 0 UA2CTL0
FFFFFA21H UARTA2 control register 1 UA2CTL1
FFFFFA22H UARTA2 control register 2 UA2CTL2
FFFFFA23H UARTA2 option control register 0 UA2OPT0
FFFFFA24H UARTA2 status register UA2STR
FFFFFA26H UARTA2 receive data register UA2RX R
FFFFFA27H UARTA2 transmit data register UA2TX R/W
FFFFFB00H TIP00 pin noise elimination control register P00NFC
FFFFFB04H TIP01 pin noise elimination control register P01NFC
FFFFFB08H TIP10 pin noise elimination control register P10NFC
FFFFFB0CH TIP11 pin noise elimination control register P11NFC
FFFFFB10H TIP20 pin noise elimination control register P20NFC
FFFFFB14H TIP21 pin noise elimination control register P21NFC
FFFFFB18H TIP30 pin noise elimination control register P30NFC
FFFFFB1CH TIP31 pin noise elimination control register P31NFC
FFFFFB50H TIQ00 pin noise elimination control register Q00NFC
FFFFFB54H TIQ01 pin noise elimination control register Q01NFC
FFFFFB58H TIQ02 pin noise elimination control register Q02NFC
FFFFFB5CH TIQ03 pin noise elimination control register Q03NFC
FFFFFB60H TIQ10 pin noise elimination control register Q10NFC
FFFFFB64H TIQ11 pin noise elimination control register Q11NFC
FFFFFB68H TIQ12 pin noise elimination control register Q12NFC
FFFFFB6CH TIQ13 pin noise elimination control register Q13NFC
FFFFFC00H External interrupt falling edge specification register 0 INTF0
FFFFFC02H External interrupt falling edge specification register 1 INTF1
FFFFFC06H External interrupt falling edge specification register 3 INTF3
FFFFFC06H External interrupt falling edge specification register 3L INTF3L
FFFFFC13H External interrupt falling edge specification register 9H INTF9H
FFFFFC20H External interrupt rising edge specification register 0 INTR0
FFFFFC22H External interrupt rising edge specification register 1 INTR1
FFFFFC26H External interrupt rising edge specification register 3 INTR3
FFFFFC26H External interrupt rising edge specification register 3L INTR3L
FFFFFC33H External interrupt rising edge specification register 9H INTR9H
FFFFFC40H Pull-up resistor option register 0 PU0
FFFFFC42H Pull-up resistor option register 1 PU1
FFFFFC46H Pull-up resistor option register 3 PU3
FFFFFC46H Pull-up resistor option register 3L PU3L
FFFFFC47H Pull-up resistor option register 3H PU3H
FFFFFC48H Pull-up resistor option register 4 PU4
FFFFFC4AH Pull-up resistor option register 5 PU5
Manipulatable Bits
1 8 16
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√
√
√
√
√
√
Default Value
FFH
FFH
10H
00H
FFH
14H
00H
FFH
FFH
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
0000H
√
00H
00H
00H
00H
0000H
√
00H
00H
00H
00H
0000H
√
00H
00H
00H
00H
(8/9)
Preliminary User’s Manual U17718EJ1V0UD
67
CHAPTER 3 CPU FUNCTION
Address
FFFFFC52H Pull-up resistor option register 9 PU9
FFFFFC52H Pull-up resistor option register 9L PU9L
FFFFFC53H Pull-up resistor option register 9H PU9H
FFFFFD00H CSIB0 control register 0 CB0CTL0
FFFFFD01H CSIB0 control register 1 CB0CTL1
FFFFFD02H CSIB0 control register 2 CB0CTL2
FFFFFD03H CSIB0 status register CB0STR
FFFFFD04H CSIB0 receive data register CB0RX
FFFFFD04H CSIB0 receive data register L CB0RXL
FFFFFD06H CSIB0 transmit data register CB0TX
FFFFFD06H CSIB0 transmit data register L CB0TXL
FFFFFD10H CSIB1 control register 0 CB1CTL0
FFFFFD11H CSIB1 control register 1 CB1CTL1
FFFFFD12H CSIB1 control register 2 CB1CTL2
FFFFFD13H CSIB1 status register CB1STR
FFFFFD14H CSIB1 receive data register CB1RX
FFFFFD14H CSIB1 receive data register L CB1RXL
FFFFFD16H CSIB1 transmit data register CB1TX
FFFFFD16H CSIB1 transmit data register L CB1TXL
Function Register Name Symbol R/W
Manipulatable Bits
1 8 16
R/W
√ √
√ √
√ √
√ √
√ √
R
R/W
√ √
√ √
√ √
R
R/W
√
√
√
√
√
√
Default Value
0000H
√
00H
00H
01H
00H
00H
00H
0000H
√
00H
0000H
√
00H
01H
00H
00H
00H
0000H
√
00H
0000H
√
00H
(9/9)
68
Preliminary User’s Manual U17718EJ1V0UD
CHAPTER 3 CPU FUNCTION
3.4.7 Special registers
Special registers are registers that are protected from being written with illegal data due to an inadvertent program
loop. The V850ES/HG2 has the following seven special registers.
• Power save control register (PSC)
• Processor clock control register (PCC)
• Clock monitor mode register (CLM)
• Reset source flag register (RESF)
• Low-voltage detection register (LVIM)
• Internal RAM data status register (RAMS)
• On-chip debug mode register (OCDM)
In addition, the PRCDM register is provided to protect against a write access to the special registers so that the
application system does not inadvertently stop due to an inadvertent program loop. A write access to the special
registers is made in a specific sequence, and an illegal store operation is reported to the SYS register.
Preliminary User’s Manual U17718EJ1V0UD
69
CHAPTER 3 CPU FUNCTION
(1) Setting data to special registers
Set data to the special registers in the following sequence.
<1> Disable DMA operation.
<2> Prepare data to be set to the special register in a general-purpose register.
<3> Write the data prepared in <2> to the PRCMD register.
<4> Write the setting data to the special register (by using the following instructions).
• Store instruction (ST/SST instruction)
• Bit manipulation instruction (SET1/CLR1/NOT1 instruction)
(<5> to <9> Insert NOP instructions (5 instructions).)
Note
<10> Enable DMA operation if necessary.
[Example] With PSC register (setting standby mode)
ST.B r11, PSMR[r0] ; Set PSMR register (setting IDLE1, IDLE2, and STOP modes).
<1>CLR1 0, DCHCn[r0] ; Disable DMA operation. n = 0 to 3
<2>MOV0x02, r10
<3>ST.B r10, PRCMD[r0] ; Write PRCMD register.
<4>ST.B r10, PSC[r0] ; Set PSC register.
<5>NOP
<6>NOP
<7>NOP
<8>NOP
<9>NOP
Note
; Dummy instruction
Note
; Dummy instruction
Note
; Dummy instruction
Note
; Dummy instruction
Note
; Dummy instruction
<10>SET1 0, DCHCn[r0] ; Enable DMA operation. n = 0 to 3
(next instruction)
There is no special sequence to read a special register.
Note Five NOP instructions or more must be inserted immediately after setting the IDLE1 mode, IDLE2
mode, or STOP mode (by setting the PSC.STP bit to 1).
Cautions 1. When a store instruction is executed to store data in the command register, interrupts are
not acknowledged. This is because it is assumed that steps <3> and <4> above are
performed by successive store instructions. If another instruction is placed between <3>
and <4>, and if an interrupt is acknowledged by that instruction, the above sequence may
not be established, causing malfunction.
2. Although dummy data is written to the PRCMD register, use the same general-purpose
register used to set the special register (<4> in Example) to write data to the PRCMD
register (<3> in Example). The same applies when a general-purpose register is used for
addressing.
70
Preliminary User’s Manual U17718EJ1V0UD
CHAPTER 3 CPU FUNCTION
(2) Command register (PRCMD)
The PRCMD register is an 8-bit register that protects the registers that may seriously affect the application
system from being written, so that the system does not inadvertently stop due to an inadvertent program loop.
The first write access to a special register is valid after data has been written in advance to the PRCMD
register. In this way, the value of the special register can be rewritten only in a specific sequence, so as to
protect the register from an illegal write access.
The PRCMD register is write-only, in 8-bit units (undefined data is read when this register is read).
After reset: Undefined W Address: FFFFF1FCH
7
REG7PRCMD
6
REG65REG54REG43REG32REG21REG10REG0
Preliminary User’s Manual U17718EJ1V0UD
71
CHAPTER 3 CPU FUNCTION
(3) System status register (SYS)
Status flags that indicate the operation status of the overall system are allocated to this register.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
After reset: 00H R/W Address: FFFFF802H
SYS 0 0 0 0 0 0 PRERR
0
PRERR
0
Protection error did not occur
1
Protection error occurred
The PRERR flag operates under the following conditions.
(a) Set condition (PRERR flag = 1)
(i) When data is written to a special register without writing anything to the PRCMD register (when <4> is
executed without executing <3> in 3.4.7 (1) Setting data to special registers)
(ii) When data is written to an on-chip peripheral I/O register other than a special register (including
execution of a bit manipulation instruction) after writing data to the PRCMD register (if <4> in 3.4.7 (1)
Setting data to special registers is not the setting of a special register)
Remark Even if an on-chip peripheral I/O register is read (except by a bit manipulation instruction)
between an operation to write the PRCMD register and an operation to write a special register,
the PRERR flag is not set, and the set data can be written to the special register.
(b) Clear condition (PRERR flag = 0)
(i) When 0 is written to the PRERR flag
(ii) When the system is reset
Cautions 1. If 0 is written to the PRERR bit of the SYS register, which is not a special register,
immediately after a write access to the PRCMD register, the PRERR bit is cleared to 0
(the write access takes precedence).
2. If data is written to the PRCMD register, which is not a special register, immediately
after a write access to the PRCMD register, the PRERR bit is set to 1.
Detects protection error
72
Preliminary User’s Manual U17718EJ1V0UD
CHAPTER 3 CPU FUNCTION
3.4.8 Cautions
(1) Registers to be set first
Be sure to set the following registers first when using the V850ES/HG2.
• System wait control register (VSWC)
• On-chip debug mode register (OCDM)
• Watchdog timer mode register 2 (WDTM2)
After setting the VSWC, OCDM, and WDTM2 registers, set the other registers as necessary.
When using the external bus, set each pin to the alternate-function bus control pin mode by using the port-
related registers after setting the above registers.
(a) System wait control register (VSWC)
The VSWC register controls wait of bus access to the on-chip peripheral I/O registers.
Three clocks are required to access an on-chip peripheral I/O register (without a wait cycle). The
V850ES/HG2 requires wait cycles according to the operating frequency. Set the following value to the
VSWC register in accordance with the frequency used.
The VSWC register can be read or written in 8-bit units (address: FFFFF06EH, default value: 77H).
Operating Frequency (fCLK) Set Value of VSWC Number of Waits
32 kHz ≤ fCLK < 16.6 MHz 00H 0 (no waits)
16.6 MHz ≤ fCLK ≤ 20 MHz 01H 1
(b) On-chip debug mode register (OCDM)
For details, see CHAPTER 25 ON-CHIP DEBUG FUNCTION.
(c) Watchdog timer mode register 2 (WDTM2)
The WDTM2 register sets the overflow time and the operation clock of watchdog timer 2.
Watchdog timer 2 automatically starts in the reset mode after reset is released. Write the WDTM2 register
to activate this operation.
For details, see CHAPTER 10 FUNCTIONS OF WATCHDOG TIMER 2.
Preliminary User’s Manual U17718EJ1V0UD
73
CHAPTER 3 CPU FUNCTION
(2) Accessing specific on-chip peripheral I/O registers
This product has two types of internal system buses.
One is a CPU bus and the other is a peripheral bus that interfaces with low-speed peripheral hardware.
The clock of the CPU bus and the clock of the peripheral bus are asynchronous. If an access to the CPU and
an access to the peripheral hardware conflict, therefore, unexpected illegal data may be transferred. If there is
a possibility of a conflict, the number of cycles for accessing the CPU changes when the peripheral hardware is
accessed, so that correct data is transferred. As a result, the CPU does not start processing of the next
instruction but enters the wait state. If this wait state occurs, the number of clocks required to execute an
instruction increases by the number of wait clocks shown below.
This must be taken into consideration if real-time processing is required.
When specific on-chip peripheral I/O registers are accessed, more wait states may be required in addition to
the wait states set by the VSWC register.
The access conditions and how to calculate the number of wait states to be inserted (number of CPU clocks)
at this time are shown below.
Peripheral Function Register Name Access k
16-bit timer/event counter P (TMP)
(n = 0 to 3)
16-bit timer/event counter Q (TMQ)
(m = 0, 1)
Watchdog timer 2 (WDT2) WDTM2 Write
A/D converter
TPnCNT Read 1 or 2
TPnCCR0, TPnCCR1
TQmCNT Read 1 or 2
TQmCCR0 to TQmCCR3
ADA0M0 Read 1 or 2
ADA0CR0 to ADA0CR15 Read 1 or 2
ADA0CR0H to ADA0CR15H Read 1 or 2
Write • 1st access: No wait
• Continuous write: 3 or 4
Read 1 or 2
Write • 1st access: No wait
• Continuous write: 3 or 4
Read 1 or 2
3
(when WDT2 operating)
Number of clocks necessary for access = 3 + i + j + (2 + j) × k
Caution Accessing the above registers is prohibited in the following statuses. If a wait cycle is
generated, it can only be cleared by a reset.
• When the CPU operates with the subclock and the main clock oscillation is stopped
• When the CPU operates with the internal oscillation clock
Remark i: Values (0 or 1) of higher 4 bits of VSWC register
j: Values (0 or 1) of lower 4 bits of VSWC register
74
Preliminary User’s Manual U17718EJ1V0UD
CHAPTER 3 CPU FUNCTION
(3) Restriction on conflict between sld instruction and interrupt request
(a) Description
If a conflict occurs between the decode operation of an instruction in <2> immediately before the sld
instruction following an instruction in <1> and an interrupt request before the instruction in <1> is
complete, the execution result of the instruction in <1> may not be stored in a register.
Instruction <1>
• ld instruction: ld.b, ld.h, ld.w, ld.bu, ld.hu
• sld instruction: sld.b, sld.h, sld.w, sld.bu, sld.hu
• Multiplication instruction: mul, mulh, mulhi, mulu
Instruction <2>
mov reg1, reg2
satadd reg1, reg2
and reg1, reg2
add reg1, reg2
mulh reg1, reg2
not reg1, reg2
satadd imm5, reg2
tst reg1, reg2
add imm5, reg2
shr imm5, reg2
satsubr reg1, reg2
or reg1, reg2
subr reg1, reg2
cmp reg1, reg2
sar imm5, reg2
<Example>
<i> ld.w [r11], r10 If the decode operation of the mov instruction <ii> immediately before the sld
•
•
•
instruction <iii> and an interrupt request conflict before execution of the ld
instruction <i> is complete, the execution result of instruction <i> may not be
stored in a register.
<ii> mov r10, r28
<iii> sld.w 0x28, r10
(b) Countermeasure
<1> When compiler (CA850) is used
Use CA850 Ver. 2.61 or later because generation of the corresponding instruction sequence can be
automatically suppressed.
<2> Countermeasure by assembler
When executing the sld instruction immediately after instruction <ii>, avoid the above operation using
either of the following methods.
• Insert a nop instruction immediately before the sld instruction.
• Do not use the same register as the sld instruction destination register in the above instruction <ii>
executed immediately before the sld instruction.
satsub reg1, reg2
xor reg1, reg2
sub reg1, reg2
cmp imm5, reg2
shl imm5, reg2
Preliminary User’s Manual U17718EJ1V0UD
75
CHAPTER 4 PORT FUNCTIONS
4.1 Features
O I/O ports: 84
O Port pins function alternately as other peripheral-function I/O pins
O Can be set in input or output mode in 1-bit units.
4.2 Basic Configuration of Ports
The V850ES/HG2 has a total of 84 I/O ports, ports 0, 1, 3 to 5, 7, 9, CM, CS, CT, and DL. The port configuration is
shown below.
Figure 4-1. Port Configuration
Port 0
Port 1
Port 3
Port 4
Port 5
Port 7
P00
P06
P10
P11
P30
P39
P40
P42
P50
P55
P70
P715
P90
P915
PCM0
PCM3
PCS0
PCS1
PCT0
PCT1
PCT4
PCT6
PDL0
PDL13
Port 9
Port CM
Port CS
Port CT
Port DL
76
Preliminary User’s Manual U17718EJ1V0UD
CHAPTER 4 PORT FUNCTIONS
Table 4-1. Configuration of Ports
Item Configuration
Control registers
Ports 84
Port mode register (PMn: n = 0, 1, 3, 4, 5, 7L, 7H, 9, CM, CS, CT, or DL)
Port mode control register (PMCn: n = 0, 1, 3, 4, 5, 9, or CM)
Port function control register (PFCn: n = 0, 3L, 5, or 9)
Port function control expansion register (PFCEn: n = 3L, 5, or 9)
Pull-up resistor option register (PUn: n = 0, 1, 3, 4, 5, or 9)
Table 4-2. Pin I/O Buffer Power Supplies
Power Supply Corresponding Pin
AVREF0 Port 7
BVDD Port CM, port CS, port CT, port DL
EVDD Port 0, port 1, port 3, port 4, port 5, port 9, RESET
Preliminary User’s Manual U17718EJ1V0UD
77
CHAPTER 4 PORT FUNCTIONS
4.3 Port Functions
4.3.1 Operation of port function
The operation of a port differs depending on setting of the input or output mode, as follows.
(1) Writing to I/O port
(a) In output mode
A value can be written to the output latch by using a transfer instruction. The contents of the output latch
are output from the pin. Once data has been written to the output latch, it is retained until new data is
written to the output latch.
(b) In input mode
A value can be written to the output latch by using a transfer instruction. Because the output buffer is off,
however, the status of the pin remains unchanged.
Once data has been written to the output latch, it is retained until new data is written to the output latch.
Caution Although a 1-bit memory manipulation instruction manipulates 1 bit, it accesses a port in
8-bit units. If a port has a mixture of input and output pins, therefore, the contents of the
output latch of a pin set in the input mode become undefined, even if the pin is not
subject to manipulation.
(2) Reading from I/O port
(a) In output mode
The contents of the output latch can be read by using a transfer instruction. The contents of the output
latch are not changed.
(b) In input mode
The status of the pin can be read by using a transfer instruction. The contents of the output latch are not
changed.
(3) Operation of I/O port
(a) In output mode
An operation is performed on the contents of the output latch and the result is written to the output latch.
The contents of the output latch are output from the pin.
Once data has been written to the output latch, it is retained until new data is written to the output latch.
(b) In input mode
The contents of the output latch become undefined. Because the output buffer is off, however, the status
of the pin remains unchanged.
Caution Although a 1-bit memory manipulation instruction manipulates 1 bit, it accesses a port in
8-bit units. If a port has a mixture of input and output pins, therefore, the contents of the
output latch of a pin set in the input mode become undefined, even if the pin is not
subject to manipulation.
78
Preliminary User’s Manual U17718EJ1V0UD
CHAPTER 4 PORT FUNCTIONS
4.3.2 Notes on setting port pins
(1) The number of ports and alternate functions differs depending on the product. Set the registers related to the
unavailable ports and alternate functions to the value after reset.
(2) Set the registers of the ports using the following procedure.
<1> Set port function control register n (PFCn) and port function control expansion register n (PFCEn).
<2> Set port mode control register n (PMCn).
<3> Set external interrupt falling edge specification register n (INTFn) and external interrupt rising edge
specification register n (INTRn).
If the PFCn and PFCEn registers are set after the PMCn register was set, an unexpected peripheral function
pin may be set while the PFCn and PFCEn registers are being set.
(3) The PUnm bit (which connects an on-chip pull-up resistor) of the PUn register is valid only in the input mode
(PMnm bit of PMn register = 1). In the output mode (PMnm bit of PMn register = 0), the on-chip pull-up
register is disconnected by hardware.
(4) Reading the pin level and port latch is controlled by the port mode register (PMn). The same applies when an
alternate function is used.
(5) The Schmitt (SHMT)-trigger input buffer does not operate as an SHMT buffer when it is read in the port mode.
Preliminary User’s Manual U17718EJ1V0UD
79
CHAPTER 4 PORT FUNCTIONS
4.3.3 Port 0
Port 0 is a 7-bit port (P00 to P06) for which I/O settings can be controlled in 1-bit units.
(1) Functions of port 0
• The input/output data of the port can be specified in 1-bit units.
Specified by port register 0 (P0)
• The input/output mode of the port can be specified in 1-bit units.
Specified by port mode register 0 (PM0)
• Port mode or control mode (alternate function) can be specified in 1-bit units.
Specified by port mode control register 0 (PMC0)
• Control mode 1 or control mode 2 can be specified in 1-bit units.
Specified by port function control register 0 (PFC0)
• An on-chip pull-up resistor can be connected in 1-bit units.
Specified by pull-up resistor option register 0 (PU0)
• The valid edge of the external interrupt (alternate function) can be specified in 1-bit units.
Specified by external interrupt falling edge specification register 0 (INTF0) and external interrupt rising edge
specification register 0 (INTR0)
Port 0 functions alternately as the following pins.
Table 4-3. Alternate-Function Pins of Port 0
Pin Name Alternate-Function Pin Name I/O Remark Block Type
Por t 0
P00 TP31/TOP31 G-1
P01 TP30/TOP30 G-1
P02 NMI
P03 INTP0/ADTRG N-1
P04 INTP1 L-1
P05 INTP2/DRST
P06 INTP3
Note 1
L-1
Note 2
AA-1
I/O –
L-2
Notes 1. The NMI pin alternately functions as the P02 pin. It functions as the P02 pin after reset.
To enable the NMI pin, set the PMC0.PMC02 bit to 1. The initial setting of the NMI pin is “No edge
detected”. Select the NMI pin valid edge using INTF0 and INTR0 registers.
2. The alternate function of the P05 pin is the on-chip debug function. After external reset, the
P05/INTP2/DRST pin is initialized as the on-chip debug pin (DRST). To use the P05 pin as a port
pin, not as an on-chip debug pin, the following actions must be taken.
<1> Clear the OCDM.OCDM0 bit (special register) to 0.
<2> Fix the P05/INTP2/DRST pin to the low level until the above action has been taken.
When the on-chip debug function is not used, inputting a high level to the DRST pin before the
above actions are taken may cause a malfunction (CPU deadlock). Exercise utmost care in
handling the P05 pin.
When a high level is not input to the P05/INTP2/DRST pin (when this pin is fixed to low level), it is
not necessary to manipulate the OCDM.OCDM0 bit.
80
Preliminary User’s Manual U17718EJ1V0UD
CHAPTER 4 PORT FUNCTIONS
Because a pull-down resistor (30 kΩ TYP.) is connected to the buffer of the P05/INTP2/DRST pin,
the pin does not have to be fixed to the low level by an external source. The pull-down resistor is
disconnected by clearing the OCDM0 bit to 0.
Caution The P00 to P06 pins have hysteresis characteristics in the input mode of the alternate
function, but do not have hysteresis characteristics in the port mode.
(2) Registers
(a) Port register 0 (P0)
Port register 0 (P0) is an 8-bit register that controls reading the pin level and writing the output level. This
register can be read or written in 8-bit or 1-bit units.
After reset: Undefined R/W Address: FFFFF400H
7 6 5 4 3 2 1 0
P0 0 P06 P05 P04 P03 P02 P01 P00
P0n Control of output data (in output mode) (n = 0 to 6)
0 Output 0.
1 Output 1.
(b) Port mode register 0 (PM0)
This is an 8-bit register that specifies the input or output mode. It can be read or written in 8-bit or 1-bit
units.
After reset: FFH R/W Address: FFFFF420H
7 6 5 4 3 2 1 0
PM0 1 PM06 PM05 PM04 PM03 PM02 PM01 PM00
PM0n Control of input/output mode (n = 0 to 6)
0 Output mode
1 Input mode
Preliminary User’s Manual U17718EJ1V0UD
81
CHAPTER 4 PORT FUNCTIONS
(c) Port mode control register 0 (PMC0)
This is an 8-bit register that specifies the port mode or control mode. It can be read or written in 8-bit or 1-
bit units.
After reset: 00H R/W Address: FFFFF440H
7 6 5 4 3 2 1 0
PMC0 0 PMC06 PMC05 PMC04 PMC03 PMC02 PMC01 PMC00
PMC06 Specification of operation mode of P06 pin
0 I/O port
1 INTP3 input
PMC05 Specification of operation mode of P05 pin
0 I/O port
1 INTP2/DRST input
PMC04 Specification of operation mode of P04 pin
0 I/O port
1 INTP1 input
PMC03 Specification of operation mode of P03 pin
0 I/O port
1 INTP0/ADTRG input
PMC02 Specification of operation mode of P02 pin
0 I/O port
1 NMI input
PMC01 Specification of operation mode of P01 pin
0 I/O port
1 TIP30/TOP30 I/O
PMC00 Specification of operation mode of P00 pin
0 I/O port
1 TIP31/TOP31 I/O
Caution The P05/INTP2/DRST pin functions as the DRST pin when the OCDM.OCDM0 bit is 1,
regardless of the value of the PMC05 bit.
82
Preliminary User’s Manual U17718EJ1V0UD
CHAPTER 4 PORT FUNCTIONS
(d) Port function control register 0 (PFC0)
This is an 8-bit register that specifies control mode 1 or control mode 2. It can be read or written in 8-bit or
1-bit units.
After reset: 00H R/W Address: FFFFF460H
7 6 5 4 3 2 1 0
PFC0 0 0 0 0 PFC03 0 PFC01 PFC00
PFC03 Specification of operation mode when P03 pin is in control mode
0 INTP0 input
1 ADTRG input
PFC01 Specification of operation mode when P01 pin is in control mode
0 TIP30 input
1 TOP30 output
PFC00 Specification of operation mode when P00 pin is in control mode
0 TIP31 input
1 TOP31 output
(e) Pull-up resistor option register 0 (PU0)
This is an 8-bit register that specifies connection of an on-chip pull-up resistor. It can be read or written in
8-bit or 1-bit units.
After reset: 00H R/W Address: FFFFFC40H
7 6 5 4 3 2 1 0
PU0 0 PU06 PU05 PU04 PU03 PU02 PU01 PU00
PU0n Control of on-chip pull-up resistor connection (n = 0 to 6)
0 Not connected
1 Connected
Preliminary User’s Manual U17718EJ1V0UD
83
CHAPTER 4 PORT FUNCTIONS
(f) External interrupt falling edge specification register 0 (INTF0)
This is an 8-bit register that specifies detection of the falling edge of the external interrupt pin. It can be
read or written in 8-bit or 1-bit units.
Cautions 1. When the external interrupt function (alternate function) is switched to the port
function, an edge may be detected. Set the port mode after clearing the INTF0n and
INTR0n bits to 0.
2. An analog-delay-based noise eliminator is connected to the external interrupt input
pin.
3. For how to set the internal noise filter (analog delay/digital delay) of INTP3, see
CHAPTER 15 INTERRUPT/EXCEPTION PROCESSING FUNCTION.
After reset: 00H R/W Address: FFFFFC00H
7 6 5 4 3 2 1 0
INTF0 0 INTF06 INTF05 INTF04 INTF03 INTF02 0 0
Remark See Table 4-4 for how to specify a valid edge.
(g) External interrupt rising edge specification register 0 (INTR0)
This is an 8-bit register that specifies detection of the rising edge of the external interrupt pin. It can be
read or written in 8-bit or 1-bit units.
Cautions 1. When the external interrupt function (alternate function) is switched to the port
function, an edge may be detected. Set the port mode after clearing the INTF0n and
INTR0n bits to 0.
2. An analog-delay-based noise eliminator is connected to the external interrupt input
pin.
3. For how to set the internal noise filter (analog delay/digital delay) of INTP3, see
CHAPTER 15 INTERRUPT/EXCEPTION PROCESSING FUNCTION.
After reset: 00H R/W Address: FFFFFC20H
7 6 5 4 3 2 1 0
INTR0 0 INTR06 INTR05 INTR04 INTR03 INTR02 0 0
Remark See Table 4-4 for how to specify a valid edge.
84
Preliminary User’s Manual U17718EJ1V0UD
CHAPTER 4 PORT FUNCTIONS
Table 4-4. Valid Edge Specification
INTF0n Bit INTR0n Bit Valid Edge Specification (n = 2 to 6)
0 0 No edge detected
0 1 Rising edge
1 0 Falling edge
1 1 Both edges
Remark n = 2: Control of NMI pin
n = 3: Control of INTP0 pin
n = 4: Control of INTP1 pin
n = 5: Control of INTP2 pin
n = 6: Control of INTP3 pin
Preliminary User’s Manual U17718EJ1V0UD
85
CHAPTER 4 PORT FUNCTIONS
4.3.4 Port 1
Port 1 is a 2-bit port (P10, P11) for which I/O settings can be controlled in 1-bit units.
(1) Functions of port 1
O The input/output data of the port can be specified in 1-bit units.
Specified by port register 1 (P1)
O The input/output mode of the port can be specified in 1-bit units.
Specified by port mode register 1 (PM1)
O Port mode or control mode (alternate function) can be specified in 1-bit units.
Specified by port mode control register 1 (PMC1)
O An on-chip pull-up resistor can be connected in 1-bit units.
Specified by pull-up resistor option register 1 (PU1)
O The valid edge of the external interrupt (alternate function) can be specified in 1-bit units.
Specified by external interrupt falling edge specification register 1 (INTF1) and external interrupt rising edge
specification register 1 (INTR1)
Port 1 functions alternately as the following pins.
Table 4-5. Alternate-Function Pins of Port 1
Pin Name Alternate-Function Pin Name I/O Remark Block Type
P10 INTP9 L-1 Por t 1
P11 INTP10
I/O –
L-1
Caution The P10 and P11 pins have hysteresis characteristics in the input mode of the alternate
function, but do not have hysteresis characteristics in the port mode.
86
Preliminary User’s Manual U17718EJ1V0UD
CHAPTER 4 PORT FUNCTIONS
(2) Registers
(a) Port register 1 (P1)
Port register 1 (P1) is an 8-bit register that controls reading the pin level and writing the output level. This
register can be read or written in 8-bit or 1-bit units.
After reset: Undefined R/W Address: FFFFF402H
7 6 5 4 3 2 1 0
P1 0 0 0 0 0 0 P11 P10
P1n Control of output data (in output mode) (n = 0, 1)
0 Output 0.
1 Output 1.
(b) Port mode register 1 (PM1)
This is an 8-bit register that specifies the input or output mode. It can be read or written in 8-bit or 1-bit
units.
After reset: FFH R/W Address: FFFFF422H
7 6 5 4 3 2 1 0
PM1 1 1 1 1 1 1 PM11 PM10
PM1n Control of input/output mode (n = 0, 1)
0 Output mode
1 Input mode
Preliminary User’s Manual U17718EJ1V0UD
87
CHAPTER 4 PORT FUNCTIONS
(c) Port mode control register 1 (PMC1)
This is an 8-bit register that specifies the port mode or control mode. It can be read or written in 8-bit or 1-
bit units.
After reset: 00H R/W Address: FFFFF442H
7 6 5 4 3 2 1 0
PMC1 0 0 0 0 0 0 PMC11 PMC10
PMC11 Specification of operation mode of P11 pin
0 I/O port
1 INTP10 input
PMC10 Specification of operation mode of P10 pin
0 I/O port
1 INTP9 input
(d) Pull-up resistor option register 1 (PU1)
This is an 8-bit register that specifies connection of an on-chip pull-up resistor. It can be read or written in
8-bit or 1-bit units.
After reset: 00H R/W Address: FFFFFC42H
7 6 5 4 3 2 1 0
PU1 0 0 0 0 0 0 PU11 PU10
PU1n Control of on-chip pull-up resistor connection (n = 0, 1)
0 Not connected
1 Connected
88
Preliminary User’s Manual U17718EJ1V0UD
CHAPTER 4 PORT FUNCTIONS
(e) External interrupt falling edge specification register 1 (INTF1)
This is an 8-bit register that specifies detection of the falling edge of the external interrupt pin. It can be
read or written in 8-bit or 1-bit units.
Cautions 1. When the external interrupt function (alternate function) is switched to the port
function, an edge may be detected. Set the port mode after clearing the INTF1n and
INTR1n bits to 0.
2. An analog-delay-based noise eliminator is connected to the external interrupt input
pin.
After reset: 00H R/W Address: FFFFFC02H
7 6 5 4 3 2 1 0
INTF1 0 0 0 0 0 0 INTF11 INTF10
Remark See Table 4-6 for how to specify a valid edge.
(f) External interrupt rising edge specification register 1 (INTR1)
This is an 8-bit register that specifies detection of the rising edge of the external interrupt pin. It can be
read or written in 8-bit or 1-bit units.
Cautions 1. When the external interrupt function (alternate function) is switched to the port
function, an edge may be detected. Set the port mode after clearing the INTF1n and
INTR1n bits to 0.
2. An analog-delay-based noise eliminator is connected to the external interrupt input
pin.
After reset: 00H R/W Address: FFFFFC22H
7 6 5 4 3 2 1 0
INTR1 0 0 0 0 0 0 INTR11 INTR10
Remark See Table 4-6 for how to specify a valid edge.
Table 4-6. Valid Edge Specification
INTF1n Bit INTR1n Bit Valid Edge Specification (n = 0, 1)
0 0 No edge detected
0 1 Rising edge
1 0 Falling edge
1 1 Both edges
Remark n = 0: Control of INTP9 pin
n = 1: Control of INTP10 pin
Preliminary User’s Manual U17718EJ1V0UD
89
CHAPTER 4 PORT FUNCTIONS
4.3.5 Port 3
Port 3 is a 10-bit port (P30 to P39) for which I/O settings can be controlled in 1-bit units.
(1) Function of port 3
• The input/output data of the port can be specified in 1-bit units.
Specified by port register 3 (P3)
• The input/output mode of the port can be specified in 1-bit units.
Specified by port mode register 3 (PM3)
• Port mode or control mode (alternate function) can be specified in 1-bit units.
Specified by port mode control register 3 (PMC3)
• Control mode can be specified in 1-bit units.
Specified by port function control register 3 (PFC3) and port function control expansion register 3L
(PFCE3L)
• An on-chip pull-up resistor can be connected in 1-bit units.
Specified by pull-up resistor option register 3 (PU3)
• The valid edge of the external interrupt (alternate function) can be specified in 1-bit units.
Specified by external interrupt falling edge specification register 3 (INTF3) and external interrupt rising edge
specification register 3 (INTR3)
Port 3 functions alternately as the following pins.
Table 4-7. Alternate-Function Pins of Port 3
Pin Name Alternate-Function Pin Name I/O Remark Block Type
Por t 3
P30 TXDA0 E-2
P31 RXDA0/INTP7 L-2
P32 ASCKA0/TIP00/TOP00/TOP01 U-13
P33 TIP01/TOP01 G-1
P34 TIP10/TOP10 G-1
P35 TIP11/TOP11 G-1
P36
P37
P38 TXDA2 E-2
P39 RXDA2/INTP8
−
−
I/O –
C-1
C-1
L-2
Caution The P31 to P35, and P39 pins have hysteresis characteristics in the input mode of the
alternate function, but do not have hysteresis characteristics in the port mode.
90
Preliminary User’s Manual U17718EJ1V0UD
CHAPTER 4 PORT FUNCTIONS
(2) Registers
(a) Port register 3 (P3)
Port register 3 (P3) is a 16-bit register that controls reading the pin level and writing the output level. This
register can be read or written in 16-bit units.
If the higher 8 bits of the P3 register are used as the P3H register, and the lower 8 bits as the P3L register,
however, these registers can be read or written in 8-bit or 1-bit units.
After reset: Undefined R/W Address: FFFFF406H, FFFFF407H
15 14 13 12 11 10 9 8
P3 (P3H
7 6 5 4 3 2 1 0
(P3L) P37 P36 P35 P34 P33 P32 P31 P30
P3n Control of output data (in output mode) (n = 0 to 9)
0 Output 0.
1 Output 1.
Note
) 0 0 0 0 0 0 P39 P38
Note To read or write bits 8 to 15 of the P3 register in 8-bit or 1-bit units, specify these bits as bits 0 to
7 of the P3H register.
(b) Port mode register 3 (PM3)
This is a 16-bit register that specifies the input or output mode. It can be read or written in 16-bit units.
If the higher 8 bits of the PM3 register are used as the PM3H register, and the lower 8 bits as the PM3L
register, however, these registers can be read or written in 8-bit or 1-bit units.
After reset: FFFFH R/W Address: FFFFF426H, FFFFF427H
15 14 13 12 11 10 9 8
PM3 (PM3H
7 6 5 4 3 2 1 0
PM3n Control of I/O mode (n = 0 to 9)
0 Output mode
1 Input mode
Note
) 1 1 1 1 1 1 PM39 PM38
(PM3L) PM37 PM36 PM35 PM34 PM33 PM32 PM31 PM30
Note To read or write bits 8 to 15 of the PM3 register in 8-bit or 1-bit units, specify these bits as bits 0
to 7 of the PM3H register.
Preliminary User’s Manual U17718EJ1V0UD
91
CHAPTER 4 PORT FUNCTIONS
(c) Port mode control register 3 (PMC3)
This is a 16-bit register that specifies the port mode or control mode. It can be read or written in 16-bit
units.
If the higher 8 bits of the PMC3 register are used as the PMC3H register, and the lower 8 bits as the
PMC3L register, however, these registers can be read or written in 8-bit or 1-bit units.
(1/2)
After reset: 0000H R/W Address: FFFFF446H, FFFFF447H
15 14 13 12 11 10 9 8
PMC3 (PMC3H
7 6 5 4 3 2 1 0
PMC39 Specification of operation mode of P39 pin
0 I/O port
1 RXDA2/INTP8 input
PMC38 Specification of operation mode of P38 pin
0 I/O port
1 TXDA2 output
PMC35 Specification of operation mode of P35 pin
0 I/O port
1 TIP11/TOP11 I/O
PMC34 Specification of operation mode of P34 pin
0 I/O port
1 TIP10/TOP10 I/O
Note 1
) 0 0 0 0 0 0 PMC39 PMC38
(PMC3L) 0 0 PMC35 PMC34 PMC33 PMC32 PMC31 PMC30
Note 2
Notes 1. To read or write bits 8 to 15 of the PMC3 register in 8-bit or 1-bit units, specify these bits as
bits 0 to 7 of the PMC3H register.
2. The INTP8 pin functions alternately as the RXDA2 pin. To use as the RXDA2 pin, invalidate
the edge detection function of the alternate-function INTP8 pin (by fixing the INTF3.INTF39
bit to 0 and the INTR3.INTR39 bit to 0). To use as the INTP8 pin, stop the reception
operation of UARTA2 (by clearing the UA2CTL0.UA2RXE bit to 0).
92
Preliminary User’s Manual U17718EJ1V0UD
CHAPTER 4 PORT FUNCTIONS
(2/2)
PMC33 Specification of operation mode of P33 pin
0 I/O port
1 TIP01/TOP01 I/O
PMC32 Specification of operation mode of P32 pin
0 I/O port
1 ASCKA0/TIP00/TOP00/TOP01 I/O
PMC31 Specification of operation mode of P31 pin
0 I/O port
1 RXDA0/INTP7 input
PMC30 Specification of operation mode of P30 pin
0 I/O port
1 TXDA0 output
Note The INTP7 pin functions alternately as the RXDA0 pin. To use as the RXDA0 pin, invalidate
Note
the edge detection function of the alternate-function INTP7 pin (by fixing the INTF3.INTF31
and INTR3.INTR31 bits to 0). To use as the INTP7 pin, stop the reception operation of
UARTA0 (by clearing the UA0CTL0.UA0RXE bit to 0).
(d) Port function control register 3L (PFC3L)
This is an 8-bit register that specifies control mode 1, 2, 3, or 4. It can be read or written in 8-bit or 1-bit
units.
After reset: 00H R/W Address: FFFFF466H
7 6 5 4 3 2 1 0
PFC3L 0 0 PFC35 PFC34 PFC33 PFC32 0 0
Remark For how to specify a control mode, see 4.3.5 (2) (f) Setting of control mode of P3 pin.
Preliminary User’s Manual U17718EJ1V0UD
93
CHAPTER 4 PORT FUNCTIONS
(e) Port function control expansion register 3L (PFCE3L)
This is an 8-bit register that specifies control mode 1, 2, 3, or 4. It can be read or written in 8-bit or 1-bit
units.
After reset: 00H R/W Address: FFFFF706H
7 6 5 4 3 2 1 0
PFCE3L 0 0 0 0 0 PFCE32 0 0
Remark For how to specify a control mode, see 4.3.5 (2) (f) Setting of control mode of P3 pin.
(f) Setting of control mode of P3 pin
PFC35 Specification of control mode of P35 pin
0 TIP11 input
1 TOP11 output
PFC34 Specification of control mode of P34 pin
0 TIP10 input
1 TOP10 output
PFC33 Specification of control mode of P33 pin
0 TIP01 input
1 TOP01 output
PFCE32 PFC32 Specification of control mode of P32 pin
0 0 ASCKA0 input
0 1 TOP01 output
1 0 TIP00 input
1 1 TOP00 output
94
Preliminary User’s Manual U17718EJ1V0UD
CHAPTER 4 PORT FUNCTIONS
(g) Pull-up resistor option register 3 (PU3)
This is a 16-bit register that specifies connection of an on-chip pull-up resistor. It can be read or written in
16- or 1-bit units.
If the higher 8 bits of the PU3 register are used as the PU3H register, and the lower 8 bits as the PU3L
register, however, these registers can be read or written in 8-bit or 1-bit units.
After reset: 00H R/W Address: FFFFFC46H, FFFFFC47H
15 14 13 12 11 10 9 8
PU3 (PU3H
7 6 5 4 3 2 1 0
PU3n Control of on-chip pull-up resistor connection (n = 0 to 9)
0 Not connected
1 Connected
Note
) 0 0 0 0 0 0 PU39 PU38
(PU3L) PU37 PU36 PU35 PU34 PU33 PU32 PU31 PU30
Note To read/write bits 8 to 15 of the PU3 register in 8-bit or 1-bit units, specify these bits as bits 0 to
7 of the PU3H register.
(h) External interrupt falling edge specification register 3 (INTF3)
This is a 16-bit register that specifies detection of the falling edge of the external interrupt pin. It can be
read or written in 16-bit units.
If the higher 8 bits of the INTF3 register are used as the INTF3H register, and the lower 8 bits as the
INTF3L register, however, these registers can be read or written in 8-bit or 1-bit units.
Cautions 1. When the external interrupt function (alternate function) is switched to the port
function, an edge may be detected. Set the port mode after clearing the INTF3n and
INTR3n bits to 0.
2. An analog-delay-based noise eliminator is connected to the external interrupt input
pin.
After reset: 00H R/W Address: FFFFFC06H, FFFFFC07H
15 14 13 12 11 10 9 8
INTF3 (INTF3H
7 6 5 4 3 2 1 0
Note
) 0 0 0 0 0 0 INTF39 0
(INTF3L) 0 0 0 0 0 0 INTF31 0
Note To read/write bits 8 to 15 of the INTF3 register in 8-bit or 1-bit units, specify these bits as bits 0
to 7 of the INTF3H register.
Remark See Table 4-8 for how to specify a valid edge.
Preliminary User’s Manual U17718EJ1V0UD
95
CHAPTER 4 PORT FUNCTIONS
(i) External interrupt rising edge specification register 3 (INTR3)
This is a 16-bit register that specifies detection of the rising edge of the external interrupt pin. It can be
read or written in 16-bit units.
If the higher 8 bits of the INTR3 register are used as the INTR3H register, and the lower 8 bits as the
INTR3L register, however, these registers can be read or written in 8-bit or 1-bit units.
Cautions 1. When the external interrupt function (alternate function) is switched to the port
function, an edge may be detected. Set the port mode after clearing the INTF3n and
INTR3n bits to 0.
2. An analog-delay-based noise eliminator is connected to the external interrupt input
pin.
After reset: 00H R/W Address: FFFFFC26H, FFFFFC27H
15 14 13 12 11 10 9 8
INTR3 (INTR3H
7 6 5 4 3 2 1 0
Note
) 0 0 0 0 0 0 INTR39 0
(INTR3L) 0 0 0 0 0 0 INTR31 0
Note To read/write bits 8 to 15 of the INTR3 register in 8-bit or 1-bit units, specify these bits as bits 0
to 7 of the INTR3H register.
Remark See Table 4-8 for how to specify a valid edge.
Table 4-8. Valid Edge Specification
INTF3n Bit INTR3n Bit Valid Edge Specification (n = 1, 9)
0 0 No edge detected
0 1 Rising edge
1 0 Falling edge
1 1 Both edges
Remark n = 1: Control of INTP7 pin
n = 9: Control of INTP8 pin
96
Preliminary User’s Manual U17718EJ1V0UD
CHAPTER 4 PORT FUNCTIONS
4.3.6 Port 4
Port 4 is a 3-bit port (P40 to P42) for which I/O settings can be controlled in 1-bit units.
(1) Functions of port 4
• The input/output data of the port can be specified in 1-bit units.
Specified by port register 4 (P4)
• The input/output mode of the port can be specified in 1-bit units.
Specified by port mode register 4 (PM4)
• Port mode or control mode (alternate function) can be specified in 1-bit units.
Specified by port mode control register 4 (PMC4)
• An on-chip pull-up resistor can be connected in 1-bit units.
Specified by pull-up resistor option register 4 (PU4)
Port 4 functions alternately as the following pins.
Table 4-9. Alternate-Function Pins of Port 4
Pin Name Alternate-Function Pin Name I/O Remark Block Type
Por t 4
P40 SIB0 E-1
P41 SOB0 E-2
P42 SCKB0
I/O –
E-3
Caution The P40 and P42 pins have hysteresis characteristics in the input mode of the alternate
function, but do not have hysteresis characteristics in the port mode.
Preliminary User’s Manual U17718EJ1V0UD
97
CHAPTER 4 PORT FUNCTIONS
(2) Registers
(a) Port register 4 (P4)
Port register 4 (P4) is an 8-bit register that controls reading the pin level and writing the output level. This
register can be read or written in 8-bit or 1-bit units.
After reset: Undefined R/W Address: FFFFF408H
7 6 5 4 3 2 1 0
P4 0 0 0 0 0 P42 P41 P40
P4n Control of output data (in output mode) (n = 0 to 2)
0 Output 0.
1 Output 1.
(b) Port mode register 4 (PM4)
This is an 8-bit register that specifies the input or output mode. It can be read or written in 8-bit or 1-bit
units.
After reset: FFH R/W Address: FFFFF428H
7 6 5 4 3 2 1 0
PM4 1 1 1 1 1 PM42 PM41 PM40
PM4n Control of input/output mode (n = 0 to 2)
0 Output mode
1 Input mode
98
Preliminary User’s Manual U17718EJ1V0UD
CHAPTER 4 PORT FUNCTIONS
(c) Port mode control register 4 (PMC4)
This is an 8-bit register that specifies the port mode or control mode. It can be read or written in 8-bit or 1-
bit units.
After reset: 00H R/W Address: FFFFF448H
7 6 5 4 3 2 1 0
PMC4 0 0 0 0 0 PMC42 PMC41 PMC40
PMC42 Specification of operation mode of P42 pin
0 I/O port
1 SCKB0 I/O
PMC41 Specification of operation mode of P41 pin
0 I/O port
1 SOB0 output
PMC40 Specification of operation mode of P40 pin
0 I/O port
1 SIB0 input
(d) Pull-up resistor option register 4 (PU4)
This is an 8-bit register that specifies connection of an on-chip pull-up resistor. It can be read or written in
8-bit or 1-bit units.
After reset: 00H R/W Address: FFFFFC48H
7 6 5 4 3 2 1 0
PU4 0 0 0 0 0 PU42 PU41 PU40
PU4n Control of on-chip pull-up resistor connection (n = 0 to 2)
0 Not connected
1 Connected
Preliminary User’s Manual U17718EJ1V0UD
99
CHAPTER 4 PORT FUNCTIONS
4.3.7 Port 5
Port 5 is a 6-bit port (P50 to P55) for which I/O settings can be controlled in 1-bit units.
(1) Functions of port 5
• The input/output data of the port can be specified in 1-bit units.
Specified by port register 5 (P5)
• The input/output mode of the port can be specified in 1-bit units.
Specified by port mode register 5 (PM5)
• Port mode or control mode (alternate function) can be specified in 1-bit units.
Specified by port mode control register 5 (PMC5)
• Control mode can be specified in 1-bit units.
Specified by port function control register 5 (PFC5) or port function control expansion register 5 (PFCE5)
• An on-chip pull-up resistor can be connected in 1-bit units.
Specified by pull-up resistor option register 5 (PU5)
Port 5 functions alternately as the following pins.
Table 4-10. Alternate-Function Pins of Port 5
Pin Name Alternate-Function Pin Name I/O Remark Block Type
Por t 5
P50 KR0/TIQ01/TOQ01 U-4
P51 KR1/TIQ02/TOQ02 U-4
P52 KR2/TIQ03/TOQ03/DDI
P53 KR3/TIQ00/TOQ00/DDO
P54 KR4/DCK
P55 KR5/DMS
Note
G-2
Note
Note
Note
I/O –
U-5
U-6
G-2
Note The DDI, DDO, DCK, and DMS pins are for the on-chip debug function. To use the DDI, DDO, DCK,
and DMS pins as port pins, not as on-chip debug pins, the following actions must be taken.
<1> Clear the OCDM0 bit of the OCDM register (special register) to 0.
<2> Fix the P05/INTP2/DRST pin to the low level until the above action has been taken.
When the on-chip debug function is not used, inputting a high level to the DRST pin before the above
actions are taken may cause a malfunction (CPU deadlock). Exercise utmost care in handling the P05
pin.
When a high level is not input to the P05/INTP2/DRST pin (when this pin is fixed to low level), it is not
necessary to manipulate the OCDM.OCDM0 bit.
Because a pull-down resistor (30 kΩ TYP.) is connected to the buffer of the P05/INTP2/DRST pin, the
pin does not have to be fixed to the low level by an external source. The pull-down resistor is
disconnected by clearing the OCDM0 bit to 0.
Caution The P50 to P55 pins have hysteresis characteristics in the input mode of the alternate
function, but do not have hysteresis characteristics in the port mode.
100
Preliminary User’s Manual U17718EJ1V0UD
Loading...